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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:31 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 01/21] soc: dt-bindings: qcom: apr: convert to yaml Date: Fri, 3 Sep 2021 12:20:12 +0100 Message-Id: <20210903112032.25834-2-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert APR bindings to yaml format so that we could add new bindings support. All the dsp services bindings are now part of apr bindings instead of adding them to audio bindings. Signed-off-by: Srinivas Kandagatla --- .../devicetree/bindings/soc/qcom/qcom,apr.txt | 134 ------------------ .../bindings/soc/qcom/qcom,apr.yaml | 128 +++++++++++++++++ 2 files changed, 128 insertions(+), 134 deletions(-) delete mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,apr.txt create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml -- 2.21.0 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.txt deleted file mode 100644 index 2e2f6dc351c0..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.txt +++ /dev/null @@ -1,134 +0,0 @@ -Qualcomm APR (Asynchronous Packet Router) binding - -This binding describes the Qualcomm APR. APR is a IPC protocol for -communication between Application processor and QDSP. APR is mainly -used for audio/voice services on the QDSP. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,apr-v", example "qcom,apr-v2" - -- qcom,apr-domain - Usage: required - Value type: - Definition: Destination processor ID. - Possible values are : - 1 - APR simulator - 2 - PC - 3 - MODEM - 4 - ADSP - 5 - APPS - 6 - MODEM2 - 7 - APPS2 - -= APR SERVICES -Each subnode of the APR node represents service tied to this apr. The name -of the nodes are not important. The properties of these nodes are defined -by the individual bindings for the specific service -- All APR services MUST contain the following property: - -- reg - Usage: required - Value type: - Definition: APR Service ID - Possible values are : - 3 - DSP Core Service - 4 - Audio Front End Service. - 5 - Voice Stream Manager Service. - 6 - Voice processing manager. - 7 - Audio Stream Manager Service. - 8 - Audio Device Manager Service. - 9 - Multimode voice manager. - 10 - Core voice stream. - 11 - Core voice processor. - 12 - Ultrasound stream manager. - 13 - Listen stream manager. - -- qcom,protection-domain - Usage: optional - Value type: - Definition: Must list the protection domain service name and path - that the particular apr service has a dependency on. - Possible values are : - "avs/audio", "msm/adsp/audio_pd". - "kernel/elf_loader", "msm/modem/wlan_pd". - "tms/servreg", "msm/adsp/audio_pd". - "tms/servreg", "msm/modem/wlan_pd". - "tms/servreg", "msm/slpi/sensor_pd". - -= EXAMPLE -The following example represents a QDSP based sound card on a MSM8996 device -which uses apr as communication between Apps and QDSP. - - apr { - compatible = "qcom,apr-v2"; - qcom,apr-domain = ; - - apr-service@3 { - compatible = "qcom,q6core"; - reg = ; - }; - - apr-service@4 { - compatible = "qcom,q6afe"; - reg = ; - - dais { - #sound-dai-cells = <1>; - dai@1 { - reg = ; - }; - }; - }; - - apr-service@7 { - compatible = "qcom,q6asm"; - reg = ; - ... - }; - - apr-service@8 { - compatible = "qcom,q6adm"; - reg = ; - ... - }; - }; - -= EXAMPLE 2 -The following example represents a QDSP based sound card with protection domain -dependencies specified. Here some of the apr services are dependent on services -running on protection domain hosted on ADSP/SLPI remote processors while others -have no such dependency. - - apr { - compatible = "qcom,apr-v2"; - qcom,glink-channels = "apr_audio_svc"; - qcom,apr-domain = ; - - apr-service@3 { - compatible = "qcom,q6core"; - reg = ; - }; - - q6afe: apr-service@4 { - compatible = "qcom,q6afe"; - reg = ; - qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; - ... - }; - - q6asm: apr-service@7 { - compatible = "qcom,q6asm"; - reg = ; - qcom,protection-domain = "tms/servreg", "msm/slpi/sensor_pd"; - ... - }; - - q6adm: apr-service@8 { - compatible = "qcom,q6adm"; - reg = ; - qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; - ... - }; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml new file mode 100644 index 000000000000..133e9c6cd961 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/qcom/qcom,apr.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm APR (Asynchronous Packet Router) binding + +maintainers: + - Srinivas Kandagatla + +description: | + This binding describes the Qualcomm APR, APR is a IPC protocol for + communication between Application processor and QDSP. APR is mainly + used for audio/voice services on the QDSP. + +properties: + compatible: + enum: + - qcom,apr-v2 + + qcom,apr-domain: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3, 4, 5, 6, 7] + description: + Selects the processor domain for apr + 1 = APR simulator + 2 = PC Domain + 3 = Modem Domain + 4 = ADSP Domain + 5 = Application processor Domain + 6 = Modem2 Domain + 7 = Application Processor2 Domain + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +#APR Services +patternProperties: + "^service@[3-9a-d]$": + type: object + description: + APR node's client devices use subnodes for desired static port services. + + properties: + compatible: + enum: + - qcom,q6core + - qcom,q6asm + - qcom,q6afe + - qcom,q6adm + + reg: + enum: [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13] + description: + APR Service ID + 3 = DSP Core Service + 4 = Audio Front End Service. + 5 = Voice Stream Manager Service. + 6 = Voice processing manager. + 7 = Audio Stream Manager Service. + 8 = Audio Device Manager Service. + 9 = Multimode voice manager. + 10 = Core voice stream. + 11 = Core voice processor. + 12 = Ultrasound stream manager. + 13 = Listen stream manager. + + qcom,protection-domain: + $ref: /schemas/types.yaml#/definitions/string-array + description: protection domain service name and path for apr service + possible values are + "avs/audio", "msm/adsp/audio_pd". + "kernel/elf_loader", "msm/modem/wlan_pd". + "tms/servreg", "msm/adsp/audio_pd". + "tms/servreg", "msm/modem/wlan_pd". + "tms/servreg", "msm/slpi/sensor_pd". + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + additionalProperties: false + +required: + - compatible + - qcom,apr-domain + +additionalProperties: false + +examples: + - | + #include + apr { + compatible = "qcom,apr-v2"; + qcom,apr-domain = ; + #address-cells = <1>; + #size-cells = <0>; + + q6core: service@3 { + compatible = "qcom,q6core"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + }; + + q6afe: service@4 { + compatible = "qcom,q6afe"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + }; + + q6asm: service@7 { + compatible = "qcom,q6asm"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + }; + + q6adm: service@8 { + compatible = "qcom,q6adm"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + }; + }; From patchwork Fri Sep 3 11:20:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 506505 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp906423jai; Fri, 3 Sep 2021 04:21:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzX/fkTxBgbPiJQ82lhOSoBRTKKTQDTt/37HEOoCY9Rd84KiNVHnG00xnOyXO9GkdG7uUt5 X-Received: by 2002:a6b:ba57:: with SMTP id k84mr174558iof.131.1630668100089; Fri, 03 Sep 2021 04:21:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1630668100; cv=none; d=google.com; s=arc-20160816; b=dN1avKF4bDp2ny5Ij0L3aED6okqHHHjrFSw3jNPFqJ8iygonRaCkuYK7yIutiSdCGR 7J/stFYDQBFTLSE41FUZrwijZc6+Fgr/6QMajIu1+NcrKA0CnK3F7z2L8bhELgCLE7bb vR42+BsLhYdaphvtx2v2LUtbYrEPlfMfPKsza0nWgrkE3pUm9fDKHw2gsaAgSdqczY7v y5U8gj3QYjS3EmvOcApWeobG1xvBD6/xNAky2RXZpTLDK/vFwNnyAtNCDcy9Ibdvq1U7 mE4uNDLtRxV+ZQjbWSky7WSHEsBwKzdeW3bV7rCgjGXhdYUwqnA3QvtXTKbRjR/gvh74 6FWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=//dKqQtyVNezpAIRnDOA9TcRJZDgQ0d9R3BICS21tDc=; b=f0Z3LH3ONrwJc5iqASMAvqvrJ8zs+G8Q3elS2FVpUzI6tOF8IQL+MG7z23NcYEIhR9 cvwyVgoNKE0H1oYrDVjC7LmEOQtXVy/kcIi9f+G599E6IFnQkVLQQ6r3vIQkaFqm/td+ stzTje/4FFBbFEV7uJYFnSZBX7gekNrCgbtHs+srWhuaiCe3z7kAGxagKRnksQUeASbJ SR6DW0FnrhczZSIlVVOuTtR5iTGD6pBbtcPbHO1dhySHJwGQMta6G3kIyYaiWWCMtlHa V3skZkGzT3NUt4+YNhVuJkJV9ewOhpMKatgw1DfhOL+LGzVUwhaG5bzHNYx4JDQUVKWK 5V5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="wmZS/Jpd"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:33 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 02/21] soc: dt-bindings: qcom: apr: deprecate qcom, apr-domain property Date: Fri, 3 Sep 2021 12:20:13 +0100 Message-Id: <20210903112032.25834-3-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org replace usage of qcom,apr-domain property with qcom,domain property so that bindings and driver can be reused. Signed-off-by: Srinivas Kandagatla --- .../devicetree/bindings/soc/qcom/qcom,apr.yaml | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) -- 2.21.0 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml index 133e9c6cd961..922c8567c134 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml @@ -31,6 +31,20 @@ properties: 5 = Application processor Domain 6 = Modem2 Domain 7 = Application Processor2 Domain + deprecated: true + + qcom,domain: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3, 4, 5, 6, 7] + description: + Selects the processor domain for apr + 1 = APR simulator + 2 = PC Domain + 3 = Modem Domain + 4 = ADSP Domain + 5 = Application processor Domain + 6 = Modem2 Domain + 7 = Application Processor2 Domain '#address-cells': const: 1 @@ -89,7 +103,7 @@ patternProperties: required: - compatible - - qcom,apr-domain + - qcom,domain additionalProperties: false @@ -98,7 +112,7 @@ examples: #include apr { compatible = "qcom,apr-v2"; - qcom,apr-domain = ; + qcom,domain = ; #address-cells = <1>; #size-cells = <0>; From patchwork Fri Sep 3 11:20:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 506508 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp906436jai; Fri, 3 Sep 2021 04:21:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwOqvUpen8cNhqt7sJA4uZmuAlTqnVoT4i9ov1Y0FeQPKYjEfD3oiZG0cAy1sfu3bmeEnrV X-Received: by 2002:a92:c5cf:: with SMTP id s15mr2217768ilt.62.1630668100795; Fri, 03 Sep 2021 04:21:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1630668100; cv=none; d=google.com; s=arc-20160816; b=yvN5dSe4vcRB2qhIJiobCTaEuDup59kRHqJg2Ns/wR0hh9cQHUqvytHi1W/D4GoVe8 ZZNvWHzF9pi4kTwoRFuFJwiXY5eK4mvt8CKgZA9OF0LoA2VCh4H+VcpVeSSJdkwCqmgo g9y5eRFe8/TAf1E2PvSrlLMAEGwc/FUEcWcHAn8WWG0jTRmnmNM2DBJVTdKjoHlr2557 ELws3sCevQM8OhFbwXMr8BpTlwEISn1D58WIaHFt6+wTdFtIcLaooghr0EU2j8MuMezq /sKA8Ma3/nd+wvPRPNts427xMVI+hB9+oisru/gBbfF9yJlYASR2IvKhR1zcPuPpJ6Xw lX8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=F17HnIrt9/nzW1yaaaZAs2cxj4cXVHJOTDX4ejIvA00=; b=xlu/iPOBaiamfRSzUJC8pvMaMwXQExOdqqf9jsOqlMUshTpcyslKeomHhFdguL8+iH 8a4cGaZ0eXyV4aZW4knhcYdyy9+26q5uN6nyZ0Z8HRi9an7e5he4rwDmx2nxcMyVw9qQ Ns0p9DAOb78URh/+33QsgTcxPsMXdlorQPyfXfK1iFHwOVPqKqm3sFtxjohoDRmW4518 Oa1VgtNMQsUEmaG5OuzD1paSyVx8pINvCDZJhAn954/hXMRDBM/yGfmFrFVw6cIw6Qms ptxzHNozULnv+dkdcP7K/tyhiNUvrk0Wn1crMu4nHtgLocPuXeYK9v35Yyr+ZlHRsNhB 8sPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eRe+qJCF; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:35 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 03/21] soc: qcom: apr: make code more reuseable Date: Fri, 3 Sep 2021 12:20:14 +0100 Message-Id: <20210903112032.25834-4-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org APR and other packet routers like GPR are pretty much same and interact with other drivers in similar way. Ex: GPR ports can be considered as APR services, only difference is they are allocated dynamically. Other difference is packet layout, which should not matter with the apis abstracted. Apart from this the rest of the functionality is pretty much identical across APR and GPR. Make the apr code more reusable by abstracting it service level, rather than device level so that we do not need to write new drivers for other new packet routers like GPR. This patch is in preparation to add GPR support to this driver. Signed-off-by: Srinivas Kandagatla --- drivers/soc/qcom/apr.c | 129 +++++++++++++++++++++-------------- include/linux/soc/qcom/apr.h | 12 +++- 2 files changed, 90 insertions(+), 51 deletions(-) -- 2.21.0 diff --git a/drivers/soc/qcom/apr.c b/drivers/soc/qcom/apr.c index 7abfc8c4fdc7..16990dc96688 100644 --- a/drivers/soc/qcom/apr.c +++ b/drivers/soc/qcom/apr.c @@ -15,13 +15,18 @@ #include #include -struct apr { +enum { + PR_TYPE_APR = 0, +}; + +struct packet_router { struct rpmsg_endpoint *ch; struct device *dev; spinlock_t svcs_lock; spinlock_t rx_lock; struct idr svcs_idr; int dest_domain_id; + int type; struct pdr_handle *pdr; struct workqueue_struct *rxwq; struct work_struct rx_work; @@ -44,21 +49,21 @@ struct apr_rx_buf { */ int apr_send_pkt(struct apr_device *adev, struct apr_pkt *pkt) { - struct apr *apr = dev_get_drvdata(adev->dev.parent); + struct packet_router *apr = dev_get_drvdata(adev->dev.parent); struct apr_hdr *hdr; unsigned long flags; int ret; - spin_lock_irqsave(&adev->lock, flags); + spin_lock_irqsave(&adev->svc.lock, flags); hdr = &pkt->hdr; hdr->src_domain = APR_DOMAIN_APPS; - hdr->src_svc = adev->svc_id; + hdr->src_svc = adev->svc.id; hdr->dest_domain = adev->domain_id; - hdr->dest_svc = adev->svc_id; + hdr->dest_svc = adev->svc.id; ret = rpmsg_trysend(apr->ch, pkt, hdr->pkt_size); - spin_unlock_irqrestore(&adev->lock, flags); + spin_unlock_irqrestore(&adev->svc.lock, flags); return ret ? ret : hdr->pkt_size; } @@ -74,7 +79,7 @@ static void apr_dev_release(struct device *dev) static int apr_callback(struct rpmsg_device *rpdev, void *buf, int len, void *priv, u32 addr) { - struct apr *apr = dev_get_drvdata(&rpdev->dev); + struct packet_router *apr = dev_get_drvdata(&rpdev->dev); struct apr_rx_buf *abuf; unsigned long flags; @@ -100,11 +105,11 @@ static int apr_callback(struct rpmsg_device *rpdev, void *buf, return 0; } - -static int apr_do_rx_callback(struct apr *apr, struct apr_rx_buf *abuf) +static int apr_do_rx_callback(struct packet_router *apr, struct apr_rx_buf *abuf) { uint16_t hdr_size, msg_type, ver, svc_id; - struct apr_device *svc = NULL; + struct pkt_router_svc *svc; + struct apr_device *adev; struct apr_driver *adrv = NULL; struct apr_resp_pkt resp; struct apr_hdr *hdr; @@ -145,12 +150,15 @@ static int apr_do_rx_callback(struct apr *apr, struct apr_rx_buf *abuf) svc_id = hdr->dest_svc; spin_lock_irqsave(&apr->svcs_lock, flags); svc = idr_find(&apr->svcs_idr, svc_id); - if (svc && svc->dev.driver) - adrv = to_apr_driver(svc->dev.driver); + if (svc && svc->dev->driver) { + adev = svc_to_apr_device(svc); + adrv = to_apr_driver(adev->dev.driver); + } spin_unlock_irqrestore(&apr->svcs_lock, flags); - if (!adrv) { - dev_err(apr->dev, "APR: service is not registered\n"); + if (!adrv || !adev) { + dev_err(apr->dev, "APR: service is not registered (%d)\n", + svc_id); return -EINVAL; } @@ -164,20 +172,26 @@ static int apr_do_rx_callback(struct apr *apr, struct apr_rx_buf *abuf) if (resp.payload_size > 0) resp.payload = buf + hdr_size; - adrv->callback(svc, &resp); + adrv->callback(adev, &resp); return 0; } static void apr_rxwq(struct work_struct *work) { - struct apr *apr = container_of(work, struct apr, rx_work); + struct packet_router *apr = container_of(work, struct packet_router, rx_work); struct apr_rx_buf *abuf, *b; unsigned long flags; if (!list_empty(&apr->rx_list)) { list_for_each_entry_safe(abuf, b, &apr->rx_list, node) { - apr_do_rx_callback(apr, abuf); + switch (apr->type) { + case PR_TYPE_APR: + apr_do_rx_callback(apr, abuf); + break; + default: + break; + } spin_lock_irqsave(&apr->rx_lock, flags); list_del(&abuf->node); spin_unlock_irqrestore(&apr->rx_lock, flags); @@ -201,7 +215,7 @@ static int apr_device_match(struct device *dev, struct device_driver *drv) while (id->domain_id != 0 || id->svc_id != 0) { if (id->domain_id == adev->domain_id && - id->svc_id == adev->svc_id) + id->svc_id == adev->svc.id) return 1; id++; } @@ -221,14 +235,14 @@ static int apr_device_remove(struct device *dev) { struct apr_device *adev = to_apr_device(dev); struct apr_driver *adrv; - struct apr *apr = dev_get_drvdata(adev->dev.parent); + struct packet_router *apr = dev_get_drvdata(adev->dev.parent); if (dev->driver) { adrv = to_apr_driver(dev->driver); if (adrv->remove) adrv->remove(adev); spin_lock(&apr->svcs_lock); - idr_remove(&apr->svcs_idr, adev->svc_id); + idr_remove(&apr->svcs_idr, adev->svc.id); spin_unlock(&apr->svcs_lock); } @@ -257,28 +271,39 @@ struct bus_type aprbus = { EXPORT_SYMBOL_GPL(aprbus); static int apr_add_device(struct device *dev, struct device_node *np, - const struct apr_device_id *id) + u32 svc_id, u32 domain_id) { - struct apr *apr = dev_get_drvdata(dev); + struct packet_router *apr = dev_get_drvdata(dev); struct apr_device *adev = NULL; + struct pkt_router_svc *svc; int ret; adev = kzalloc(sizeof(*adev), GFP_KERNEL); if (!adev) return -ENOMEM; - spin_lock_init(&adev->lock); + adev->svc_id = svc_id; + svc = &adev->svc; + + svc->id = svc_id; + svc->pr = apr; + svc->priv = adev; + svc->dev = dev; + spin_lock_init(&svc->lock); + + adev->domain_id = domain_id; - adev->svc_id = id->svc_id; - adev->domain_id = id->domain_id; - adev->version = id->svc_version; if (np) snprintf(adev->name, APR_NAME_SIZE, "%pOFn", np); - else - strscpy(adev->name, id->name, APR_NAME_SIZE); - dev_set_name(&adev->dev, "aprsvc:%s:%x:%x", adev->name, - id->domain_id, id->svc_id); + switch (apr->type) { + case PR_TYPE_APR: + dev_set_name(&adev->dev, "aprsvc:%s:%x:%x", adev->name, + domain_id, svc_id); + break; + default: + break; + } adev->dev.bus = &aprbus; adev->dev.parent = dev; @@ -287,8 +312,7 @@ static int apr_add_device(struct device *dev, struct device_node *np, adev->dev.driver = NULL; spin_lock(&apr->svcs_lock); - idr_alloc(&apr->svcs_idr, adev, id->svc_id, - id->svc_id + 1, GFP_ATOMIC); + idr_alloc(&apr->svcs_idr, svc, svc_id, svc_id + 1, GFP_ATOMIC); spin_unlock(&apr->svcs_lock); of_property_read_string_index(np, "qcom,protection-domain", @@ -308,7 +332,7 @@ static int apr_add_device(struct device *dev, struct device_node *np, static int of_apr_add_pd_lookups(struct device *dev) { const char *service_name, *service_path; - struct apr *apr = dev_get_drvdata(dev); + struct packet_router *apr = dev_get_drvdata(dev); struct device_node *node; struct pdr_service *pds; int ret; @@ -338,13 +362,14 @@ static int of_apr_add_pd_lookups(struct device *dev) static void of_register_apr_devices(struct device *dev, const char *svc_path) { - struct apr *apr = dev_get_drvdata(dev); + struct packet_router *apr = dev_get_drvdata(dev); struct device_node *node; const char *service_path; int ret; for_each_child_of_node(dev->of_node, node) { - struct apr_device_id id = { {0} }; + u32 svc_id; + u32 domain_id; /* * This function is called with svc_path NULL during @@ -374,13 +399,13 @@ static void of_register_apr_devices(struct device *dev, const char *svc_path) continue; } - if (of_property_read_u32(node, "reg", &id.svc_id)) + if (of_property_read_u32(node, "reg", &svc_id)) continue; - id.domain_id = apr->dest_domain_id; + domain_id = apr->dest_domain_id; - if (apr_add_device(dev, node, &id)) - dev_err(dev, "Failed to add apr %d svc\n", id.svc_id); + if (apr_add_device(dev, node, svc_id, domain_id)) + dev_err(dev, "Failed to add apr %d svc\n", svc_id); } } @@ -400,7 +425,7 @@ static int apr_remove_device(struct device *dev, void *svc_path) static void apr_pd_status(int state, char *svc_path, void *priv) { - struct apr *apr = (struct apr *)priv; + struct packet_router *apr = (struct packet_router *)priv; switch (state) { case SERVREG_SERVICE_STATE_UP: @@ -415,16 +440,20 @@ static void apr_pd_status(int state, char *svc_path, void *priv) static int apr_probe(struct rpmsg_device *rpdev) { struct device *dev = &rpdev->dev; - struct apr *apr; + struct packet_router *apr; int ret; apr = devm_kzalloc(dev, sizeof(*apr), GFP_KERNEL); if (!apr) return -ENOMEM; - ret = of_property_read_u32(dev->of_node, "qcom,apr-domain", &apr->dest_domain_id); + ret = of_property_read_u32(dev->of_node, "qcom,domain", &apr->dest_domain_id); + if (ret) /* try deprecated apr-domain property */ + ret = of_property_read_u32(dev->of_node, "qcom,apr-domain", + &apr->dest_domain_id); + apr->type = PR_TYPE_APR; if (ret) { - dev_err(dev, "APR Domain ID not specified in DT\n"); + dev_err(dev, "Domain ID not specified in DT\n"); return ret; } @@ -467,7 +496,7 @@ static int apr_probe(struct rpmsg_device *rpdev) static void apr_remove(struct rpmsg_device *rpdev) { - struct apr *apr = dev_get_drvdata(&rpdev->dev); + struct packet_router *apr = dev_get_drvdata(&rpdev->dev); pdr_handle_release(apr->pdr); device_for_each_child(&rpdev->dev, NULL, apr_remove_device); @@ -504,20 +533,20 @@ void apr_driver_unregister(struct apr_driver *drv) } EXPORT_SYMBOL_GPL(apr_driver_unregister); -static const struct of_device_id apr_of_match[] = { +static const struct of_device_id pkt_router_of_match[] = { { .compatible = "qcom,apr"}, { .compatible = "qcom,apr-v2"}, {} }; -MODULE_DEVICE_TABLE(of, apr_of_match); +MODULE_DEVICE_TABLE(of, pkt_router_of_match); -static struct rpmsg_driver apr_driver = { +static struct rpmsg_driver packet_router_driver = { .probe = apr_probe, .remove = apr_remove, .callback = apr_callback, .drv = { .name = "qcom,apr", - .of_match_table = apr_of_match, + .of_match_table = pkt_router_of_match, }, }; @@ -527,7 +556,7 @@ static int __init apr_init(void) ret = bus_register(&aprbus); if (!ret) - ret = register_rpmsg_driver(&apr_driver); + ret = register_rpmsg_driver(&packet_router_driver); else bus_unregister(&aprbus); @@ -537,7 +566,7 @@ static int __init apr_init(void) static void __exit apr_exit(void) { bus_unregister(&aprbus); - unregister_rpmsg_driver(&apr_driver); + unregister_rpmsg_driver(&packet_router_driver); } subsys_initcall(apr_init); diff --git a/include/linux/soc/qcom/apr.h b/include/linux/soc/qcom/apr.h index 137f9f2ac4c3..7bca213a3f83 100644 --- a/include/linux/soc/qcom/apr.h +++ b/include/linux/soc/qcom/apr.h @@ -79,6 +79,15 @@ struct apr_resp_pkt { #define APR_SVC_MAJOR_VERSION(v) ((v >> 16) & 0xFF) #define APR_SVC_MINOR_VERSION(v) (v & 0xFF) +struct packet_router; +struct pkt_router_svc { + struct device *dev; + struct packet_router *pr; + spinlock_t lock; + int id; + void *priv; +}; + struct apr_device { struct device dev; uint16_t svc_id; @@ -86,11 +95,12 @@ struct apr_device { uint32_t version; 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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:36 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 04/21] soc: dt-bindings: qcom: add gpr bindings Date: Fri, 3 Sep 2021 12:20:15 +0100 Message-Id: <20210903112032.25834-5-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Qualcomm Generic Packet router aka GPR is the IPC mechanism found in AudioReach next generation signal processing framework to perform command and response messages between various processors. GPR has concepts of static and dynamic port, all static services like APM (Audio Processing Manager), PRM (Proxy resource manager) have fixed port numbers where as dynamic services like graphs have dynamic port numbers which are allocated at runtime. All GPR packet messages will have source and destination domain and port along with opcode and payload. This support is added using existing APR driver to reuse most of the code. Signed-off-by: Srinivas Kandagatla --- .../bindings/soc/qcom/qcom,apr.yaml | 41 +++++++++++++++---- include/dt-bindings/soc/qcom,gpr.h | 18 ++++++++ 2 files changed, 52 insertions(+), 7 deletions(-) create mode 100644 include/dt-bindings/soc/qcom,gpr.h -- 2.21.0 diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml index 922c8567c134..14d75f6a556e 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml @@ -4,20 +4,21 @@ $id: "http://devicetree.org/schemas/soc/qcom/qcom,apr.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: Qualcomm APR (Asynchronous Packet Router) binding +title: Qualcomm APR/GPR (Asynchronous/Generic Packet Router) binding maintainers: - Srinivas Kandagatla description: | - This binding describes the Qualcomm APR, APR is a IPC protocol for - communication between Application processor and QDSP. APR is mainly + This binding describes the Qualcomm APR/GPR, APR/GPR is a IPC protocol for + communication between Application processor and QDSP. APR/GPR is mainly used for audio/voice services on the QDSP. properties: compatible: enum: - qcom,apr-v2 + - qcom,gpr qcom,apr-domain: $ref: /schemas/types.yaml#/definitions/uint32 @@ -45,6 +46,10 @@ properties: 5 = Application processor Domain 6 = Modem2 Domain 7 = Application Processor2 Domain + Selects the processor domain for gpr + 1 = Modem Domain + 2 = Audio DSP Domain + 3 = Application Processor Domain '#address-cells': const: 1 @@ -52,12 +57,12 @@ properties: '#size-cells': const: 0 -#APR Services +#APR/GPR Services patternProperties: - "^service@[3-9a-d]$": + "^service@[1-9a-d]$": type: object description: - APR node's client devices use subnodes for desired static port services. + APR/GPR node's client devices use subnodes for desired static port services. properties: compatible: @@ -66,9 +71,11 @@ patternProperties: - qcom,q6asm - qcom,q6afe - qcom,q6adm + - qcom,q6apm + - qcom,q6prm reg: - enum: [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13] + enum: [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13] description: APR Service ID 3 = DSP Core Service @@ -82,6 +89,11 @@ patternProperties: 11 = Core voice processor. 12 = Ultrasound stream manager. 13 = Listen stream manager. + GPR Service ID + 1 = Audio Process Manager Service + 2 = Proxy Resource Manager Service. + 3 = AMDB Service. + 4 = Voice processing manager. qcom,protection-domain: $ref: /schemas/types.yaml#/definitions/string-array @@ -140,3 +152,18 @@ examples: qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; }; }; + + - | + #include + gpr { + compatible = "qcom,gpr"; + qcom,domain = ; + #address-cells = <1>; + #size-cells = <0>; + + service@1 { + compatible = "qcom,q6apm"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + }; + }; diff --git a/include/dt-bindings/soc/qcom,gpr.h b/include/dt-bindings/soc/qcom,gpr.h new file mode 100644 index 000000000000..1c68906e079c --- /dev/null +++ b/include/dt-bindings/soc/qcom,gpr.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_QCOM_GPR_H +#define __DT_BINDINGS_QCOM_GPR_H + +/* DOMAINS */ + +#define GPR_DOMAIN_ID_MODEM 1 +#define GPR_DOMAIN_ID_ADSP 2 +#define GPR_DOMAIN_ID_APPS 3 + +/* Static Services */ + +#define GPR_APM_MODULE_IID 1 +#define GPR_PRM_MODULE_IID 2 +#define GPR_AMDB_MODULE_IID 3 +#define GPR_VCPM_MODULE_IID 4 + +#endif /* __DT_BINDINGS_QCOM_GPR_H */ From patchwork Fri Sep 3 11:20:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 506509 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp906445jai; Fri, 3 Sep 2021 04:21:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx72v+eml0YJo0GkYamyDcuMeVIEWTPqCnxqKfCpf3mPgrVnqyLlUINRCaIsj6rH696czKq X-Received: by 2002:a05:6e02:1522:: with SMTP id i2mr2253349ilu.208.1630668101547; Fri, 03 Sep 2021 04:21:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1630668101; cv=none; d=google.com; s=arc-20160816; b=vvKzceb//1jSxuprVvNdAQPNS6pGMbIAHvFtTUVdzi/TR335RQJ9lPzt+tcPDk85cD 1yU04fhx4DgcbuO2oPP/TsMTH3ELMQsh9clYZ1avANeCRBWr/emmwg/sRmOsaBy2aUdb PzhSLD7RnodSvvBm3VW63rB8nmPBC5kn+r0L7a6/Py1ZePX/jsfhhjL4WMG2YBg5X6uI yNTP8Z8uNXMLR+7jh9EMXBLuaiPV8FRlttBa+LtGRYnbQ3jaDTBHPl7rrq0GEag3AoaZ nay4KHx4Ww06OOZuxxJShGwddRakmEUs3zSY3K/B9G+mEq1hjqu/Vk/jstkKpzEgkeFi Owfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=OFfdu/uODk0jypkXS1Nm9oV0W5uq3YCcN5TeP0tadKo=; b=nEAWwirkztGhjOKyc9UUujF262xertjFait1n+nWmMg+YT3e3cGxWJ+J1w3nxuR3b9 RWqjKNdSKHUelOuntYLPI1kp0z3qtX0TT1NTDRU4tL5DKwBsN/pgl8fZ+Msifo1M3aHA i9VAYONOYXzCWIwpcobzBdBqVWI7jw+PVP7EbEpkNKqUXO3uKeTqmuf2TOY4Pq9aIdj4 l7wo1sLo7qmiEkubMy1/woHAxhsEsGxKf+kjiWHQG7lh+rhP30Jb0IEvoPiZDQqOOkPi bByvlHc8ZFd3fvwI0zOEnXRwz9yY6BMvMQK3d/2901ON7KUh4T21ZL9P2c2SBztAPj19 xuiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cLZbS6Zy; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:37 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 05/21] soc: qcom: apr: Add GPR support Date: Fri, 3 Sep 2021 12:20:16 +0100 Message-Id: <20210903112032.25834-6-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Qualcomm Generic Packet router aka GPR is the IPC mechanism found in AudioReach next generation signal processing framework to perform command and response messages between various processors. GPR has concepts of static and dynamic port, all static services like APM (Audio Processing Manager), PRM (Proxy resource manager) have fixed port numbers where as dynamic services like graphs have dynamic port numbers which are allocated at runtime. All GPR packet messages will have source and destination domain and port along with opcode and payload. Signed-off-by: Srinivas Kandagatla --- drivers/soc/qcom/Kconfig | 8 ++ drivers/soc/qcom/apr.c | 168 +++++++++++++++++++++++++++++++++-- include/linux/soc/qcom/apr.h | 58 ++++++++++++ 3 files changed, 228 insertions(+), 6 deletions(-) -- 2.21.0 Reported-by: kernel test robot Reported-by: kernel test robot diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 79b568f82a1c..0b6e6412c98e 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -209,4 +209,12 @@ config QCOM_APR application processor and QDSP6. APR is used by audio driver to configure QDSP6 ASM, ADM and AFE modules. + +config QCOM_GPR + tristate "Qualcomm GPR Bus (Generic Packet Router)" + select QCOM_APR + help + Enable GPR IPC protocol support between + application processor and QDSP6. GPR is + used by audio driver to configure QDSP6. endmenu diff --git a/drivers/soc/qcom/apr.c b/drivers/soc/qcom/apr.c index 16990dc96688..1e46690e9fc7 100644 --- a/drivers/soc/qcom/apr.c +++ b/drivers/soc/qcom/apr.c @@ -17,8 +17,13 @@ enum { PR_TYPE_APR = 0, + PR_TYPE_GPR, }; +/* Some random values tbh which does not collide with static modules */ +#define GPR_DYNAMIC_PORT_START 0x10000000 +#define GPR_DYNAMIC_PORT_END 0x20000000 + struct packet_router { struct rpmsg_endpoint *ch; struct device *dev; @@ -69,6 +74,85 @@ int apr_send_pkt(struct apr_device *adev, struct apr_pkt *pkt) } EXPORT_SYMBOL_GPL(apr_send_pkt); +void gpr_free_port(gpr_port_t *port) +{ + struct packet_router *gpr = port->pr; + unsigned long flags; + + spin_lock_irqsave(&gpr->svcs_lock, flags); + idr_remove(&gpr->svcs_idr, port->id); + spin_unlock_irqrestore(&gpr->svcs_lock, flags); + + kfree(port); +} +EXPORT_SYMBOL_GPL(gpr_free_port); + +gpr_port_t *gpr_alloc_port(struct apr_device *gdev, struct device *dev, + gpr_port_cb cb, void *priv) +{ + struct packet_router *pr = dev_get_drvdata(gdev->dev.parent); + gpr_port_t *port; + struct pkt_router_svc *svc; + int id; + + port = kzalloc(sizeof(*port), GFP_KERNEL); + if (!port) + return ERR_PTR(-ENOMEM); + + svc = port; + svc->callback = cb; + svc->pr = pr; + svc->priv = priv; + svc->dev = dev; + spin_lock_init(&svc->lock); + + spin_lock(&pr->svcs_lock); + id = idr_alloc_cyclic(&pr->svcs_idr, svc, GPR_DYNAMIC_PORT_START, + GPR_DYNAMIC_PORT_END, GFP_ATOMIC); + if (id < 0) { + dev_err(dev, "Unable to allocate dynamic GPR src port\n"); + kfree(port); + spin_unlock(&pr->svcs_lock); + return ERR_PTR(-ENOMEM); + } + + svc->id = id; + spin_unlock(&pr->svcs_lock); + + dev_info(dev, "Adding GPR src port (%x)\n", svc->id); + + return port; +} +EXPORT_SYMBOL_GPL(gpr_alloc_port); + +static int pkt_router_send_svc_pkt(struct pkt_router_svc *svc, struct gpr_pkt *pkt) +{ + struct packet_router *pr = svc->pr; + struct gpr_hdr *hdr; + unsigned long flags; + int ret; + + hdr = &pkt->hdr; + + spin_lock_irqsave(&svc->lock, flags); + ret = rpmsg_trysend(pr->ch, pkt, hdr->pkt_size); + spin_unlock_irqrestore(&svc->lock, flags); + + return ret ? ret : hdr->pkt_size; +} + +int gpr_send_pkt(struct apr_device *gdev, struct gpr_pkt *pkt) +{ + return pkt_router_send_svc_pkt(&gdev->svc, pkt); +} +EXPORT_SYMBOL_GPL(gpr_send_pkt); + +int gpr_send_port_pkt(gpr_port_t *port, struct gpr_pkt *pkt) +{ + return pkt_router_send_svc_pkt(port, pkt); +} +EXPORT_SYMBOL_GPL(gpr_send_port_pkt); + static void apr_dev_release(struct device *dev) { struct apr_device *adev = to_apr_device(dev); @@ -177,6 +261,59 @@ static int apr_do_rx_callback(struct packet_router *apr, struct apr_rx_buf *abuf return 0; } +static int gpr_do_rx_callback(struct packet_router *gpr, struct apr_rx_buf *abuf) +{ + uint16_t hdr_size, ver; + struct pkt_router_svc *svc = NULL; + struct gpr_resp_pkt resp; + struct gpr_hdr *hdr; + unsigned long flags; + void *buf = abuf->buf; + int len = abuf->len; + + hdr = buf; + ver = hdr->version; + if (ver > GPR_PKT_VER + 1) + return -EINVAL; + + hdr_size = hdr->hdr_size; + if (hdr_size < GPR_PKT_HEADER_WORD_SIZE) { + dev_err(gpr->dev, "GPR: Wrong hdr size:%d\n", hdr_size); + return -EINVAL; + } + + if (hdr->pkt_size < GPR_PKT_HEADER_BYTE_SIZE || hdr->pkt_size != len) { + dev_err(gpr->dev, "GPR: Wrong packet size\n"); + return -EINVAL; + } + + resp.hdr = *hdr; + resp.payload_size = hdr->pkt_size - (hdr_size * 4); + + /* + * NOTE: hdr_size is not same as GPR_HDR_SIZE as remote can include + * optional headers in to gpr_hdr which should be ignored + */ + if (resp.payload_size > 0) + resp.payload = buf + (hdr_size * 4); + + + spin_lock_irqsave(&gpr->svcs_lock, flags); + svc = idr_find(&gpr->svcs_idr, hdr->dest_port); + spin_unlock_irqrestore(&gpr->svcs_lock, flags); + + if (!svc) { + dev_err(gpr->dev, "GPR: Port(%x) is not registered\n", + hdr->dest_port); + return -EINVAL; + } + + if (svc->callback) + svc->callback(&resp, svc->priv, 0); + + return 0; +} + static void apr_rxwq(struct work_struct *work) { struct packet_router *apr = container_of(work, struct packet_router, rx_work); @@ -189,6 +326,9 @@ static void apr_rxwq(struct work_struct *work) case PR_TYPE_APR: apr_do_rx_callback(apr, abuf); break; + case PR_TYPE_GPR: + gpr_do_rx_callback(apr, abuf); + break; default: break; } @@ -227,8 +367,13 @@ static int apr_device_probe(struct device *dev) { struct apr_device *adev = to_apr_device(dev); struct apr_driver *adrv = to_apr_driver(dev->driver); + int ret; - return adrv->probe(adev); + ret = adrv->probe(adev); + if (!ret) + adev->svc.callback = adrv->gpr_callback; + + return ret; } static int apr_device_remove(struct device *dev) @@ -301,6 +446,10 @@ static int apr_add_device(struct device *dev, struct device_node *np, dev_set_name(&adev->dev, "aprsvc:%s:%x:%x", adev->name, domain_id, svc_id); break; + case PR_TYPE_GPR: + dev_set_name(&adev->dev, "gprsvc:%s:%x:%x", adev->name, + domain_id, svc_id); + break; default: break; } @@ -318,7 +467,7 @@ static int apr_add_device(struct device *dev, struct device_node *np, of_property_read_string_index(np, "qcom,protection-domain", 1, &adev->service_path); - dev_info(dev, "Adding APR dev: %s\n", dev_name(&adev->dev)); + dev_info(dev, "Adding APR/GPR dev: %s\n", dev_name(&adev->dev)); ret = device_register(&adev->dev); if (ret) { @@ -448,10 +597,16 @@ static int apr_probe(struct rpmsg_device *rpdev) return -ENOMEM; ret = of_property_read_u32(dev->of_node, "qcom,domain", &apr->dest_domain_id); - if (ret) /* try deprecated apr-domain property */ - ret = of_property_read_u32(dev->of_node, "qcom,apr-domain", - &apr->dest_domain_id); - apr->type = PR_TYPE_APR; + + if (of_device_is_compatible(dev->of_node, "qcom,gpr")) { + apr->type = PR_TYPE_GPR; + } else { + if (ret) /* try deprecated apr-domain property */ + ret = of_property_read_u32(dev->of_node, "qcom,apr-domain", + &apr->dest_domain_id); + apr->type = PR_TYPE_APR; + } + if (ret) { dev_err(dev, "Domain ID not specified in DT\n"); return ret; @@ -536,6 +691,7 @@ EXPORT_SYMBOL_GPL(apr_driver_unregister); static const struct of_device_id pkt_router_of_match[] = { { .compatible = "qcom,apr"}, { .compatible = "qcom,apr-v2"}, + { .compatible = "qcom,gpr"}, {} }; MODULE_DEVICE_TABLE(of, pkt_router_of_match); diff --git a/include/linux/soc/qcom/apr.h b/include/linux/soc/qcom/apr.h index 7bca213a3f83..a45373260128 100644 --- a/include/linux/soc/qcom/apr.h +++ b/include/linux/soc/qcom/apr.h @@ -7,6 +7,7 @@ #include #include #include +#include extern struct bus_type aprbus; @@ -75,19 +76,65 @@ struct apr_resp_pkt { int payload_size; }; +struct gpr_hdr { + uint32_t version:4; + uint32_t hdr_size:4; + uint32_t pkt_size:24; + uint32_t dest_domain:8; + uint32_t src_domain:8; + uint32_t reserved:16; + uint32_t src_port; + uint32_t dest_port; + uint32_t token; + uint32_t opcode; +} __packed; + +struct gpr_pkt { + struct gpr_hdr hdr; + uint32_t payload[0]; +}; + +struct gpr_resp_pkt { + struct gpr_hdr hdr; + void *payload; + int payload_size; +}; + +#define GPR_HDR_SIZE sizeof(struct gpr_hdr) +#define GPR_PKT_VER 0x0 +#define GPR_PKT_HEADER_WORD_SIZE ((sizeof(struct gpr_pkt) + 3) >> 2) +#define GPR_PKT_HEADER_BYTE_SIZE (GPR_PKT_HEADER_WORD_SIZE << 2) + +#define GPR_BASIC_RSP_RESULT 0x02001005 + +struct gpr_ibasic_rsp_result_t { + uint32_t opcode; + uint32_t status; +}; + +#define GPR_BASIC_EVT_ACCEPTED 0x02001006 + +struct gpr_ibasic_rsp_accepted_t { + uint32_t opcode; +}; + /* Bits 0 to 15 -- Minor version, Bits 16 to 31 -- Major version */ #define APR_SVC_MAJOR_VERSION(v) ((v >> 16) & 0xFF) #define APR_SVC_MINOR_VERSION(v) (v & 0xFF) +typedef int (*gpr_port_cb) (struct gpr_resp_pkt *d, void *priv, int op); struct packet_router; struct pkt_router_svc { struct device *dev; + gpr_port_cb callback; struct packet_router *pr; spinlock_t lock; int id; void *priv; }; +typedef struct pkt_router_svc gpr_port_t; + struct apr_device { struct device dev; uint16_t svc_id; @@ -99,6 +146,8 @@ struct apr_device { struct list_head node; }; +typedef struct apr_device gpr_device_t; + #define to_apr_device(d) container_of(d, struct apr_device, dev) #define svc_to_apr_device(d) container_of(d, struct apr_device, svc) @@ -107,10 +156,12 @@ struct apr_driver { int (*remove)(struct apr_device *sl); int (*callback)(struct apr_device *a, struct apr_resp_pkt *d); + int (*gpr_callback)(struct gpr_resp_pkt *d, void *data, int op); struct device_driver driver; const struct apr_device_id *id_table; }; +typedef struct apr_driver gpr_driver_t; #define to_apr_driver(d) container_of(d, struct apr_driver, driver) /* @@ -133,7 +184,14 @@ void apr_driver_unregister(struct apr_driver *drv); #define module_apr_driver(__apr_driver) \ module_driver(__apr_driver, apr_driver_register, \ apr_driver_unregister) +#define module_gpr_driver(__gpr_driver) module_apr_driver(__gpr_driver) int apr_send_pkt(struct apr_device *adev, struct apr_pkt *pkt); +gpr_port_t *gpr_alloc_port(gpr_device_t *gdev, struct device *dev, + gpr_port_cb cb, void *priv); +void gpr_free_port(gpr_port_t *port); +int gpr_send_port_pkt(gpr_port_t *port, struct gpr_pkt *pkt); +int gpr_send_pkt(gpr_device_t *gdev, struct gpr_pkt *pkt); + #endif /* __QCOM_APR_H_ */ From patchwork Fri Sep 3 11:20:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 506510 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp906464jai; Fri, 3 Sep 2021 04:21:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw5J9czMuzdaMWHV/nuKGF/0r2Nzi0UK6s0SorWqjxbPBC+7qTgaKOFrRxSEA/PK4qBPULP X-Received: by 2002:a5d:9c53:: with SMTP id 19mr2716483iof.192.1630668102652; Fri, 03 Sep 2021 04:21:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1630668102; cv=none; d=google.com; s=arc-20160816; b=vWPvORHsfAmV+aAfuSkalu4o9t7oQKZu7na70bHafG8XjEOINk8ptXALorhruwAwoT y1jytg7hK1x8hRjJ3QN1zApr9acAQKVQTXccTkHAXgsxp1cXdflWzErufbvUp2HMH1ag YWkWBFCAOXGN6UyaTwWaVjj4swtb5g4pKVixihXnTuhBrUSo6eb8XkLgVQmV4EbfZpkR oWhIvD0HKTLZKv6K3I0/4OSbvJWkauGNevH69tI5gxDIjqLt+q3FxyITXJn0L19Wk8rc OJnsiw0SRuvf4IkjZTTb8oWSoBPHmGF1MEauoTlO+9LjrInl78e0wCGAK0ZpsCra1a7u baOQ== ARC-Message-Signature: i=1; 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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:39 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 06/21] ASoC: dt-bindings: move LPASS dai related bindings out of q6afe Date: Fri, 3 Sep 2021 12:20:17 +0100 Message-Id: <20210903112032.25834-7-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org q6afe (Audio Front End) is one of the DSP service that handles both LPASS (Low Power Audio SubSystem) Audio ports and LPASS clocks. As LPASS is a hardwware IP and commonly used by Qualcomm Audio DSP. In order to allow multiple DSP frameworks to use these bindings its best to move it out from the dsp specific bindings. For compatibility reasons and not breaking which is already working we still maintain same compatible string "qcom,q6afe-dais" Also as part of this change convert these LPASS dai related bindings into yaml format. Signed-off-by: Srinivas Kandagatla --- .../devicetree/bindings/sound/qcom,q6afe.txt | 158 ---------------- .../sound/qcom,q6dsp-lpass-ports.yaml | 178 ++++++++++++++++++ 2 files changed, 178 insertions(+), 158 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml -- 2.21.0 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/sound/qcom,q6afe.txt b/Documentation/devicetree/bindings/sound/qcom,q6afe.txt index 2d6fb2ea75a0..fcf81058504c 100644 --- a/Documentation/devicetree/bindings/sound/qcom,q6afe.txt +++ b/Documentation/devicetree/bindings/sound/qcom,q6afe.txt @@ -12,92 +12,6 @@ used by all apr services. Must contain the following properties. from DSP. example "qcom,q6afe" -= AFE DAIs (Digial Audio Interface) -"dais" subnode of the AFE node. It represents afe dais, each afe dai is a -subnode of "dais" representing board specific dai setup. -"dais" node should have following properties followed by dai children. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,q6afe-dais" - -- #sound-dai-cells - Usage: required - Value type: - Definition: Must be 1 - -- #address-cells - Usage: required - Value type: - Definition: Must be 1 - -- #size-cells - Usage: required - Value type: - Definition: Must be 0 - -== AFE DAI is subnode of "dais" and represent a dai, it includes board specific -configuration of each dai. Must contain the following properties. - -- reg - Usage: required - Value type: - Definition: Must be dai id - -- qcom,sd-lines - Usage: required for mi2s interface - Value type: - Definition: Must be list of serial data lines used by this dai. - should be one or more of the 0-3 sd lines. - - - qcom,tdm-sync-mode: - Usage: required for tdm interface - Value type: - Definition: Synchronization mode. - 0 - Short sync bit mode - 1 - Long sync mode - 2 - Short sync slot mode - - - qcom,tdm-sync-src: - Usage: required for tdm interface - Value type: - Definition: Synchronization source. - 0 - External source - 1 - Internal source - - - qcom,tdm-data-out: - Usage: required for tdm interface - Value type: - Definition: Data out signal to drive with other masters. - 0 - Disable - 1 - Enable - - - qcom,tdm-invert-sync: - Usage: required for tdm interface - Value type: - Definition: Invert the sync. - 0 - Normal - 1 - Invert - - - qcom,tdm-data-delay: - Usage: required for tdm interface - Value type: - Definition: Number of bit clock to delay data - with respect to sync edge. - 0 - 0 bit clock cycle - 1 - 1 bit clock cycle - 2 - 2 bit clock cycle - - - qcom,tdm-data-align: - Usage: required for tdm interface - Value type: - Definition: Indicate how data is packed - within the slot. For example, 32 slot width in case of - sample bit width is 24. - 0 - MSB - 1 - LSB - = AFE CLOCKSS "clocks" subnode of the AFE node. It represents q6afe clocks "clocks" node should have following properties. @@ -122,78 +36,6 @@ apr-service@4 { compatible = "qcom,q6afe"; reg = ; - dais { - compatible = "qcom,q6afe-dais"; - #sound-dai-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - dai@1 { - reg = ; - }; - - dai@24 { - reg = ; - qcom,tdm-sync-mode = <1>: - qcom,tdm-sync-src = <1>; - qcom,tdm-data-out = <0>; - qcom,tdm-invert-sync = <1>; - qcom,tdm-data-delay = <1>; - qcom,tdm-data-align = <0>; - - }; - - dai@25 { - reg = ; - qcom,tdm-sync-mode = <1>: - qcom,tdm-sync-src = <1>; - qcom,tdm-data-out = <0>; - qcom,tdm-invert-sync = <1>; - qcom,tdm-data-delay <1>: - qcom,tdm-data-align = <0>; - }; - - dai@16 { - reg = ; - qcom,sd-lines = <0 2>; - }; - - dai@17 { - reg = ; - qcom,sd-lines = <1>; - }; - - dai@18 { - reg = ; - qcom,sd-lines = <0 3>; - }; - - dai@19 { - reg = ; - qcom,sd-lines = <1>; - }; - - dai@20 { - reg = ; - qcom,sd-lines = <1 3>; - }; - - dai@21 { - reg = ; - qcom,sd-lines = <0>; - }; - - dai@22 { - reg = ; - qcom,sd-lines = <0>; - }; - - dai@23 { - reg = ; - qcom,sd-lines = <1>; - }; - }; - clocks { compatible = "qcom,q6afe-clocks"; #clock-cells = <2>; diff --git a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml new file mode 100644 index 000000000000..e6148c17419b --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/sound/qcom,q6dsp-lpass-ports.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm DSP LPASS(Low Power Audio SubSystem) Audio Ports binding + +maintainers: + - Srinivas Kandagatla + +description: | + This binding describes the Qualcomm DSP LPASS Audio ports + +properties: + compatible: + enum: + - qcom,q6afe-dais + + reg: + maxItems: 1 + + '#sound-dai-cells': + const: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +#Digital Audio Interfaces +patternProperties: + '^dai@[0-9]+$': + type: object + description: + Q6DSP Digital Audio Interfaces. + + properties: + reg: + description: + Digital Audio Interface ID + + qcom,sd-lines: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + List of serial data lines used by this dai.should be one or more of the 0-3 sd lines. + minItems: 1 + maxItems: 4 + uniqueItems: true + items: + minimum: 0 + maximum: 3 + + qcom,tdm-sync-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + description: + TDM Synchronization mode + 0 = Short sync bit mode + 1 = Long sync mode + 2 = Short sync slot mode + + qcom,tdm-sync-src: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + TDM Synchronization source + 0 = External source + 1 = Internal source + + qcom,tdm-data-out: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + TDM Data out signal to drive with other masters + 0 = Disable + 1 = Enable + + qcom,tdm-invert-sync: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + TDM Invert the sync + 0 = Normal + 1 = Invert + + qcom,tdm-data-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + description: + TDM Number of bit clock to delay data + 0 = 0 bit clock cycle + 1 = 1 bit clock cycle + 2 = 2 bit clock cycle + + qcom,tdm-data-align: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + Indicate how data is packed within the slot. For example, 32 slot + width in case of sample bit width is 24TDM Invert the sync. + 0 = MSB + 1 = LSB + + required: + - reg + + allOf: + - if: + properties: + reg: + contains: + # TDM DAI ID range from PRIMARY_TDM_RX_0 - QUINARY_TDM_TX_7 + items: + minimum: 24 + maximum: 103 + then: + required: + - qcom,tdm-sync-mode + - qcom,tdm-sync-src + - qcom,tdm-data-out + - qcom,tdm-invert-sync + - qcom,tdm-data-delay + - qcom,tdm-data-align + + - if: + properties: + reg: + contains: + # MI2S DAI ID range PRIMARY_MI2S_RX - QUATERNARY_MI2S_TX and + # QUINARY_MI2S_RX - QUINARY_MI2S_TX + items: + oneOf: + - minimum: 16 + maximum: 23 + - minimum: 127 + maximum: 128 + then: + required: + - qcom,sd-lines + + additionalProperties: false + +required: + - compatible + - reg + - "#sound-dai-cells" + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include + #include + apr { + #address-cells = <1>; + #size-cells = <0>; + apr-service@4 { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + q6afedai@1 { + compatible = "qcom,q6afe-dais"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + + dai@22 { + reg = ; + qcom,sd-lines = <0 1 2 3>; + }; + }; + }; + }; From patchwork Fri Sep 3 11:20:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 506511 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp906483jai; Fri, 3 Sep 2021 04:21:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwEvnf86KMY8/dpeoajyPO9lK1sFbQO4QvElWoUCGMF6rUKS/v3XhEYqwknGJj7bToPmTSH X-Received: by 2002:a6b:7519:: with SMTP id l25mr2470074ioh.169.1630668103718; Fri, 03 Sep 2021 04:21:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1630668103; cv=none; d=google.com; s=arc-20160816; b=HqFT6h8nv9/lboJ0k41haDaMgvKd2b6hif220DqI56LioQtlry/PyGU9RYehZOwgxD mIhDNJjwpaz/X0MbtDuSpUmPYtDRf2YuKbS6qQmZzjoc9l6CWtSeDdtcREoKt7kiJ+FG rNc8bi/vKK4HFEwt8//8kF1/VfrJxbHvpkQWsr+dbOzV14r51QOUcG/3EOFOHAmMXANo 0mP6dWWFIE5A28YnFcEwrJtdZ4hLgEEEBhx+1FlD9E42SQUuFtsq4JFb6A8g2ubvbyWg a+Jg6rolhudJGsTEzdKcs96EZZuAquofJ8t13AUuF21sH5jSsEhKietyWLLuQacGn7QE uSBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=d5Vm8czTL3+cyI2rjmlcRETsvgdq2hCBoaTdt0tcxRk=; b=CLtoPr3Ebr9kexkZrADnPgrmeqrlS2IBqxcKgSqSWDOloWxD4XVqMq6GQVIp/o453W 8JPbPJuoFLYu3C5aTQwyvGu0aRWv/YeVSiLn5NmugcGYl/59DCsNA8PtC9QG6ppDeMmJ uQKu9HaoPgHRkYgGbWiOgv2vn70TzdAZVG/LmQNaT78oB455RgWZNK4N1RgXV6f4Tp6B aWp9mGVUF/vCC+oZHLOZShl6FehN1mMG4VbH7zXmQRgMTW9iKAQWjPxTWAFCMqUapD5I utRforKtkzuIU1iJWzNWmqd0XpqYVUQsjLEVgVuEWfaN9bc0uFM23DTzvdZMykbZepg5 abBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ltqb+2DW; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:40 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 07/21] ASoC: dt-bindings: move LPASS clocks related bindings out of q6afe Date: Fri, 3 Sep 2021 12:20:18 +0100 Message-Id: <20210903112032.25834-8-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org q6afe (Audio Front End) is one of the DSP service that handles both LPASS (Low Power Audio SubSystem) Audio ports and LPASS clocks. As LPASS is a hardwware IP and commonly used by Qualcomm Audio DSP. In order to allow multiple DSP frameworks to use these bindings its best to move it out from the dsp specific bindings. For compatibility reasons and not breaking which is already working we still maintain same compatible string "qcom,q6afe-clocks" Also as part of this change convert these LPASS clocks related bindings into yaml format. Signed-off-by: Srinivas Kandagatla Reviewed-by: Rob Herring --- .../devicetree/bindings/sound/qcom,q6afe.txt | 23 -------- .../sound/qcom,q6dsp-lpass-clocks.yaml | 56 +++++++++++++++++++ 2 files changed, 56 insertions(+), 23 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml -- 2.21.0 diff --git a/Documentation/devicetree/bindings/sound/qcom,q6afe.txt b/Documentation/devicetree/bindings/sound/qcom,q6afe.txt index fcf81058504c..bc6b5f1fe4f1 100644 --- a/Documentation/devicetree/bindings/sound/qcom,q6afe.txt +++ b/Documentation/devicetree/bindings/sound/qcom,q6afe.txt @@ -12,32 +12,9 @@ used by all apr services. Must contain the following properties. from DSP. example "qcom,q6afe" -= AFE CLOCKSS -"clocks" subnode of the AFE node. It represents q6afe clocks -"clocks" node should have following properties. -- compatible: - Usage: required - Value type: - Definition: must be "qcom,q6afe-clocks" - -- #clock-cells: - Usage: required - Value type: - Definition: Must be 2. Clock Id followed by - below valid clock coupling attributes. - 1 - for no coupled clock - 2 - for dividend of the coupled clock - 3 - for divisor of the coupled clock - 4 - for inverted and no couple clock - = EXAMPLE apr-service@4 { compatible = "qcom,q6afe"; reg = ; - - clocks { - compatible = "qcom,q6afe-clocks"; - #clock-cells = <2>; - }; }; diff --git a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml new file mode 100644 index 000000000000..589c3f1e2008 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/sound/qcom,q6dsp-lpass-clocks.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm DSP LPASS Clock Controller binding + +maintainers: + - Srinivas Kandagatla + +description: | + This binding describes the Qualcomm DSP Clock Controller + +properties: + compatible: + enum: + - qcom,q6afe-clocks + + reg: + maxItems: 1 + + '#clock-cells': + const: 2 + description: + Clock Id is followed by clock coupling attributes. + 1 = for no coupled clock + 2 = for dividend of the coupled clock + 3 = for divisor of the coupled clock + 4 = for inverted and no couple clock + +required: + - compatible + - reg + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include + #include + apr { + #address-cells = <1>; + #size-cells = <0>; + apr-service@4 { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + q6afecc@2 { + compatible = "qcom,q6afe-clocks"; + reg = <2>; + #clock-cells = <2>; + }; + }; + }; From patchwork Fri Sep 3 11:20:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 506512 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp906498jai; Fri, 3 Sep 2021 04:21:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx7oDu7tZtHChxnEx1+C/KmpyDsCLJhsWL9VH4zGNcCou7miy1TfRge6NFi/7cMzqjaFDxt X-Received: by 2002:a92:cb12:: with SMTP id s18mr2196870ilo.32.1630668105052; Fri, 03 Sep 2021 04:21:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1630668105; cv=none; d=google.com; s=arc-20160816; b=seQ0KUgwDsLCPqpE1EP9EZ2n+RBYXeXj5buLEeF0v/KF/U5I0ehxsH91uZoSXfDfad pEeWNYhVgQfLhcbUAihSGS7qoCvTjEUv+A2SlAHL8tUYnOOfN02zaOfHSFoJdasq/BVb +t0dp8cxxLEqDa7tnvGlymjVTmamJ90UcpdHOT48m0cLOxwUAEGa2BTAxO9UnmPgh5wx czhDIkSnvR7q8T8i+1qVcN7nmTxLpOQrpnIJ4eSlJYLNJcQbU1Ckq78DZfTLPbRzJ43L Moej6vC7gslVOp/81xzevMJoa5+bQC4XnTKxX45mcuXFyx9vYuXHY1bW+uat+Z0Chss/ gyvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=jONUN0C6XA6UJsv3RxwoGrHmtYxRlaTGrHYolrxpDUg=; b=nifZjfebCThPQAeEH3EcrUQlp9fwVGIkCEcxpCdlGpvrA6jaBsVqSFvcMOpu92/gsz q1dtWWu7H4/bpbxvCvB38UejsmtvXU3gWogtYMIJBEGtSe5Dg3zUCV6CWw02YNFciyWo 6kHs2vGcaTVAawjyCEbt3lDDIwtXurcPZdKVxS+0rjOzb05bpTUqTZbLWiwLFFMoGNoX vYtKMfIWAE4RbnXpcxm7Saho2iPncq80aqp2WRLsXobpnr0RYJ1ThpeVwU7Ojq3vZfqM KGmLrKuAnrXyK6J3FMTRE+zxbpFtHjO4ABkPDClPCpNABlvv16SlzhCgo3uw8XOSPCLO RKnA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=e6+fImB2; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:41 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 08/21] ASoC: dt-bindings: rename q6afe.h to q6dsp-lpass-ports.h Date: Fri, 3 Sep 2021 12:20:19 +0100 Message-Id: <20210903112032.25834-9-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org move all LPASS audio ports defines from q6afe.h to q6dsp-lpass-ports.h as these belong to LPASS IP. Also this move helps in reusing this header across multiple audio frameworks on Qualcomm Audio DSP. This patch is split out of the dt-bindings patch to enable easy review. Signed-off-by: Srinivas Kandagatla --- include/dt-bindings/sound/qcom,q6afe.h | 203 +---------------- .../sound/qcom,q6dsp-lpass-ports.h | 208 ++++++++++++++++++ 2 files changed, 210 insertions(+), 201 deletions(-) create mode 100644 include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h -- 2.21.0 Acked-by: Rob Herring diff --git a/include/dt-bindings/sound/qcom,q6afe.h b/include/dt-bindings/sound/qcom,q6afe.h index 66c21ab03eef..9d5d89cfabcf 100644 --- a/include/dt-bindings/sound/qcom,q6afe.h +++ b/include/dt-bindings/sound/qcom,q6afe.h @@ -2,207 +2,8 @@ #ifndef __DT_BINDINGS_Q6_AFE_H__ #define __DT_BINDINGS_Q6_AFE_H__ -/* Audio Front End (AFE) virtual ports IDs */ -#define HDMI_RX 1 -#define SLIMBUS_0_RX 2 -#define SLIMBUS_0_TX 3 -#define SLIMBUS_1_RX 4 -#define SLIMBUS_1_TX 5 -#define SLIMBUS_2_RX 6 -#define SLIMBUS_2_TX 7 -#define SLIMBUS_3_RX 8 -#define SLIMBUS_3_TX 9 -#define SLIMBUS_4_RX 10 -#define SLIMBUS_4_TX 11 -#define SLIMBUS_5_RX 12 -#define SLIMBUS_5_TX 13 -#define SLIMBUS_6_RX 14 -#define SLIMBUS_6_TX 15 -#define PRIMARY_MI2S_RX 16 -#define PRIMARY_MI2S_TX 17 -#define SECONDARY_MI2S_RX 18 -#define SECONDARY_MI2S_TX 19 -#define TERTIARY_MI2S_RX 20 -#define TERTIARY_MI2S_TX 21 -#define QUATERNARY_MI2S_RX 22 -#define QUATERNARY_MI2S_TX 23 -#define PRIMARY_TDM_RX_0 24 -#define PRIMARY_TDM_TX_0 25 -#define PRIMARY_TDM_RX_1 26 -#define PRIMARY_TDM_TX_1 27 -#define PRIMARY_TDM_RX_2 28 -#define PRIMARY_TDM_TX_2 29 -#define PRIMARY_TDM_RX_3 30 -#define PRIMARY_TDM_TX_3 31 -#define PRIMARY_TDM_RX_4 32 -#define PRIMARY_TDM_TX_4 33 -#define PRIMARY_TDM_RX_5 34 -#define PRIMARY_TDM_TX_5 35 -#define PRIMARY_TDM_RX_6 36 -#define PRIMARY_TDM_TX_6 37 -#define PRIMARY_TDM_RX_7 38 -#define PRIMARY_TDM_TX_7 39 -#define SECONDARY_TDM_RX_0 40 -#define SECONDARY_TDM_TX_0 41 -#define SECONDARY_TDM_RX_1 42 -#define SECONDARY_TDM_TX_1 43 -#define SECONDARY_TDM_RX_2 44 -#define SECONDARY_TDM_TX_2 45 -#define SECONDARY_TDM_RX_3 46 -#define SECONDARY_TDM_TX_3 47 -#define SECONDARY_TDM_RX_4 48 -#define SECONDARY_TDM_TX_4 49 -#define SECONDARY_TDM_RX_5 50 -#define SECONDARY_TDM_TX_5 51 -#define SECONDARY_TDM_RX_6 52 -#define SECONDARY_TDM_TX_6 53 -#define SECONDARY_TDM_RX_7 54 -#define SECONDARY_TDM_TX_7 55 -#define TERTIARY_TDM_RX_0 56 -#define TERTIARY_TDM_TX_0 57 -#define TERTIARY_TDM_RX_1 58 -#define TERTIARY_TDM_TX_1 59 -#define TERTIARY_TDM_RX_2 60 -#define TERTIARY_TDM_TX_2 61 -#define TERTIARY_TDM_RX_3 62 -#define TERTIARY_TDM_TX_3 63 -#define TERTIARY_TDM_RX_4 64 -#define TERTIARY_TDM_TX_4 65 -#define TERTIARY_TDM_RX_5 66 -#define TERTIARY_TDM_TX_5 67 -#define TERTIARY_TDM_RX_6 68 -#define TERTIARY_TDM_TX_6 69 -#define TERTIARY_TDM_RX_7 70 -#define TERTIARY_TDM_TX_7 71 -#define QUATERNARY_TDM_RX_0 72 -#define QUATERNARY_TDM_TX_0 73 -#define QUATERNARY_TDM_RX_1 74 -#define QUATERNARY_TDM_TX_1 75 -#define QUATERNARY_TDM_RX_2 76 -#define QUATERNARY_TDM_TX_2 77 -#define QUATERNARY_TDM_RX_3 78 -#define QUATERNARY_TDM_TX_3 79 -#define QUATERNARY_TDM_RX_4 80 -#define QUATERNARY_TDM_TX_4 81 -#define QUATERNARY_TDM_RX_5 82 -#define QUATERNARY_TDM_TX_5 83 -#define QUATERNARY_TDM_RX_6 84 -#define QUATERNARY_TDM_TX_6 85 -#define QUATERNARY_TDM_RX_7 86 -#define QUATERNARY_TDM_TX_7 87 -#define QUINARY_TDM_RX_0 88 -#define QUINARY_TDM_TX_0 89 -#define QUINARY_TDM_RX_1 90 -#define QUINARY_TDM_TX_1 91 -#define QUINARY_TDM_RX_2 92 -#define QUINARY_TDM_TX_2 93 -#define QUINARY_TDM_RX_3 94 -#define QUINARY_TDM_TX_3 95 -#define QUINARY_TDM_RX_4 96 -#define QUINARY_TDM_TX_4 97 -#define QUINARY_TDM_RX_5 98 -#define QUINARY_TDM_TX_5 99 -#define QUINARY_TDM_RX_6 100 -#define QUINARY_TDM_TX_6 101 -#define QUINARY_TDM_RX_7 102 -#define QUINARY_TDM_TX_7 103 -#define DISPLAY_PORT_RX 104 -#define WSA_CODEC_DMA_RX_0 105 -#define WSA_CODEC_DMA_TX_0 106 -#define WSA_CODEC_DMA_RX_1 107 -#define WSA_CODEC_DMA_TX_1 108 -#define WSA_CODEC_DMA_TX_2 109 -#define VA_CODEC_DMA_TX_0 110 -#define VA_CODEC_DMA_TX_1 111 -#define VA_CODEC_DMA_TX_2 112 -#define RX_CODEC_DMA_RX_0 113 -#define TX_CODEC_DMA_TX_0 114 -#define RX_CODEC_DMA_RX_1 115 -#define TX_CODEC_DMA_TX_1 116 -#define RX_CODEC_DMA_RX_2 117 -#define TX_CODEC_DMA_TX_2 118 -#define RX_CODEC_DMA_RX_3 119 -#define TX_CODEC_DMA_TX_3 120 -#define RX_CODEC_DMA_RX_4 121 -#define TX_CODEC_DMA_TX_4 122 -#define RX_CODEC_DMA_RX_5 123 -#define TX_CODEC_DMA_TX_5 124 -#define RX_CODEC_DMA_RX_6 125 -#define RX_CODEC_DMA_RX_7 126 -#define QUINARY_MI2S_RX 127 -#define QUINARY_MI2S_TX 128 +/* This file exists due to backward compatibility reasons, Please do not DELETE! */ -#define LPASS_CLK_ID_PRI_MI2S_IBIT 1 -#define LPASS_CLK_ID_PRI_MI2S_EBIT 2 -#define LPASS_CLK_ID_SEC_MI2S_IBIT 3 -#define LPASS_CLK_ID_SEC_MI2S_EBIT 4 -#define LPASS_CLK_ID_TER_MI2S_IBIT 5 -#define LPASS_CLK_ID_TER_MI2S_EBIT 6 -#define LPASS_CLK_ID_QUAD_MI2S_IBIT 7 -#define LPASS_CLK_ID_QUAD_MI2S_EBIT 8 -#define LPASS_CLK_ID_SPEAKER_I2S_IBIT 9 -#define LPASS_CLK_ID_SPEAKER_I2S_EBIT 10 -#define LPASS_CLK_ID_SPEAKER_I2S_OSR 11 -#define LPASS_CLK_ID_QUI_MI2S_IBIT 12 -#define LPASS_CLK_ID_QUI_MI2S_EBIT 13 -#define LPASS_CLK_ID_SEN_MI2S_IBIT 14 -#define LPASS_CLK_ID_SEN_MI2S_EBIT 15 -#define LPASS_CLK_ID_INT0_MI2S_IBIT 16 -#define LPASS_CLK_ID_INT1_MI2S_IBIT 17 -#define LPASS_CLK_ID_INT2_MI2S_IBIT 18 -#define LPASS_CLK_ID_INT3_MI2S_IBIT 19 -#define LPASS_CLK_ID_INT4_MI2S_IBIT 20 -#define LPASS_CLK_ID_INT5_MI2S_IBIT 21 -#define LPASS_CLK_ID_INT6_MI2S_IBIT 22 -#define LPASS_CLK_ID_QUI_MI2S_OSR 23 -#define LPASS_CLK_ID_PRI_PCM_IBIT 24 -#define LPASS_CLK_ID_PRI_PCM_EBIT 25 -#define LPASS_CLK_ID_SEC_PCM_IBIT 26 -#define LPASS_CLK_ID_SEC_PCM_EBIT 27 -#define LPASS_CLK_ID_TER_PCM_IBIT 28 -#define LPASS_CLK_ID_TER_PCM_EBIT 29 -#define LPASS_CLK_ID_QUAD_PCM_IBIT 30 -#define LPASS_CLK_ID_QUAD_PCM_EBIT 31 -#define LPASS_CLK_ID_QUIN_PCM_IBIT 32 -#define LPASS_CLK_ID_QUIN_PCM_EBIT 33 -#define LPASS_CLK_ID_QUI_PCM_OSR 34 -#define LPASS_CLK_ID_PRI_TDM_IBIT 35 -#define LPASS_CLK_ID_PRI_TDM_EBIT 36 -#define LPASS_CLK_ID_SEC_TDM_IBIT 37 -#define LPASS_CLK_ID_SEC_TDM_EBIT 38 -#define LPASS_CLK_ID_TER_TDM_IBIT 39 -#define LPASS_CLK_ID_TER_TDM_EBIT 40 -#define LPASS_CLK_ID_QUAD_TDM_IBIT 41 -#define LPASS_CLK_ID_QUAD_TDM_EBIT 42 -#define LPASS_CLK_ID_QUIN_TDM_IBIT 43 -#define LPASS_CLK_ID_QUIN_TDM_EBIT 44 -#define LPASS_CLK_ID_QUIN_TDM_OSR 45 -#define LPASS_CLK_ID_MCLK_1 46 -#define LPASS_CLK_ID_MCLK_2 47 -#define LPASS_CLK_ID_MCLK_3 48 -#define LPASS_CLK_ID_MCLK_4 49 -#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 50 -#define LPASS_CLK_ID_INT_MCLK_0 51 -#define LPASS_CLK_ID_INT_MCLK_1 52 -#define LPASS_CLK_ID_MCLK_5 53 -#define LPASS_CLK_ID_WSA_CORE_MCLK 54 -#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55 -#define LPASS_CLK_ID_VA_CORE_MCLK 56 -#define LPASS_CLK_ID_TX_CORE_MCLK 57 -#define LPASS_CLK_ID_TX_CORE_NPL_MCLK 58 -#define LPASS_CLK_ID_RX_CORE_MCLK 59 -#define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60 -#define LPASS_CLK_ID_VA_CORE_2X_MCLK 61 - -#define LPASS_HW_AVTIMER_VOTE 101 -#define LPASS_HW_MACRO_VOTE 102 -#define LPASS_HW_DCODEC_VOTE 103 - -#define Q6AFE_MAX_CLK_ID 104 - -#define LPASS_CLK_ATTRIBUTE_INVALID 0x0 -#define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1 -#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2 -#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3 +#include #endif /* __DT_BINDINGS_Q6_AFE_H__ */ diff --git a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h new file mode 100644 index 000000000000..0d3276c8fc11 --- /dev/null +++ b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h @@ -0,0 +1,208 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_Q6_AUDIO_PORTS_H__ +#define __DT_BINDINGS_Q6_AUDIO_PORTS_H__ + +/* LPASS Audio virtual ports IDs */ +#define HDMI_RX 1 +#define SLIMBUS_0_RX 2 +#define SLIMBUS_0_TX 3 +#define SLIMBUS_1_RX 4 +#define SLIMBUS_1_TX 5 +#define SLIMBUS_2_RX 6 +#define SLIMBUS_2_TX 7 +#define SLIMBUS_3_RX 8 +#define SLIMBUS_3_TX 9 +#define SLIMBUS_4_RX 10 +#define SLIMBUS_4_TX 11 +#define SLIMBUS_5_RX 12 +#define SLIMBUS_5_TX 13 +#define SLIMBUS_6_RX 14 +#define SLIMBUS_6_TX 15 +#define PRIMARY_MI2S_RX 16 +#define PRIMARY_MI2S_TX 17 +#define SECONDARY_MI2S_RX 18 +#define SECONDARY_MI2S_TX 19 +#define TERTIARY_MI2S_RX 20 +#define TERTIARY_MI2S_TX 21 +#define QUATERNARY_MI2S_RX 22 +#define QUATERNARY_MI2S_TX 23 +#define PRIMARY_TDM_RX_0 24 +#define PRIMARY_TDM_TX_0 25 +#define PRIMARY_TDM_RX_1 26 +#define PRIMARY_TDM_TX_1 27 +#define PRIMARY_TDM_RX_2 28 +#define PRIMARY_TDM_TX_2 29 +#define PRIMARY_TDM_RX_3 30 +#define PRIMARY_TDM_TX_3 31 +#define PRIMARY_TDM_RX_4 32 +#define PRIMARY_TDM_TX_4 33 +#define PRIMARY_TDM_RX_5 34 +#define PRIMARY_TDM_TX_5 35 +#define PRIMARY_TDM_RX_6 36 +#define PRIMARY_TDM_TX_6 37 +#define PRIMARY_TDM_RX_7 38 +#define PRIMARY_TDM_TX_7 39 +#define SECONDARY_TDM_RX_0 40 +#define SECONDARY_TDM_TX_0 41 +#define SECONDARY_TDM_RX_1 42 +#define SECONDARY_TDM_TX_1 43 +#define SECONDARY_TDM_RX_2 44 +#define SECONDARY_TDM_TX_2 45 +#define SECONDARY_TDM_RX_3 46 +#define SECONDARY_TDM_TX_3 47 +#define SECONDARY_TDM_RX_4 48 +#define SECONDARY_TDM_TX_4 49 +#define SECONDARY_TDM_RX_5 50 +#define SECONDARY_TDM_TX_5 51 +#define SECONDARY_TDM_RX_6 52 +#define SECONDARY_TDM_TX_6 53 +#define SECONDARY_TDM_RX_7 54 +#define SECONDARY_TDM_TX_7 55 +#define TERTIARY_TDM_RX_0 56 +#define TERTIARY_TDM_TX_0 57 +#define TERTIARY_TDM_RX_1 58 +#define TERTIARY_TDM_TX_1 59 +#define TERTIARY_TDM_RX_2 60 +#define TERTIARY_TDM_TX_2 61 +#define TERTIARY_TDM_RX_3 62 +#define TERTIARY_TDM_TX_3 63 +#define TERTIARY_TDM_RX_4 64 +#define TERTIARY_TDM_TX_4 65 +#define TERTIARY_TDM_RX_5 66 +#define TERTIARY_TDM_TX_5 67 +#define TERTIARY_TDM_RX_6 68 +#define TERTIARY_TDM_TX_6 69 +#define TERTIARY_TDM_RX_7 70 +#define TERTIARY_TDM_TX_7 71 +#define QUATERNARY_TDM_RX_0 72 +#define QUATERNARY_TDM_TX_0 73 +#define QUATERNARY_TDM_RX_1 74 +#define QUATERNARY_TDM_TX_1 75 +#define QUATERNARY_TDM_RX_2 76 +#define QUATERNARY_TDM_TX_2 77 +#define QUATERNARY_TDM_RX_3 78 +#define QUATERNARY_TDM_TX_3 79 +#define QUATERNARY_TDM_RX_4 80 +#define QUATERNARY_TDM_TX_4 81 +#define QUATERNARY_TDM_RX_5 82 +#define QUATERNARY_TDM_TX_5 83 +#define QUATERNARY_TDM_RX_6 84 +#define QUATERNARY_TDM_TX_6 85 +#define QUATERNARY_TDM_RX_7 86 +#define QUATERNARY_TDM_TX_7 87 +#define QUINARY_TDM_RX_0 88 +#define QUINARY_TDM_TX_0 89 +#define QUINARY_TDM_RX_1 90 +#define QUINARY_TDM_TX_1 91 +#define QUINARY_TDM_RX_2 92 +#define QUINARY_TDM_TX_2 93 +#define QUINARY_TDM_RX_3 94 +#define QUINARY_TDM_TX_3 95 +#define QUINARY_TDM_RX_4 96 +#define QUINARY_TDM_TX_4 97 +#define QUINARY_TDM_RX_5 98 +#define QUINARY_TDM_TX_5 99 +#define QUINARY_TDM_RX_6 100 +#define QUINARY_TDM_TX_6 101 +#define QUINARY_TDM_RX_7 102 +#define QUINARY_TDM_TX_7 103 +#define DISPLAY_PORT_RX 104 +#define WSA_CODEC_DMA_RX_0 105 +#define WSA_CODEC_DMA_TX_0 106 +#define WSA_CODEC_DMA_RX_1 107 +#define WSA_CODEC_DMA_TX_1 108 +#define WSA_CODEC_DMA_TX_2 109 +#define VA_CODEC_DMA_TX_0 110 +#define VA_CODEC_DMA_TX_1 111 +#define VA_CODEC_DMA_TX_2 112 +#define RX_CODEC_DMA_RX_0 113 +#define TX_CODEC_DMA_TX_0 114 +#define RX_CODEC_DMA_RX_1 115 +#define TX_CODEC_DMA_TX_1 116 +#define RX_CODEC_DMA_RX_2 117 +#define TX_CODEC_DMA_TX_2 118 +#define RX_CODEC_DMA_RX_3 119 +#define TX_CODEC_DMA_TX_3 120 +#define RX_CODEC_DMA_RX_4 121 +#define TX_CODEC_DMA_TX_4 122 +#define RX_CODEC_DMA_RX_5 123 +#define TX_CODEC_DMA_TX_5 124 +#define RX_CODEC_DMA_RX_6 125 +#define RX_CODEC_DMA_RX_7 126 +#define QUINARY_MI2S_RX 127 +#define QUINARY_MI2S_TX 128 + +#define LPASS_CLK_ID_PRI_MI2S_IBIT 1 +#define LPASS_CLK_ID_PRI_MI2S_EBIT 2 +#define LPASS_CLK_ID_SEC_MI2S_IBIT 3 +#define LPASS_CLK_ID_SEC_MI2S_EBIT 4 +#define LPASS_CLK_ID_TER_MI2S_IBIT 5 +#define LPASS_CLK_ID_TER_MI2S_EBIT 6 +#define LPASS_CLK_ID_QUAD_MI2S_IBIT 7 +#define LPASS_CLK_ID_QUAD_MI2S_EBIT 8 +#define LPASS_CLK_ID_SPEAKER_I2S_IBIT 9 +#define LPASS_CLK_ID_SPEAKER_I2S_EBIT 10 +#define LPASS_CLK_ID_SPEAKER_I2S_OSR 11 +#define LPASS_CLK_ID_QUI_MI2S_IBIT 12 +#define LPASS_CLK_ID_QUI_MI2S_EBIT 13 +#define LPASS_CLK_ID_SEN_MI2S_IBIT 14 +#define LPASS_CLK_ID_SEN_MI2S_EBIT 15 +#define LPASS_CLK_ID_INT0_MI2S_IBIT 16 +#define LPASS_CLK_ID_INT1_MI2S_IBIT 17 +#define LPASS_CLK_ID_INT2_MI2S_IBIT 18 +#define LPASS_CLK_ID_INT3_MI2S_IBIT 19 +#define LPASS_CLK_ID_INT4_MI2S_IBIT 20 +#define LPASS_CLK_ID_INT5_MI2S_IBIT 21 +#define LPASS_CLK_ID_INT6_MI2S_IBIT 22 +#define LPASS_CLK_ID_QUI_MI2S_OSR 23 +#define LPASS_CLK_ID_PRI_PCM_IBIT 24 +#define LPASS_CLK_ID_PRI_PCM_EBIT 25 +#define LPASS_CLK_ID_SEC_PCM_IBIT 26 +#define LPASS_CLK_ID_SEC_PCM_EBIT 27 +#define LPASS_CLK_ID_TER_PCM_IBIT 28 +#define LPASS_CLK_ID_TER_PCM_EBIT 29 +#define LPASS_CLK_ID_QUAD_PCM_IBIT 30 +#define LPASS_CLK_ID_QUAD_PCM_EBIT 31 +#define LPASS_CLK_ID_QUIN_PCM_IBIT 32 +#define LPASS_CLK_ID_QUIN_PCM_EBIT 33 +#define LPASS_CLK_ID_QUI_PCM_OSR 34 +#define LPASS_CLK_ID_PRI_TDM_IBIT 35 +#define LPASS_CLK_ID_PRI_TDM_EBIT 36 +#define LPASS_CLK_ID_SEC_TDM_IBIT 37 +#define LPASS_CLK_ID_SEC_TDM_EBIT 38 +#define LPASS_CLK_ID_TER_TDM_IBIT 39 +#define LPASS_CLK_ID_TER_TDM_EBIT 40 +#define LPASS_CLK_ID_QUAD_TDM_IBIT 41 +#define LPASS_CLK_ID_QUAD_TDM_EBIT 42 +#define LPASS_CLK_ID_QUIN_TDM_IBIT 43 +#define LPASS_CLK_ID_QUIN_TDM_EBIT 44 +#define LPASS_CLK_ID_QUIN_TDM_OSR 45 +#define LPASS_CLK_ID_MCLK_1 46 +#define LPASS_CLK_ID_MCLK_2 47 +#define LPASS_CLK_ID_MCLK_3 48 +#define LPASS_CLK_ID_MCLK_4 49 +#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 50 +#define LPASS_CLK_ID_INT_MCLK_0 51 +#define LPASS_CLK_ID_INT_MCLK_1 52 +#define LPASS_CLK_ID_MCLK_5 53 +#define LPASS_CLK_ID_WSA_CORE_MCLK 54 +#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55 +#define LPASS_CLK_ID_VA_CORE_MCLK 56 +#define LPASS_CLK_ID_TX_CORE_MCLK 57 +#define LPASS_CLK_ID_TX_CORE_NPL_MCLK 58 +#define LPASS_CLK_ID_RX_CORE_MCLK 59 +#define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60 +#define LPASS_CLK_ID_VA_CORE_2X_MCLK 61 + +#define LPASS_HW_AVTIMER_VOTE 101 +#define LPASS_HW_MACRO_VOTE 102 +#define LPASS_HW_DCODEC_VOTE 103 + +#define Q6AFE_MAX_CLK_ID 104 + +#define LPASS_CLK_ATTRIBUTE_INVALID 0x0 +#define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1 +#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2 +#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3 + +#endif /* __DT_BINDINGS_Q6_AUDIO_PORTS_H__ */ From patchwork Fri Sep 3 11:20:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 506513 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp906512jai; Fri, 3 Sep 2021 04:21:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw7bXHaJQCZtH9D1N/Jld9ntUYBcowJwR/l80g4Pyy9vebnk9zCp9ftkr/1xtBzGIUZZjYu X-Received: by 2002:a6b:e50e:: with SMTP id y14mr2697732ioc.54.1630668106927; Fri, 03 Sep 2021 04:21:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1630668106; cv=none; d=google.com; s=arc-20160816; b=G4Mhv2E85DbEusQ4lcP/XIuCFhvtg/8yYl9DhZdBSz2VBTozk2e5A2Z7bC9Ryu9Uz7 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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:42 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 09/21] ASoC: qdsp6: q6afe-dai: move lpass audio ports to common file Date: Fri, 3 Sep 2021 12:20:20 +0100 Message-Id: <20210903112032.25834-10-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Various Q6DSP frameworks will use LPASS Audio IP, so move all the hardware specific details to a common file so that they could be reused across multiple Q6DSP frameworks. In this case all the audio ports definations can be moved to a common file so that AudioReach and Elite Framework can reuse this. Signed-off-by: Srinivas Kandagatla --- sound/soc/qcom/qdsp6/Makefile | 4 +- sound/soc/qcom/qdsp6/q6afe-dai.c | 687 +---------------------- sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c | 627 +++++++++++++++++++++ sound/soc/qcom/qdsp6/q6dsp-lpass-ports.h | 22 + 4 files changed, 667 insertions(+), 673 deletions(-) create mode 100644 sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c create mode 100644 sound/soc/qcom/qdsp6/q6dsp-lpass-ports.h -- 2.21.0 diff --git a/sound/soc/qcom/qdsp6/Makefile b/sound/soc/qcom/qdsp6/Makefile index 3c1dd9f32f1d..11e8705bbc5c 100644 --- a/sound/soc/qcom/qdsp6/Makefile +++ b/sound/soc/qcom/qdsp6/Makefile @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_SND_SOC_QDSP6_COMMON) += q6dsp-common.o +snd-q6dsp-common-objs := q6dsp-common.o q6dsp-lpass-ports.o + +obj-$(CONFIG_SND_SOC_QDSP6_COMMON) += snd-q6dsp-common.o obj-$(CONFIG_SND_SOC_QDSP6_CORE) += q6core.o obj-$(CONFIG_SND_SOC_QDSP6_AFE) += q6afe.o obj-$(CONFIG_SND_SOC_QDSP6_AFE_DAI) += q6afe-dai.o diff --git a/sound/soc/qcom/qdsp6/q6afe-dai.c b/sound/soc/qcom/qdsp6/q6afe-dai.c index ac8f7324e94b..a293e325a1ea 100644 --- a/sound/soc/qcom/qdsp6/q6afe-dai.c +++ b/sound/soc/qcom/qdsp6/q6afe-dai.c @@ -11,91 +11,9 @@ #include #include #include +#include "q6dsp-lpass-ports.h" #include "q6afe.h" -#define Q6AFE_TDM_PB_DAI(pre, num, did) { \ - .playback = { \ - .stream_name = pre" TDM"#num" Playback", \ - .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ - SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ - SNDRV_PCM_RATE_176400, \ - .formats = SNDRV_PCM_FMTBIT_S16_LE | \ - SNDRV_PCM_FMTBIT_S24_LE | \ - SNDRV_PCM_FMTBIT_S32_LE, \ - .channels_min = 1, \ - .channels_max = 8, \ - .rate_min = 8000, \ - .rate_max = 176400, \ - }, \ - .name = #did, \ - .ops = &q6tdm_ops, \ - .id = did, \ - .probe = msm_dai_q6_dai_probe, \ - .remove = msm_dai_q6_dai_remove, \ - } - -#define Q6AFE_TDM_CAP_DAI(pre, num, did) { \ - .capture = { \ - .stream_name = pre" TDM"#num" Capture", \ - .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ - SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ - SNDRV_PCM_RATE_176400, \ - .formats = SNDRV_PCM_FMTBIT_S16_LE | \ - SNDRV_PCM_FMTBIT_S24_LE | \ - SNDRV_PCM_FMTBIT_S32_LE, \ - .channels_min = 1, \ - .channels_max = 8, \ - .rate_min = 8000, \ - .rate_max = 176400, \ - }, \ - .name = #did, \ - .ops = &q6tdm_ops, \ - .id = did, \ - .probe = msm_dai_q6_dai_probe, \ - .remove = msm_dai_q6_dai_remove, \ - } - -#define Q6AFE_CDC_DMA_RX_DAI(did) { \ - .playback = { \ - .stream_name = #did" Playback", \ - .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ - SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ - SNDRV_PCM_RATE_176400, \ - .formats = SNDRV_PCM_FMTBIT_S16_LE | \ - SNDRV_PCM_FMTBIT_S24_LE | \ - SNDRV_PCM_FMTBIT_S32_LE, \ - .channels_min = 1, \ - .channels_max = 8, \ - .rate_min = 8000, \ - .rate_max = 176400, \ - }, \ - .name = #did, \ - .ops = &q6dma_ops, \ - .id = did, \ - .probe = msm_dai_q6_dai_probe, \ - .remove = msm_dai_q6_dai_remove, \ - } - -#define Q6AFE_CDC_DMA_TX_DAI(did) { \ - .capture = { \ - .stream_name = #did" Capture", \ - .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ - SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ - SNDRV_PCM_RATE_176400, \ - .formats = SNDRV_PCM_FMTBIT_S16_LE | \ - SNDRV_PCM_FMTBIT_S24_LE | \ - SNDRV_PCM_FMTBIT_S32_LE, \ - .channels_min = 1, \ - .channels_max = 8, \ - .rate_min = 8000, \ - .rate_max = 176400, \ - }, \ - .name = #did, \ - .ops = &q6dma_ops, \ - .id = did, \ - .probe = msm_dai_q6_dai_probe, \ - .remove = msm_dai_q6_dai_remove, \ - } struct q6afe_dai_priv_data { uint32_t sd_line_mask; @@ -784,591 +702,6 @@ static int msm_dai_q6_dai_remove(struct snd_soc_dai *dai) return 0; } -static struct snd_soc_dai_driver q6afe_dais[] = { - { - .playback = { - .stream_name = "HDMI Playback", - .rates = SNDRV_PCM_RATE_48000 | - SNDRV_PCM_RATE_96000 | - SNDRV_PCM_RATE_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, - .channels_min = 2, - .channels_max = 8, - .rate_max = 192000, - .rate_min = 48000, - }, - .ops = &q6hdmi_ops, - .id = HDMI_RX, - .name = "HDMI", - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - }, { - .name = "SLIMBUS_0_RX", - .ops = &q6slim_ops, - .id = SLIMBUS_0_RX, - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - .playback = { - .stream_name = "Slimbus Playback", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 | - SNDRV_PCM_RATE_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, - .channels_min = 1, - .channels_max = 8, - .rate_min = 8000, - .rate_max = 192000, - }, - }, { - .name = "SLIMBUS_0_TX", - .ops = &q6slim_ops, - .id = SLIMBUS_0_TX, - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - .capture = { - .stream_name = "Slimbus Capture", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 | - SNDRV_PCM_RATE_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, - .channels_min = 1, - .channels_max = 8, - .rate_min = 8000, - .rate_max = 192000, - }, - }, { - .playback = { - .stream_name = "Slimbus1 Playback", - .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | - SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | - SNDRV_PCM_RATE_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, - .channels_min = 1, - .channels_max = 2, - .rate_min = 8000, - .rate_max = 192000, - }, - .name = "SLIMBUS_1_RX", - .ops = &q6slim_ops, - .id = SLIMBUS_1_RX, - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - }, { - .name = "SLIMBUS_1_TX", - .ops = &q6slim_ops, - .id = SLIMBUS_1_TX, - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - .capture = { - .stream_name = "Slimbus1 Capture", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 | - SNDRV_PCM_RATE_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, - .channels_min = 1, - .channels_max = 8, - .rate_min = 8000, - .rate_max = 192000, - }, - }, { - .playback = { - .stream_name = "Slimbus2 Playback", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 | - SNDRV_PCM_RATE_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, - .channels_min = 1, - .channels_max = 8, - .rate_min = 8000, - .rate_max = 192000, - }, - .name = "SLIMBUS_2_RX", - .ops = &q6slim_ops, - .id = SLIMBUS_2_RX, - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - - }, { - .name = "SLIMBUS_2_TX", - .ops = &q6slim_ops, - .id = SLIMBUS_2_TX, - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - .capture = { - .stream_name = "Slimbus2 Capture", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 | - SNDRV_PCM_RATE_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, - .channels_min = 1, - .channels_max = 8, - .rate_min = 8000, - .rate_max = 192000, - }, - }, { - .playback = { - .stream_name = "Slimbus3 Playback", - .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | - SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | - SNDRV_PCM_RATE_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, - .channels_min = 1, - .channels_max = 2, - .rate_min = 8000, - .rate_max = 192000, - }, - .name = "SLIMBUS_3_RX", - .ops = &q6slim_ops, - .id = SLIMBUS_3_RX, - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - - }, { - .name = "SLIMBUS_3_TX", - .ops = &q6slim_ops, - .id = SLIMBUS_3_TX, - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - .capture = { - .stream_name = "Slimbus3 Capture", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 | - SNDRV_PCM_RATE_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, - .channels_min = 1, - .channels_max = 8, - .rate_min = 8000, - .rate_max = 192000, - }, - }, { - .playback = { - .stream_name = "Slimbus4 Playback", - .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | - SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | - SNDRV_PCM_RATE_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, - .channels_min = 1, - .channels_max = 2, - .rate_min = 8000, - .rate_max = 192000, - }, - .name = "SLIMBUS_4_RX", - .ops = &q6slim_ops, - .id = SLIMBUS_4_RX, - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - - }, { - .name = "SLIMBUS_4_TX", - .ops = &q6slim_ops, - .id = SLIMBUS_4_TX, - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - .capture = { - .stream_name = "Slimbus4 Capture", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 | - SNDRV_PCM_RATE_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, - .channels_min = 1, - .channels_max = 8, - .rate_min = 8000, - .rate_max = 192000, - }, - }, { - .playback = { - .stream_name = "Slimbus5 Playback", - .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | - SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | - SNDRV_PCM_RATE_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, - .channels_min = 1, - .channels_max = 2, - .rate_min = 8000, - .rate_max = 192000, - }, - .name = "SLIMBUS_5_RX", - .ops = &q6slim_ops, - .id = SLIMBUS_5_RX, - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - - }, { - .name = "SLIMBUS_5_TX", - .ops = &q6slim_ops, - .id = SLIMBUS_5_TX, - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - .capture = { - .stream_name = "Slimbus5 Capture", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 | - SNDRV_PCM_RATE_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, - .channels_min = 1, - .channels_max = 8, - .rate_min = 8000, - .rate_max = 192000, - }, - }, { - .playback = { - .stream_name = "Slimbus6 Playback", - .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | - SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | - SNDRV_PCM_RATE_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, - .channels_min = 1, - .channels_max = 2, - .rate_min = 8000, - .rate_max = 192000, - }, - .ops = &q6slim_ops, - .name = "SLIMBUS_6_RX", - .id = SLIMBUS_6_RX, - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - - }, { - .name = "SLIMBUS_6_TX", - .ops = &q6slim_ops, - .id = SLIMBUS_6_TX, - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - .capture = { - .stream_name = "Slimbus6 Capture", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 | - SNDRV_PCM_RATE_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, - .channels_min = 1, - .channels_max = 8, - .rate_min = 8000, - .rate_max = 192000, - }, - }, { - .playback = { - .stream_name = "Primary MI2S Playback", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000, - .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, - .channels_min = 1, - .channels_max = 8, - .rate_min = 8000, - .rate_max = 48000, - }, - .id = PRIMARY_MI2S_RX, - .name = "PRI_MI2S_RX", - .ops = &q6i2s_ops, - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - }, { - .capture = { - .stream_name = "Primary MI2S Capture", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000, - .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, - .channels_min = 1, - .channels_max = 8, - .rate_min = 8000, - .rate_max = 48000, - }, - .id = PRIMARY_MI2S_TX, - .name = "PRI_MI2S_TX", - .ops = &q6i2s_ops, - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - }, { - .playback = { - .stream_name = "Secondary MI2S Playback", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000, - .formats = SNDRV_PCM_FMTBIT_S16_LE, - .channels_min = 1, - .channels_max = 8, - .rate_min = 8000, - .rate_max = 48000, - }, - .name = "SEC_MI2S_RX", - .id = SECONDARY_MI2S_RX, - .ops = &q6i2s_ops, - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - }, { - .capture = { - .stream_name = "Secondary MI2S Capture", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000, - .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, - .channels_min = 1, - .channels_max = 8, - .rate_min = 8000, - .rate_max = 48000, - }, - .id = SECONDARY_MI2S_TX, - .name = "SEC_MI2S_TX", - .ops = &q6i2s_ops, - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - }, { - .playback = { - .stream_name = "Tertiary MI2S Playback", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000, - .formats = SNDRV_PCM_FMTBIT_S16_LE, - .channels_min = 1, - .channels_max = 8, - .rate_min = 8000, - .rate_max = 48000, - }, - .name = "TERT_MI2S_RX", - .id = TERTIARY_MI2S_RX, - .ops = &q6i2s_ops, - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - }, { - .capture = { - .stream_name = "Tertiary MI2S Capture", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000, - .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, - .channels_min = 1, - .channels_max = 8, - .rate_min = 8000, - .rate_max = 48000, - }, - .id = TERTIARY_MI2S_TX, - .name = "TERT_MI2S_TX", - .ops = &q6i2s_ops, - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - }, { - .playback = { - .stream_name = "Quaternary MI2S Playback", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000, - .formats = SNDRV_PCM_FMTBIT_S16_LE, - .channels_min = 1, - .channels_max = 8, - .rate_min = 8000, - .rate_max = 48000, - }, - .name = "QUAT_MI2S_RX", - .id = QUATERNARY_MI2S_RX, - .ops = &q6i2s_ops, - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - }, { - .capture = { - .stream_name = "Quaternary MI2S Capture", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000, - .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, - .channels_min = 1, - .channels_max = 8, - .rate_min = 8000, - .rate_max = 48000, - }, - .id = QUATERNARY_MI2S_TX, - .name = "QUAT_MI2S_TX", - .ops = &q6i2s_ops, - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - }, { - .playback = { - .stream_name = "Quinary MI2S Playback", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 | - SNDRV_PCM_RATE_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE, - .channels_min = 1, - .channels_max = 8, - .rate_min = 8000, - .rate_max = 192000, - }, - .id = QUINARY_MI2S_RX, - .name = "QUIN_MI2S_RX", - .ops = &q6i2s_ops, - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - }, { - .capture = { - .stream_name = "Quinary MI2S Capture", - .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | - SNDRV_PCM_RATE_16000, - .formats = SNDRV_PCM_FMTBIT_S16_LE, - .channels_min = 1, - .channels_max = 8, - .rate_min = 8000, - .rate_max = 48000, - }, - .id = QUINARY_MI2S_TX, - .name = "QUIN_MI2S_TX", - .ops = &q6i2s_ops, - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - }, - Q6AFE_TDM_PB_DAI("Primary", 0, PRIMARY_TDM_RX_0), - Q6AFE_TDM_PB_DAI("Primary", 1, PRIMARY_TDM_RX_1), - Q6AFE_TDM_PB_DAI("Primary", 2, PRIMARY_TDM_RX_2), - Q6AFE_TDM_PB_DAI("Primary", 3, PRIMARY_TDM_RX_3), - Q6AFE_TDM_PB_DAI("Primary", 4, PRIMARY_TDM_RX_4), - Q6AFE_TDM_PB_DAI("Primary", 5, PRIMARY_TDM_RX_5), - Q6AFE_TDM_PB_DAI("Primary", 6, PRIMARY_TDM_RX_6), - Q6AFE_TDM_PB_DAI("Primary", 7, PRIMARY_TDM_RX_7), - Q6AFE_TDM_CAP_DAI("Primary", 0, PRIMARY_TDM_TX_0), - Q6AFE_TDM_CAP_DAI("Primary", 1, PRIMARY_TDM_TX_1), - Q6AFE_TDM_CAP_DAI("Primary", 2, PRIMARY_TDM_TX_2), - Q6AFE_TDM_CAP_DAI("Primary", 3, PRIMARY_TDM_TX_3), - Q6AFE_TDM_CAP_DAI("Primary", 4, PRIMARY_TDM_TX_4), - Q6AFE_TDM_CAP_DAI("Primary", 5, PRIMARY_TDM_TX_5), - Q6AFE_TDM_CAP_DAI("Primary", 6, PRIMARY_TDM_TX_6), - Q6AFE_TDM_CAP_DAI("Primary", 7, PRIMARY_TDM_TX_7), - Q6AFE_TDM_PB_DAI("Secondary", 0, SECONDARY_TDM_RX_0), - Q6AFE_TDM_PB_DAI("Secondary", 1, SECONDARY_TDM_RX_1), - Q6AFE_TDM_PB_DAI("Secondary", 2, SECONDARY_TDM_RX_2), - Q6AFE_TDM_PB_DAI("Secondary", 3, SECONDARY_TDM_RX_3), - Q6AFE_TDM_PB_DAI("Secondary", 4, SECONDARY_TDM_RX_4), - Q6AFE_TDM_PB_DAI("Secondary", 5, SECONDARY_TDM_RX_5), - Q6AFE_TDM_PB_DAI("Secondary", 6, SECONDARY_TDM_RX_6), - Q6AFE_TDM_PB_DAI("Secondary", 7, SECONDARY_TDM_RX_7), - Q6AFE_TDM_CAP_DAI("Secondary", 0, SECONDARY_TDM_TX_0), - Q6AFE_TDM_CAP_DAI("Secondary", 1, SECONDARY_TDM_TX_1), - Q6AFE_TDM_CAP_DAI("Secondary", 2, SECONDARY_TDM_TX_2), - Q6AFE_TDM_CAP_DAI("Secondary", 3, SECONDARY_TDM_TX_3), - Q6AFE_TDM_CAP_DAI("Secondary", 4, SECONDARY_TDM_TX_4), - Q6AFE_TDM_CAP_DAI("Secondary", 5, SECONDARY_TDM_TX_5), - Q6AFE_TDM_CAP_DAI("Secondary", 6, SECONDARY_TDM_TX_6), - Q6AFE_TDM_CAP_DAI("Secondary", 7, SECONDARY_TDM_TX_7), - Q6AFE_TDM_PB_DAI("Tertiary", 0, TERTIARY_TDM_RX_0), - Q6AFE_TDM_PB_DAI("Tertiary", 1, TERTIARY_TDM_RX_1), - Q6AFE_TDM_PB_DAI("Tertiary", 2, TERTIARY_TDM_RX_2), - Q6AFE_TDM_PB_DAI("Tertiary", 3, TERTIARY_TDM_RX_3), - Q6AFE_TDM_PB_DAI("Tertiary", 4, TERTIARY_TDM_RX_4), - Q6AFE_TDM_PB_DAI("Tertiary", 5, TERTIARY_TDM_RX_5), - Q6AFE_TDM_PB_DAI("Tertiary", 6, TERTIARY_TDM_RX_6), - Q6AFE_TDM_PB_DAI("Tertiary", 7, TERTIARY_TDM_RX_7), - Q6AFE_TDM_CAP_DAI("Tertiary", 0, TERTIARY_TDM_TX_0), - Q6AFE_TDM_CAP_DAI("Tertiary", 1, TERTIARY_TDM_TX_1), - Q6AFE_TDM_CAP_DAI("Tertiary", 2, TERTIARY_TDM_TX_2), - Q6AFE_TDM_CAP_DAI("Tertiary", 3, TERTIARY_TDM_TX_3), - Q6AFE_TDM_CAP_DAI("Tertiary", 4, TERTIARY_TDM_TX_4), - Q6AFE_TDM_CAP_DAI("Tertiary", 5, TERTIARY_TDM_TX_5), - Q6AFE_TDM_CAP_DAI("Tertiary", 6, TERTIARY_TDM_TX_6), - Q6AFE_TDM_CAP_DAI("Tertiary", 7, TERTIARY_TDM_TX_7), - Q6AFE_TDM_PB_DAI("Quaternary", 0, QUATERNARY_TDM_RX_0), - Q6AFE_TDM_PB_DAI("Quaternary", 1, QUATERNARY_TDM_RX_1), - Q6AFE_TDM_PB_DAI("Quaternary", 2, QUATERNARY_TDM_RX_2), - Q6AFE_TDM_PB_DAI("Quaternary", 3, QUATERNARY_TDM_RX_3), - Q6AFE_TDM_PB_DAI("Quaternary", 4, QUATERNARY_TDM_RX_4), - Q6AFE_TDM_PB_DAI("Quaternary", 5, QUATERNARY_TDM_RX_5), - Q6AFE_TDM_PB_DAI("Quaternary", 6, QUATERNARY_TDM_RX_6), - Q6AFE_TDM_PB_DAI("Quaternary", 7, QUATERNARY_TDM_RX_7), - Q6AFE_TDM_CAP_DAI("Quaternary", 0, QUATERNARY_TDM_TX_0), - Q6AFE_TDM_CAP_DAI("Quaternary", 1, QUATERNARY_TDM_TX_1), - Q6AFE_TDM_CAP_DAI("Quaternary", 2, QUATERNARY_TDM_TX_2), - Q6AFE_TDM_CAP_DAI("Quaternary", 3, QUATERNARY_TDM_TX_3), - Q6AFE_TDM_CAP_DAI("Quaternary", 4, QUATERNARY_TDM_TX_4), - Q6AFE_TDM_CAP_DAI("Quaternary", 5, QUATERNARY_TDM_TX_5), - Q6AFE_TDM_CAP_DAI("Quaternary", 6, QUATERNARY_TDM_TX_6), - Q6AFE_TDM_CAP_DAI("Quaternary", 7, QUATERNARY_TDM_TX_7), - Q6AFE_TDM_PB_DAI("Quinary", 0, QUINARY_TDM_RX_0), - Q6AFE_TDM_PB_DAI("Quinary", 1, QUINARY_TDM_RX_1), - Q6AFE_TDM_PB_DAI("Quinary", 2, QUINARY_TDM_RX_2), - Q6AFE_TDM_PB_DAI("Quinary", 3, QUINARY_TDM_RX_3), - Q6AFE_TDM_PB_DAI("Quinary", 4, QUINARY_TDM_RX_4), - Q6AFE_TDM_PB_DAI("Quinary", 5, QUINARY_TDM_RX_5), - Q6AFE_TDM_PB_DAI("Quinary", 6, QUINARY_TDM_RX_6), - Q6AFE_TDM_PB_DAI("Quinary", 7, QUINARY_TDM_RX_7), - Q6AFE_TDM_CAP_DAI("Quinary", 0, QUINARY_TDM_TX_0), - Q6AFE_TDM_CAP_DAI("Quinary", 1, QUINARY_TDM_TX_1), - Q6AFE_TDM_CAP_DAI("Quinary", 2, QUINARY_TDM_TX_2), - Q6AFE_TDM_CAP_DAI("Quinary", 3, QUINARY_TDM_TX_3), - Q6AFE_TDM_CAP_DAI("Quinary", 4, QUINARY_TDM_TX_4), - Q6AFE_TDM_CAP_DAI("Quinary", 5, QUINARY_TDM_TX_5), - Q6AFE_TDM_CAP_DAI("Quinary", 6, QUINARY_TDM_TX_6), - Q6AFE_TDM_CAP_DAI("Quinary", 7, QUINARY_TDM_TX_7), - { - .playback = { - .stream_name = "Display Port Playback", - .rates = SNDRV_PCM_RATE_48000 | - SNDRV_PCM_RATE_96000 | - SNDRV_PCM_RATE_192000, - .formats = SNDRV_PCM_FMTBIT_S16_LE | - SNDRV_PCM_FMTBIT_S24_LE, - .channels_min = 2, - .channels_max = 8, - .rate_max = 192000, - .rate_min = 48000, - }, - .ops = &q6hdmi_ops, - .id = DISPLAY_PORT_RX, - .name = "DISPLAY_PORT", - .probe = msm_dai_q6_dai_probe, - .remove = msm_dai_q6_dai_remove, - }, - Q6AFE_CDC_DMA_RX_DAI(WSA_CODEC_DMA_RX_0), - Q6AFE_CDC_DMA_TX_DAI(WSA_CODEC_DMA_TX_0), - Q6AFE_CDC_DMA_RX_DAI(WSA_CODEC_DMA_RX_1), - Q6AFE_CDC_DMA_TX_DAI(WSA_CODEC_DMA_TX_1), - Q6AFE_CDC_DMA_TX_DAI(WSA_CODEC_DMA_TX_2), - Q6AFE_CDC_DMA_TX_DAI(VA_CODEC_DMA_TX_0), - Q6AFE_CDC_DMA_TX_DAI(VA_CODEC_DMA_TX_1), - Q6AFE_CDC_DMA_TX_DAI(VA_CODEC_DMA_TX_2), - Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_0), - Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_0), - Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_1), - Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_1), - Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_2), - Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_2), - Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_3), - Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_3), - Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_4), - Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_4), - Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_5), - Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_5), - Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_6), - Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_7), -}; - -static int q6afe_of_xlate_dai_name(struct snd_soc_component *component, - const struct of_phandle_args *args, - const char **dai_name) -{ - int id = args->args[0]; - int ret = -EINVAL; - int i; - - for (i = 0; i < ARRAY_SIZE(q6afe_dais); i++) { - if (q6afe_dais[i].id == id) { - *dai_name = q6afe_dais[i].name; - ret = 0; - break; - } - } - - return ret; -} - static const struct snd_soc_dapm_widget q6afe_dai_widgets[] = { SND_SOC_DAPM_AIF_IN("HDMI_RX", NULL, 0, SND_SOC_NOPM, 0, 0), SND_SOC_DAPM_AIF_IN("SLIMBUS_0_RX", NULL, 0, SND_SOC_NOPM, 0, 0), @@ -1627,7 +960,7 @@ static const struct snd_soc_component_driver q6afe_dai_component = { .num_dapm_widgets = ARRAY_SIZE(q6afe_dai_widgets), .dapm_routes = q6afe_dapm_routes, .num_dapm_routes = ARRAY_SIZE(q6afe_dapm_routes), - .of_xlate_dai_name = q6afe_of_xlate_dai_name, + .of_xlate_dai_name = q6dsp_audio_ports_of_xlate_dai_name, }; @@ -1715,19 +1048,29 @@ static void of_q6afe_parse_dai_data(struct device *dev, static int q6afe_dai_dev_probe(struct platform_device *pdev) { + struct q6dsp_audio_port_dai_driver_config cfg; + struct snd_soc_dai_driver *dais; struct q6afe_dai_data *dai_data; struct device *dev = &pdev->dev; + int num_dais; dai_data = devm_kzalloc(dev, sizeof(*dai_data), GFP_KERNEL); if (!dai_data) return -ENOMEM; dev_set_drvdata(dev, dai_data); - of_q6afe_parse_dai_data(dev, dai_data); - return devm_snd_soc_register_component(dev, &q6afe_dai_component, - q6afe_dais, ARRAY_SIZE(q6afe_dais)); + cfg.probe = msm_dai_q6_dai_probe; + cfg.remove = msm_dai_q6_dai_remove; + cfg.q6hdmi_ops = &q6hdmi_ops; + cfg.q6slim_ops = &q6slim_ops; + cfg.q6i2s_ops = &q6i2s_ops; + cfg.q6tdm_ops = &q6tdm_ops; + cfg.q6dma_ops = &q6dma_ops; + dais = q6dsp_audio_ports_set_config(dev, &cfg, &num_dais); + + return devm_snd_soc_register_component(dev, &q6afe_dai_component, dais, num_dais); } #ifdef CONFIG_OF diff --git a/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c b/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c new file mode 100644 index 000000000000..f67c16fd90b9 --- /dev/null +++ b/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.c @@ -0,0 +1,627 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2020, Linaro Limited + +#include +#include +#include +#include +#include "q6dsp-lpass-ports.h" + +#define Q6AFE_TDM_PB_DAI(pre, num, did) { \ + .playback = { \ + .stream_name = pre" TDM"#num" Playback", \ + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ + SNDRV_PCM_RATE_176400, \ + .formats = SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE, \ + .channels_min = 1, \ + .channels_max = 8, \ + .rate_min = 8000, \ + .rate_max = 176400, \ + }, \ + .name = #did, \ + .id = did, \ + } + +#define Q6AFE_TDM_CAP_DAI(pre, num, did) { \ + .capture = { \ + .stream_name = pre" TDM"#num" Capture", \ + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ + SNDRV_PCM_RATE_176400, \ + .formats = SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE, \ + .channels_min = 1, \ + .channels_max = 8, \ + .rate_min = 8000, \ + .rate_max = 176400, \ + }, \ + .name = #did, \ + .id = did, \ + } + +#define Q6AFE_CDC_DMA_RX_DAI(did) { \ + .playback = { \ + .stream_name = #did" Playback", \ + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ + SNDRV_PCM_RATE_176400, \ + .formats = SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE, \ + .channels_min = 1, \ + .channels_max = 8, \ + .rate_min = 8000, \ + .rate_max = 176400, \ + }, \ + .name = #did, \ + .id = did, \ + } + +#define Q6AFE_CDC_DMA_TX_DAI(did) { \ + .capture = { \ + .stream_name = #did" Capture", \ + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ + SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ + SNDRV_PCM_RATE_176400, \ + .formats = SNDRV_PCM_FMTBIT_S16_LE | \ + SNDRV_PCM_FMTBIT_S24_LE | \ + SNDRV_PCM_FMTBIT_S32_LE, \ + .channels_min = 1, \ + .channels_max = 8, \ + .rate_min = 8000, \ + .rate_max = 176400, \ + }, \ + .name = #did, \ + .id = did, \ + } + + +static struct snd_soc_dai_driver q6dsp_audio_fe_dais[] = { + { + .playback = { + .stream_name = "HDMI Playback", + .rates = SNDRV_PCM_RATE_48000 | + SNDRV_PCM_RATE_96000 | + SNDRV_PCM_RATE_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE, + .channels_min = 2, + .channels_max = 8, + .rate_max = 192000, + .rate_min = 48000, + }, + .id = HDMI_RX, + .name = "HDMI", + }, { + .name = "SLIMBUS_0_RX", + .id = SLIMBUS_0_RX, + .playback = { + .stream_name = "Slimbus Playback", + .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 | + SNDRV_PCM_RATE_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE, + .channels_min = 1, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 192000, + }, + }, { + .name = "SLIMBUS_0_TX", + .id = SLIMBUS_0_TX, + .capture = { + .stream_name = "Slimbus Capture", + .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 | + SNDRV_PCM_RATE_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE, + .channels_min = 1, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 192000, + }, + }, { + .playback = { + .stream_name = "Slimbus1 Playback", + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | + SNDRV_PCM_RATE_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE, + .channels_min = 1, + .channels_max = 2, + .rate_min = 8000, + .rate_max = 192000, + }, + .name = "SLIMBUS_1_RX", + .id = SLIMBUS_1_RX, + }, { + .name = "SLIMBUS_1_TX", + .id = SLIMBUS_1_TX, + .capture = { + .stream_name = "Slimbus1 Capture", + .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 | + SNDRV_PCM_RATE_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE, + .channels_min = 1, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 192000, + }, + }, { + .playback = { + .stream_name = "Slimbus2 Playback", + .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 | + SNDRV_PCM_RATE_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE, + .channels_min = 1, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 192000, + }, + .name = "SLIMBUS_2_RX", + .id = SLIMBUS_2_RX, + + }, { + .name = "SLIMBUS_2_TX", + .id = SLIMBUS_2_TX, + .capture = { + .stream_name = "Slimbus2 Capture", + .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 | + SNDRV_PCM_RATE_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE, + .channels_min = 1, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 192000, + }, + }, { + .playback = { + .stream_name = "Slimbus3 Playback", + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | + SNDRV_PCM_RATE_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE, + .channels_min = 1, + .channels_max = 2, + .rate_min = 8000, + .rate_max = 192000, + }, + .name = "SLIMBUS_3_RX", + .id = SLIMBUS_3_RX, + + }, { + .name = "SLIMBUS_3_TX", + .id = SLIMBUS_3_TX, + .capture = { + .stream_name = "Slimbus3 Capture", + .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 | + SNDRV_PCM_RATE_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE, + .channels_min = 1, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 192000, + }, + }, { + .playback = { + .stream_name = "Slimbus4 Playback", + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | + SNDRV_PCM_RATE_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE, + .channels_min = 1, + .channels_max = 2, + .rate_min = 8000, + .rate_max = 192000, + }, + .name = "SLIMBUS_4_RX", + .id = SLIMBUS_4_RX, + + }, { + .name = "SLIMBUS_4_TX", + .id = SLIMBUS_4_TX, + .capture = { + .stream_name = "Slimbus4 Capture", + .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 | + SNDRV_PCM_RATE_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE, + .channels_min = 1, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 192000, + }, + }, { + .playback = { + .stream_name = "Slimbus5 Playback", + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | + SNDRV_PCM_RATE_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE, + .channels_min = 1, + .channels_max = 2, + .rate_min = 8000, + .rate_max = 192000, + }, + .name = "SLIMBUS_5_RX", + .id = SLIMBUS_5_RX, + + }, { + .name = "SLIMBUS_5_TX", + .id = SLIMBUS_5_TX, + .capture = { + .stream_name = "Slimbus5 Capture", + .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 | + SNDRV_PCM_RATE_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE, + .channels_min = 1, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 192000, + }, + }, { + .playback = { + .stream_name = "Slimbus6 Playback", + .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | + SNDRV_PCM_RATE_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE, + .channels_min = 1, + .channels_max = 2, + .rate_min = 8000, + .rate_max = 192000, + }, + .name = "SLIMBUS_6_RX", + .id = SLIMBUS_6_RX, + + }, { + .name = "SLIMBUS_6_TX", + .id = SLIMBUS_6_TX, + .capture = { + .stream_name = "Slimbus6 Capture", + .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 | + SNDRV_PCM_RATE_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE, + .channels_min = 1, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 192000, + }, + }, { + .playback = { + .stream_name = "Primary MI2S Playback", + .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | + SNDRV_PCM_RATE_16000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE, + .channels_min = 1, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 48000, + }, + .id = PRIMARY_MI2S_RX, + .name = "PRI_MI2S_RX", + }, { + .capture = { + .stream_name = "Primary MI2S Capture", + .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | + SNDRV_PCM_RATE_16000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE, + .channels_min = 1, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 48000, + }, + .id = PRIMARY_MI2S_TX, + .name = "PRI_MI2S_TX", + }, { + .playback = { + .stream_name = "Secondary MI2S Playback", + .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | + SNDRV_PCM_RATE_16000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + .channels_min = 1, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 48000, + }, + .name = "SEC_MI2S_RX", + .id = SECONDARY_MI2S_RX, + }, { + .capture = { + .stream_name = "Secondary MI2S Capture", + .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | + SNDRV_PCM_RATE_16000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE, + .channels_min = 1, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 48000, + }, + .id = SECONDARY_MI2S_TX, + .name = "SEC_MI2S_TX", + }, { + .playback = { + .stream_name = "Tertiary MI2S Playback", + .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | + SNDRV_PCM_RATE_16000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + .channels_min = 1, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 48000, + }, + .name = "TERT_MI2S_RX", + .id = TERTIARY_MI2S_RX, + }, { + .capture = { + .stream_name = "Tertiary MI2S Capture", + .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | + SNDRV_PCM_RATE_16000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE, + .channels_min = 1, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 48000, + }, + .id = TERTIARY_MI2S_TX, + .name = "TERT_MI2S_TX", + }, { + .playback = { + .stream_name = "Quaternary MI2S Playback", + .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | + SNDRV_PCM_RATE_16000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + .channels_min = 1, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 48000, + }, + .name = "QUAT_MI2S_RX", + .id = QUATERNARY_MI2S_RX, + }, { + .capture = { + .stream_name = "Quaternary MI2S Capture", + .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | + SNDRV_PCM_RATE_16000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE, + .channels_min = 1, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 48000, + }, + .id = QUATERNARY_MI2S_TX, + .name = "QUAT_MI2S_TX", + }, { + .playback = { + .stream_name = "Quinary MI2S Playback", + .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | + SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_96000 | + SNDRV_PCM_RATE_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + .channels_min = 1, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 192000, + }, + .id = QUINARY_MI2S_RX, + .name = "QUIN_MI2S_RX", + }, { + .capture = { + .stream_name = "Quinary MI2S Capture", + .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_8000 | + SNDRV_PCM_RATE_16000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + .channels_min = 1, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 48000, + }, + .id = QUINARY_MI2S_TX, + .name = "QUIN_MI2S_TX", + }, + Q6AFE_TDM_PB_DAI("Primary", 0, PRIMARY_TDM_RX_0), + Q6AFE_TDM_PB_DAI("Primary", 1, PRIMARY_TDM_RX_1), + Q6AFE_TDM_PB_DAI("Primary", 2, PRIMARY_TDM_RX_2), + Q6AFE_TDM_PB_DAI("Primary", 3, PRIMARY_TDM_RX_3), + Q6AFE_TDM_PB_DAI("Primary", 4, PRIMARY_TDM_RX_4), + Q6AFE_TDM_PB_DAI("Primary", 5, PRIMARY_TDM_RX_5), + Q6AFE_TDM_PB_DAI("Primary", 6, PRIMARY_TDM_RX_6), + Q6AFE_TDM_PB_DAI("Primary", 7, PRIMARY_TDM_RX_7), + Q6AFE_TDM_CAP_DAI("Primary", 0, PRIMARY_TDM_TX_0), + Q6AFE_TDM_CAP_DAI("Primary", 1, PRIMARY_TDM_TX_1), + Q6AFE_TDM_CAP_DAI("Primary", 2, PRIMARY_TDM_TX_2), + Q6AFE_TDM_CAP_DAI("Primary", 3, PRIMARY_TDM_TX_3), + Q6AFE_TDM_CAP_DAI("Primary", 4, PRIMARY_TDM_TX_4), + Q6AFE_TDM_CAP_DAI("Primary", 5, PRIMARY_TDM_TX_5), + Q6AFE_TDM_CAP_DAI("Primary", 6, PRIMARY_TDM_TX_6), + Q6AFE_TDM_CAP_DAI("Primary", 7, PRIMARY_TDM_TX_7), + Q6AFE_TDM_PB_DAI("Secondary", 0, SECONDARY_TDM_RX_0), + Q6AFE_TDM_PB_DAI("Secondary", 1, SECONDARY_TDM_RX_1), + Q6AFE_TDM_PB_DAI("Secondary", 2, SECONDARY_TDM_RX_2), + Q6AFE_TDM_PB_DAI("Secondary", 3, SECONDARY_TDM_RX_3), + Q6AFE_TDM_PB_DAI("Secondary", 4, SECONDARY_TDM_RX_4), + Q6AFE_TDM_PB_DAI("Secondary", 5, SECONDARY_TDM_RX_5), + Q6AFE_TDM_PB_DAI("Secondary", 6, SECONDARY_TDM_RX_6), + Q6AFE_TDM_PB_DAI("Secondary", 7, SECONDARY_TDM_RX_7), + Q6AFE_TDM_CAP_DAI("Secondary", 0, SECONDARY_TDM_TX_0), + Q6AFE_TDM_CAP_DAI("Secondary", 1, SECONDARY_TDM_TX_1), + Q6AFE_TDM_CAP_DAI("Secondary", 2, SECONDARY_TDM_TX_2), + Q6AFE_TDM_CAP_DAI("Secondary", 3, SECONDARY_TDM_TX_3), + Q6AFE_TDM_CAP_DAI("Secondary", 4, SECONDARY_TDM_TX_4), + Q6AFE_TDM_CAP_DAI("Secondary", 5, SECONDARY_TDM_TX_5), + Q6AFE_TDM_CAP_DAI("Secondary", 6, SECONDARY_TDM_TX_6), + Q6AFE_TDM_CAP_DAI("Secondary", 7, SECONDARY_TDM_TX_7), + Q6AFE_TDM_PB_DAI("Tertiary", 0, TERTIARY_TDM_RX_0), + Q6AFE_TDM_PB_DAI("Tertiary", 1, TERTIARY_TDM_RX_1), + Q6AFE_TDM_PB_DAI("Tertiary", 2, TERTIARY_TDM_RX_2), + Q6AFE_TDM_PB_DAI("Tertiary", 3, TERTIARY_TDM_RX_3), + Q6AFE_TDM_PB_DAI("Tertiary", 4, TERTIARY_TDM_RX_4), + Q6AFE_TDM_PB_DAI("Tertiary", 5, TERTIARY_TDM_RX_5), + Q6AFE_TDM_PB_DAI("Tertiary", 6, TERTIARY_TDM_RX_6), + Q6AFE_TDM_PB_DAI("Tertiary", 7, TERTIARY_TDM_RX_7), + Q6AFE_TDM_CAP_DAI("Tertiary", 0, TERTIARY_TDM_TX_0), + Q6AFE_TDM_CAP_DAI("Tertiary", 1, TERTIARY_TDM_TX_1), + Q6AFE_TDM_CAP_DAI("Tertiary", 2, TERTIARY_TDM_TX_2), + Q6AFE_TDM_CAP_DAI("Tertiary", 3, TERTIARY_TDM_TX_3), + Q6AFE_TDM_CAP_DAI("Tertiary", 4, TERTIARY_TDM_TX_4), + Q6AFE_TDM_CAP_DAI("Tertiary", 5, TERTIARY_TDM_TX_5), + Q6AFE_TDM_CAP_DAI("Tertiary", 6, TERTIARY_TDM_TX_6), + Q6AFE_TDM_CAP_DAI("Tertiary", 7, TERTIARY_TDM_TX_7), + Q6AFE_TDM_PB_DAI("Quaternary", 0, QUATERNARY_TDM_RX_0), + Q6AFE_TDM_PB_DAI("Quaternary", 1, QUATERNARY_TDM_RX_1), + Q6AFE_TDM_PB_DAI("Quaternary", 2, QUATERNARY_TDM_RX_2), + Q6AFE_TDM_PB_DAI("Quaternary", 3, QUATERNARY_TDM_RX_3), + Q6AFE_TDM_PB_DAI("Quaternary", 4, QUATERNARY_TDM_RX_4), + Q6AFE_TDM_PB_DAI("Quaternary", 5, QUATERNARY_TDM_RX_5), + Q6AFE_TDM_PB_DAI("Quaternary", 6, QUATERNARY_TDM_RX_6), + Q6AFE_TDM_PB_DAI("Quaternary", 7, QUATERNARY_TDM_RX_7), + Q6AFE_TDM_CAP_DAI("Quaternary", 0, QUATERNARY_TDM_TX_0), + Q6AFE_TDM_CAP_DAI("Quaternary", 1, QUATERNARY_TDM_TX_1), + Q6AFE_TDM_CAP_DAI("Quaternary", 2, QUATERNARY_TDM_TX_2), + Q6AFE_TDM_CAP_DAI("Quaternary", 3, QUATERNARY_TDM_TX_3), + Q6AFE_TDM_CAP_DAI("Quaternary", 4, QUATERNARY_TDM_TX_4), + Q6AFE_TDM_CAP_DAI("Quaternary", 5, QUATERNARY_TDM_TX_5), + Q6AFE_TDM_CAP_DAI("Quaternary", 6, QUATERNARY_TDM_TX_6), + Q6AFE_TDM_CAP_DAI("Quaternary", 7, QUATERNARY_TDM_TX_7), + Q6AFE_TDM_PB_DAI("Quinary", 0, QUINARY_TDM_RX_0), + Q6AFE_TDM_PB_DAI("Quinary", 1, QUINARY_TDM_RX_1), + Q6AFE_TDM_PB_DAI("Quinary", 2, QUINARY_TDM_RX_2), + Q6AFE_TDM_PB_DAI("Quinary", 3, QUINARY_TDM_RX_3), + Q6AFE_TDM_PB_DAI("Quinary", 4, QUINARY_TDM_RX_4), + Q6AFE_TDM_PB_DAI("Quinary", 5, QUINARY_TDM_RX_5), + Q6AFE_TDM_PB_DAI("Quinary", 6, QUINARY_TDM_RX_6), + Q6AFE_TDM_PB_DAI("Quinary", 7, QUINARY_TDM_RX_7), + Q6AFE_TDM_CAP_DAI("Quinary", 0, QUINARY_TDM_TX_0), + Q6AFE_TDM_CAP_DAI("Quinary", 1, QUINARY_TDM_TX_1), + Q6AFE_TDM_CAP_DAI("Quinary", 2, QUINARY_TDM_TX_2), + Q6AFE_TDM_CAP_DAI("Quinary", 3, QUINARY_TDM_TX_3), + Q6AFE_TDM_CAP_DAI("Quinary", 4, QUINARY_TDM_TX_4), + Q6AFE_TDM_CAP_DAI("Quinary", 5, QUINARY_TDM_TX_5), + Q6AFE_TDM_CAP_DAI("Quinary", 6, QUINARY_TDM_TX_6), + Q6AFE_TDM_CAP_DAI("Quinary", 7, QUINARY_TDM_TX_7), + { + .playback = { + .stream_name = "Display Port Playback", + .rates = SNDRV_PCM_RATE_48000 | + SNDRV_PCM_RATE_96000 | + SNDRV_PCM_RATE_192000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE, + .channels_min = 2, + .channels_max = 8, + .rate_max = 192000, + .rate_min = 48000, + }, + .id = DISPLAY_PORT_RX, + .name = "DISPLAY_PORT", + }, + Q6AFE_CDC_DMA_RX_DAI(WSA_CODEC_DMA_RX_0), + Q6AFE_CDC_DMA_TX_DAI(WSA_CODEC_DMA_TX_0), + Q6AFE_CDC_DMA_RX_DAI(WSA_CODEC_DMA_RX_1), + Q6AFE_CDC_DMA_TX_DAI(WSA_CODEC_DMA_TX_1), + Q6AFE_CDC_DMA_TX_DAI(WSA_CODEC_DMA_TX_2), + Q6AFE_CDC_DMA_TX_DAI(VA_CODEC_DMA_TX_0), + Q6AFE_CDC_DMA_TX_DAI(VA_CODEC_DMA_TX_1), + Q6AFE_CDC_DMA_TX_DAI(VA_CODEC_DMA_TX_2), + Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_0), + Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_0), + Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_1), + Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_1), + Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_2), + Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_2), + Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_3), + Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_3), + Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_4), + Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_4), + Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_5), + Q6AFE_CDC_DMA_TX_DAI(TX_CODEC_DMA_TX_5), + Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_6), + Q6AFE_CDC_DMA_RX_DAI(RX_CODEC_DMA_RX_7), +}; + +int q6dsp_audio_ports_of_xlate_dai_name(struct snd_soc_component *component, + const struct of_phandle_args *args, + const char **dai_name) +{ + int id = args->args[0]; + int ret = -EINVAL; + int i; + + for (i = 0; i < ARRAY_SIZE(q6dsp_audio_fe_dais); i++) { + if (q6dsp_audio_fe_dais[i].id == id) { + *dai_name = q6dsp_audio_fe_dais[i].name; + ret = 0; + break; + } + } + + return ret; +} +EXPORT_SYMBOL_GPL(q6dsp_audio_ports_of_xlate_dai_name); + +struct snd_soc_dai_driver *q6dsp_audio_ports_set_config(struct device *dev, + struct q6dsp_audio_port_dai_driver_config *cfg, + int *num_dais) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(q6dsp_audio_fe_dais); i++) { + q6dsp_audio_fe_dais[i].probe = cfg->probe; + q6dsp_audio_fe_dais[i].remove = cfg->remove; + + switch (q6dsp_audio_fe_dais[i].id) { + case HDMI_RX: + case DISPLAY_PORT_RX: + q6dsp_audio_fe_dais[i].ops = cfg->q6hdmi_ops; + break; + case SLIMBUS_0_RX ... SLIMBUS_6_TX: + q6dsp_audio_fe_dais[i].ops = cfg->q6slim_ops; + break; + case QUINARY_MI2S_RX ... QUINARY_MI2S_TX: + case PRIMARY_MI2S_RX ... QUATERNARY_MI2S_TX: + q6dsp_audio_fe_dais[i].ops = cfg->q6i2s_ops; + break; + case PRIMARY_TDM_RX_0 ... QUINARY_TDM_TX_7: + q6dsp_audio_fe_dais[i].ops = cfg->q6tdm_ops; + break; + case WSA_CODEC_DMA_RX_0 ... RX_CODEC_DMA_RX_7: + q6dsp_audio_fe_dais[i].ops = cfg->q6dma_ops; + break; + default: + break; + } + } + + *num_dais = ARRAY_SIZE(q6dsp_audio_fe_dais); + return q6dsp_audio_fe_dais; +} +EXPORT_SYMBOL_GPL(q6dsp_audio_ports_set_config); diff --git a/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.h b/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.h new file mode 100644 index 000000000000..7f052c8a1257 --- /dev/null +++ b/sound/soc/qcom/qdsp6/q6dsp-lpass-ports.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __Q6DSP_AUDIO_PORTS_H__ +#define __Q6DSP_AUDIO_PORTS_H__ + +struct q6dsp_audio_port_dai_driver_config { + int (*probe)(struct snd_soc_dai *dai); + int (*remove)(struct snd_soc_dai *dai); + const struct snd_soc_dai_ops *q6hdmi_ops; + const struct snd_soc_dai_ops *q6slim_ops; + const struct snd_soc_dai_ops *q6i2s_ops; + const struct snd_soc_dai_ops *q6tdm_ops; + const struct snd_soc_dai_ops *q6dma_ops; +}; + +struct snd_soc_dai_driver *q6dsp_audio_ports_set_config(struct device *dev, + struct q6dsp_audio_port_dai_driver_config *cfg, + int *num_dais); +int q6dsp_audio_ports_of_xlate_dai_name(struct snd_soc_component *component, + const struct of_phandle_args *args, + const char **dai_name); +#endif /* __Q6DSP_AUDIO_PORTS_H__ */ From patchwork Fri Sep 3 11:20:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 506514 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp906592jai; Fri, 3 Sep 2021 04:21:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzsWNhXGcxU7G0d5a0JIs6yj7iP/YV9zIMuY7DQsIzhByeragXZEzjmOBSGefZlVTXFGye4 X-Received: by 2002:a6b:b20c:: with SMTP id b12mr2616961iof.145.1630668113946; Fri, 03 Sep 2021 04:21:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1630668113; cv=none; d=google.com; s=arc-20160816; b=Ed+A7DrivVBL2Ov25pLEGE9JxOKkl5xf2UBwDyMQKhMyTT3hYMVg275ePIUwF+huxE dC+HBvTDS3IdxyX6Rf/I1/YPT0ylcPJWIFLxh++EWUw4IkhiQA/qns7EYvm1l5WUYfls 3VDSKiHQ+jSt+fesZUg/C90gqSLo5WAvz7Q4gkowAG2QEqfd8I961BWDh/ylp3OMUDgf vJznzSGKgdnsO6Qip1Gip1R3B2QfN2/vVDnDFDbQci1dWYoq93YJhHCKRh704h4962nE 76/yTKJoMJRwRwkDHhj7COthrSBE8xBk8yfQLt6fvEGPAB1G6ItYlSqXqB4zUDycRjUH /Hag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=P/GrQum7HqFjwAP4vzAUmK4U+IxXkHWKdXR4vGSO5YU=; b=cBE6Y4NKoSf/RkvpP6VJ/Z6DWqr9LKt3oeQgL8eBljJJavBVO6q92h8bjq4qIpSd2S wu6mSUiPqU6oZnubztlNAoiLxbmt6ZkO33Am0p2uTe0N81L4fVHS/A4/QQD5h6zUAEWK AlLEFJFvLUHGDxXDWK9JY01gb9V80U0WMvjP7TKbYlqYBAjgTZm5FvaXK/McB6swjYei BQIrxRRNh1+KFmjRqyYidjNiMKeNBn/Z4SqDsSe8MhX7akQ+J7zCsb7sSytr+BwYrBdY rbQCC9pfIL+bJs0dmrfDAMuRbRKB+I6wxOKGOHuT2Ac6x1ufhVg+GPnEt94zRkvULdw0 BtCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ifKAFuwC; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:44 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 10/21] ASoC: qdsp6: q6afe-clocks: move audio-clocks to common file Date: Fri, 3 Sep 2021 12:20:21 +0100 Message-Id: <20210903112032.25834-11-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Move common parts of q6afe-clocks to q6dsp-lpass-clocks so that we could reuse most of the driver for new Q6DSP audio frameworks. This is to make the code reuseable for new Q6DSP AudioReach framework. Signed-off-by: Srinivas Kandagatla --- sound/soc/qcom/qdsp6/Makefile | 2 +- sound/soc/qcom/qdsp6/q6afe-clocks.c | 187 ++-------------------- sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c | 186 +++++++++++++++++++++ sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.h | 30 ++++ 4 files changed, 232 insertions(+), 173 deletions(-) create mode 100644 sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c create mode 100644 sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.h -- 2.21.0 Reported-by: kernel test robot diff --git a/sound/soc/qcom/qdsp6/Makefile b/sound/soc/qcom/qdsp6/Makefile index 11e8705bbc5c..a4191d395557 100644 --- a/sound/soc/qcom/qdsp6/Makefile +++ b/sound/soc/qcom/qdsp6/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -snd-q6dsp-common-objs := q6dsp-common.o q6dsp-lpass-ports.o +snd-q6dsp-common-objs := q6dsp-common.o q6dsp-lpass-ports.o q6dsp-lpass-clocks.o obj-$(CONFIG_SND_SOC_QDSP6_COMMON) += snd-q6dsp-common.o obj-$(CONFIG_SND_SOC_QDSP6_CORE) += q6core.o diff --git a/sound/soc/qcom/qdsp6/q6afe-clocks.c b/sound/soc/qcom/qdsp6/q6afe-clocks.c index 9431656283cd..0eddba7895db 100644 --- a/sound/soc/qcom/qdsp6/q6afe-clocks.c +++ b/sound/soc/qcom/qdsp6/q6afe-clocks.c @@ -7,115 +7,18 @@ #include #include #include -#include -#include +#include "q6dsp-lpass-clocks.h" #include "q6afe.h" #define Q6AFE_CLK(id) { \ .clk_id = id, \ - .afe_clk_id = Q6AFE_##id, \ + .q6dsp_clk_id = Q6AFE_##id, \ .name = #id, \ .rate = 19200000, \ } -#define Q6AFE_VOTE_CLK(id, blkid, n) { \ - .clk_id = id, \ - .afe_clk_id = blkid, \ - .name = n, \ - } - -struct q6afe_clk_init { - int clk_id; - int afe_clk_id; - char *name; - int rate; -}; - -struct q6afe_clk { - struct device *dev; - int afe_clk_id; - int attributes; - int rate; - uint32_t handle; - struct clk_hw hw; -}; - -#define to_q6afe_clk(_hw) container_of(_hw, struct q6afe_clk, hw) - -struct q6afe_cc { - struct device *dev; - struct q6afe_clk *clks[Q6AFE_MAX_CLK_ID]; -}; - -static int clk_q6afe_prepare(struct clk_hw *hw) -{ - struct q6afe_clk *clk = to_q6afe_clk(hw); - - return q6afe_set_lpass_clock(clk->dev, clk->afe_clk_id, clk->attributes, - Q6AFE_LPASS_CLK_ROOT_DEFAULT, clk->rate); -} - -static void clk_q6afe_unprepare(struct clk_hw *hw) -{ - struct q6afe_clk *clk = to_q6afe_clk(hw); - - q6afe_set_lpass_clock(clk->dev, clk->afe_clk_id, clk->attributes, - Q6AFE_LPASS_CLK_ROOT_DEFAULT, 0); -} - -static int clk_q6afe_set_rate(struct clk_hw *hw, unsigned long rate, - unsigned long parent_rate) -{ - struct q6afe_clk *clk = to_q6afe_clk(hw); - - clk->rate = rate; - - return 0; -} - -static unsigned long clk_q6afe_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) -{ - struct q6afe_clk *clk = to_q6afe_clk(hw); - - return clk->rate; -} - -static long clk_q6afe_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) -{ - return rate; -} - -static const struct clk_ops clk_q6afe_ops = { - .prepare = clk_q6afe_prepare, - .unprepare = clk_q6afe_unprepare, - .set_rate = clk_q6afe_set_rate, - .round_rate = clk_q6afe_round_rate, - .recalc_rate = clk_q6afe_recalc_rate, -}; - -static int clk_vote_q6afe_block(struct clk_hw *hw) -{ - struct q6afe_clk *clk = to_q6afe_clk(hw); - - return q6afe_vote_lpass_core_hw(clk->dev, clk->afe_clk_id, - clk_hw_get_name(&clk->hw), &clk->handle); -} -static void clk_unvote_q6afe_block(struct clk_hw *hw) -{ - struct q6afe_clk *clk = to_q6afe_clk(hw); - - q6afe_unvote_lpass_core_hw(clk->dev, clk->afe_clk_id, clk->handle); -} - -static const struct clk_ops clk_vote_q6afe_ops = { - .prepare = clk_vote_q6afe_block, - .unprepare = clk_unvote_q6afe_block, -}; - -static const struct q6afe_clk_init q6afe_clks[] = { +static const struct q6dsp_clk_init q6afe_clks[] = { Q6AFE_CLK(LPASS_CLK_ID_PRI_MI2S_IBIT), Q6AFE_CLK(LPASS_CLK_ID_PRI_MI2S_EBIT), Q6AFE_CLK(LPASS_CLK_ID_SEC_MI2S_IBIT), @@ -176,88 +79,28 @@ static const struct q6afe_clk_init q6afe_clks[] = { Q6AFE_CLK(LPASS_CLK_ID_RX_CORE_MCLK), Q6AFE_CLK(LPASS_CLK_ID_RX_CORE_NPL_MCLK), Q6AFE_CLK(LPASS_CLK_ID_VA_CORE_2X_MCLK), - Q6AFE_VOTE_CLK(LPASS_HW_AVTIMER_VOTE, + Q6DSP_VOTE_CLK(LPASS_HW_AVTIMER_VOTE, Q6AFE_LPASS_CORE_AVTIMER_BLOCK, "LPASS_AVTIMER_MACRO"), - Q6AFE_VOTE_CLK(LPASS_HW_MACRO_VOTE, + Q6DSP_VOTE_CLK(LPASS_HW_MACRO_VOTE, Q6AFE_LPASS_CORE_HW_MACRO_BLOCK, "LPASS_HW_MACRO"), - Q6AFE_VOTE_CLK(LPASS_HW_DCODEC_VOTE, + Q6DSP_VOTE_CLK(LPASS_HW_DCODEC_VOTE, Q6AFE_LPASS_CORE_HW_DCODEC_BLOCK, "LPASS_HW_DCODEC"), }; -static struct clk_hw *q6afe_of_clk_hw_get(struct of_phandle_args *clkspec, - void *data) -{ - struct q6afe_cc *cc = data; - unsigned int idx = clkspec->args[0]; - unsigned int attr = clkspec->args[1]; - - if (idx >= Q6AFE_MAX_CLK_ID || attr > LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR) { - dev_err(cc->dev, "Invalid clk specifier (%d, %d)\n", idx, attr); - return ERR_PTR(-EINVAL); - } - - if (cc->clks[idx]) { - cc->clks[idx]->attributes = attr; - return &cc->clks[idx]->hw; - } - - return ERR_PTR(-ENOENT); -} - -static int q6afe_clock_dev_probe(struct platform_device *pdev) -{ - struct q6afe_cc *cc; - struct device *dev = &pdev->dev; - int i, ret; - - cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL); - if (!cc) - return -ENOMEM; - - cc->dev = dev; - for (i = 0; i < ARRAY_SIZE(q6afe_clks); i++) { - unsigned int id = q6afe_clks[i].clk_id; - struct clk_init_data init = { - .name = q6afe_clks[i].name, - }; - struct q6afe_clk *clk; - - clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL); - if (!clk) - return -ENOMEM; - - clk->dev = dev; - clk->afe_clk_id = q6afe_clks[i].afe_clk_id; - clk->rate = q6afe_clks[i].rate; - clk->hw.init = &init; - - if (clk->rate) - init.ops = &clk_q6afe_ops; - else - init.ops = &clk_vote_q6afe_ops; - - cc->clks[id] = clk; - - ret = devm_clk_hw_register(dev, &clk->hw); - if (ret) - return ret; - } - - ret = devm_of_clk_add_hw_provider(dev, q6afe_of_clk_hw_get, cc); - if (ret) - return ret; - - dev_set_drvdata(dev, cc); - - return 0; -} +static const struct q6dsp_clk_desc q6dsp_clk_q6afe = { + .clks = q6afe_clks, + .num_clks = ARRAY_SIZE(q6afe_clks), + .lpass_set_clk = q6afe_set_lpass_clock, + .lpass_vote_clk = q6afe_vote_lpass_core_hw, + .lpass_unvote_clk = q6afe_unvote_lpass_core_hw, +}; #ifdef CONFIG_OF static const struct of_device_id q6afe_clock_device_id[] = { - { .compatible = "qcom,q6afe-clocks" }, + { .compatible = "qcom,q6afe-clocks", .data = &q6dsp_clk_q6afe }, {}, }; MODULE_DEVICE_TABLE(of, q6afe_clock_device_id); @@ -268,7 +111,7 @@ static struct platform_driver q6afe_clock_platform_driver = { .name = "q6afe-clock", .of_match_table = of_match_ptr(q6afe_clock_device_id), }, - .probe = q6afe_clock_dev_probe, + .probe = q6dsp_clock_dev_probe, }; module_platform_driver(q6afe_clock_platform_driver); diff --git a/sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c b/sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c new file mode 100644 index 000000000000..4613867d1133 --- /dev/null +++ b/sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2020, Linaro Limited + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "q6dsp-lpass-clocks.h" + +#define Q6DSP_MAX_CLK_ID 104 +#define Q6DSP_LPASS_CLK_ROOT_DEFAULT 0 + + +struct q6dsp_clk { + struct device *dev; + int q6dsp_clk_id; + int attributes; + int rate; + uint32_t handle; + struct clk_hw hw; +}; + +#define to_q6dsp_clk(_hw) container_of(_hw, struct q6dsp_clk, hw) + +struct q6dsp_cc { + struct device *dev; + struct q6dsp_clk *clks[Q6DSP_MAX_CLK_ID]; + const struct q6dsp_clk_desc *desc; +}; + +static int clk_q6dsp_prepare(struct clk_hw *hw) +{ + struct q6dsp_clk *clk = to_q6dsp_clk(hw); + struct q6dsp_cc *cc = dev_get_drvdata(clk->dev); + + return cc->desc->lpass_set_clk(clk->dev, clk->q6dsp_clk_id, clk->attributes, + Q6DSP_LPASS_CLK_ROOT_DEFAULT, clk->rate); +} + +static void clk_q6dsp_unprepare(struct clk_hw *hw) +{ + struct q6dsp_clk *clk = to_q6dsp_clk(hw); + struct q6dsp_cc *cc = dev_get_drvdata(clk->dev); + + cc->desc->lpass_set_clk(clk->dev, clk->q6dsp_clk_id, clk->attributes, + Q6DSP_LPASS_CLK_ROOT_DEFAULT, 0); +} + +static int clk_q6dsp_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct q6dsp_clk *clk = to_q6dsp_clk(hw); + + clk->rate = rate; + + return 0; +} + +static unsigned long clk_q6dsp_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct q6dsp_clk *clk = to_q6dsp_clk(hw); + + return clk->rate; +} + +static long clk_q6dsp_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + return rate; +} + +static const struct clk_ops clk_q6dsp_ops = { + .prepare = clk_q6dsp_prepare, + .unprepare = clk_q6dsp_unprepare, + .set_rate = clk_q6dsp_set_rate, + .round_rate = clk_q6dsp_round_rate, + .recalc_rate = clk_q6dsp_recalc_rate, +}; + +static int clk_vote_q6dsp_block(struct clk_hw *hw) +{ + struct q6dsp_clk *clk = to_q6dsp_clk(hw); + struct q6dsp_cc *cc = dev_get_drvdata(clk->dev); + + return cc->desc->lpass_vote_clk(clk->dev, clk->q6dsp_clk_id, + clk_hw_get_name(&clk->hw), &clk->handle); +} + +static void clk_unvote_q6dsp_block(struct clk_hw *hw) +{ + struct q6dsp_clk *clk = to_q6dsp_clk(hw); + struct q6dsp_cc *cc = dev_get_drvdata(clk->dev); + + cc->desc->lpass_unvote_clk(clk->dev, clk->q6dsp_clk_id, clk->handle); +} + +static const struct clk_ops clk_vote_q6dsp_ops = { + .prepare = clk_vote_q6dsp_block, + .unprepare = clk_unvote_q6dsp_block, +}; + + +static struct clk_hw *q6dsp_of_clk_hw_get(struct of_phandle_args *clkspec, + void *data) +{ + struct q6dsp_cc *cc = data; + unsigned int idx = clkspec->args[0]; + unsigned int attr = clkspec->args[1]; + + if (idx >= Q6DSP_MAX_CLK_ID || attr > LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR) { + dev_err(cc->dev, "Invalid clk specifier (%d, %d)\n", idx, attr); + return ERR_PTR(-EINVAL); + } + + if (cc->clks[idx]) { + cc->clks[idx]->attributes = attr; + return &cc->clks[idx]->hw; + } + + return ERR_PTR(-ENOENT); +} + +int q6dsp_clock_dev_probe(struct platform_device *pdev) +{ + struct q6dsp_cc *cc; + struct device *dev = &pdev->dev; + const struct q6dsp_clk_init *q6dsp_clks; + const struct q6dsp_clk_desc *desc; + int i, ret; + + cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL); + if (!cc) + return -ENOMEM; + + desc = of_device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + + cc->desc = desc; + cc->dev = dev; + q6dsp_clks = desc->clks; + + for (i = 0; i < desc->num_clks; i++) { + unsigned int id = q6dsp_clks[i].clk_id; + struct clk_init_data init = { + .name = q6dsp_clks[i].name, + }; + struct q6dsp_clk *clk; + + clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL); + if (!clk) + return -ENOMEM; + + clk->dev = dev; + clk->q6dsp_clk_id = q6dsp_clks[i].q6dsp_clk_id; + clk->rate = q6dsp_clks[i].rate; + clk->hw.init = &init; + + if (clk->rate) + init.ops = &clk_q6dsp_ops; + else + init.ops = &clk_vote_q6dsp_ops; + + cc->clks[id] = clk; + + ret = devm_clk_hw_register(dev, &clk->hw); + if (ret) + return ret; + } + + ret = devm_of_clk_add_hw_provider(dev, q6dsp_of_clk_hw_get, cc); + if (ret) + return ret; + + dev_set_drvdata(dev, cc); + + return 0; +} +EXPORT_SYMBOL_GPL(q6dsp_clock_dev_probe); diff --git a/sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.h b/sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.h new file mode 100644 index 000000000000..3770d81f2bd6 --- /dev/null +++ b/sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __Q6DSP_AUDIO_CLOCKS_H__ +#define __Q6DSP_AUDIO_CLOCKS_H__ + +struct q6dsp_clk_init { + int clk_id; + int q6dsp_clk_id; + char *name; + int rate; +}; + +#define Q6DSP_VOTE_CLK(id, blkid, n) { \ + .clk_id = id, \ + .q6dsp_clk_id = blkid, \ + .name = n, \ + } + +struct q6dsp_clk_desc { + const struct q6dsp_clk_init *clks; + size_t num_clks; + int (*lpass_set_clk)(struct device *dev, int clk_id, int attr, + int root_clk, unsigned int freq); + int (*lpass_vote_clk)(struct device *dev, uint32_t hid, const char *n, uint32_t *h); + int (*lpass_unvote_clk)(struct device *dev, uint32_t hid, uint32_t h); +}; + +int q6dsp_clock_dev_probe(struct platform_device *pdev); + +#endif /* __Q6DSP_AUDIO_CLOCKS_H__ */ From patchwork Fri Sep 3 11:20:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 506517 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp906613jai; Fri, 3 Sep 2021 04:21:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzRHfNmdSnAXYAALOXv1QMMjVynWjOD3aekfM2hkRYiXjPRytlcav6hiFdGTzP6eyToB/ZC X-Received: by 2002:a05:6638:34a6:: with SMTP id t38mr2214054jal.19.1630668115232; Fri, 03 Sep 2021 04:21:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1630668115; cv=none; d=google.com; s=arc-20160816; b=lfxC3eEeSyG4NB96OA+TouYuD97qG3YnaWfZNTThXxxK/eIvLGT1vCBOuisDsdBrOX 3y6AkgKiRzhfvkOrKM5O9JmmFXySPbPRe8wgp8ok468r8GATkGDrR18W39ij9cpZLNPg gpznTlDO16liDDihO41ftMEE9y57CoB40DzSPOJRKT443VezMQJQW2dTX2uVoNUmw37l QhNDPO3A3FuooqqTUdW9nnfoGP5lOZ+naEw0sMOLR/JSO1ZfSRMvsSqEOrf8V8dmZP+d 0s1Y4lZmHdjD/3QJjsxbIXAplk2lCMhLij/b7emAz1jD01zXDHCFz3YVxY+vkGJbiyXR lcZg== ARC-Message-Signature: i=1; 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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:45 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 11/21] ASoC: dt-bindings: q6dsp: add q6apm-lpass-dai compatible Date: Fri, 3 Sep 2021 12:20:22 +0100 Message-Id: <20210903112032.25834-12-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org on AudioReach audio Framework access to LPASS ports is via Q6APM(Audio Process Manager) service, so add a dedicated compatible string for this. Signed-off-by: Srinivas Kandagatla --- .../sound/qcom,q6dsp-lpass-ports.yaml | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) -- 2.21.0 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml index e6148c17419b..92a641dfe04f 100644 --- a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml @@ -16,6 +16,7 @@ properties: compatible: enum: - qcom,q6afe-dais + - qcom,q6apm-lpass-dais reg: maxItems: 1 @@ -169,6 +170,29 @@ examples: #size-cells = <0>; #sound-dai-cells = <1>; + dai@22 { + reg = ; + qcom,sd-lines = <0 1 2 3>; + }; + }; + }; + }; + - | + #include + gpr { + #address-cells = <1>; + #size-cells = <0>; + gpr-service@1 { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + q6apmdai@1 { + compatible = "qcom,q6apm-lpass-dais"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + dai@22 { reg = ; qcom,sd-lines = <0 1 2 3>; From patchwork Fri Sep 3 11:20:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 506515 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp906598jai; Fri, 3 Sep 2021 04:21:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxryGa14932sg+hS5jtTBp1vyQvGiai6408ens8GqsjSdfyGYJHcncYy5hWh3VEUevM2Uic X-Received: by 2002:a05:6e02:1094:: with SMTP id r20mr2165013ilj.55.1630668114436; Fri, 03 Sep 2021 04:21:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1630668114; cv=none; d=google.com; s=arc-20160816; b=v4r3l9UkDMUTZgghGOMnsCn8zfK4UtV42MVzW4fq9udu86yQjQEKO3AXgEdgLH9E19 a9eRj4Bw2fa18WWEuJCLIyvFe5v/zXjZS2bM3+o0HUt5GTXioZZeCw2KFMdGHmkda698 MB8YA5mPmq3jyZVbjdsEjZ6/1V37lGXQe+qoGsti4m0JsmC5GzrRdVpbHNe3YbE7U1uB xiO+rHIVXDIJsn6mefRIuXnJ7NSWc1ZYPS1gORkUPtLrzji8CCEgoFMTVSSM3tQ5qGaT qGG+yqMePZUERgnoUNzILrbUodPKOWuEGEo+ipdamkI123e2Ak4ua5LGd/T0q+IpFimF ILEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XrcdWigOrJBOqNH3/v+b+R+GIipVI1XmPMk0yejMbMo=; b=Soef1qT0PmzYjmcNltZ3ctP2zMoyrs9PM7Xd7N8x/58IVUdAB81DHN9FiDswlySWD/ mKr6mOzHbGa0wjMtEokGbT1+V8LbXtcHH/DHr+I7RTdFENeqHkdHSoNHLMLHkh/WgvLd NhcgoPz1B71bFw1TQy5/rXbFt51BzlOMc9e3N0MHSWq13EOK16POpmmbviYoyBivVG5o UnQx8bL9L3o/JhYdjaIzORzBCcW6Qy9O100ke682VcjtpIrgq3pzSY4wYisO9DLyTPxT UMTnoVUE0BfC/YnvBBUkccufYmNQlJUbDCH9k0gc7ObGMfh6tu0rehOWbjbFfpMZ7pL2 8/XQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=m3dU1nsk; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:46 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 12/21] ASoC: dt-bindings: lpass-clocks: add q6prm clocks compatible Date: Fri, 3 Sep 2021 12:20:23 +0100 Message-Id: <20210903112032.25834-13-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On AudioReach audio Framework access to LPASS ports is via Q6PRM (Proxy Resource Manager) service, so add a dedicated lpass-clock compatible string for this. Signed-off-by: Srinivas Kandagatla --- .../sound/qcom,q6dsp-lpass-clocks.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) -- 2.21.0 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml index 589c3f1e2008..9f3de2307d1c 100644 --- a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml @@ -16,6 +16,7 @@ properties: compatible: enum: - qcom,q6afe-clocks + - qcom,q6prm-lpass-clocks reg: maxItems: 1 @@ -54,3 +55,20 @@ examples: }; }; }; + + - | + #include + gpr { + #address-cells = <1>; + #size-cells = <0>; + gpr-service@2 { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + q6prmcc@2 { + compatible = "qcom,q6prm-lpass-clocks"; + reg = <2>; + #clock-cells = <2>; + }; + }; + }; From patchwork Fri Sep 3 11:20:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 506516 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp906610jai; Fri, 3 Sep 2021 04:21:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyhuX45MjN7qkZKbJWMFJOC2fvcqZuwUX7EyYdlWXxTpcOIQjZ4NMJIwN2Yncs+PJkwrn5G X-Received: by 2002:a02:cebc:: with SMTP id z28mr2233706jaq.49.1630668114865; Fri, 03 Sep 2021 04:21:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1630668114; cv=none; d=google.com; s=arc-20160816; b=qXpllWnpjZ08Gl/eES2pDwAtynTQMmvSM9eTnOx6ZbANG5StQ1KDSL3Re1s3tp+RHn xv/w6i4isGJbA01U9bPa0SjKf6Udnn9aS2I5MOR68b3N68gJ00+614ENncRkeNZ2RB2y ay7vQ3ZDatLTfvG8umUzXH8hWdhVZbkfjIeWz7TrU/EJaXKvQtHMQrBxrQt8PtulyI2u IZBggPtPeOfi644b1/PVvv2Q4sQggVP7izLDBUEL/nKzH5PODYcjl8MXB4py6Hj2EU7W 6qtsqL8EGuUANgkxpb1yu+vwBde9FuZMiTROlGHaiequZY03RefYk414KxYCONtYYoh3 TIfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=RwkBekoVHbR6mINfcBzFLlTHGm7nkcct6qC3KOCM4UE=; b=hLhFRfMFgfJM+GzR5U/+jCBdelwrplyHs0EPM/ULL47O2bZ2AT3U4cl6Pxqeu5UZLE YJ/12IExKrKGtodoegp92+s7eWO6ce7XgHDZtsSO3xotJzQ+jhHbShoJ0siWOYCsa7Rk ecaY2o/z36fzD5LoJCCZg/34ezKpyPdIZGZYktZrUXL9E2JK1ni/I5WtZ887awkycpJj dbX5t8OcnzM3s/EUF1YUEhEDt0+rTqyDuqI6qn8aBV3nNFxjx44VQ/q6+9ON0prU/T8F GAhW7vMzr/Ys1yAU7XY0yKURA91iIfxqwzO0J4IpLCtzMaDzjEg47kBV/WpUehcbJuFT 934g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nnDuaGdz; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:48 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 13/21] ASoC: dt-bindings: add q6apm digital audio stream bindings Date: Fri, 3 Sep 2021 12:20:24 +0100 Message-Id: <20210903112032.25834-14-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On AudioReach audio Framework, Audio Streams (PCM/Compressed) are managed by Q6APM(Audio Process Manager) service. This patch adds bindings for this DAIs exposed by the DSP. Signed-off-by: Srinivas Kandagatla --- .../bindings/sound/qcom,q6apm-dai.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml -- 2.21.0 diff --git a/Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml b/Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml new file mode 100644 index 000000000000..75431d1c0b2a --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/sound/qcom,q6apm-dai.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Audio Process Manager Digital Audio Interfaces binding + +maintainers: + - Srinivas Kandagatla + +description: | + This binding describes the Qualcomm APM DAIs in DSP + +properties: + compatible: + const: qcom,q6apm-dais + + reg: + maxItems: 1 + + iommus: + maxItems: 1 + +required: + - compatible + - iommus + - reg + +additionalProperties: false + +examples: + - | + gpr { + #address-cells = <1>; + #size-cells = <0>; + gprservice@1 { + compatible = "qcom,q6apm"; + reg = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + apm@1 { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1801 0x0>; + reg = <1>; + }; + }; + }; From patchwork Fri Sep 3 11:20:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 506518 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp906620jai; Fri, 3 Sep 2021 04:21:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyDqKF2nvdgGKT7cydakeJOGTwzm9uq4EM2hhcnw4uSJB/jIX2lRVbNeVggd/iHYxbCYHpi X-Received: by 2002:a6b:f114:: with SMTP id e20mr2636463iog.41.1630668115590; Fri, 03 Sep 2021 04:21:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1630668115; cv=none; d=google.com; s=arc-20160816; b=yvBy82toEXfmbOsnbh8Q/2r3E7/EtddK7E9hnK8Jd4sb8cD7xgEO5Tdou9urAPexLx D9/Q7C5alWwqOCjHB7rx4eBZmyEs3ddPrP0SP7fQKJncsH2MjFnvmFw2CaNSX7yQvq/D nYZndsy3X5dBZRAUGsrDibmQOP1HmMU6RUMgo8BByxLtGBMpS3nxXSVEWa/n5fK9yiFe bqfsTxlxH4uqmW8u1f6ZcQzO4USpuPVkUgffnTeVjt4cKvx5+SHt9iec/Kx8sZHZKRG6 mAICLzIvsVNehc43iqz/ILA0OGPCLkRpBnzFOIsvhqk9Xjeiip/+UksV3SwQfW6x7jCo 1J4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mdHSOtZKZi82k5x9arR8GnQETBTJJBRQLGJNM4JkJJM=; b=EjfWkkEP+RdVhohscfYTSywDMHGzNe/6LiBZHE+aVDiZEpwJaRd+dxOorPmUPSbGkb CDtjZ59xCPcHJE+koltkxR/y8VKSImFfQ8jmUIk1EOb8jYAteNVw/hFZcedrHVzRTm0R v9/jHeEVCn75D3ZDgRHDqrCatQuKuWggAOopnTfKxcGSkHzQrkTQi8EtEnwXMqeiSoGL zWdBhh73dKcRod+5iGnW0stka2aNelxuibEF2iqkYQL08ABN0icoJhdBkOgewxZmLREA 6m/aB2LFDLOafr/3VINh3FMPi+siZBgxzd7QUDIZL5mP64zllktfzcTSggGD+RFLhsUa uvRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="X/xFSydO"; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:49 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 14/21] ASoC: qdsp6: audioreach: add basic pkt alloc support Date: Fri, 3 Sep 2021 12:20:25 +0100 Message-Id: <20210903112032.25834-15-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add basic helper functions for AudioReach. Signed-off-by: Srinivas Kandagatla --- sound/soc/qcom/qdsp6/audioreach.c | 277 +++++++++++++ sound/soc/qcom/qdsp6/audioreach.h | 636 ++++++++++++++++++++++++++++++ 2 files changed, 913 insertions(+) create mode 100644 sound/soc/qcom/qdsp6/audioreach.c create mode 100644 sound/soc/qcom/qdsp6/audioreach.h -- 2.21.0 diff --git a/sound/soc/qcom/qdsp6/audioreach.c b/sound/soc/qcom/qdsp6/audioreach.c new file mode 100644 index 000000000000..8e9a19a9d614 --- /dev/null +++ b/sound/soc/qcom/qdsp6/audioreach.c @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2020, Linaro Limited + +#include +#include +#include +#include +#include "audioreach.h" + +/* SubGraph Config */ +struct apm_sub_graph_data { + struct apm_sub_graph_cfg sub_graph_cfg; + struct apm_prop_data perf_data; + struct apm_sg_prop_id_perf_mode perf; + struct apm_prop_data dir_data; + struct apm_sg_prop_id_direction dir; + struct apm_prop_data sid_data; + struct apm_sg_prop_id_scenario_id sid; + +} __packed; + +#define APM_SUB_GRAPH_CFG_NPROP 3 + +struct apm_sub_graph_params { + struct apm_module_param_data param_data; + uint32_t num_sub_graphs; + struct apm_sub_graph_data sg_cfg[0]; +} __packed; + +#define APM_SUB_GRAPH_PSIZE(n) ALIGN(sizeof(struct apm_sub_graph_params) + \ + n * sizeof(struct apm_sub_graph_data), 8) +/* container config */ +struct apm_container_obj { + struct apm_container_cfg container_cfg; + /* Capability ID list */ + struct apm_prop_data cap_data; + uint32_t num_capablity_id; + uint32_t capability_id; + + /* Container graph Position */ + struct apm_prop_data pos_data; + struct apm_cont_prop_id_graph_pos pos; + + /* Container Stack size */ + struct apm_prop_data stack_data; + struct apm_cont_prop_id_stack_size stack; + + /* Container proc domain id */ + struct apm_prop_data domain_data; + struct apm_cont_prop_id_domain domain; +} __packed; + +struct apm_container_params { + struct apm_module_param_data param_data; + uint32_t num_containers; + struct apm_container_obj cont_obj[0]; +} __packed; + +#define APM_CONTAINER_PSIZE(n) ALIGN(sizeof(struct apm_container_params) + \ + n * sizeof(struct apm_container_obj), 8) + +/* Module List config */ +struct apm_mod_list_obj { + /* Modules list cfg */ + uint32_t sub_graph_id; + uint32_t container_id; + uint32_t num_modules; + struct apm_module_obj mod_cfg[0]; +} __packed; + +struct apm_module_list_params { + struct apm_module_param_data param_data; + uint32_t num_modules_list; + /* Module list config array */ + struct apm_mod_list_obj mod_list_obj[0]; + +} __packed; + +#define APM_MOD_LIST_OBJ_PSIZE(m) (sizeof(struct apm_mod_list_obj) + \ + m * sizeof(struct apm_module_obj)) + +/* n modules list m mod per list */ +#define APM_MOD_LIST_PSIZE(n, m) ALIGN(sizeof(struct apm_module_list_params) + \ + n * (sizeof(struct apm_mod_list_obj) + \ + m * sizeof(struct apm_module_obj)), 8) + +/* Module Properties */ +struct apm_mod_prop_obj { + u32 instance_id; + u32 num_props; + struct apm_prop_data prop_data_1; + struct apm_module_prop_id_port_info prop_id_port; +} __packed; + +struct apm_prop_list_params { + struct apm_module_param_data param_data; + u32 num_modules_prop_cfg; + struct apm_mod_prop_obj mod_prop_obj[0]; + +} __packed; + +#define APM_MOD_PROP_PSIZE(n) ALIGN(sizeof(struct apm_prop_list_params) + \ + n * sizeof(struct apm_mod_prop_obj), 8) + +/* Module Connections */ +struct apm_mod_conn_list_params { + struct apm_module_param_data param_data; + u32 num_connections; + struct apm_module_conn_obj conn_obj[0]; + +} __packed; + +#define APM_MOD_CONN_PSIZE(n) ALIGN(sizeof(struct apm_mod_conn_list_params) + \ + n * sizeof(struct apm_module_conn_obj), 8) + +struct apm_graph_open_params { + struct apm_cmd_header *cmd_header; + struct apm_sub_graph_params *sg_data; + struct apm_container_params *cont_data; + struct apm_module_list_params *mod_list_data; + struct apm_prop_list_params *mod_prop_data; + struct apm_mod_conn_list_params *mod_conn_list_data; +} __packed; + +struct apm_pcm_module_media_fmt_cmd { + struct apm_module_param_data param_data; + struct param_id_pcm_output_format_cfg header; + struct payload_pcm_output_format_cfg media_cfg; +} __packed; + +struct apm_rd_shmem_module_config_cmd { + struct apm_module_param_data param_data; + struct param_id_rd_sh_mem_cfg cfg; +} __packed; + +struct apm_sh_module_media_fmt_cmd { + struct media_format header; + struct payload_media_fmt_pcm cfg; +} __packed; + +#define APM_SHMEM_FMT_CFG_PSIZE(n) ALIGN( \ + sizeof(struct apm_sh_module_media_fmt_cmd) + \ + n * sizeof(uint8_t), 8) + +/* num of channels as argument */ +#define APM_PCM_MODULE_FMT_CMD_PSIZE(n) ALIGN( \ + sizeof(struct apm_pcm_module_media_fmt_cmd) + \ + n * sizeof(uint8_t), 8) +#define APM_PCM_OUT_FMT_CFG_PSIZE(n) ALIGN((sizeof( \ + struct payload_pcm_output_format_cfg) + \ + n * sizeof(uint8_t)), 4) + +struct apm_i2s_module_intf_cfg { + struct apm_module_param_data param_data; + struct param_id_i2s_intf_cfg cfg; +} __packed; +#define APM_I2S_INTF_CFG_PSIZE ALIGN(sizeof(struct apm_i2s_module_intf_cfg), \ + 8) + +struct apm_module_hw_ep_mf_cfg { + struct apm_module_param_data param_data; + struct param_id_hw_ep_mf mf; +} __packed; +#define APM_HW_EP_CFG_PSIZE ALIGN( \ + sizeof(struct apm_module_hw_ep_mf_cfg), \ + 8) + +struct apm_module_frame_size_factor_cfg { + struct apm_module_param_data param_data; + uint32_t frame_size_factor; +} __packed; +#define APM_FS_CFG_PSIZE ALIGN( \ + sizeof(struct apm_module_frame_size_factor_cfg), \ + 8) + +struct apm_module_hw_ep_power_mode_cfg { + struct apm_module_param_data param_data; + struct param_id_hw_ep_power_mode_cfg power_mode; +} __packed; +#define APM_HW_EP_PMODE_CFG_PSIZE ALIGN( \ + sizeof(struct apm_module_hw_ep_power_mode_cfg), \ + 8) + +struct apm_module_hw_ep_dma_data_align_cfg { + struct apm_module_param_data param_data; + struct param_id_hw_ep_dma_data_align align; +} __packed; +#define APM_HW_EP_DALIGN_CFG_PSIZE ALIGN( \ + sizeof(struct apm_module_hw_ep_dma_data_align_cfg), \ + 8) + +struct apm_gain_module_cfg { + struct apm_module_param_data param_data; + struct param_id_gain_cfg gain_cfg; +} __packed; +#define APM_GAIN_CFG_PSIZE ALIGN(sizeof(struct apm_gain_module_cfg), 8) + +struct apm_codec_dma_module_intf_cfg { + struct apm_module_param_data param_data; + struct param_id_codec_dma_intf_cfg cfg; +} __packed; +#define APM_CDMA_INTF_CFG_PSIZE ALIGN( \ + sizeof(struct apm_codec_dma_module_intf_cfg), 8) + +static void *__audioreach_alloc_pkt(int payload_size, uint32_t opcode, + uint32_t token, uint32_t src_port, + uint32_t dest_port, bool has_cmd_hdr) +{ + struct gpr_pkt *pkt; + void *p; + int pkt_size = GPR_HDR_SIZE + payload_size; + + if (has_cmd_hdr) + pkt_size += APM_CMD_HDR_SIZE; + + p = kzalloc(pkt_size, GFP_KERNEL); + if (!p) + return ERR_PTR(-ENOMEM); + + pkt = p; + pkt->hdr.version = GPR_PKT_VER; + pkt->hdr.hdr_size = GPR_PKT_HEADER_WORD_SIZE; + pkt->hdr.pkt_size = pkt_size; + pkt->hdr.dest_port = dest_port; + pkt->hdr.src_port = src_port; + + pkt->hdr.dest_domain = GPR_DOMAIN_ID_ADSP; + pkt->hdr.src_domain = GPR_DOMAIN_ID_APPS; + pkt->hdr.token = token; + pkt->hdr.opcode = opcode; + + if (has_cmd_hdr) { + struct apm_cmd_header *cmd_header; + + p = p + GPR_HDR_SIZE; + cmd_header = p; + cmd_header->payload_size = payload_size; + } + + return pkt; +} + +void *audioreach_alloc_pkt(int payload_size, uint32_t opcode, + uint32_t token, uint32_t src_port, + uint32_t dest_port) +{ + return __audioreach_alloc_pkt(payload_size, opcode, token, src_port, + dest_port, false); +} +EXPORT_SYMBOL_GPL(audioreach_alloc_pkt); + +void *audioreach_alloc_apm_pkt(int pkt_size, uint32_t opcode, + uint32_t token, uint32_t src_port) +{ + return __audioreach_alloc_pkt(pkt_size, opcode, token, src_port, + APM_MODULE_INSTANCE_ID, false); +} +EXPORT_SYMBOL_GPL(audioreach_alloc_apm_pkt); + +void *audioreach_alloc_cmd_pkt(int payload_size, uint32_t opcode, + uint32_t token, uint32_t src_port, + uint32_t dest_port) +{ + return __audioreach_alloc_pkt(payload_size, opcode, token, src_port, + dest_port, true); +} +EXPORT_SYMBOL_GPL(audioreach_alloc_cmd_pkt); + +void *audioreach_alloc_apm_cmd_pkt(int pkt_size, uint32_t opcode, + uint32_t token) +{ + return __audioreach_alloc_pkt(pkt_size, opcode, token, + GPR_APM_MODULE_IID, + APM_MODULE_INSTANCE_ID, + true); +} +EXPORT_SYMBOL_GPL(audioreach_alloc_apm_cmd_pkt); diff --git a/sound/soc/qcom/qdsp6/audioreach.h b/sound/soc/qcom/qdsp6/audioreach.h new file mode 100644 index 000000000000..8ef015aca3b2 --- /dev/null +++ b/sound/soc/qcom/qdsp6/audioreach.h @@ -0,0 +1,636 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __AUDIOREACH_H__ +#define __AUDIOREACH_H__ +#include +#include +#include + +/* Module IDs */ +#define MODULE_ID_WR_SHARED_MEM_EP 0x07001000 +#define MODULE_ID_RD_SHARED_MEM_EP 0x07001001 +#define MODULE_ID_GAIN 0x07001002 +#define MODULE_ID_PCM_CNV 0x07001003 +#define MODULE_ID_PCM_ENC 0x07001004 +#define MODULE_ID_PCM_DEC 0x07001005 +#define MODULE_ID_CODEC_DMA_SINK 0x07001023 +#define MODULE_ID_CODEC_DMA_SOURCE 0x07001024 +#define MODULE_ID_I2S_SINK 0x0700100A +#define MODULE_ID_I2S_SOURCE 0x0700100b +#define MODULE_ID_DATA_LOGGING 0x0700101A + +#define APM_CMD_GET_SPF_STATE 0x01001021 +#define APM_CMD_RSP_GET_SPF_STATE 0x02001007 + +#define APM_MODULE_INSTANCE_ID 0x00000001 +#define PRM_MODULE_INSTANCE_ID 0x00000002 +#define AMDB_MODULE_INSTANCE_ID 0x00000003 +#define VCPM_MODULE_INSTANCE_ID 0x00000004 +#define AR_MODULE_INSTANCE_ID_START 0x00006000 +#define AR_MODULE_INSTANCE_ID_END 0x00007000 +#define AR_MODULE_DYNAMIC_INSTANCE_ID_START 0x00007000 +#define AR_MODULE_DYNAMIC_INSTANCE_ID_END 0x00008000 +#define AR_CONT_INSTANCE_ID_START 0x00005000 +#define AR_CONT_INSTANCE_ID_END 0x00006000 +#define AR_SG_INSTANCE_ID_START 0x00004000 + +#define APM_CMD_GRAPH_OPEN 0x01001000 +#define APM_CMD_GRAPH_PREPARE 0x01001001 +#define APM_CMD_GRAPH_START 0x01001002 +#define APM_CMD_GRAPH_STOP 0x01001003 +#define APM_CMD_GRAPH_CLOSE 0x01001004 +#define APM_CMD_GRAPH_FLUSH 0x01001005 +#define APM_CMD_SET_CFG 0x01001006 +#define APM_CMD_GET_CFG 0x01001007 +#define APM_CMD_SHARED_MEM_MAP_REGIONS 0x0100100c +#define APM_CMD_SHARED_MEM_UNMAP_REGIONS 0x0100100d +#define APM_CMD_RSP_SHARED_MEM_MAP_REGIONS 0x02001001 +#define APM_CMD_RSP_GET_CFG 0x02001000 +#define APM_CMD_CLOSE_ALL 0x01001013 +#define APM_CMD_REGISTER_SHARED_CFG 0x0100100A + +#define APM_MEMORY_MAP_SHMEM8_4K_POOL 3 +struct apm_cmd_shared_mem_map_regions { + uint16_t mem_pool_id; + uint16_t num_regions; + uint32_t property_flag; +} __packed; + +struct apm_shared_map_region_payload { + uint32_t shm_addr_lsw; + uint32_t shm_addr_msw; + uint32_t mem_size_bytes; +} __packed; + +struct apm_cmd_shared_mem_unmap_regions { + uint32_t mem_map_handle; +} __packed; + +struct apm_cmd_rsp_shared_mem_map_regions { + uint32_t mem_map_handle; +} __packed; + +/* APM module */ +#define APM_PARAM_ID_SUB_GRAPH_LIST 0x08001005 + +#define APM_PARAM_ID_MODULE_LIST 0x08001002 +struct apm_param_id_modules_list { + uint32_t num_modules_list; +} __packed; + +#define APM_PARAM_ID_MODULE_PROP 0x08001003 +struct apm_param_id_module_prop { + uint32_t num_modules_prop_cfg; +} __packed; + +struct apm_module_prop_cfg { + uint32_t instance_id; + uint32_t num_props; +} __packed; + +#define APM_PARAM_ID_MODULE_CONN 0x08001004 +struct apm_param_id_module_conn { + uint32_t num_connections; +} __packed; + +struct apm_module_conn_obj { + uint32_t src_mod_inst_id; + uint32_t src_mod_op_port_id; + uint32_t dst_mod_inst_id; + uint32_t dst_mod_ip_port_id; +} __packed; + +#define APM_PARAM_ID_GAIN 0x08001006 +struct param_id_gain_cfg { + uint16_t gain; + uint16_t reserved; +}; + +#define PARAM_ID_PCM_OUTPUT_FORMAT_CFG 0x08001008 +struct param_id_pcm_output_format_cfg { + uint32_t data_format; + uint32_t fmt_id; + uint32_t payload_size; +} __packed; + +struct payload_pcm_output_format_cfg { + uint16_t bit_width; + uint16_t alignment; + uint16_t bits_per_sample; + uint16_t q_factor; + uint16_t endianness; + uint16_t interleaved; + uint16_t reserved; + uint16_t num_channels; + uint8_t channel_mapping[]; +} __packed; + +#define PARAM_ID_ENC_BITRATE 0x08001052 +struct param_id_enc_bitrate_param { + uint32_t bitrate; +} __packed; + +#define DATA_FORMAT_FIXED_POINT 1 +#define PCM_LSB_ALIGNED 1 +#define PCM_MSB_ALIGNED 2 +#define PCM_LITTLE_ENDIAN 1 +#define PCM_BIT_ENDIAN 2 + +#define MEDIA_FMT_ID_PCM 0x09001000 +#define PCM_CHANNEL_L 1 +#define PCM_CHANNEL_R 2 +#define SAMPLE_RATE_48K 48000 +#define BIT_WIDTH_16 16 + +#define APM_PARAM_ID_PROP_PORT_INFO 0x08001015 +struct apm_modules_prop_info { + uint32_t max_ip_port; + uint32_t max_op_port; +} __packed; + +//Shared memory module +#define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER 0x04001000 +#define WR_SH_MEM_EP_TIMESTAMP_VALID_FLAG BIT(31) +#define WR_SH_MEM_EP_LAST_BUFFER_FLAG BIT(30) +#define WR_SH_MEM_EP_TS_CONTINUE_FLAG BIT(29) +#define WR_SH_MEM_EP_EOF_FLAG BIT(4) +struct apm_data_cmd_wr_sh_mem_ep_data_buffer { + uint32_t buf_addr_lsw; + uint32_t buf_addr_msw; + uint32_t mem_map_handle; + uint32_t buf_size; + uint32_t timestamp_lsw; + uint32_t timestamp_msw; + uint32_t flags; +} __packed; + +#define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER_V2 0x0400100A +struct apm_data_cmd_wr_sh_mem_ep_data_buffer_v2 { + uint32_t buf_addr_lsw; + uint32_t buf_addr_msw; + uint32_t mem_map_handle; + uint32_t buf_size; + uint32_t timestamp_lsw; + uint32_t timestamp_msw; + uint32_t flags; + uint32_t md_addr_lsw; + uint32_t md_addr_msw; + uint32_t md_map_handle; + uint32_t md_buf_size; +} __packed; + +#define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE 0x05001000 +struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done { + uint32_t buf_addr_lsw; + uint32_t buf_addr_msw; + uint32_t mem_map_handle; + uint32_t status; + +} __packed; + +#define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE_V2 0x05001004 +struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done_v2 { + uint32_t buf_addr_lsw; + uint32_t buf_addr_msw; + uint32_t mem_map_handle; + uint32_t status; + uint32_t md_buf_addr_lsw; + uint32_t md_buf_addr_msw; + uint32_t md_mem_map_handle; + uint32_t md_status; +} __packed; + +#define PARAM_ID_MEDIA_FORMAT 0x0800100C +#define DATA_CMD_WR_SH_MEM_EP_MEDIA_FORMAT 0x04001001 +struct apm_media_format { + uint32_t data_format; + uint32_t fmt_id; + uint32_t payload_size; +} __packed; + +#define DATA_CMD_WR_SH_MEM_EP_EOS 0x04001002 +#define WR_SH_MEM_EP_EOS_POLICY_LAST 1 +#define WR_SH_MEM_EP_EOS_POLICY_EACH 2 + +struct data_cmd_wr_sh_mem_ep_eos { + uint32_t policy; + +} __packed; + +#define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER 0x04001003 +struct data_cmd_rd_sh_mem_ep_data_buffer { + uint32_t buf_addr_lsw; + uint32_t buf_addr_msw; + uint32_t mem_map_handle; + uint32_t buf_size; +}; + +#define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER 0x05001002 +struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done { + uint32_t status; + uint32_t buf_addr_lsw; + uint32_t buf_addr_msw; + uint32_t mem_map_handle; + uint32_t data_size; + uint32_t offset; + uint32_t timestamp_lsw; + uint32_t timestamp_msw; + uint32_t flags; + uint32_t num_frames; +}; + +#define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER_V2 0x0400100B +struct data_cmd_rd_sh_mem_ep_data_buffer_v2 { + uint32_t buf_addr_lsw; + uint32_t buf_addr_msw; + uint32_t mem_map_handle; + uint32_t buf_size; + uint32_t md_buf_addr_lsw; + uint32_t md_buf_addr_msw; + uint32_t md_mem_map_handle; + uint32_t md_buf_size; +}; + +#define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER_V2 0x05001005 +struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done_v2 { + uint32_t status; + uint32_t buf_addr_lsw; + uint32_t buf_addr_msw; + uint32_t mem_map_handle; + uint32_t data_size; + uint32_t offset; + uint32_t timestamp_lsw; + uint32_t timestamp_msw; + uint32_t flags; + uint32_t num_frames; + uint32_t md_status; + uint32_t md_buf_addr_lsw; + uint32_t md_buf_addr_msw; + uint32_t md_mem_map_handle; + uint32_t md_size; +} __packed; + +#define PARAM_ID_RD_SH_MEM_CFG 0x08001007 +struct param_id_rd_sh_mem_cfg { + uint32_t num_frames_per_buffer; + uint32_t metadata_control_flags; + +} __packed; +#define DATA_CMD_WR_SH_MEM_EP_EOS_RENDERED 0x05001001 +struct data_cmd_wr_sh_mem_ep_eos_rendered { + uint32_t module_instance_id; + uint32_t render_status; +} __packed; + +#define MODULE_ID_WR_SHARED_MEM_EP 0x07001000 + +struct apm_cmd_header { + uint32_t payload_address_lsw; + uint32_t payload_address_msw; + uint32_t mem_map_handle; + uint32_t payload_size; +} __packed; + +#define APM_CMD_HDR_SIZE sizeof(struct apm_cmd_header) + +struct apm_module_param_data { + uint32_t module_instance_id; + uint32_t param_id; + uint32_t param_size; + uint32_t error_code; +} __packed; + +#define APM_MODULE_PARAM_DATA_SIZE sizeof(struct apm_module_param_data) +struct apm_module_param_shared_data { + uint32_t param_id; + uint32_t param_size; +} __packed; + +struct apm_prop_data { + uint32_t prop_id; + uint32_t prop_size; +} __packed; + +/* Sub-Graph Properties */ +#define APM_PARAM_ID_SUB_GRAPH_CONFIG 0x08001001 + +struct apm_param_id_sub_graph_cfg { + uint32_t num_sub_graphs; +} __packed; + +struct apm_sub_graph_cfg { + uint32_t sub_graph_id; + uint32_t num_sub_graph_prop; +} __packed; + +#define APM_SUB_GRAPH_PROP_ID_PERF_MODE 0x0800100E + +struct apm_sg_prop_id_perf_mode { + uint32_t perf_mode; +} __packed; + +#define APM_SG_PROP_ID_PERF_MODE_SIZE 4 + +#define APM_SUB_GRAPH_PROP_ID_DIRECTION 0x0800100F + +struct apm_sg_prop_id_direction { + uint32_t direction; +} __packed; + +#define APM_SG_PROP_ID_DIR_SIZE 4 + +#define APM_SUB_GRAPH_PROP_ID_SCENARIO_ID 0x08001010 +#define APM_SUB_GRAPH_SID_AUDIO_PLAYBACK 0x1 +#define APM_SUB_GRAPH_SID_AUDIO_RECORD 0x2 +#define APM_SUB_GRAPH_SID_AUDIO_VOICE_CALL 0x3 + +struct apm_sg_prop_id_scenario_id { + uint32_t scenario_id; +} __packed; + +#define APM_SG_PROP_ID_SID_SIZE 4 +//container api +#define APM_PARAM_ID_CONTAINER_CONFIG 0x08001000 +struct apm_param_id_container_cfg { + uint32_t num_containers; +} __packed; + +struct apm_container_cfg { + uint32_t container_id; + uint32_t num_prop; +} __packed; + +struct apm_cont_capablity { + uint32_t capability_id; +} __packed; + +#define APM_CONTAINER_PROP_ID_CAPABILITY_LIST 0x08001011 +#define APM_CONTAINER_PROP_ID_CAPABILITY_SIZE 8 + +#define APM_PROP_ID_INVALID 0x0 +#define APM_CONTAINER_CAP_ID_PP 0x1 +#define APM_CONTAINER_CAP_ID_PP 0x1 + +struct apm_cont_prop_id_cap_list { + uint32_t num_capablity_id; +} __packed; + +#define APM_CONTAINER_PROP_ID_GRAPH_POS 0x08001012 + +struct apm_cont_prop_id_graph_pos { + uint32_t graph_pos; +} __packed; + +#define APM_CONTAINER_PROP_ID_STACK_SIZE 0x08001013 +struct apm_cont_prop_id_stack_size { + uint32_t stack_size; +} __packed; + +#define APM_CONTAINER_PROP_ID_PROC_DOMAIN 0x08001014 +struct apm_cont_prop_id_domain { + uint32_t proc_domain; +} __packed; + +#define CONFIG_I2S_WS_SRC_EXTERNAL 0x0 +#define CONFIG_I2S_WS_SRC_INTERNAL 0x1 + +#define PARAM_ID_I2S_INTF_CFG 0x08001019 +struct param_id_i2s_intf_cfg { + uint32_t lpaif_type; + uint32_t intf_idx; + uint16_t sd_line_idx; + uint16_t ws_src; +} __packed; + +#define I2S_INTF_TYPE_PRIMARY 0 +#define I2S_INTF_TYPE_SECOINDARY 1 +#define I2S_INTF_TYPE_TERTINARY 2 +#define I2S_INTF_TYPE_QUATERNARY 3 +#define I2S_INTF_TYPE_QUINARY 4 +#define I2S_SD0 1 +#define I2S_SD1 2 +#define I2S_SD2 3 +#define I2S_SD3 4 + +#define PORT_ID_I2S_INPUT 2 +#define PORT_ID_I2S_OUPUT 1 +#define I2S_STACK_SIZE 2048 + +#define PARAM_ID_HW_EP_MF_CFG 0x08001017 +struct param_id_hw_ep_mf { + uint32_t sample_rate; + uint16_t bit_width; + uint16_t num_channels; + uint32_t data_format; +} __packed; + +#define PARAM_ID_HW_EP_FRAME_SIZE_FACTOR 0x08001018 + +struct param_id_fram_size_factor { + uint32_t frame_size_factor; +} __packed; + +#define APM_CONTAINER_PROP_ID_PARENT_CONTAINER_ID 0x080010CB +struct apm_cont_prop_id_parent_container { + uint32_t parent_container_id; +} __packed; + +#define APM_CONTAINER_PROP_ID_HEAP_ID 0x08001174 +#define APM_CONT_HEAP_DEFAULT 0x1 +#define APM_CONT_HEAP_LOW_POWER 0x2 +struct apm_cont_prop_id_headp_id { + uint32_t heap_id; +} __packed; + +struct apm_modules_list { + uint32_t sub_graph_id; + uint32_t container_id; + uint32_t num_modules; +} __packed; + +struct apm_module_obj { + uint32_t module_id; + uint32_t instance_id; +} __packed; + +#define APM_MODULE_PROP_ID_PORT_INFO 0x08001015 +#define APM_MODULE_PROP_ID_PORT_INFO_SZ 8 +struct apm_module_prop_id_port_info { + uint32_t max_ip_port; + uint32_t max_op_port; +} __packed; + +#define DATA_LOGGING_MAX_INPUT_PORTS 0x1 +#define DATA_LOGGING_MAX_OUTPUT_PORTS 0x1 +#define DATA_LOGGING_STACK_SIZE 2048 +#define PARAM_ID_DATA_LOGGING_CONFIG 0x08001031 +struct data_logging_config { + uint32_t log_code; + uint32_t log_tap_point_id; + uint32_t mode; +} __packed; + +#define PARAM_ID_MFC_OUTPUT_MEDIA_FORMAT 0x08001024 +struct param_id_mfc_media_format { + uint32_t sample_rate; + uint16_t bit_width; + uint16_t num_channels; + uint16_t channel_mapping[]; +} __packed; + +struct media_format { + uint32_t data_format; + uint32_t fmt_id; + uint32_t payload_size; +} __packed; + +struct payload_media_fmt_pcm { + uint32_t sample_rate; + uint16_t bit_width; + uint16_t alignment; + uint16_t bits_per_sample; + uint16_t q_factor; + uint16_t endianness; + uint16_t num_channels; + uint8_t channel_mapping[]; +} __packed; + +#define PARAM_ID_CODEC_DMA_INTF_CFG 0x08001063 +struct param_id_codec_dma_intf_cfg { + /* 1 - RXTX + * 2 - WSA + * 3 - VA + * 4 - AXI + */ + uint32_t lpaif_type; + /* + * RX0 | TX0 = 1 + * RX1 | TX1 = 2 + * RX2 | TX2 = 3... so on + */ + uint32_t intf_index; + uint32_t active_channels_mask; +} __packed; + +struct audio_hw_clk_cfg { + uint32_t clock_id; + uint32_t clock_freq; + uint32_t clock_attri; + uint32_t clock_root; +} __packed; + +#define PARAM_ID_HW_EP_POWER_MODE_CFG 0x8001176 +#define POWER_MODE_0 0 /* default */ +#define POWER_MODE_1 1 /* XO Shutdown allowed */ +#define POWER_MODE_2 2 /* XO Shutdown not allowed */ +struct param_id_hw_ep_power_mode_cfg { + uint32_t power_mode; +} __packed; + +#define PARAM_ID_HW_EP_DMA_DATA_ALIGN 0x08001233 +#define DMA_DATA_ALIGN_MSB 0 +#define DMA_DATA_ALIGN_LSB 1 + +#define PCM_MAX_NUM_CHANNEL 8 +struct param_id_hw_ep_dma_data_align { + uint32_t dma_data_align; +} __packed; + +/* Graph */ +struct audioreach_connection { + /* Connections */ + uint32_t src_mod_inst_id; + uint32_t src_mod_op_port_id; + uint32_t dst_mod_inst_id; + uint32_t dst_mod_ip_port_id; + struct list_head node; +}; + +struct audioreach_graph_info { + int id; + uint32_t num_sub_graphs; + struct list_head sg_list; + struct list_head connection_list; + spinlock_t sg_list_lock; +}; + +struct audioreach_sub_graph { + uint32_t sub_graph_id; + uint32_t perf_mode; + uint32_t direction; + uint32_t scenario_id; + struct list_head node; + + struct audioreach_graph_info *info; + uint32_t num_containers; + struct list_head container_list; +}; + +struct audioreach_container { + uint32_t container_id; + uint32_t capability_id; + uint32_t graph_pos; + uint32_t stack_size; + uint32_t proc_domain; + struct list_head node; + + uint32_t num_modules; + struct list_head modules_list; + struct audioreach_sub_graph *sub_graph; +}; + +struct audioreach_module { + uint32_t module_id; + uint32_t instance_id; + + uint32_t max_ip_port; + uint32_t max_op_port; + + uint32_t in_port; + uint32_t out_port; + + /* Connections */ + uint32_t src_mod_inst_id; + uint32_t src_mod_op_port_id; + uint32_t dst_mod_inst_id; + uint32_t dst_mod_ip_port_id; + + /* Format specifics */ + uint32_t ch_fmt; + uint32_t rate; + uint32_t bit_depth; + + /* I2S module */ + uint32_t hw_interface_idx; + uint32_t sd_line_idx; + uint32_t ws_src; + uint32_t frame_size_factor; + uint32_t data_format; + uint32_t hw_interface_type; + + /* PCM module specific */ + uint32_t interleave_type; + + /* GAIN/Vol Control Module */ + uint16_t gain; + /* Logging */ + uint32_t log_code; + uint32_t log_tap_point_id; + uint32_t mode; + struct list_head node; + struct audioreach_container *container; + struct snd_soc_dapm_widget *widget; +}; + +/* Packet Allocation routines */ +void *audioreach_alloc_apm_cmd_pkt(int pkt_size, uint32_t opcode, uint32_t + token); +void *audioreach_alloc_cmd_pkt(int payload_size, uint32_t opcode, + uint32_t token, uint32_t src_port, + uint32_t dest_port); +void *audioreach_alloc_apm_pkt(int pkt_size, uint32_t opcode, uint32_t token, + uint32_t src_port); +void *audioreach_alloc_pkt(int payload_size, uint32_t opcode, + uint32_t token, uint32_t src_port, + uint32_t dest_port); +#endif /* __AUDIOREACH_H__ */ From patchwork Fri Sep 3 11:20:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 506520 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp906624jai; Fri, 3 Sep 2021 04:21:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwMoAjaIeh5Z2Yc6w+u1L22AnhvIs4mp5PC+f8TYdqgSRyzezNCAILbPt1I4FEqhNlFBYKF X-Received: by 2002:a5d:87d2:: with SMTP id q18mr2704094ios.78.1630668115985; Fri, 03 Sep 2021 04:21:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1630668115; cv=none; d=google.com; s=arc-20160816; b=i1sof63t57OpFUZTKkjUh+MEnzTXNl0PTTk60rxe0kU8ZEiHCJC1jbEpHWgtMjOEkS DJt0rO/Z90lN58Zo4k7qHOqiEXSDWQ+Kshmy5n72RezWB0YAxA4yvuNf9IxUd+Qzy/UH vB8SMjVuiQ0cfRlczSYdhaAF0hANLPACpO/9LfOSl8dyAAd4bC7looyAONM9RwRT3Thy foGUw/F+NG97USRqGxu7tsvPrzvBn++f+HMz/wADfGE4GvFmEfrSXQnYxfqw5YDXX5O7 whimqZR9WjCwd9CojnfZSTD/Uj2UH0GW57BmAlpWyodiFvEGmKUO6vS1PSzABHPoeloW ySQQ== ARC-Message-Signature: i=1; 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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:50 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 15/21] ASoC: qdsp6: audioreach: add q6apm support Date: Fri, 3 Sep 2021 12:20:26 +0100 Message-Id: <20210903112032.25834-16-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support to q6apm (Audio Process Manager) component which is core Audioreach service running in the DSP. Signed-off-by: Srinivas Kandagatla --- sound/soc/qcom/qdsp6/audioreach.c | 309 ++++++++++++++ sound/soc/qcom/qdsp6/audioreach.h | 30 ++ sound/soc/qcom/qdsp6/q6apm.c | 660 ++++++++++++++++++++++++++++++ sound/soc/qcom/qdsp6/q6apm.h | 154 +++++++ 4 files changed, 1153 insertions(+) create mode 100644 sound/soc/qcom/qdsp6/q6apm.c create mode 100644 sound/soc/qcom/qdsp6/q6apm.h -- 2.21.0 diff --git a/sound/soc/qcom/qdsp6/audioreach.c b/sound/soc/qcom/qdsp6/audioreach.c index 8e9a19a9d614..6106ee46990e 100644 --- a/sound/soc/qcom/qdsp6/audioreach.c +++ b/sound/soc/qcom/qdsp6/audioreach.c @@ -5,6 +5,7 @@ #include #include #include +#include "q6apm.h" #include "audioreach.h" /* SubGraph Config */ @@ -275,3 +276,311 @@ void *audioreach_alloc_apm_cmd_pkt(int pkt_size, uint32_t opcode, true); } EXPORT_SYMBOL_GPL(audioreach_alloc_apm_cmd_pkt); + +static void apm_populate_container_config( + struct apm_container_obj *cfg, + struct audioreach_container *cont) +{ + + /* Container Config */ + cfg->container_cfg.container_id = cont->container_id; + cfg->container_cfg.num_prop = 4; + + /* Capability list */ + cfg->cap_data.prop_id = APM_CONTAINER_PROP_ID_CAPABILITY_LIST; + cfg->cap_data.prop_size = APM_CONTAINER_PROP_ID_CAPABILITY_SIZE; + cfg->num_capablity_id = 1; + cfg->capability_id = cont->capability_id; + + /* Graph Position */ + cfg->pos_data.prop_id = APM_CONTAINER_PROP_ID_GRAPH_POS; + cfg->pos_data.prop_size = sizeof(struct apm_cont_prop_id_graph_pos); + cfg->pos.graph_pos = cont->graph_pos; + + /* Stack size */ + cfg->stack_data.prop_id = APM_CONTAINER_PROP_ID_STACK_SIZE; + cfg->stack_data.prop_size = sizeof(struct + apm_cont_prop_id_stack_size); + cfg->stack.stack_size = cont->stack_size; + + /* Proc domain */ + cfg->domain_data.prop_id = APM_CONTAINER_PROP_ID_PROC_DOMAIN; + cfg->domain_data.prop_size = sizeof(struct + apm_cont_prop_id_domain); + cfg->domain.proc_domain = cont->proc_domain; +} + +static void apm_populate_sub_graph_config( + struct apm_sub_graph_data *cfg, + struct audioreach_sub_graph *sg) +{ + cfg->sub_graph_cfg.sub_graph_id = sg->sub_graph_id; + cfg->sub_graph_cfg.num_sub_graph_prop = APM_SUB_GRAPH_CFG_NPROP; + + /* Perf Mode */ + cfg->perf_data.prop_id = APM_SUB_GRAPH_PROP_ID_PERF_MODE; + cfg->perf_data.prop_size = APM_SG_PROP_ID_PERF_MODE_SIZE; + cfg->perf.perf_mode = sg->perf_mode; + + /* Direction */ + cfg->dir_data.prop_id = APM_SUB_GRAPH_PROP_ID_DIRECTION; + cfg->dir_data.prop_size = APM_SG_PROP_ID_DIR_SIZE; + cfg->dir.direction = sg->direction; + + /* Scenario ID */ + cfg->sid_data.prop_id = APM_SUB_GRAPH_PROP_ID_SCENARIO_ID; + cfg->sid_data.prop_size = APM_SG_PROP_ID_SID_SIZE; + cfg->sid.scenario_id = sg->scenario_id; +} + +static void apm_populate_connection_obj(struct apm_module_conn_obj *obj, + struct audioreach_module *module) +{ + obj->src_mod_inst_id = module->src_mod_inst_id; + obj->src_mod_op_port_id = module->src_mod_op_port_id; + obj->dst_mod_inst_id = module->instance_id; + obj->dst_mod_ip_port_id = module->in_port; +} + +static void apm_populate_module_prop_obj(struct apm_mod_prop_obj *obj, + struct audioreach_module *module) +{ + + obj->instance_id = module->instance_id; + obj->num_props = 1; + obj->prop_data_1.prop_id = APM_MODULE_PROP_ID_PORT_INFO; + obj->prop_data_1.prop_size = APM_MODULE_PROP_ID_PORT_INFO_SZ; + obj->prop_id_port.max_ip_port = module->max_ip_port; + obj->prop_id_port.max_op_port = module->max_op_port; +} + +struct audioreach_module *audioreach_get_container_last_module( + struct audioreach_container *container) +{ + struct audioreach_module *module; + + list_for_each_entry(module, &container->modules_list, node) { + if (module->dst_mod_inst_id == 0) + return module; + } + + return NULL; +} +EXPORT_SYMBOL_GPL(audioreach_get_container_last_module); + +static bool is_module_in_container(struct audioreach_container *container, int + module_iid) +{ + struct audioreach_module *module; + + list_for_each_entry(module, &container->modules_list, node) { + if (module->instance_id == module_iid) + return true; + } + + return false; +} + +struct audioreach_module *audioreach_get_container_first_module( + struct audioreach_container *container) +{ + struct audioreach_module *module; + + list_for_each_entry(module, &container->modules_list, node) { + if (module->src_mod_inst_id == 0 || + !is_module_in_container(container, module->src_mod_inst_id)) + return module; + } + return NULL; +} +EXPORT_SYMBOL_GPL(audioreach_get_container_first_module); + +struct audioreach_module *audioreach_get_container_next_module( + struct audioreach_container *container, + struct audioreach_module *module) +{ + int nmodule_iid = module->dst_mod_inst_id; + struct audioreach_module *nmodule; + + list_for_each_entry(nmodule, &container->modules_list, node) { + if (nmodule->instance_id == nmodule_iid) + return nmodule; + } + + return NULL; +} +EXPORT_SYMBOL_GPL(audioreach_get_container_next_module); + +static void apm_populate_module_list_obj(struct apm_mod_list_obj *obj, + struct audioreach_container *container, + int sub_graph_id) +{ + struct audioreach_module *module; + int i; + + obj->sub_graph_id = sub_graph_id; + obj->container_id = container->container_id; + obj->num_modules = container->num_modules; + i = 0; + list_for_each_container_module(module, container) { + obj->mod_cfg[i].module_id = module->module_id; + obj->mod_cfg[i].instance_id = module->instance_id; + i++; + } +} + +static void audioreach_populate_graph(struct apm_graph_open_params *open, + struct list_head *sg_list, + int num_sub_graphs) +{ + struct apm_sub_graph_params *sg_data = open->sg_data; + struct apm_container_params *c_data = open->cont_data; + struct apm_module_list_params *ml_data = open->mod_list_data; + struct apm_prop_list_params *mp_data = open->mod_prop_data; + struct apm_mod_conn_list_params *mc_data = open->mod_conn_list_data; + struct apm_container_obj *cobj; + struct audioreach_container *container; + struct audioreach_module *module; + struct apm_mod_list_obj *mlobj; + struct apm_mod_prop_obj *module_prop_obj; + struct apm_module_conn_obj *conn_obj; + int ncontainer = 0, nmodule = 0, nconn = 0; + struct audioreach_sub_graph *sg; + int i = 0; + + mlobj = &ml_data->mod_list_obj[0]; + + list_for_each_entry(sg, sg_list, node) { + struct apm_sub_graph_data *sg_cfg = &sg_data->sg_cfg[i++]; + + apm_populate_sub_graph_config(sg_cfg, sg); + + list_for_each_entry(container, &sg->container_list, node) { + cobj = &c_data->cont_obj[ncontainer]; + + apm_populate_container_config(cobj, container); + apm_populate_module_list_obj(mlobj, container, + sg->sub_graph_id); + + list_for_each_container_module(module, container) { + uint32_t src_mod_inst_id; + + src_mod_inst_id = module->src_mod_inst_id; + + module_prop_obj = &mp_data->mod_prop_obj[nmodule]; + apm_populate_module_prop_obj(module_prop_obj, + module); + + if (src_mod_inst_id /*&& dst_mod_inst_id*/) { + conn_obj = &mc_data->conn_obj[nconn]; + apm_populate_connection_obj(conn_obj, module); + nconn++; + } + + nmodule++; + } + mlobj = (void *) mlobj + + APM_MOD_LIST_OBJ_PSIZE(container->num_modules); + + ncontainer++; + } + } +} + +void *audioreach_alloc_graph_pkt(struct q6apm *apm, + struct list_head *sg_list, + int graph_id) +{ + void *p; + int payload_size, sg_sz, cont_sz, ml_sz, mp_sz, mc_sz; + struct gpr_pkt *pkt; + struct apm_graph_open_params params; + struct apm_module_param_data *param_data; + struct audioreach_container *container; + int num_containers = 0; + int num_modules = 0; + int num_modules_list; + int num_modules_per_list; + int num_connections = 0; + int num_sub_graphs = 0; + struct audioreach_sub_graph *sgs; + struct audioreach_module *module; + + list_for_each_entry(sgs, sg_list, node) { + num_sub_graphs++; + list_for_each_entry(container, &sgs->container_list, node) { + num_containers++; + num_modules += container->num_modules; + list_for_each_container_module(module, container) { + if (module->src_mod_inst_id) + num_connections++; + } + } + } + + num_modules_list = num_containers; + num_modules_per_list = num_modules/num_containers; + sg_sz = APM_SUB_GRAPH_PSIZE(num_sub_graphs); + cont_sz = APM_CONTAINER_PSIZE(num_containers); + ml_sz = APM_MOD_LIST_PSIZE(num_modules_list, num_modules_per_list); + mp_sz = APM_MOD_PROP_PSIZE(num_modules); + mc_sz = APM_MOD_CONN_PSIZE(num_connections); + + payload_size = sg_sz + cont_sz + ml_sz + mp_sz + mc_sz; + p = audioreach_alloc_apm_cmd_pkt(payload_size, APM_CMD_GRAPH_OPEN, 0); + if (IS_ERR(p)) + return p; + + pkt = p; + p = p + GPR_HDR_SIZE + APM_CMD_HDR_SIZE; + + /* SubGraph */ + params.sg_data = p; + param_data = ¶ms.sg_data->param_data; + param_data->module_instance_id = APM_MODULE_INSTANCE_ID; + param_data->param_id = APM_PARAM_ID_SUB_GRAPH_CONFIG; + param_data->param_size = sg_sz - APM_MODULE_PARAM_DATA_SIZE; + params.sg_data->num_sub_graphs = num_sub_graphs; + p += sg_sz; + + /* Container */ + params.cont_data = p; + param_data = ¶ms.cont_data->param_data; + param_data->module_instance_id = APM_MODULE_INSTANCE_ID; + param_data->param_id = APM_PARAM_ID_CONTAINER_CONFIG; + param_data->param_size = cont_sz - APM_MODULE_PARAM_DATA_SIZE; + params.cont_data->num_containers = num_containers; + p += cont_sz; + + /* Module List*/ + params.mod_list_data = p; + param_data = ¶ms.mod_list_data->param_data; + param_data->module_instance_id = APM_MODULE_INSTANCE_ID; + param_data->param_id = APM_PARAM_ID_MODULE_LIST; + param_data->param_size = ml_sz - APM_MODULE_PARAM_DATA_SIZE; + params.mod_list_data->num_modules_list = num_sub_graphs; + p += ml_sz; + + /* Module Properties */ + params.mod_prop_data = p; + param_data = ¶ms.mod_prop_data->param_data; + param_data->module_instance_id = APM_MODULE_INSTANCE_ID; + param_data->param_id = APM_PARAM_ID_MODULE_PROP; + param_data->param_size = mp_sz - APM_MODULE_PARAM_DATA_SIZE; + params.mod_prop_data->num_modules_prop_cfg = num_modules; + p += mp_sz; + + /* Module Connections */ + params.mod_conn_list_data = p; + param_data = ¶ms.mod_conn_list_data->param_data; + param_data->module_instance_id = APM_MODULE_INSTANCE_ID; + param_data->param_id = APM_PARAM_ID_MODULE_CONN; + param_data->param_size = mc_sz - APM_MODULE_PARAM_DATA_SIZE; + params.mod_conn_list_data->num_connections = num_connections; + p += mc_sz; + + audioreach_populate_graph(¶ms, sg_list, num_sub_graphs); + + return pkt; +} +EXPORT_SYMBOL_GPL(audioreach_alloc_graph_pkt); diff --git a/sound/soc/qcom/qdsp6/audioreach.h b/sound/soc/qcom/qdsp6/audioreach.h index 8ef015aca3b2..d25ea8c48b41 100644 --- a/sound/soc/qcom/qdsp6/audioreach.h +++ b/sound/soc/qcom/qdsp6/audioreach.h @@ -5,6 +5,9 @@ #include #include #include +struct q6apm; +struct q6apm_graph; + /* Module IDs */ #define MODULE_ID_WR_SHARED_MEM_EP 0x07001000 @@ -622,6 +625,20 @@ struct audioreach_module { struct snd_soc_dapm_widget *widget; }; +struct audioreach_module_config { + int direction; + u16 sample_rate; + u16 bit_width; + u16 bits_per_sample; + + u16 data_format; + u16 num_channels; + u16 active_channels_mask; + u32 sd_line_mask; + int fmt; + u8 channel_map[PCM_MAX_NUM_CHANNEL]; +}; + /* Packet Allocation routines */ void *audioreach_alloc_apm_cmd_pkt(int pkt_size, uint32_t opcode, uint32_t token); @@ -633,4 +650,17 @@ void *audioreach_alloc_apm_pkt(int pkt_size, uint32_t opcode, uint32_t token, void *audioreach_alloc_pkt(int payload_size, uint32_t opcode, uint32_t token, uint32_t src_port, uint32_t dest_port); +void *audioreach_alloc_graph_pkt(struct q6apm *apm, + struct list_head *sg_list, + int graph_id); +struct audioreach_module *audioreach_get_container_last_module( + struct audioreach_container *container); +struct audioreach_module *audioreach_get_container_first_module( + struct audioreach_container *container); +struct audioreach_module *audioreach_get_container_next_module( + struct audioreach_container *container, + struct audioreach_module *module); +#define list_for_each_container_module(mod, cont) \ + for (mod = audioreach_get_container_first_module(cont); mod != NULL; \ + mod = audioreach_get_container_next_module(cont, mod)) #endif /* __AUDIOREACH_H__ */ diff --git a/sound/soc/qcom/qdsp6/q6apm.c b/sound/soc/qcom/qdsp6/q6apm.c new file mode 100644 index 000000000000..5de85f477179 --- /dev/null +++ b/sound/soc/qcom/qdsp6/q6apm.c @@ -0,0 +1,660 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2020, Linaro Limited + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "audioreach.h" +#include "q6apm.h" + +/* Graph Management */ +struct apm_graph_mgmt_cmd { + struct apm_module_param_data param_data; + uint32_t num_sub_graphs; + uint32_t sub_graph_id_list[0]; +} __packed; + +#define APM_GRAPH_MGMT_PSIZE(n) ALIGN(sizeof(struct apm_graph_mgmt_cmd) + \ + n * sizeof(uint32_t), 8) + +int q6apm_send_cmd_sync(struct q6apm *apm, struct gpr_pkt *pkt, + uint32_t rsp_opcode) +{ + gpr_device_t *gdev = apm->gdev; + struct gpr_hdr *hdr = &pkt->hdr; + int rc; + + mutex_lock(&apm->cmd_lock); + apm->result.opcode = 0; + apm->result.status = 0; + + rc = gpr_send_pkt(apm->gdev, pkt); + if (rc < 0) + goto err; + + if (rsp_opcode) + rc = wait_event_timeout(apm->wait, + (apm->result.opcode == hdr->opcode) || + (apm->result.opcode == rsp_opcode), + 5 * HZ); + else + rc = wait_event_timeout(apm->wait, + (apm->result.opcode == hdr->opcode), + 5 * HZ); + + if (!rc) { + dev_err(&gdev->dev, "CMD timeout for [%x] opcode\n", + hdr->opcode); + rc = -ETIMEDOUT; + } else if (apm->result.status > 0) { + dev_err(&gdev->dev, "DSP returned error[%x] %x\n", hdr->opcode, + apm->result.status); + rc = -EINVAL; + } else { + dev_err(&gdev->dev, "DSP returned [%x]\n", + apm->result.status); + rc = 0; + } + +err: + mutex_unlock(&apm->cmd_lock); + return rc; +} + +static struct audioreach_graph *q6apm_get_audioreach_graph(struct q6apm *apm, + uint32_t graph_id) +{ + struct audioreach_graph *graph; + struct audioreach_graph_info *info; + unsigned long flags; + + spin_lock_irqsave(&apm->lock, flags); + graph = idr_find(&apm->graph_idr, graph_id); + spin_unlock_irqrestore(&apm->lock, flags); + + if (graph) { + kref_get(&graph->refcount); + return graph; + } + + info = idr_find(&apm->graph_info_idr, graph_id); + + if (!info) + return ERR_PTR(-ENODEV); + + graph = kzalloc(sizeof(*graph), GFP_KERNEL); + if (!graph) + return ERR_PTR(-ENOMEM); + + graph->apm = apm; + graph->info = info; + graph->id = graph_id; + + /* Assuming Linear Graphs only for now! */ + graph->graph = audioreach_alloc_graph_pkt(apm, &info->sg_list, graph_id); + if (IS_ERR(graph->graph)) { + kfree(graph); + return ERR_PTR(-ENOMEM); + } + + spin_lock(&apm->lock); + idr_alloc(&apm->graph_idr, graph, graph_id, + graph_id + 1, GFP_ATOMIC); + spin_unlock(&apm->lock); + + kref_init(&graph->refcount); + + q6apm_send_cmd_sync(apm, graph->graph, 0); + + return graph; +} + +static int audioreach_graph_mgmt_cmd(struct audioreach_graph *graph, + uint32_t opcode) +{ + struct gpr_pkt *pkt; + void *p; + int i = 0, rc, payload_size; + struct q6apm *apm = graph->apm; + struct audioreach_graph_info *info = graph->info; + int num_sub_graphs = info->num_sub_graphs; + struct apm_graph_mgmt_cmd *mgmt_cmd; + struct apm_module_param_data *param_data; + struct audioreach_sub_graph *sg; + + payload_size = APM_GRAPH_MGMT_PSIZE(num_sub_graphs); + + p = audioreach_alloc_apm_cmd_pkt(payload_size, opcode, 0); + if (IS_ERR(p)) + return -ENOMEM; + + pkt = p; + p = p + GPR_HDR_SIZE + APM_CMD_HDR_SIZE; + + mgmt_cmd = p; + mgmt_cmd->num_sub_graphs = num_sub_graphs; + + param_data = &mgmt_cmd->param_data; + param_data->module_instance_id = APM_MODULE_INSTANCE_ID; + param_data->param_id = APM_PARAM_ID_SUB_GRAPH_LIST; + param_data->param_size = payload_size - APM_MODULE_PARAM_DATA_SIZE; + + list_for_each_entry(sg, &info->sg_list, node) { + mgmt_cmd->sub_graph_id_list[i++] = sg->sub_graph_id; + } + + rc = q6apm_send_cmd_sync(apm, pkt, 0); + + kfree(pkt); + + return rc; +} + +static void q6apm_put_audioreach_graph(struct kref *ref) +{ + struct audioreach_graph *graph; + struct q6apm *apm; + unsigned long flags; + + graph = container_of(ref, struct audioreach_graph, refcount); + apm = graph->apm; + + audioreach_graph_mgmt_cmd(graph, APM_CMD_GRAPH_CLOSE); + + spin_lock_irqsave(&apm->lock, flags); + graph = idr_remove(&apm->graph_idr, graph->id); + spin_unlock_irqrestore(&apm->lock, flags); + + kfree(graph->graph); + kfree(graph); +} + +static bool q6apm_get_apm_state(struct q6apm *apm) +{ + struct gpr_pkt *pkt; + + pkt = audioreach_alloc_apm_cmd_pkt(0, APM_CMD_GET_SPF_STATE, 0); + if (IS_ERR(pkt)) + return -ENOMEM; + + q6apm_send_cmd_sync(apm, pkt, APM_CMD_RSP_GET_SPF_STATE); + + kfree(pkt); + + return !apm->state ? false : true; +} + +static struct audioreach_module *__q6apm_find_module_by_mid(struct q6apm *apm, + struct audioreach_graph_info *info, + uint32_t mid) +{ + struct audioreach_sub_graph *sgs; + struct audioreach_container *container; + struct audioreach_module *module; + + list_for_each_entry(sgs, &info->sg_list, node) { + list_for_each_entry(container, &sgs->container_list, node) { + list_for_each_entry(module, &container->modules_list, node) { + if (mid == module->module_id) + return module; + } + } + } + + return NULL; +} + +static struct audioreach_module *q6apm_graph_get_last_module(struct q6apm *apm, + u32 sgid) +{ + struct audioreach_sub_graph *sg; + struct audioreach_module *module; + struct audioreach_container *container; + + spin_lock(&apm->lock); + sg = idr_find(&apm->sub_graphs_idr, sgid); + spin_unlock(&apm->lock); + if (!sg) + return NULL; + + container = list_last_entry(&sg->container_list, struct audioreach_container, node); + module = audioreach_get_container_last_module(container); + + return module; +} + +static struct audioreach_module *q6apm_graph_get_first_module(struct q6apm *apm, + u32 sgid) +{ + struct audioreach_sub_graph *sg; + struct audioreach_module *module; + struct audioreach_container *container; + + spin_lock(&apm->lock); + sg = idr_find(&apm->sub_graphs_idr, sgid); + spin_unlock(&apm->lock); + if (!sg) + return NULL; + + container = list_first_entry(&sg->container_list, struct audioreach_container, node); + module = audioreach_get_container_first_module(container); + + return module; +} + +bool q6apm_is_sub_graphs_connected(struct q6apm *apm, u32 src_sgid, u32 dst_sgid) +{ + struct audioreach_module *module; + u32 iid; + + module = q6apm_graph_get_last_module(apm, src_sgid); + if (!module) + return false; + + iid = module->instance_id; + module = q6apm_graph_get_first_module(apm, dst_sgid); + if (!module) + return false; + + if (module->src_mod_inst_id == iid) + return true; + + return false; +} + +int q6apm_connect_sub_graphs(struct q6apm *apm, u32 src_sgid, + u32 dst_sgid, bool connect) +{ + + struct audioreach_module *module; + u32 iid; + + if (connect) { + module = q6apm_graph_get_last_module(apm, src_sgid); + if (!module) + return -ENODEV; + + iid = module->instance_id; + } else { + iid = 0; + } + + module = q6apm_graph_get_first_module(apm, dst_sgid); + if (!module) + return -ENODEV; + + /* set src module in dst subgraph first module */ + module->src_mod_inst_id = iid; + + return 0; +} + +int q6apm_graph_get_rx_shmem_module_iid(struct q6apm_graph *graph) +{ + struct audioreach_module *module; + + module = q6apm_find_module_by_mid(graph, MODULE_ID_WR_SHARED_MEM_EP); + if (!module) + return -ENODEV; + + return module->instance_id; + +} +EXPORT_SYMBOL_GPL(q6apm_graph_get_rx_shmem_module_iid); + +static int graph_callback(struct gpr_resp_pkt *data, void *priv, int op) +{ + struct q6apm_graph *graph = priv; + struct device *dev = graph->dev; + struct gpr_hdr *hdr = &data->hdr; + struct gpr_ibasic_rsp_result_t *result; + int ret = -EINVAL; + uint32_t client_event = 0; + struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done_v2 *done; + struct apm_cmd_rsp_shared_mem_map_regions *rsp; + phys_addr_t phys; + unsigned long flags; + int token; + + result = data->payload; + + switch (hdr->opcode) { + case DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE_V2: + client_event = APM_CLIENT_EVENT_DATA_WRITE_DONE; + spin_lock_irqsave(&graph->lock, flags); + token = hdr->token & APM_WRITE_TOKEN_MASK; + + done = data->payload; + phys = graph->rx_data.buf[token].phys; + + if (lower_32_bits(phys) != done->buf_addr_lsw || + upper_32_bits(phys) != done->buf_addr_msw) { + dev_err(dev, "WR BUFF Expected Token %d addr %pa\n", token, &phys); + ret = -EINVAL; + } else { + ret = 0; + graph->result.opcode = hdr->opcode; + graph->result.status = done->status; + } + spin_unlock_irqrestore(&graph->lock, flags); + if (graph->cb) + graph->cb(client_event, hdr->token, data->payload, + graph->priv); + + break; + case APM_CMD_RSP_SHARED_MEM_MAP_REGIONS: + graph->result.opcode = hdr->opcode; + graph->result.status = 0; + rsp = data->payload; + + if (hdr->token == SNDRV_PCM_STREAM_PLAYBACK) + graph->rx_data.mem_map_handle = rsp->mem_map_handle; + else + graph->tx_data.mem_map_handle = rsp->mem_map_handle; + + wake_up(&graph->cmd_wait); + ret = 0; + break; + case DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER_V2: + done = data->payload; + spin_lock_irqsave(&graph->lock, flags); + phys = graph->tx_data.buf[hdr->token].phys; + if (upper_32_bits(phys) != done->buf_addr_msw || + lower_32_bits(phys) != done->buf_addr_lsw) { + dev_err(dev, "RD BUFF Expected addr %pa %08x-%08x\n", + &phys, + done->buf_addr_lsw, + done->buf_addr_msw); + ret = -EINVAL; + } else { + ret = 0; + } + spin_unlock_irqrestore(&graph->lock, flags); + client_event = APM_CLIENT_EVENT_DATA_READ_DONE; + wake_up(&graph->cmd_wait); + + if (graph->cb) + graph->cb(client_event, hdr->token, data->payload, + graph->priv); + break; + case DATA_CMD_WR_SH_MEM_EP_EOS_RENDERED: + break; + case GPR_BASIC_RSP_RESULT: + switch (result->opcode) { + case APM_CMD_SHARED_MEM_UNMAP_REGIONS: + graph->result.opcode = result->opcode; + graph->result.status = 0; + if (hdr->token == SNDRV_PCM_STREAM_PLAYBACK) + graph->rx_data.mem_map_handle = 0; + else + graph->tx_data.mem_map_handle = 0; + + wake_up(&graph->cmd_wait); + ret = 0; + break; + case APM_CMD_SHARED_MEM_MAP_REGIONS: + case DATA_CMD_WR_SH_MEM_EP_MEDIA_FORMAT: + case APM_CMD_SET_CFG: + graph->result.opcode = result->opcode; + graph->result.status = result->status; + if (result->status) { + dev_err(dev, + "Error (%d) Processing 0x%08x cmd\n", + result->status, result->opcode); + ret = -EINVAL; + } else { + ret = 0; + } + wake_up(&graph->cmd_wait); + if (graph->cb) + graph->cb(client_event, hdr->token, data->payload, + graph->priv); + + } + break; + } + + return ret; +} + +struct q6apm_graph *q6apm_graph_open(struct device *dev, q6apm_cb cb, + void *priv, int graph_id) +{ + struct q6apm *apm = dev_get_drvdata(dev->parent); + struct q6apm_graph *graph; + struct audioreach_graph *ar_graph; + int ret; + + dev_err(dev, "%s :graph id %d\n", __func__, graph_id); + ar_graph = q6apm_get_audioreach_graph(apm, graph_id); + if (IS_ERR(ar_graph)) { + dev_err(dev, "No graph found with id %d\n", graph_id); + return ERR_CAST(ar_graph); + } + + graph = kzalloc(sizeof(*graph), GFP_KERNEL); + if (!graph) { + ret = -ENOMEM; + goto err; + } + + graph->apm = apm; + graph->priv = priv; + graph->cb = cb; + graph->info = ar_graph->info; + graph->ar_graph = ar_graph; + graph->id = ar_graph->id; + graph->dev = dev; + + spin_lock_init(&graph->lock); + init_waitqueue_head(&graph->cmd_wait); + mutex_init(&graph->cmd_lock); + + graph->port = gpr_alloc_port(apm->gdev, dev, graph_callback, graph); + if (!graph->port) { + kfree(graph); + ret = -ENOMEM; + goto err; + } + + dev_dbg(dev, "%s: GRAPH-DEBUG Opening graph id %d with port id 0x%08x\n", __func__, + graph_id, graph->port->id); + + return graph; +err: + kref_put(&ar_graph->refcount, q6apm_put_audioreach_graph); + return ERR_PTR(ret); +} +EXPORT_SYMBOL_GPL(q6apm_graph_open); + +int q6apm_graph_close(struct q6apm_graph *graph) +{ + struct audioreach_graph *ar_graph = graph->ar_graph; + + gpr_free_port(graph->port); + graph->port = NULL; + kref_put(&ar_graph->refcount, q6apm_put_audioreach_graph); + kfree(graph); + + return 0; +} +EXPORT_SYMBOL_GPL(q6apm_graph_close); + +int q6apm_graph_prepare(struct q6apm_graph *graph) +{ + return audioreach_graph_mgmt_cmd(graph->ar_graph, + APM_CMD_GRAPH_PREPARE); +} +EXPORT_SYMBOL_GPL(q6apm_graph_prepare); + +int q6apm_graph_start(struct q6apm_graph *graph) +{ + struct audioreach_graph *ar_graph = graph->ar_graph; + int ret = 0; + + if (ar_graph->start_count == 0) + ret = audioreach_graph_mgmt_cmd(ar_graph, APM_CMD_GRAPH_START); + + ar_graph->start_count++; + + return ret; +} +EXPORT_SYMBOL_GPL(q6apm_graph_start); + +int q6apm_graph_stop(struct q6apm_graph *graph) +{ + struct audioreach_graph *ar_graph = graph->ar_graph; + + if (--ar_graph->start_count > 0) + return 0; + + return audioreach_graph_mgmt_cmd(ar_graph, APM_CMD_GRAPH_STOP); +} +EXPORT_SYMBOL_GPL(q6apm_graph_stop); + +int q6apm_graph_flush(struct q6apm_graph *graph) +{ + return audioreach_graph_mgmt_cmd(graph->ar_graph, APM_CMD_GRAPH_FLUSH); +} +EXPORT_SYMBOL_GPL(q6apm_graph_flush); + +static int q6apm_audio_probe(struct snd_soc_component *component) +{ + return 0; +} + +static void q6apm_audio_remove(struct snd_soc_component *component) +{ +} + +#define APM_AUDIO_DRV_NAME "q6apm-audio" + +static const struct snd_soc_component_driver q6apm_audio_component = { + .name = APM_AUDIO_DRV_NAME, + .probe = q6apm_audio_probe, + .remove = q6apm_audio_remove, +}; + +static int apm_probe(gpr_device_t *gdev) +{ + struct device *dev = &gdev->dev; + struct q6apm *apm; + + apm = devm_kzalloc(dev, sizeof(*apm), GFP_KERNEL); + if (!apm) + return -ENOMEM; + + dev_set_drvdata(dev, apm); + + mutex_init(&apm->cmd_lock); + apm->dev = dev; + apm->gdev = gdev; + init_waitqueue_head(&apm->wait); + + idr_init(&apm->graph_idr); + idr_init(&apm->graph_info_idr); + idr_init(&apm->sub_graphs_idr); + idr_init(&apm->containers_idr); + + idr_init(&apm->modules_idr); + spin_lock_init(&apm->lock); + + q6apm_get_apm_state(apm); + + devm_snd_soc_register_component(dev, &q6apm_audio_component, NULL, 0); + + return of_platform_populate(dev->of_node, NULL, NULL, dev); +} + +static int apm_exit(gpr_device_t *gdev) +{ + return 0; +} + +struct audioreach_module *q6apm_find_module_by_mid(struct q6apm_graph *graph, + uint32_t mid) +{ + struct audioreach_graph_info *info = graph->info; + struct q6apm *apm = graph->apm; + + return __q6apm_find_module_by_mid(apm, info, mid); + +} + +static int apm_callback(struct gpr_resp_pkt *data, void *priv, int op) +{ + gpr_device_t *gdev = priv; + struct q6apm *apm = dev_get_drvdata(&gdev->dev); + struct device *dev = &gdev->dev; + struct gpr_ibasic_rsp_result_t *result; + struct gpr_hdr *hdr = &data->hdr; + int ret = -EINVAL; + + result = data->payload; + + switch (hdr->opcode) { + case APM_CMD_RSP_GET_SPF_STATE: + apm->result.opcode = hdr->opcode; + apm->result.status = 0; + /* First word of result it state */ + apm->state = result->opcode; + wake_up(&apm->wait); + break; + case GPR_BASIC_RSP_RESULT: + switch (result->opcode) { + case APM_CMD_GRAPH_START: + case APM_CMD_GRAPH_OPEN: + case APM_CMD_GRAPH_PREPARE: + case APM_CMD_GRAPH_CLOSE: + case APM_CMD_GRAPH_FLUSH: + case APM_CMD_GRAPH_STOP: + case APM_CMD_SET_CFG: + apm->result.opcode = result->opcode; + apm->result.status = result->status; + if (result->status) { + dev_err(dev, + "Error (%d) Processing 0x%08x cmd\n", + result->status, result->opcode); + ret = -EINVAL; + } else { + ret = 0; + } + wake_up(&apm->wait); + + } + break; + } + + return ret; +} + +static const struct of_device_id apm_device_id[] = { + { .compatible = "qcom,q6apm" }, + {}, +}; +MODULE_DEVICE_TABLE(of, apm_device_id); + +static gpr_driver_t apm_driver = { + .probe = apm_probe, + .remove = apm_exit, + .gpr_callback = apm_callback, + .driver = { + .name = "qcom-apm", + .of_match_table = of_match_ptr(apm_device_id), + }, +}; + +module_gpr_driver(apm_driver); +MODULE_DESCRIPTION("Audio Process Manager"); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/qcom/qdsp6/q6apm.h b/sound/soc/qcom/qdsp6/q6apm.h new file mode 100644 index 000000000000..8956a060d7cc --- /dev/null +++ b/sound/soc/qcom/qdsp6/q6apm.h @@ -0,0 +1,154 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __Q6APM_H__ +#define __Q6APM_H__ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "audioreach.h" + +#define APM_PORT_MAX 127 +#define APM_PORT_MAX_AUDIO_CHAN_CNT 8 +#define PCM_CHANNEL_NULL 0 +#define PCM_CHANNEL_FL 1 /* Front left channel. */ +#define PCM_CHANNEL_FR 2 /* Front right channel. */ +#define PCM_CHANNEL_FC 3 /* Front center channel. */ +#define PCM_CHANNEL_LS 4 /* Left surround channel. */ +#define PCM_CHANNEL_RS 5 /* Right surround channel. */ +#define PCM_CHANNEL_LFE 6 /* Low frequency effect channel. */ +#define PCM_CHANNEL_CS 7 /* Center surround channel; Rear center ch */ +#define PCM_CHANNEL_LB 8 /* Left back channel; Rear left channel. */ +#define PCM_CHANNEL_RB 9 /* Right back channel; Rear right channel. */ +#define PCM_CHANNELS 10 /* Top surround channel. */ + +#define NO_TIMESTAMP 0xFF00 +#define FORMAT_LINEAR_PCM 0x0000 +/* APM client callback events */ +#define CMD_EOS 0x0003 +#define APM_CLIENT_EVENT_CMD_EOS_DONE 0x1003 +#define CMD_CLOSE 0x0004 +#define APM_CLIENT_EVENT_CMD_CLOSE_DONE 0x1004 +#define APM_CLIENT_EVENT_CMD_RUN_DONE 0x1008 +#define APM_CLIENT_EVENT_DATA_WRITE_DONE 0x1009 +#define APM_CLIENT_EVENT_DATA_READ_DONE 0x100a +#define APM_WRITE_TOKEN_MASK GENMASK(15, 0) +#define APM_WRITE_TOKEN_LEN_MASK GENMASK(31, 16) +#define APM_WRITE_TOKEN_LEN_SHIFT 16 + +#define MAX_SESSIONS 8 + +struct q6apm { + struct device *dev; + gpr_port_t *port; + gpr_device_t *gdev; + /* For Graph OPEN/START/STOP/CLOSE operations */ + wait_queue_head_t wait; + struct gpr_ibasic_rsp_result_t result; + + struct mutex cmd_lock; + uint32_t state; + + spinlock_t lock; + struct idr graph_idr; + struct idr graph_info_idr; + struct idr sub_graphs_idr; + struct idr containers_idr; + struct idr modules_idr; +}; + +struct audio_buffer { + phys_addr_t phys; + uint32_t size; /* size of buffer */ +}; + +struct audioreach_graph_data { + struct audio_buffer *buf; + uint32_t num_periods; + uint32_t dsp_buf; + uint32_t mem_map_handle; +}; + +struct audioreach_graph { + struct audioreach_graph_info *info; + uint32_t id; + int state; + int start_count; + /* Cached Graph data */ + void *graph; + struct kref refcount; + struct q6apm *apm; +}; + +typedef void (*q6apm_cb) (uint32_t opcode, uint32_t token, + void *payload, void *priv); +struct q6apm_graph { + void *priv; + q6apm_cb cb; + uint32_t id; + struct device *dev; + struct q6apm *apm; + gpr_port_t *port; + struct audioreach_graph_data rx_data; + struct audioreach_graph_data tx_data; + struct gpr_ibasic_rsp_result_t result; + spinlock_t lock; + wait_queue_head_t cmd_wait; + struct mutex cmd_lock; + struct audioreach_graph *ar_graph; + struct audioreach_graph_info *info; +}; + +/* Graph Operations */ +struct q6apm_graph *q6apm_graph_open(struct device *dev, q6apm_cb cb, + void *priv, int graph_id); +int q6apm_graph_close(struct q6apm_graph *graph); +int q6apm_graph_prepare(struct q6apm_graph *graph); +int q6apm_graph_start(struct q6apm_graph *graph); +int q6apm_graph_stop(struct q6apm_graph *graph); +int q6apm_graph_flush(struct q6apm_graph *graph); + +/* Media Format */ +int q6apm_graph_media_format_pcm(struct q6apm_graph *graph, + struct audioreach_module_config *cfg); + +int q6apm_graph_media_format_shmem(struct q6apm_graph *graph, + struct audioreach_module_config *cfg); + +/* read/write related */ +int q6apm_send_eos_nowait(struct q6apm_graph *graph); +int q6apm_read(struct q6apm_graph *graph); +int q6apm_write_async(struct q6apm_graph *graph, uint32_t len, uint32_t msw_ts, + uint32_t lsw_ts, uint32_t wflags); + +/* Memory Map related */ +int q6apm_map_memory_regions(struct q6apm_graph *graph, + unsigned int dir, phys_addr_t phys, + size_t period_sz, unsigned int periods); +int q6apm_unmap_memory_regions(struct q6apm_graph *graph, + unsigned int dir); +/* Helpers */ +int q6apm_send_cmd_sync(struct q6apm *apm, struct gpr_pkt *pkt, + uint32_t rsp_opcode); + +/* Callback for graph specific */ +struct audioreach_module *q6apm_find_module_by_mid(struct q6apm_graph *graph, + uint32_t mid); + +void q6apm_set_fe_dai_ops(struct snd_soc_dai_driver *dai_drv); +int q6apm_connect_sub_graphs(struct q6apm *apm, u32 src_sgid, u32 dst_sgid, + bool connect); +bool q6apm_is_sub_graphs_connected(struct q6apm *apm, u32 src_sgid, + u32 dst_sgid); +int q6apm_graph_get_rx_shmem_module_iid(struct q6apm_graph *graph); + +#endif /* __APM_GRAPH_ */ From patchwork Fri Sep 3 11:20:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 506519 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp906627jai; Fri, 3 Sep 2021 04:21:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyC6UZQRHWwNWshOGFs43Yn3dxeUP4bhLdT6DWRd+2p4RFQGsfezKFs1q2JkRtMqNK9cTN1 X-Received: by 2002:a02:1cc5:: with SMTP id c188mr2226753jac.46.1630668116354; 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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:52 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 16/21] ASoC: qdsp6: audioreach: add module configuration command helpers Date: Fri, 3 Sep 2021 12:20:27 +0100 Message-Id: <20210903112032.25834-17-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Audioreach module configuration helpers, which will be used by the q6apm-dai driver. Also add Kconfig and Makefile changes as now all the code for audioreach and q6apm are in at this point. Signed-off-by: Srinivas Kandagatla --- sound/soc/qcom/Kconfig | 4 + sound/soc/qcom/qdsp6/Makefile | 3 + sound/soc/qcom/qdsp6/audioreach.c | 584 ++++++++++++++++++++++++++++++ sound/soc/qcom/qdsp6/audioreach.h | 26 ++ sound/soc/qcom/qdsp6/q6apm.c | 254 +++++++++++++ 5 files changed, 871 insertions(+) -- 2.21.0 Reported-by: kernel test robot diff --git a/sound/soc/qcom/Kconfig b/sound/soc/qcom/Kconfig index cc7c1de2f1d9..5a693f83fd6c 100644 --- a/sound/soc/qcom/Kconfig +++ b/sound/soc/qcom/Kconfig @@ -84,6 +84,9 @@ config SND_SOC_QDSP6_ASM_DAI select SND_SOC_COMPRESS tristate +config SND_SOC_QDSP6_APM + tristate + config SND_SOC_QDSP6 tristate "SoC ALSA audio driver for QDSP6" depends on QCOM_APR @@ -97,6 +100,7 @@ config SND_SOC_QDSP6 select SND_SOC_QDSP6_ROUTING select SND_SOC_QDSP6_ASM select SND_SOC_QDSP6_ASM_DAI + select SND_SOC_QDSP6_APM help To add support for MSM QDSP6 Soc Audio. This will enable sound soc platform specific diff --git a/sound/soc/qcom/qdsp6/Makefile b/sound/soc/qcom/qdsp6/Makefile index a4191d395557..1a0803d97eec 100644 --- a/sound/soc/qcom/qdsp6/Makefile +++ b/sound/soc/qcom/qdsp6/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only snd-q6dsp-common-objs := q6dsp-common.o q6dsp-lpass-ports.o q6dsp-lpass-clocks.o +snd-q6apm-objs := q6apm.o audioreach.o obj-$(CONFIG_SND_SOC_QDSP6_COMMON) += snd-q6dsp-common.o obj-$(CONFIG_SND_SOC_QDSP6_CORE) += q6core.o @@ -10,3 +11,5 @@ obj-$(CONFIG_SND_SOC_QDSP6_ADM) += q6adm.o obj-$(CONFIG_SND_SOC_QDSP6_ROUTING) += q6routing.o obj-$(CONFIG_SND_SOC_QDSP6_ASM) += q6asm.o obj-$(CONFIG_SND_SOC_QDSP6_ASM_DAI) += q6asm-dai.o + +obj-$(CONFIG_SND_SOC_QDSP6_APM) += snd-q6apm.o diff --git a/sound/soc/qcom/qdsp6/audioreach.c b/sound/soc/qcom/qdsp6/audioreach.c index 6106ee46990e..e34a3094cdca 100644 --- a/sound/soc/qcom/qdsp6/audioreach.c +++ b/sound/soc/qcom/qdsp6/audioreach.c @@ -4,6 +4,10 @@ #include #include #include +#include +#include +#include +#include #include #include "q6apm.h" #include "audioreach.h" @@ -584,3 +588,583 @@ void *audioreach_alloc_graph_pkt(struct q6apm *apm, return pkt; } EXPORT_SYMBOL_GPL(audioreach_alloc_graph_pkt); + +int audioreach_graph_send_cmd_sync(struct q6apm_graph *graph, + struct gpr_pkt *pkt, uint32_t rsp_opcode) +{ + + struct device *dev = graph->dev; + struct gpr_hdr *hdr = &pkt->hdr; + int rc; + + mutex_lock(&graph->cmd_lock); + graph->result.opcode = 0; + graph->result.status = 0; + + rc = gpr_send_port_pkt(graph->port, pkt); + if (rc < 0) + goto err; + + if (rsp_opcode) + rc = wait_event_timeout(graph->cmd_wait, + (graph->result.opcode == hdr->opcode) || + (graph->result.opcode == rsp_opcode), + 5 * HZ); + else + rc = wait_event_timeout(graph->cmd_wait, + (graph->result.opcode == hdr->opcode), + 5 * HZ); + + if (!rc) { + dev_err(dev, "CMD timeout for [%x] opcode\n", hdr->opcode); + rc = -ETIMEDOUT; + } else if (graph->result.status > 0) { + dev_err(dev, "DSP returned error[%x] %x\n", hdr->opcode, + graph->result.status); + rc = -EINVAL; + } else { + dev_err(dev, "DSP returned [%x]\n", graph->result.status); + rc = 0; + } + +err: + mutex_unlock(&graph->cmd_lock); + return rc; +} +EXPORT_SYMBOL_GPL(audioreach_graph_send_cmd_sync); + +static int audioreach_codec_dma_set_media_format(struct q6apm_graph *graph, + struct audioreach_module *module, + struct audioreach_module_config *cfg) +{ + struct apm_module_param_data *param_data; + struct apm_codec_dma_module_intf_cfg *intf_cfg; + struct apm_module_hw_ep_mf_cfg *hw_cfg; + struct apm_module_frame_size_factor_cfg *fs_cfg; + struct apm_module_hw_ep_power_mode_cfg *pm_cfg; + int ic_sz, ep_sz, fs_sz, pm_sz, dl_sz; + int rc, payload_size; + struct gpr_pkt *pkt; + void *p; + + ic_sz = APM_CDMA_INTF_CFG_PSIZE; + ep_sz = APM_HW_EP_CFG_PSIZE; + fs_sz = APM_FS_CFG_PSIZE; + pm_sz = APM_HW_EP_PMODE_CFG_PSIZE; + dl_sz = 0; + + payload_size = ic_sz + ep_sz + fs_sz + pm_sz + dl_sz; + + p = audioreach_alloc_apm_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0); + if (IS_ERR(p)) + return -ENOMEM; + + pkt = p; + p = p + GPR_HDR_SIZE + APM_CMD_HDR_SIZE; + + hw_cfg = p; + param_data = &hw_cfg->param_data; + param_data->module_instance_id = module->instance_id; + param_data->error_code = 0; + param_data->param_id = PARAM_ID_HW_EP_MF_CFG; + param_data->param_size = ep_sz - APM_MODULE_PARAM_DATA_SIZE; + + hw_cfg->mf.sample_rate = cfg->sample_rate; + hw_cfg->mf.bit_width = cfg->bit_width; + hw_cfg->mf.num_channels = cfg->num_channels; + hw_cfg->mf.data_format = module->data_format; + p += ep_sz; + + fs_cfg = p; + param_data = &fs_cfg->param_data; + param_data->module_instance_id = module->instance_id; + param_data->error_code = 0; + param_data->param_id = PARAM_ID_HW_EP_FRAME_SIZE_FACTOR; + param_data->param_size = fs_sz - APM_MODULE_PARAM_DATA_SIZE; + fs_cfg->frame_size_factor = 1; + p += fs_sz; + + intf_cfg = p; + param_data = &intf_cfg->param_data; + param_data->module_instance_id = module->instance_id; + param_data->error_code = 0; + param_data->param_id = PARAM_ID_CODEC_DMA_INTF_CFG; + param_data->param_size = ic_sz - APM_MODULE_PARAM_DATA_SIZE; + + intf_cfg->cfg.lpaif_type = module->hw_interface_type; + intf_cfg->cfg.intf_index = module->hw_interface_idx; + intf_cfg->cfg.active_channels_mask = (1 << cfg->num_channels) - 1; + p += ic_sz; + + pm_cfg = p; + param_data = &pm_cfg->param_data; + param_data->module_instance_id = module->instance_id; + param_data->error_code = 0; + param_data->param_id = PARAM_ID_HW_EP_POWER_MODE_CFG; + param_data->param_size = pm_sz - APM_MODULE_PARAM_DATA_SIZE; + pm_cfg->power_mode.power_mode = 0; + + rc = q6apm_send_cmd_sync(graph->apm, pkt, 0); + + kfree(pkt); + + return rc; +} + +static int audioreach_i2s_set_media_format(struct q6apm_graph *graph, + struct audioreach_module *module, + struct audioreach_module_config *cfg) +{ + struct apm_module_frame_size_factor_cfg *fs_cfg; + struct apm_module_param_data *param_data; + struct apm_i2s_module_intf_cfg *intf_cfg; + struct apm_module_hw_ep_mf_cfg *hw_cfg; + int ic_sz, ep_sz, fs_sz; + int rc, payload_size; + struct gpr_pkt *pkt; + void *p; + + ic_sz = APM_I2S_INTF_CFG_PSIZE; + ep_sz = APM_HW_EP_CFG_PSIZE; + fs_sz = APM_FS_CFG_PSIZE; + + payload_size = ic_sz + ep_sz + fs_sz; + + p = audioreach_alloc_apm_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0); + if (IS_ERR(p)) + return -ENOMEM; + + pkt = p; + p = p + GPR_HDR_SIZE + APM_CMD_HDR_SIZE; + intf_cfg = p; + + param_data = &intf_cfg->param_data; + param_data->module_instance_id = module->instance_id; + param_data->error_code = 0; + param_data->param_id = PARAM_ID_I2S_INTF_CFG; + param_data->param_size = ic_sz - APM_MODULE_PARAM_DATA_SIZE; + + intf_cfg->cfg.intf_idx = module->hw_interface_idx; + intf_cfg->cfg.sd_line_idx = module->sd_line_idx; + + switch (cfg->fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + intf_cfg->cfg.ws_src = CONFIG_I2S_WS_SRC_INTERNAL; + break; + case SND_SOC_DAIFMT_CBM_CFM: + /* CPU is slave */ + intf_cfg->cfg.ws_src = CONFIG_I2S_WS_SRC_EXTERNAL; + break; + default: + break; + } + + p += ic_sz; + hw_cfg = p; + param_data = &hw_cfg->param_data; + param_data->module_instance_id = module->instance_id; + param_data->error_code = 0; + param_data->param_id = PARAM_ID_HW_EP_MF_CFG; + param_data->param_size = ep_sz - APM_MODULE_PARAM_DATA_SIZE; + + hw_cfg->mf.sample_rate = cfg->sample_rate; + hw_cfg->mf.bit_width = cfg->bit_width; + hw_cfg->mf.num_channels = cfg->num_channels; + hw_cfg->mf.data_format = module->data_format; + + p += ep_sz; + fs_cfg = p; + param_data = &fs_cfg->param_data; + param_data->module_instance_id = module->instance_id; + param_data->error_code = 0; + param_data->param_id = PARAM_ID_HW_EP_FRAME_SIZE_FACTOR; + param_data->param_size = fs_sz - APM_MODULE_PARAM_DATA_SIZE; + fs_cfg->frame_size_factor = 1; + + rc = q6apm_send_cmd_sync(graph->apm, pkt, 0); + + kfree(pkt); + + return rc; +} + +static int audioreach_logging_set_media_format(struct q6apm_graph *graph, + struct audioreach_module *module) +{ + struct apm_module_param_data *param_data; + struct data_logging_config *cfg; + int rc, payload_size; + struct gpr_pkt *pkt; + void *p; + + payload_size = sizeof(*cfg) + APM_MODULE_PARAM_DATA_SIZE; + p = audioreach_alloc_apm_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0); + if (IS_ERR(p)) + return -ENOMEM; + + pkt = p; + p = p + GPR_HDR_SIZE + APM_CMD_HDR_SIZE; + + param_data = p; + param_data->module_instance_id = module->instance_id; + param_data->error_code = 0; + param_data->param_id = PARAM_ID_DATA_LOGGING_CONFIG; + param_data->param_size = payload_size - APM_MODULE_PARAM_DATA_SIZE; + + p = p + APM_MODULE_PARAM_DATA_SIZE; + cfg = p; + cfg->log_code = module->log_code; + cfg->log_tap_point_id = module->log_tap_point_id; + cfg->mode = module->mode; + + rc = q6apm_send_cmd_sync(graph->apm, pkt, 0); + + kfree(pkt); + + return rc; +} + +static int audioreach_pcm_set_media_format(struct q6apm_graph *graph, + struct audioreach_module *module, + struct audioreach_module_config *mcfg) +{ + struct apm_pcm_module_media_fmt_cmd *cfg; + struct apm_module_param_data *param_data; + uint32_t num_channels = mcfg->num_channels; + int rc, payload_size; + struct gpr_pkt *pkt; + void *p; + + payload_size = APM_PCM_MODULE_FMT_CMD_PSIZE(num_channels); + + p = audioreach_alloc_apm_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0); + if (IS_ERR(p)) + return -ENOMEM; + + pkt = p; + p = p + GPR_HDR_SIZE + APM_CMD_HDR_SIZE; + cfg = p; + + param_data = &cfg->param_data; + param_data->module_instance_id = module->instance_id; + param_data->error_code = 0; + param_data->param_id = PARAM_ID_PCM_OUTPUT_FORMAT_CFG; + param_data->param_size = payload_size - APM_MODULE_PARAM_DATA_SIZE; + + cfg->header.data_format = DATA_FORMAT_FIXED_POINT; + cfg->header.fmt_id = MEDIA_FMT_ID_PCM; + cfg->header.payload_size = APM_PCM_OUT_FMT_CFG_PSIZE(num_channels); + + cfg->media_cfg.alignment = PCM_LSB_ALIGNED; + cfg->media_cfg.bit_width = mcfg->bit_width; + cfg->media_cfg.endianness = PCM_LITTLE_ENDIAN; + cfg->media_cfg.interleaved = module->interleave_type; + cfg->media_cfg.num_channels = mcfg->num_channels; + cfg->media_cfg.q_factor = mcfg->bit_width - 1; + cfg->media_cfg.bits_per_sample = mcfg->bit_width; + + if (num_channels == 1) { + cfg->media_cfg.channel_mapping[0] = PCM_CHANNEL_L; + } else if (num_channels == 2) { + cfg->media_cfg.channel_mapping[0] = PCM_CHANNEL_L; + cfg->media_cfg.channel_mapping[1] = PCM_CHANNEL_R; + } else { + dev_err(graph->dev, "Error: Invalid channels (%d)!\n", num_channels); + rc = -EINVAL; + goto err; + + } + + rc = q6apm_send_cmd_sync(graph->apm, pkt, 0); +err: + kfree(pkt); + + return rc; +} + +static int audioreach_shmem_set_media_format(struct q6apm_graph *graph, + struct audioreach_module *module, + struct audioreach_module_config *mcfg) +{ + struct apm_module_param_data *param_data; + struct payload_media_fmt_pcm *cfg; + struct media_format *header; + int rc, payload_size; + struct gpr_pkt *pkt; + void *p; + uint32_t num_channels = mcfg->num_channels; + + if (num_channels > 2) { + dev_err(graph->dev, "Error: Invalid channels (%d)!\n", num_channels); + return -EINVAL; + } + + payload_size = APM_SHMEM_FMT_CFG_PSIZE(num_channels) + APM_MODULE_PARAM_DATA_SIZE; + + p = audioreach_alloc_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0, + graph->port->id, module->instance_id); + if (IS_ERR(p)) + return -ENOMEM; + + pkt = p; + p = p + GPR_HDR_SIZE + APM_CMD_HDR_SIZE; + + param_data = p; + param_data->module_instance_id = module->instance_id; + param_data->error_code = 0; + param_data->param_id = PARAM_ID_MEDIA_FORMAT; + param_data->param_size = payload_size - APM_MODULE_PARAM_DATA_SIZE; + p = p + APM_MODULE_PARAM_DATA_SIZE; + + header = p; + header->data_format = DATA_FORMAT_FIXED_POINT; + header->fmt_id = MEDIA_FMT_ID_PCM; + header->payload_size = payload_size - sizeof(*header); + + p = p + sizeof(*header); + cfg = p; + cfg->sample_rate = mcfg->sample_rate; + cfg->bit_width = mcfg->bit_width; + cfg->alignment = PCM_LSB_ALIGNED; + cfg->bits_per_sample = mcfg->bit_width; + cfg->q_factor = mcfg->bit_width - 1; + cfg->endianness = PCM_LITTLE_ENDIAN; + cfg->num_channels = mcfg->num_channels; + + if (mcfg->num_channels == 1) { + cfg->channel_mapping[0] = PCM_CHANNEL_L; + } else if (num_channels == 2) { + cfg->channel_mapping[0] = PCM_CHANNEL_L; + cfg->channel_mapping[1] = PCM_CHANNEL_R; + } else { + dev_err(graph->dev, "Error: Invalid channels (%d)!\n", num_channels); + rc = -EINVAL; + goto err; + } + + rc = audioreach_graph_send_cmd_sync(graph, pkt, 0); +err: + kfree(pkt); + + return rc; +} + +int audioreach_gain_set_vol_ctrl(struct q6apm *apm, struct audioreach_module + *module, int vol) +{ + struct apm_module_param_data *param_data; + struct param_id_vol_ctrl_master_gain *cfg; + int rc, payload_size; + struct gpr_pkt *pkt; + void *p; + + payload_size = sizeof(*cfg) + APM_MODULE_PARAM_DATA_SIZE; + p = audioreach_alloc_apm_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0); + if (IS_ERR(p)) + return -ENOMEM; + + pkt = p; + p = p + GPR_HDR_SIZE + APM_CMD_HDR_SIZE; + + param_data = p; + param_data->module_instance_id = module->instance_id; + param_data->error_code = 0; + param_data->param_id = PARAM_ID_VOL_CTRL_MASTER_GAIN; + param_data->param_size = payload_size - APM_MODULE_PARAM_DATA_SIZE; + + p = p + APM_MODULE_PARAM_DATA_SIZE; + cfg = p; + cfg->master_gain = vol; + rc = q6apm_send_cmd_sync(apm, pkt, 0); + + kfree(pkt); + + return rc; +} +EXPORT_SYMBOL_GPL(audioreach_gain_set_vol_ctrl); + +static int audioreach_gain_set(struct q6apm_graph *graph, + struct audioreach_module *module) +{ + struct apm_module_param_data *param_data; + struct apm_gain_module_cfg *cfg; + int rc, payload_size; + struct gpr_pkt *pkt; + void *p; + + payload_size = APM_GAIN_CFG_PSIZE; + p = audioreach_alloc_apm_cmd_pkt(payload_size, APM_CMD_SET_CFG, 0); + if (IS_ERR(p)) + return -ENOMEM; + + pkt = p; + p = p + GPR_HDR_SIZE + APM_CMD_HDR_SIZE; + cfg = p; + + param_data = &cfg->param_data; + param_data->module_instance_id = module->instance_id; + param_data->error_code = 0; + param_data->param_id = APM_PARAM_ID_GAIN; + param_data->param_size = payload_size - APM_MODULE_PARAM_DATA_SIZE; + + cfg->gain_cfg.gain = module->gain; + + rc = q6apm_send_cmd_sync(graph->apm, pkt, 0); + + kfree(pkt); + + return rc; +} + +int audioreach_set_media_format(struct q6apm_graph *graph, + struct audioreach_module *module, + struct audioreach_module_config *cfg) +{ + int rc; + + switch (module->module_id) { + case MODULE_ID_DATA_LOGGING: + rc = audioreach_logging_set_media_format(graph, module); + break; + case MODULE_ID_PCM_DEC: + case MODULE_ID_PCM_ENC: + case MODULE_ID_PCM_CNV: + rc = audioreach_pcm_set_media_format(graph, module, cfg); + break; + case MODULE_ID_I2S_SOURCE: + case MODULE_ID_I2S_SINK: + rc = audioreach_i2s_set_media_format(graph, module, cfg); + break; + case MODULE_ID_WR_SHARED_MEM_EP: + rc = audioreach_shmem_set_media_format(graph, module, cfg); + break; + case MODULE_ID_GAIN: + rc = audioreach_gain_set(graph, module); + break; + case MODULE_ID_CODEC_DMA_SINK: + case MODULE_ID_CODEC_DMA_SOURCE: + rc = audioreach_codec_dma_set_media_format(graph, module, cfg); + break; + default: + rc = 0; + } + + return rc; +} +EXPORT_SYMBOL_GPL(audioreach_set_media_format); + +void audioreach_graph_free_buf(struct q6apm_graph *graph) +{ + struct audioreach_graph_data *port; + unsigned long flags; + + spin_lock_irqsave(&graph->lock, flags); + port = &graph->rx_data; + port->num_periods = 0; + kfree(port->buf); + port->buf = NULL; + + port = &graph->tx_data; + port->num_periods = 0; + kfree(port->buf); + port->buf = NULL; + spin_unlock_irqrestore(&graph->lock, flags); +} +EXPORT_SYMBOL_GPL(audioreach_graph_free_buf); + +int audioreach_map_memory_regions(struct q6apm_graph *graph, + unsigned int dir, size_t period_sz, + unsigned int periods, + bool is_contiguous) +{ + struct apm_shared_map_region_payload *mregions; + struct apm_cmd_shared_mem_map_regions *cmd; + uint32_t num_regions, buf_sz, payload_size; + struct audioreach_graph_data *data; + unsigned long flags; + struct gpr_pkt *pkt; + void *p; + int rc, i; + + if (dir == SNDRV_PCM_STREAM_PLAYBACK) + data = &graph->rx_data; + else + data = &graph->tx_data; + + if (is_contiguous) { + num_regions = 1; + buf_sz = period_sz * periods; + } else { + buf_sz = period_sz; + num_regions = periods; + } + + /* DSP expects size should be aligned to 4K */ + buf_sz = ALIGN(buf_sz, 4096); + + payload_size = sizeof(*cmd) + (sizeof(*mregions) * num_regions); + + p = audioreach_alloc_apm_pkt(payload_size, + APM_CMD_SHARED_MEM_MAP_REGIONS, dir, + graph->port->id); + if (IS_ERR(p)) + return -ENOMEM; + + pkt = p; + p = p + GPR_HDR_SIZE; + cmd = p; + cmd->mem_pool_id = APM_MEMORY_MAP_SHMEM8_4K_POOL; + cmd->num_regions = num_regions; + + cmd->property_flag = 0x0; + + mregions = p + sizeof(*cmd); + + spin_lock_irqsave(&graph->lock, flags); + + for (i = 0; i < num_regions; i++) { + struct audio_buffer *ab; + + ab = &data->buf[i]; + mregions->shm_addr_lsw = lower_32_bits(ab->phys); + mregions->shm_addr_msw = upper_32_bits(ab->phys); + mregions->mem_size_bytes = buf_sz; + ++mregions; + } + spin_unlock_irqrestore(&graph->lock, flags); + + rc = audioreach_graph_send_cmd_sync(graph, pkt, + APM_CMD_RSP_SHARED_MEM_MAP_REGIONS); + + kfree(pkt); + + return rc; +} +EXPORT_SYMBOL_GPL(audioreach_map_memory_regions); + +int audioreach_shared_memory_send_eos(struct q6apm_graph *graph) +{ + struct data_cmd_wr_sh_mem_ep_eos *eos; + struct gpr_pkt *pkt; + int rc = 0, iid; + void *p; + + iid = q6apm_graph_get_rx_shmem_module_iid(graph); + p = audioreach_alloc_cmd_pkt(sizeof(*eos), + DATA_CMD_WR_SH_MEM_EP_EOS, + 0, + graph->port->id, iid); + if (IS_ERR(p)) + return -ENOMEM; + + pkt = p; + eos = p + GPR_HDR_SIZE + APM_CMD_HDR_SIZE; + + eos->policy = WR_SH_MEM_EP_EOS_POLICY_LAST; + + rc = gpr_send_port_pkt(graph->port, pkt); + kfree(pkt); + + return rc; +} +EXPORT_SYMBOL_GPL(audioreach_shared_memory_send_eos); diff --git a/sound/soc/qcom/qdsp6/audioreach.h b/sound/soc/qcom/qdsp6/audioreach.h index d25ea8c48b41..68bf62764220 100644 --- a/sound/soc/qcom/qdsp6/audioreach.h +++ b/sound/soc/qcom/qdsp6/audioreach.h @@ -539,6 +539,14 @@ struct param_id_hw_ep_dma_data_align { uint32_t dma_data_align; } __packed; +#define PARAM_ID_VOL_CTRL_MASTER_GAIN 0x08001035 +#define VOL_CTRL_DEFAULT_GAIN 0x2000 +struct param_id_vol_ctrl_master_gain { + uint16_t master_gain; + uint16_t reserved; +} __packed; + + /* Graph */ struct audioreach_connection { /* Connections */ @@ -653,6 +661,24 @@ void *audioreach_alloc_pkt(int payload_size, uint32_t opcode, void *audioreach_alloc_graph_pkt(struct q6apm *apm, struct list_head *sg_list, int graph_id); +/* Topology specific */ +int audioreach_tplg_init(struct snd_soc_component *component); + +/* Module specific */ +void audioreach_graph_free_buf(struct q6apm_graph *graph); +int audioreach_map_memory_regions(struct q6apm_graph *graph, + unsigned int dir, size_t period_sz, + unsigned int periods, + bool is_contiguous); +int audioreach_graph_send_cmd_sync(struct q6apm_graph *graph, + struct gpr_pkt *pkt, + uint32_t rsp_opcode); +int audioreach_set_media_format(struct q6apm_graph *graph, + struct audioreach_module *module, + struct audioreach_module_config *cfg); +int audioreach_shared_memory_send_eos(struct q6apm_graph *graph); +int audioreach_gain_set_vol_ctrl(struct q6apm *apm, + struct audioreach_module *module, int vol); struct audioreach_module *audioreach_get_container_last_module( struct audioreach_container *container); struct audioreach_module *audioreach_get_container_first_module( diff --git a/sound/soc/qcom/qdsp6/q6apm.c b/sound/soc/qcom/qdsp6/q6apm.c index 5de85f477179..acb9c7ad6fcd 100644 --- a/sound/soc/qcom/qdsp6/q6apm.c +++ b/sound/soc/qcom/qdsp6/q6apm.c @@ -300,6 +300,162 @@ int q6apm_connect_sub_graphs(struct q6apm *apm, u32 src_sgid, return 0; } +int q6apm_graph_media_format_shmem(struct q6apm_graph *graph, + struct audioreach_module_config *cfg) +{ + struct audioreach_module *module; + + if (cfg->direction == SNDRV_PCM_STREAM_CAPTURE) + module = q6apm_find_module_by_mid(graph, + MODULE_ID_RD_SHARED_MEM_EP); + else + module = q6apm_find_module_by_mid(graph, + MODULE_ID_WR_SHARED_MEM_EP); + + if (!module) + return -ENODEV; + + + audioreach_set_media_format(graph, module, cfg); + + return 0; + +} +EXPORT_SYMBOL_GPL(q6apm_graph_media_format_shmem); + +int q6apm_map_memory_regions(struct q6apm_graph *graph, + unsigned int dir, phys_addr_t phys, + size_t period_sz, unsigned int periods) +{ + struct audioreach_graph_data *data; + struct audio_buffer *buf; + unsigned long flags; + int cnt; + int rc; + + if (dir == SNDRV_PCM_STREAM_PLAYBACK) + data = &graph->rx_data; + else + data = &graph->tx_data; + + spin_lock_irqsave(&graph->lock, flags); + + if (data->buf) { + dev_err(graph->dev, "Buffer already allocated\n"); + spin_unlock_irqrestore(&graph->lock, flags); + return 0; + } + + buf = kzalloc(((sizeof(struct audio_buffer)) * periods), GFP_ATOMIC); + if (!buf) { + spin_unlock_irqrestore(&graph->lock, flags); + return -ENOMEM; + } + + if (dir == SNDRV_PCM_STREAM_PLAYBACK) + data = &graph->rx_data; + else + data = &graph->tx_data; + + data->buf = buf; + + buf[0].phys = phys; + buf[0].size = period_sz; + + for (cnt = 1; cnt < periods; cnt++) { + if (period_sz > 0) { + buf[cnt].phys = buf[0].phys + (cnt * period_sz); + buf[cnt].size = period_sz; + } + } + data->num_periods = periods; + + spin_unlock_irqrestore(&graph->lock, flags); + + rc = audioreach_map_memory_regions(graph, dir, period_sz, + periods, 1); + if (rc < 0) { + dev_err(graph->dev, "Memory_map_regions failed\n"); + audioreach_graph_free_buf(graph); + } + + return rc; +} +EXPORT_SYMBOL_GPL(q6apm_map_memory_regions); + +int q6apm_unmap_memory_regions(struct q6apm_graph *graph, + unsigned int dir) +{ + struct audioreach_graph_data *data; + struct apm_cmd_shared_mem_unmap_regions *cmd = NULL; + struct gpr_pkt *pkt; + void *p; + int rc; + + if (dir == SNDRV_PCM_STREAM_PLAYBACK) + data = &graph->rx_data; + else + data = &graph->tx_data; + + if (!data->mem_map_handle) + return 0; + + p = audioreach_alloc_apm_pkt(sizeof(*cmd), + APM_CMD_SHARED_MEM_UNMAP_REGIONS, dir, + graph->port->id); + if (IS_ERR(p)) + return -ENOMEM; + + pkt = p; + cmd = p + GPR_HDR_SIZE; + cmd->mem_map_handle = data->mem_map_handle; + + rc = audioreach_graph_send_cmd_sync(graph, pkt, APM_CMD_SHARED_MEM_UNMAP_REGIONS); + kfree(pkt); + + audioreach_graph_free_buf(graph); + + return rc; +} +EXPORT_SYMBOL_GPL(q6apm_unmap_memory_regions); + +int q6apm_graph_media_format_pcm(struct q6apm_graph *graph, + struct audioreach_module_config *cfg) +{ + struct audioreach_graph_info *info = graph->info; + struct audioreach_sub_graph *sgs; + struct audioreach_container *container; + struct audioreach_module *module; + + list_for_each_entry(sgs, &info->sg_list, node) { + list_for_each_entry(container, &sgs->container_list, node) { + list_for_each_entry(module, &container->modules_list, node) { + if ((module->module_id == MODULE_ID_WR_SHARED_MEM_EP) || + (module->module_id == MODULE_ID_RD_SHARED_MEM_EP)) + continue; + + audioreach_set_media_format(graph, module, cfg); + } + } + } + + return 0; + +} +EXPORT_SYMBOL_GPL(q6apm_graph_media_format_pcm); + +static int q6apm_graph_get_tx_shmem_module_iid(struct q6apm_graph *graph) +{ + struct audioreach_module *module; + + module = q6apm_find_module_by_mid(graph, MODULE_ID_RD_SHARED_MEM_EP); + if (!module) + return -ENODEV; + + return module->instance_id; + +} + int q6apm_graph_get_rx_shmem_module_iid(struct q6apm_graph *graph) { struct audioreach_module *module; @@ -313,6 +469,104 @@ int q6apm_graph_get_rx_shmem_module_iid(struct q6apm_graph *graph) } EXPORT_SYMBOL_GPL(q6apm_graph_get_rx_shmem_module_iid); +int q6apm_write_async(struct q6apm_graph *graph, uint32_t len, uint32_t msw_ts, + uint32_t lsw_ts, uint32_t wflags) +{ + struct gpr_pkt *pkt; + void *p; + int rc, payload_size, iid; + struct apm_data_cmd_wr_sh_mem_ep_data_buffer_v2 *write; + struct audio_buffer *ab; + unsigned long flags; + + payload_size = sizeof(*write); + + iid = q6apm_graph_get_rx_shmem_module_iid(graph); + p = audioreach_alloc_pkt(payload_size, + DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER_V2, + graph->rx_data.dsp_buf | (len << APM_WRITE_TOKEN_LEN_SHIFT), + graph->port->id, iid); + if (IS_ERR(p)) + return -ENOMEM; + + pkt = p; + p = p + GPR_HDR_SIZE; + write = p; + + spin_lock_irqsave(&graph->lock, flags); + ab = &graph->rx_data.buf[graph->rx_data.dsp_buf]; + + write->buf_addr_lsw = lower_32_bits(ab->phys); + write->buf_addr_msw = upper_32_bits(ab->phys); + write->buf_size = len; + write->timestamp_lsw = lsw_ts; + write->timestamp_msw = msw_ts; + write->mem_map_handle = graph->rx_data.mem_map_handle; + + if (wflags == NO_TIMESTAMP) + write->flags = 0; + else + write->flags = 0x80000000; + + graph->rx_data.dsp_buf++; + + if (graph->rx_data.dsp_buf >= graph->rx_data.num_periods) + graph->rx_data.dsp_buf = 0; + + spin_unlock_irqrestore(&graph->lock, flags); + + rc = gpr_send_port_pkt(graph->port, pkt); + + kfree(pkt); + + return rc; +} +EXPORT_SYMBOL_GPL(q6apm_write_async); + +int q6apm_read(struct q6apm_graph *graph) +{ + struct data_cmd_rd_sh_mem_ep_data_buffer_v2 *read; + struct audioreach_graph_data *port; + struct audio_buffer *ab; + struct gpr_pkt *pkt; + unsigned long flags; + int rc = 0, iid; + void *p; + + iid = q6apm_graph_get_tx_shmem_module_iid(graph); + p = audioreach_alloc_pkt(sizeof(*read), + DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER_V2, + graph->tx_data.dsp_buf, + graph->port->id, iid); + if (IS_ERR(p)) + return -ENOMEM; + + pkt = p; + read = p + GPR_HDR_SIZE; + + spin_lock_irqsave(&graph->lock, flags); + port = &graph->tx_data; + ab = &port->buf[port->dsp_buf]; + + read->buf_addr_lsw = lower_32_bits(ab->phys); + read->buf_addr_msw = upper_32_bits(ab->phys); + read->mem_map_handle = port->mem_map_handle; + read->buf_size = ab->size; + + port->dsp_buf++; + + if (port->dsp_buf >= port->num_periods) + port->dsp_buf = 0; + + spin_unlock_irqrestore(&graph->lock, flags); + + rc = gpr_send_port_pkt(graph->port, pkt); + kfree(pkt); + + return rc; +} +EXPORT_SYMBOL_GPL(q6apm_read); + static int graph_callback(struct gpr_resp_pkt *data, void *priv, int op) { struct q6apm_graph *graph = priv; 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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:53 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 17/21] ASoC: qdsp6: audioreach: add topology support Date: Fri, 3 Sep 2021 12:20:28 +0100 Message-Id: <20210903112032.25834-18-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add ASoC topology support in audioreach Signed-off-by: Srinivas Kandagatla --- include/uapi/sound/snd_ar_tokens.h | 203 +++++ sound/soc/qcom/Kconfig | 1 + sound/soc/qcom/qdsp6/Makefile | 2 +- sound/soc/qcom/qdsp6/q6apm.c | 4 +- sound/soc/qcom/qdsp6/topology.c | 1118 ++++++++++++++++++++++++++++ 5 files changed, 1326 insertions(+), 2 deletions(-) create mode 100644 include/uapi/sound/snd_ar_tokens.h create mode 100644 sound/soc/qcom/qdsp6/topology.c -- 2.21.0 Reported-by: kernel test robot diff --git a/include/uapi/sound/snd_ar_tokens.h b/include/uapi/sound/snd_ar_tokens.h new file mode 100644 index 000000000000..1a2582af0251 --- /dev/null +++ b/include/uapi/sound/snd_ar_tokens.h @@ -0,0 +1,203 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ + +#ifndef __SND_AR_TOKENS_H__ +#define __SND_AR_TOKENS_H__ + +#define APM_SUB_GRAPH_PERF_MODE_LOW_POWER 0x1 +#define APM_SUB_GRAPH_PERF_MODE_LOW_LATENCY 0x2 + +#define APM_SUB_GRAPH_DIRECTION_TX 0x1 +#define APM_SUB_GRAPH_DIRECTION_RX 0x2 + +/** Scenario ID Audio Playback */ +#define APM_SUB_GRAPH_SID_AUDIO_PLAYBACK 0x1 +/* Scenario ID Audio Record */ +#define APM_SUB_GRAPH_SID_AUDIO_RECORD 0x2 +/* Scenario ID Voice call. */ +#define APM_SUB_GRAPH_SID_VOICE_CALL 0x3 + +/* container capability ID Pre/Post Processing (PP) */ +#define APM_CONTAINER_CAP_ID_PP 0x1 +/* container capability ID Compression/Decompression (CD) */ +#define APM_CONTAINER_CAP_ID_CD 0x2 +/* container capability ID End Point(EP) */ +#define APM_CONTAINER_CAP_ID_EP 0x3 +/* container capability ID Offload (OLC) */ +#define APM_CONTAINER_CAP_ID_OLC 0x4 + +/* container graph position Stream */ +#define APM_CONT_GRAPH_POS_STREAM 0x1 +/* container graph position Per Stream Per Device*/ +#define APM_CONT_GRAPH_POS_PER_STR_PER_DEV 0x2 +/* container graph position Stream-Device */ +#define APM_CONT_GRAPH_POS_STR_DEV 0x3 +/* container graph position Global Device */ +#define APM_CONT_GRAPH_POS_GLOBAL_DEV 0x4 + +#define APM_PROC_DOMAIN_ID_MDSP 0x1 +#define APM_PROC_DOMAIN_ID_ADSP 0x2 +#define APM_PROC_DOMAIN_ID_SDSP 0x4 +#define APM_PROC_DOMAIN_ID_CDSP 0x5 + +#define PCM_INTERLEAVED 1 +#define PCM_DEINTERLEAVED_PACKED 2 +#define PCM_DEINTERLEAVED_UNPACKED 3 +#define AR_I2S_WS_SRC_EXTERNAL 0 +#define AR_I2S_WS_SRC_INTERNAL 1 + +/* + * Kcontrol IDs + */ +#define SND_SOC_AR_TPLG_FE_BE_GRAPH_CTL_MIX 256 +#define SND_SOC_AR_TPLG_VOL_CTL 257 + +/** + * %AR_TKN_U32_SUB_GRAPH_INSTANCE_ID: Sub Graph Instance Id + * + * %AR_TKN_U32_SUB_GRAPH_PERF_MODE: Performance mode of subgraph + * APM_SUB_GRAPH_PERF_MODE_LOW_POWER = 1, + * APM_SUB_GRAPH_PERF_MODE_LOW_LATENCY = 2 + * + * %AR_TKN_U32_SUB_GRAPH_DIRECTION: Direction of subgraph + * APM_SUB_GRAPH_DIRECTION_TX = 1, + * APM_SUB_GRAPH_DIRECTION_RX = 2 + * + * %AR_TKN_U32_SUB_GRAPH_SCENARIO_ID: Scenario ID for subgraph + * APM_SUB_GRAPH_SID_AUDIO_PLAYBACK = 1, + * APM_SUB_GRAPH_SID_AUDIO_RECORD = 2, + * APM_SUB_GRAPH_SID_VOICE_CALL = 3 + * + * %AR_TKN_U32_CONTAINER_INSTANCE_ID: Container Instance ID + * + * %AR_TKN_U32_CONTAINER_CAPABILITY_ID: Container capability ID + * APM_CONTAINER_CAP_ID_PP = 1, + * APM_CONTAINER_CAP_ID_CD = 2, + * APM_CONTAINER_CAP_ID_EP = 3, + * APM_CONTAINER_CAP_ID_OLC = 4 + * + * %AR_TKN_U32_CONTAINER_STACK_SIZE: Stack size in the container. + * + * %AR_TKN_U32_CONTAINER_GRAPH_POS: Graph Position + * APM_CONT_GRAPH_POS_STREAM = 1, + * APM_CONT_GRAPH_POS_PER_STR_PER_DEV = 2, + * APM_CONT_GRAPH_POS_STR_DEV = 3, + * APM_CONT_GRAPH_POS_GLOBAL_DEV = 4 + * + * %AR_TKN_U32_CONTAINER_PROC_DOMAIN: Processor domain of container + * APM_PROC_DOMAIN_ID_MDSP = 1, + * APM_PROC_DOMAIN_ID_ADSP = 2, + * APM_PROC_DOMAIN_ID_SDSP = 4, + * APM_PROC_DOMAIN_ID_CDSP = 5 + * + * %AR_TKN_U32_MODULE_ID: Module ID + * + * %AR_TKN_U32_MODULE_INSTANCE_ID: Module Instance ID. + * + * %AR_TKN_U32_MODULE_MAX_IP_PORTS: Module maximum input ports + * + * %AR_TKN_U32_MODULE_MAX_OP_PORTS: Module maximum output ports. + * + * %AR_TKN_U32_MODULE_IN_PORTS: Number of in ports + * + * %AR_TKN_U32_MODULE_OUT_PORTS: Number of out ports. + * + * %AR_TKN_U32_MODULE_SRC_OP_PORT_ID: Source module output port ID + * + * %AR_TKN_U32_MODULE_DST_IN_PORT_ID: Destination module input port ID + * + * %AR_TKN_U32_MODULE_HW_IF_IDX: Interface index types for I2S/LPAIF + * + * %AR_TKN_U32_MODULE_HW_IF_TYPE: Interface type + * LPAIF = 0, + * LPAIF_RXTX = 1, + * LPAIF_WSA = 2, + * LPAIF_VA = 3, + * LPAIF_AXI = 4 + * + * %AR_TKN_U32_MODULE_FMT_INTERLEAVE: PCM Interleaving + * PCM_INTERLEAVED = 1, + * PCM_DEINTERLEAVED_PACKED = 2, + * PCM_DEINTERLEAVED_UNPACKED = 3 + * + * %AR_TKN_U32_MODULE_FMT_DATA: data format + * FIXED POINT = 1, + * IEC60958 PACKETIZED = 3, + * IEC60958 PACKETIZED NON LINEAR = 8, + * COMPR OVER PCM PACKETIZED = 7, + * IEC61937 PACKETIZED = 2, + * GENERIC COMPRESSED = 5 + * + * %AR_TKN_U32_MODULE_FMT_FREQ: bit rate + * + * %AR_TKN_U32_MODULE_FMT_BIT_DEPTH: bit depth + * + * %AR_TKN_U32_MODULE_SD_LINE_IDX: I2S serial data line idx + * I2S_SD0 = 1, + * I2S_SD1 = 2, + * I2S_SD2 = 3, + * I2S_SD3 = 4, + * I2S_QUAD01 = 5, + * I2S_QUAD23 = 6, + * I2S_6CHS = 7, + * I2S_8CHS = 8 + * + * %AR_TKN_U32_MODULE_WS_SRC: Word Select Source + * AR_I2S_WS_SRC_EXTERNAL = 0, + * AR_I2S_WS_SRC_INTERNAL = 1, + * + * %AR_TKN_U32_MODULE_FRAME_SZ_FACTOR: Frame size factor + * + * %AR_TKN_U32_MODULE_LOG_CODE: Log Module Code + * + * %AR_TKN_U32_MODULE_LOG_TAP_POINT_ID: logging tap point of this module + * + * %AR_TKN_U32_MODULE_LOG_MODE: logging mode + * LOG_WAIT = 0, + * LOG_IMMEDIATELY = 1 + * + * %AR_TKN_DAI_INDEX: dai index + * + */ + +/* DAI Tokens */ +#define AR_TKN_DAI_INDEX 1 +/* SUB GRAPH Tokens */ +#define AR_TKN_U32_SUB_GRAPH_INSTANCE_ID 2 +#define AR_TKN_U32_SUB_GRAPH_PERF_MODE 3 +#define AR_TKN_U32_SUB_GRAPH_DIRECTION 4 +#define AR_TKN_U32_SUB_GRAPH_SCENARIO_ID 5 + +/* Container Tokens */ +#define AR_TKN_U32_CONTAINER_INSTANCE_ID 100 +#define AR_TKN_U32_CONTAINER_CAPABILITY_ID 101 +#define AR_TKN_U32_CONTAINER_STACK_SIZE 102 +#define AR_TKN_U32_CONTAINER_GRAPH_POS 103 +#define AR_TKN_U32_CONTAINER_PROC_DOMAIN 104 + +/* Module Tokens */ +#define AR_TKN_U32_MODULE_ID 200 +#define AR_TKN_U32_MODULE_INSTANCE_ID 201 +#define AR_TKN_U32_MODULE_MAX_IP_PORTS 202 +#define AR_TKN_U32_MODULE_MAX_OP_PORTS 203 +#define AR_TKN_U32_MODULE_IN_PORTS 204 +#define AR_TKN_U32_MODULE_OUT_PORTS 205 +#define AR_TKN_U32_MODULE_SRC_OP_PORT_ID 206 +#define AR_TKN_U32_MODULE_DST_IN_PORT_ID 207 +#define AR_TKN_U32_MODULE_SRC_INSTANCE_ID 208 +#define AR_TKN_U32_MODULE_DST_INSTANCE_ID 209 + + +#define AR_TKN_U32_MODULE_HW_IF_IDX 250 +#define AR_TKN_U32_MODULE_HW_IF_TYPE 251 +#define AR_TKN_U32_MODULE_FMT_INTERLEAVE 252 +#define AR_TKN_U32_MODULE_FMT_DATA 253 +#define AR_TKN_U32_MODULE_FMT_FREQ 254 +#define AR_TKN_U32_MODULE_FMT_BIT_DEPTH 255 +#define AR_TKN_U32_MODULE_SD_LINE_IDX 256 +#define AR_TKN_U32_MODULE_WS_SRC 257 +#define AR_TKN_U32_MODULE_FRAME_SZ_FACTOR 258 +#define AR_TKN_U32_MODULE_LOG_CODE 259 +#define AR_TKN_U32_MODULE_LOG_TAP_POINT_ID 260 +#define AR_TKN_U32_MODULE_LOG_MODE 261 + +#endif /* __SND_AR_TOKENS_H__ */ diff --git a/sound/soc/qcom/Kconfig b/sound/soc/qcom/Kconfig index 5a693f83fd6c..66d8436ab0a8 100644 --- a/sound/soc/qcom/Kconfig +++ b/sound/soc/qcom/Kconfig @@ -100,6 +100,7 @@ config SND_SOC_QDSP6 select SND_SOC_QDSP6_ROUTING select SND_SOC_QDSP6_ASM select SND_SOC_QDSP6_ASM_DAI + select SND_SOC_TOPOLOGY select SND_SOC_QDSP6_APM help To add support for MSM QDSP6 Soc Audio. diff --git a/sound/soc/qcom/qdsp6/Makefile b/sound/soc/qcom/qdsp6/Makefile index 1a0803d97eec..766b824f6597 100644 --- a/sound/soc/qcom/qdsp6/Makefile +++ b/sound/soc/qcom/qdsp6/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only snd-q6dsp-common-objs := q6dsp-common.o q6dsp-lpass-ports.o q6dsp-lpass-clocks.o -snd-q6apm-objs := q6apm.o audioreach.o +snd-q6apm-objs := q6apm.o audioreach.o topology.o obj-$(CONFIG_SND_SOC_QDSP6_COMMON) += snd-q6dsp-common.o obj-$(CONFIG_SND_SOC_QDSP6_CORE) += q6core.o diff --git a/sound/soc/qcom/qdsp6/q6apm.c b/sound/soc/qcom/qdsp6/q6apm.c index acb9c7ad6fcd..1b7ba454f87d 100644 --- a/sound/soc/qcom/qdsp6/q6apm.c +++ b/sound/soc/qcom/qdsp6/q6apm.c @@ -785,11 +785,13 @@ EXPORT_SYMBOL_GPL(q6apm_graph_flush); static int q6apm_audio_probe(struct snd_soc_component *component) { - return 0; + return audioreach_tplg_init(component); } static void q6apm_audio_remove(struct snd_soc_component *component) { + /* remove topology */ + snd_soc_tplg_component_remove(component); } #define APM_AUDIO_DRV_NAME "q6apm-audio" diff --git a/sound/soc/qcom/qdsp6/topology.c b/sound/soc/qcom/qdsp6/topology.c new file mode 100644 index 000000000000..37d21d7898f1 --- /dev/null +++ b/sound/soc/qcom/qdsp6/topology.c @@ -0,0 +1,1118 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2020, Linaro Limited + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "q6apm.h" +#include "audioreach.h" + +struct snd_ar_control { + u32 sgid; /* Sub Graph ID */ + struct snd_soc_component *scomp; +}; + +static struct audioreach_graph_info *audioreach_tplg_alloc_graph_info( + struct q6apm *apm, uint32_t graph_id, + bool *found) +{ + struct audioreach_graph_info *info; + int ret; + + spin_lock(&apm->lock); + info = idr_find(&apm->graph_info_idr, graph_id); + spin_unlock(&apm->lock); + + if (info) { + *found = true; + return info; + } + + *found = false; + info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) + return ERR_PTR(-ENOMEM); + + + INIT_LIST_HEAD(&info->sg_list); + spin_lock_init(&info->sg_list_lock); + + spin_lock(&apm->lock); + ret = idr_alloc(&apm->graph_info_idr, info, graph_id, + graph_id + 1, GFP_ATOMIC); + spin_unlock(&apm->lock); + + if (ret < 0) { + dev_err(apm->dev, "Failed to allocate Graph ID (%x)\n", graph_id); + kfree(info); + return ERR_PTR(ret); + } + + info->id = ret; + + return info; +} + +static void audioreach_tplg_add_sub_graph(struct audioreach_sub_graph *sg, + struct audioreach_graph_info *info) +{ + list_add_tail(&sg->node, &info->sg_list); + sg->info = info; + info->num_sub_graphs++; +} + + +static struct audioreach_sub_graph *audioreach_tplg_alloc_sub_graph( + struct q6apm *apm, + uint32_t sub_graph_id, + bool *found) +{ + struct audioreach_sub_graph *sg = NULL; + int ret; + + if (!sub_graph_id) + return ERR_PTR(-EINVAL); + + /* Find if there is already a matching sub-graph */ + spin_lock(&apm->lock); + sg = idr_find(&apm->sub_graphs_idr, sub_graph_id); + spin_unlock(&apm->lock); + + + if (sg) { + *found = true; + return sg; + } + + *found = false; + sg = kzalloc(sizeof(*sg), GFP_KERNEL); + if (!sg) + return ERR_PTR(-ENOMEM); + + INIT_LIST_HEAD(&sg->container_list); + + spin_lock(&apm->lock); + ret = idr_alloc(&apm->sub_graphs_idr, sg, sub_graph_id, + sub_graph_id + 1, GFP_ATOMIC); + spin_unlock(&apm->lock); + + if (ret < 0) { + dev_err(apm->dev, + "Failed to allocate Sub-Graph Instance ID (%x)\n", + sub_graph_id); + kfree(sg); + return ERR_PTR(ret); + } + + sg->sub_graph_id = ret; + + return sg; +} + +static struct audioreach_container *audioreach_tplg_alloc_container(struct q6apm *apm, + struct audioreach_sub_graph *sg, + uint32_t container_id, + bool *found) +{ + struct audioreach_container *cont = NULL; + int ret; + + if (!container_id) + return ERR_PTR(-EINVAL); + + spin_lock(&apm->lock); + cont = idr_find(&apm->containers_idr, container_id); + spin_unlock(&apm->lock); + + if (cont) { + *found = true; + return cont; + } + *found = false; + + cont = kzalloc(sizeof(*cont), GFP_KERNEL); + if (!cont) + return ERR_PTR(-ENOMEM); + + INIT_LIST_HEAD(&cont->modules_list); + + spin_lock(&apm->lock); + ret = idr_alloc(&apm->containers_idr, cont, container_id, + container_id + 1, GFP_ATOMIC); + spin_unlock(&apm->lock); + + if (ret < 0) { + dev_err(apm->dev, + "Failed to allocate Container Instance ID (%x)\n", + container_id); + kfree(cont); + return ERR_PTR(ret); + } + + cont->container_id = ret; + cont->sub_graph = sg; + /* add to container list */ + list_add_tail(&cont->node, &sg->container_list); + sg->num_containers++; + + return cont; +} + +static struct audioreach_module *audioreach_tplg_alloc_module(struct q6apm *apm, + struct audioreach_container *cont, + struct snd_soc_dapm_widget *w, + uint32_t module_id, + bool *found) +{ + struct audioreach_module *mod; + int ret; + + spin_lock(&apm->lock); + mod = idr_find(&apm->modules_idr, module_id); + spin_unlock(&apm->lock); + + if (mod) { + *found = true; + return mod; + } + *found = false; + mod = kzalloc(sizeof(*mod), GFP_KERNEL); + if (!mod) + return ERR_PTR(-ENOMEM); + + spin_lock(&apm->lock); + if (!module_id) { /* alloc module id dynamically */ + ret = idr_alloc_cyclic(&apm->modules_idr, mod, + AR_MODULE_DYNAMIC_INSTANCE_ID_START, + AR_MODULE_DYNAMIC_INSTANCE_ID_END, + GFP_ATOMIC); + } else { + ret = idr_alloc(&apm->modules_idr, mod, module_id, + module_id + 1, GFP_ATOMIC); + } + spin_unlock(&apm->lock); + + if (ret < 0) { + dev_err(apm->dev, + "Failed to allocate Module Instance ID (%x)\n", module_id); + kfree(mod); + return ERR_PTR(ret); + } + + mod->instance_id = ret; + dev_err(apm->dev, "Module Instance ID (0x%08x) allocated\n", ret); + /* add to module list */ + list_add_tail(&mod->node, &cont->modules_list); + mod->container = cont; + mod->widget = w; + cont->num_modules++; + + return mod; +} + +static struct snd_soc_tplg_vendor_array *audioreach_get_sg_array( + struct snd_soc_tplg_private *private) +{ + struct snd_soc_tplg_vendor_array *sg_array = NULL; + bool found = false; + int sz; + + for (sz = 0; !found && (sz < le32_to_cpu(private->size)); ) { + struct snd_soc_tplg_vendor_value_elem *sg_elem; + int tkn_count = 0; + + sg_array = (struct snd_soc_tplg_vendor_array *)((u8 *)private->array + sz); + sg_elem = sg_array->value; + sz = sz + le32_to_cpu(sg_array->size); + while (!found && tkn_count <= (le32_to_cpu(sg_array->num_elems) - 1)) { + switch (le32_to_cpu(sg_elem->token)) { + case AR_TKN_U32_SUB_GRAPH_INSTANCE_ID: + found = true; + break; + default: + break; + } + tkn_count++; + sg_elem++; + } + } + + if (found) + return sg_array; + + return NULL; +} + +static struct snd_soc_tplg_vendor_array *audioreach_get_cont_array( + struct snd_soc_tplg_private *private) +{ + struct snd_soc_tplg_vendor_array *cont_array = NULL; + bool found = false; + int sz; + + for (sz = 0; !found && (sz < le32_to_cpu(private->size)); ) { + struct snd_soc_tplg_vendor_value_elem *cont_elem; + int tkn_count = 0; + + cont_array = (struct snd_soc_tplg_vendor_array *)((u8 *)private->array + sz); + cont_elem = cont_array->value; + sz = sz + le32_to_cpu(cont_array->size); + while (!found && tkn_count <= (le32_to_cpu(cont_array->num_elems) - 1)) { + switch (le32_to_cpu(cont_elem->token)) { + case AR_TKN_U32_CONTAINER_INSTANCE_ID: + found = true; + break; + default: + break; + } + tkn_count++; + cont_elem++; + } + } + + if (found) + return cont_array; + + return NULL; +} + +static struct snd_soc_tplg_vendor_array *audioreach_get_module_array( + struct snd_soc_tplg_private *private) +{ + struct snd_soc_tplg_vendor_array *mod_array = NULL; + bool found = false; + int sz = 0; + + for (sz = 0; !found && (sz < le32_to_cpu(private->size)); ) { + struct snd_soc_tplg_vendor_value_elem *mod_elem; + int tkn_count = 0; + + mod_array = (struct snd_soc_tplg_vendor_array *)((u8 *)private->array + sz); + mod_elem = mod_array->value; + sz = sz + le32_to_cpu(mod_array->size); + while (!found && tkn_count <= (le32_to_cpu(mod_array->num_elems) - 1)) { + switch (le32_to_cpu(mod_elem->token)) { + case AR_TKN_U32_MODULE_INSTANCE_ID: + found = true; + break; + default: + break; + } + tkn_count++; + mod_elem++; + } + } + + if (found) + return mod_array; + + return NULL; +} + +static struct audioreach_sub_graph *audioreach_parse_sg_tokens(struct q6apm *apm, + struct snd_soc_tplg_private *private) +{ + struct audioreach_graph_info *info = NULL; + struct snd_soc_tplg_vendor_array *sg_array; + struct snd_soc_tplg_vendor_value_elem *sg_elem; + struct audioreach_sub_graph *sg; + int graph_id, sub_graph_id, tkn_count = 0; + bool found; + + sg_array = audioreach_get_sg_array(private); + sg_elem = sg_array->value; + + while (tkn_count <= (le32_to_cpu(sg_array->num_elems) - 1)) { + switch (le32_to_cpu(sg_elem->token)) { + case AR_TKN_U32_SUB_GRAPH_INSTANCE_ID: + sub_graph_id = le32_to_cpu(sg_elem->value); + sg = audioreach_tplg_alloc_sub_graph(apm, sub_graph_id, &found); + if (IS_ERR(sg)) { + return sg; + } else if (found) { + /* Already parsed data for this sub-graph */ + return sg; + } + dev_err(apm->dev, "%s: New subgraph id : 0x%08x\n", __func__, + sub_graph_id); + break; + case AR_TKN_DAI_INDEX: + /* Sub graph is associated with predefined graph */ + graph_id = le32_to_cpu(sg_elem->value); + info = audioreach_tplg_alloc_graph_info(apm, graph_id, &found); + if (IS_ERR(info)) + return ERR_CAST(info); + break; + case AR_TKN_U32_SUB_GRAPH_PERF_MODE: + sg->perf_mode = le32_to_cpu(sg_elem->value); + break; + case AR_TKN_U32_SUB_GRAPH_DIRECTION: + sg->direction = le32_to_cpu(sg_elem->value); + break; + case AR_TKN_U32_SUB_GRAPH_SCENARIO_ID: + sg->scenario_id = le32_to_cpu(sg_elem->value); + break; + default: + dev_err(apm->dev, "Not a valid token %d for graph\n", + sg_elem->token); + break; + + } + tkn_count++; + sg_elem++; + } + + /* Sub graph is associated with predefined graph */ + if (info) { + dev_err(apm->dev, "%s: adding subgraph id : 0x%08x -> %d\n", __func__, + sub_graph_id, graph_id); + + audioreach_tplg_add_sub_graph(sg, info); + } + + return sg; +} + +static struct audioreach_container *audioreach_parse_cont_tokens(struct q6apm *apm, + struct audioreach_sub_graph *sg, + struct snd_soc_tplg_private *private) +{ + struct snd_soc_tplg_vendor_array *cont_array; + struct snd_soc_tplg_vendor_value_elem *cont_elem; + struct audioreach_container *cont; + int container_id, tkn_count = 0; + bool found = false; + + cont_array = audioreach_get_cont_array(private); + cont_elem = cont_array->value; + + while (tkn_count <= (le32_to_cpu(cont_array->num_elems) - 1)) { + switch (le32_to_cpu(cont_elem->token)) { + case AR_TKN_U32_CONTAINER_INSTANCE_ID: + container_id = le32_to_cpu(cont_elem->value); + cont = audioreach_tplg_alloc_container(apm, sg, container_id, &found); + if (IS_ERR(cont)) + return ERR_PTR(-ENOMEM); + else if (found) /* Already parsed container data */ + return cont; + + break; + case AR_TKN_U32_CONTAINER_CAPABILITY_ID: + cont->capability_id = le32_to_cpu(cont_elem->value); + break; + case AR_TKN_U32_CONTAINER_STACK_SIZE: + cont->stack_size = le32_to_cpu(cont_elem->value); + break; + case AR_TKN_U32_CONTAINER_GRAPH_POS: + cont->graph_pos = le32_to_cpu(cont_elem->value); + break; + case AR_TKN_U32_CONTAINER_PROC_DOMAIN: + cont->proc_domain = le32_to_cpu(cont_elem->value); + break; + default: + dev_err(apm->dev, "Not a valid token %d for graph\n", + cont_elem->token); + break; + + } + tkn_count++; + cont_elem++; + } + + return cont; +} + +static struct audioreach_module *audioreach_parse_common_tokens(struct q6apm *apm, + struct audioreach_container *cont, + struct snd_soc_tplg_private *private, + struct snd_soc_dapm_widget *w) +{ + struct snd_soc_tplg_vendor_array *mod_array; + struct snd_soc_tplg_vendor_value_elem *mod_elem; + uint32_t max_ip_port = 0, max_op_port = 0, in_port = 0, out_port = 0; + uint32_t src_mod_inst_id = 0, src_mod_op_port_id = 0; + uint32_t dst_mod_inst_id = 0, dst_mod_ip_port_id = 0; + int module_id = 0, instance_id = 0, tkn_count = 0; + struct audioreach_module *mod = NULL; + bool found; + + mod_array = audioreach_get_module_array(private); + mod_elem = mod_array->value; + + while (tkn_count <= (le32_to_cpu(mod_array->num_elems) - 1)) { + switch (le32_to_cpu(mod_elem->token)) { + /* common module info */ + case AR_TKN_U32_MODULE_ID: + module_id = le32_to_cpu(mod_elem->value); + break; + case AR_TKN_U32_MODULE_INSTANCE_ID: + instance_id = le32_to_cpu(mod_elem->value); + mod = audioreach_tplg_alloc_module(apm, cont, w, + instance_id, &found); + if (IS_ERR(mod)) { + return ERR_PTR(-ENOMEM); + } else if (found) { + dev_err(apm->dev, "Duplicate Module Instance ID 0x%08x found\n", + instance_id); + return ERR_PTR(-EINVAL); + } + + break; + case AR_TKN_U32_MODULE_MAX_IP_PORTS: + max_ip_port = le32_to_cpu(mod_elem->value); + break; + case AR_TKN_U32_MODULE_MAX_OP_PORTS: + max_op_port = le32_to_cpu(mod_elem->value); + break; + case AR_TKN_U32_MODULE_IN_PORTS: + in_port = le32_to_cpu(mod_elem->value); + break; + case AR_TKN_U32_MODULE_OUT_PORTS: + out_port = le32_to_cpu(mod_elem->value); + break; + case AR_TKN_U32_MODULE_SRC_OP_PORT_ID: + src_mod_op_port_id = le32_to_cpu(mod_elem->value); + break; + case AR_TKN_U32_MODULE_SRC_INSTANCE_ID: + src_mod_inst_id = le32_to_cpu(mod_elem->value); + break; + case AR_TKN_U32_MODULE_DST_INSTANCE_ID: + dst_mod_inst_id = le32_to_cpu(mod_elem->value); + break; + case AR_TKN_U32_MODULE_DST_IN_PORT_ID: + dst_mod_ip_port_id = le32_to_cpu(mod_elem->value); + + default: + break; + + } + tkn_count++; + mod_elem++; + } + + if (mod) { + mod->module_id = module_id; + mod->max_ip_port = max_ip_port; + mod->max_op_port = max_op_port; + mod->in_port = in_port; + mod->out_port = out_port; + mod->src_mod_inst_id = src_mod_inst_id; + mod->src_mod_op_port_id = src_mod_op_port_id; + mod->dst_mod_inst_id = dst_mod_inst_id; + mod->dst_mod_ip_port_id = dst_mod_ip_port_id; + } + + return mod; +} + +static int audioreach_widget_load_module_common(struct snd_soc_component *component, + int index, struct snd_soc_dapm_widget *w, + struct snd_soc_tplg_dapm_widget *tplg_w) +{ + struct q6apm *apm = dev_get_drvdata(component->dev); + struct audioreach_sub_graph *sg; + struct audioreach_container *cont; + struct audioreach_module *mod; + struct snd_soc_dobj *dobj; + + sg = audioreach_parse_sg_tokens(apm, &tplg_w->priv); + if (IS_ERR(sg)) + return PTR_ERR(sg); + + cont = audioreach_parse_cont_tokens(apm, sg, &tplg_w->priv); + if (IS_ERR(cont)) + return PTR_ERR(cont); + + mod = audioreach_parse_common_tokens(apm, cont, &tplg_w->priv, w); + if (IS_ERR(mod)) + return PTR_ERR(mod); + + dobj = &w->dobj; + dobj->private = mod; + + return 0; +} + +static int audioreach_widget_load_enc_dec_cnv(struct snd_soc_component *component, + int index, struct snd_soc_dapm_widget *w, + struct snd_soc_tplg_dapm_widget *tplg_w) +{ + struct snd_soc_tplg_vendor_array *mod_array; + struct snd_soc_tplg_vendor_value_elem *mod_elem; + struct audioreach_module *mod; + struct snd_soc_dobj *dobj; + int tkn_count = 0; + int ret; + + ret = audioreach_widget_load_module_common(component, index, w, tplg_w); + if (ret) + return ret; + + dobj = &w->dobj; + mod = dobj->private; + mod_array = audioreach_get_module_array(&tplg_w->priv); + mod_elem = mod_array->value; + + while (tkn_count <= (le32_to_cpu(mod_array->num_elems) - 1)) { + switch (le32_to_cpu(mod_elem->token)) { + case AR_TKN_U32_MODULE_FMT_INTERLEAVE: + mod->interleave_type = le32_to_cpu(mod_elem->value); + break; + case AR_TKN_U32_MODULE_FMT_FREQ: + mod->rate = le32_to_cpu(mod_elem->value); + break; + case AR_TKN_U32_MODULE_FMT_BIT_DEPTH: + mod->bit_depth = le32_to_cpu(mod_elem->value); + break; + default: + break; + } + tkn_count++; + mod_elem++; + } + + return 0; +} + +static int audioreach_widget_log_module_load(struct audioreach_module *mod, + struct snd_soc_tplg_vendor_array *mod_array) +{ + struct snd_soc_tplg_vendor_value_elem *mod_elem; + int tkn_count = 0; + + mod_elem = mod_array->value; + + while (tkn_count <= (le32_to_cpu(mod_array->num_elems) - 1)) { + switch (le32_to_cpu(mod_elem->token)) { + + case AR_TKN_U32_MODULE_LOG_CODE: + mod->log_code = le32_to_cpu(mod_elem->value); + break; + case AR_TKN_U32_MODULE_LOG_TAP_POINT_ID: + mod->log_tap_point_id = le32_to_cpu(mod_elem->value); + break; + case AR_TKN_U32_MODULE_LOG_MODE: + mod->mode = le32_to_cpu(mod_elem->value); + break; + default: + break; + } + tkn_count++; + mod_elem++; + } + + return 0; +} + +static int audioreach_widget_dma_module_load(struct audioreach_module *mod, + struct snd_soc_tplg_vendor_array *mod_array) +{ + struct snd_soc_tplg_vendor_value_elem *mod_elem; + int tkn_count = 0; + + mod_elem = mod_array->value; + + while (tkn_count <= (le32_to_cpu(mod_array->num_elems) - 1)) { + switch (le32_to_cpu(mod_elem->token)) { + case AR_TKN_U32_MODULE_HW_IF_IDX: + mod->hw_interface_idx = le32_to_cpu(mod_elem->value); + break; + case AR_TKN_U32_MODULE_FMT_DATA: + mod->data_format = le32_to_cpu(mod_elem->value); + break; + case AR_TKN_U32_MODULE_HW_IF_TYPE: + mod->hw_interface_type = le32_to_cpu(mod_elem->value); + break; + default: + break; + } + tkn_count++; + mod_elem++; + } + + return 0; +} + +static int audioreach_widget_i2s_module_load(struct audioreach_module *mod, + struct snd_soc_tplg_vendor_array *mod_array) +{ + struct snd_soc_tplg_vendor_value_elem *mod_elem; + int tkn_count = 0; + + mod_elem = mod_array->value; + + while (tkn_count <= (le32_to_cpu(mod_array->num_elems) - 1)) { + switch (le32_to_cpu(mod_elem->token)) { + case AR_TKN_U32_MODULE_HW_IF_IDX: + mod->hw_interface_idx = le32_to_cpu(mod_elem->value); + break; + case AR_TKN_U32_MODULE_FMT_DATA: + mod->data_format = le32_to_cpu(mod_elem->value); + break; + case AR_TKN_U32_MODULE_HW_IF_TYPE: + mod->hw_interface_type = le32_to_cpu(mod_elem->value); + break; + case AR_TKN_U32_MODULE_SD_LINE_IDX: + mod->sd_line_idx = le32_to_cpu(mod_elem->value); + break; + case AR_TKN_U32_MODULE_WS_SRC: + mod->ws_src = le32_to_cpu(mod_elem->value); + break; + default: + break; + } + tkn_count++; + mod_elem++; + } + + return 0; +} + +static int audioreach_widget_load_buffer(struct snd_soc_component *component, + int index, struct snd_soc_dapm_widget *w, + struct snd_soc_tplg_dapm_widget *tplg_w) +{ + struct snd_soc_tplg_vendor_array *mod_array; + struct audioreach_module *mod; + struct snd_soc_dobj *dobj; + int ret; + + ret = audioreach_widget_load_module_common(component, index, w, tplg_w); + if (ret) + return ret; + + dobj = &w->dobj; + mod = dobj->private; + + mod_array = audioreach_get_module_array(&tplg_w->priv); + + switch (mod->module_id) { + case MODULE_ID_CODEC_DMA_SINK: + case MODULE_ID_CODEC_DMA_SOURCE: + audioreach_widget_dma_module_load(mod, mod_array); + break; + case MODULE_ID_DATA_LOGGING: + audioreach_widget_log_module_load(mod, mod_array); + break; + case MODULE_ID_I2S_SINK: + case MODULE_ID_I2S_SOURCE: + audioreach_widget_i2s_module_load(mod, mod_array); + break; + } + + return 0; +} + +static int audioreach_widget_load_mixer(struct snd_soc_component *component, + int index, struct snd_soc_dapm_widget *w, + struct snd_soc_tplg_dapm_widget *tplg_w) +{ + struct snd_soc_tplg_vendor_value_elem *w_elem; + struct snd_soc_tplg_vendor_array *w_array; + struct snd_ar_control *scontrol; + struct snd_soc_dobj *dobj; + int tkn_count = 0; + + w_array = &tplg_w->priv.array[0]; + + scontrol = kzalloc(sizeof(*scontrol), GFP_KERNEL); + if (!scontrol) + return -ENOMEM; + + scontrol->scomp = component; + dobj = &w->dobj; + dobj->private = scontrol; + + w_elem = w_array->value; + while (tkn_count <= (le32_to_cpu(w_array->num_elems) - 1)) { + switch (le32_to_cpu(w_elem->token)) { + case AR_TKN_U32_SUB_GRAPH_INSTANCE_ID: + scontrol->sgid = le32_to_cpu(w_elem->value); + break; + default: /* ignore other tokens */ + break; + } + tkn_count++; + w_elem++; + } + + return 0; +} + +static int audioreach_widget_load_pga(struct snd_soc_component *component, + int index, struct snd_soc_dapm_widget *w, + struct snd_soc_tplg_dapm_widget *tplg_w) +{ + struct audioreach_module *mod; + struct snd_soc_dobj *dobj; + int ret; + + ret = audioreach_widget_load_module_common(component, index, w, tplg_w); + if (ret) + return ret; + + dobj = &w->dobj; + mod = dobj->private; + mod->gain = VOL_CTRL_DEFAULT_GAIN; + + return 0; +} + +static int audioreach_widget_ready(struct snd_soc_component *component, + int index, struct snd_soc_dapm_widget *w, + struct snd_soc_tplg_dapm_widget *tplg_w) +{ + switch (w->id) { + case snd_soc_dapm_aif_in: + case snd_soc_dapm_aif_out: + audioreach_widget_load_buffer(component, index, w, tplg_w); + break; + case snd_soc_dapm_decoder: + case snd_soc_dapm_encoder: + case snd_soc_dapm_src: + audioreach_widget_load_enc_dec_cnv(component, index, w, tplg_w); + break; + case snd_soc_dapm_buffer: + audioreach_widget_load_buffer(component, index, w, tplg_w); + break; + case snd_soc_dapm_mixer: + return audioreach_widget_load_mixer(component, index, w, tplg_w); + case snd_soc_dapm_pga: + return audioreach_widget_load_pga(component, index, w, tplg_w); + case snd_soc_dapm_dai_link: + case snd_soc_dapm_scheduler: + case snd_soc_dapm_out_drv: + default: + dev_err(component->dev, "Widget type (0x%x) not yet supported\n", + w->id); + break; + } + + return 0; +} + + +static int audioreach_widget_unload(struct snd_soc_component *scomp, + struct snd_soc_dobj *dobj) +{ + struct q6apm *apm = dev_get_drvdata(scomp->dev); + struct audioreach_container *cont; + struct audioreach_module *mod; + struct snd_soc_dapm_widget *w = + container_of(dobj, struct snd_soc_dapm_widget, dobj); + + mod = dobj->private; + cont = mod->container; + + if (w->id == snd_soc_dapm_mixer) { + /* virtual widget */ + kfree(dobj->private); + return 0; + } + + spin_lock(&apm->lock); + idr_remove(&apm->modules_idr, mod->instance_id); + cont->num_modules--; + + /* delete list */ + list_del(&mod->node); + /* free memory */ + kfree(mod); + + if (list_empty(&cont->modules_list)) { /* remove container */ + struct audioreach_sub_graph *sg = cont->sub_graph; + + idr_remove(&apm->containers_idr, cont->container_id); + list_del(&cont->node); + sg->num_containers--; + kfree(cont); + if (list_empty(&sg->container_list)) { /* remove sg */ + struct audioreach_graph_info *info = sg->info; + + idr_remove(&apm->sub_graphs_idr, sg->sub_graph_id); + list_del(&sg->node); + info->num_sub_graphs--; + kfree(sg); + if (list_empty(&info->sg_list)) { /* remove graph info */ + idr_remove(&apm->graph_info_idr, info->id); + kfree(info); + } + } + } + + spin_unlock(&apm->lock); + + return 0; +} + +static struct audioreach_module *audioreach_find_widget(struct snd_soc_component *comp, + const char *name) +{ + struct q6apm *apm = dev_get_drvdata(comp->dev); + struct audioreach_module *module; + int id = 0; + + idr_for_each_entry(&apm->modules_idr, module, id) { + if (!strcmp(name, module->widget->name)) + return module; + } + + return NULL; +} + +static int audioreach_route_load(struct snd_soc_component *scomp, int index, + struct snd_soc_dapm_route *route) +{ + struct audioreach_module *src, *sink; + + src = audioreach_find_widget(scomp, route->source); + sink = audioreach_find_widget(scomp, route->sink); + + if (src && sink) { + src->dst_mod_inst_id = sink->instance_id; + sink->src_mod_inst_id = src->instance_id; + } + + return 0; +} + +static int audioreach_route_unload(struct snd_soc_component *scomp, + struct snd_soc_dobj *dobj) +{ + + return 0; +} + +static void audioreach_tplg_complete(struct snd_soc_component *component) +{ + /* TBD */ +} + +/* DAI link - used for any driver specific init */ +static int audioreach_link_load(struct snd_soc_component *component, int index, + struct snd_soc_dai_link *link, + struct snd_soc_tplg_link_config *cfg) +{ + link->nonatomic = true; + link->dynamic = true; + link->platforms->name = NULL; + link->platforms->of_node = of_get_compatible_child(component->dev->of_node, + "qcom,q6apm-dais"); + link->trigger[0] = SND_SOC_DPCM_TRIGGER_POST; + link->trigger[1] = SND_SOC_DPCM_TRIGGER_POST; + + return 0; +} + +static int audioreach_get_audio_mixer(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget *dw = snd_soc_dapm_kcontrol_widget(kcontrol); + struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol); + struct snd_soc_component *c = snd_soc_dapm_to_component(dapm); + struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; + struct snd_ar_control *scontrol = mc->dobj.private; + struct snd_ar_control *dapm_scontrol = dw->dobj.private; + struct q6apm *data = dev_get_drvdata(c->dev); + bool connected; + + connected = q6apm_is_sub_graphs_connected(data, scontrol->sgid, + dapm_scontrol->sgid); + if (connected) + ucontrol->value.integer.value[0] = 1; + else + ucontrol->value.integer.value[0] = 0; + + return 0; +} + +static int audioreach_put_audio_mixer(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget *dw = snd_soc_dapm_kcontrol_widget(kcontrol); + struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol); + struct snd_soc_component *c = snd_soc_dapm_to_component(dapm); + struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; + struct snd_ar_control *scontrol = mc->dobj.private; + struct snd_ar_control *dapm_scontrol = dw->dobj.private; + struct q6apm *data = dev_get_drvdata(c->dev); + struct snd_soc_dapm_update *update = NULL; + + if (ucontrol->value.integer.value[0]) { + q6apm_connect_sub_graphs(data, scontrol->sgid, + dapm_scontrol->sgid, true); + snd_soc_dapm_mixer_update_power(dapm, kcontrol, 1, update); + } else { + q6apm_connect_sub_graphs(data, scontrol->sgid, + dapm_scontrol->sgid, false); + snd_soc_dapm_mixer_update_power(dapm, kcontrol, 0, update); + } + return 0; +} + +static int audioreach_get_vol_ctrl_audio_mixer(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget *dw = snd_soc_dapm_kcontrol_widget(kcontrol); + struct audioreach_module *mod = dw->dobj.private; + + /* Check if the graph is active or not */ + ucontrol->value.integer.value[0] = mod->gain; + + return 0; +} + +static int audioreach_put_vol_ctrl_audio_mixer(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget *dw = snd_soc_dapm_kcontrol_widget(kcontrol); + struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol); + struct snd_soc_component *c = snd_soc_dapm_to_component(dapm); + struct audioreach_module *mod = dw->dobj.private; + struct q6apm *apm = dev_get_drvdata(c->dev); + int vol = ucontrol->value.integer.value[0]; + + /* Check if the graph is active or not */ + if (dw->power) { + audioreach_gain_set_vol_ctrl(apm, mod, vol); + mod->gain = vol; + return 1; + } + + dev_err(apm->dev, "Unable to set volume as graph is not active\n"); + return 0; + +} + +static int audioreach_control_load_mix(struct snd_soc_component *scomp, + struct snd_ar_control *scontrol, + struct snd_kcontrol_new *kc, + struct snd_soc_tplg_ctl_hdr *hdr) +{ + struct snd_soc_tplg_mixer_control *mc; + struct snd_soc_tplg_vendor_array *c_array; + struct snd_soc_tplg_vendor_value_elem *c_elem; + int tkn_count = 0; + + mc = container_of(hdr, struct snd_soc_tplg_mixer_control, hdr); + c_array = (struct snd_soc_tplg_vendor_array *)mc->priv.data; + + c_elem = c_array->value; + + while (tkn_count <= (le32_to_cpu(c_array->num_elems) - 1)) { + switch (le32_to_cpu(c_elem->token)) { + case AR_TKN_U32_SUB_GRAPH_INSTANCE_ID: + scontrol->sgid = le32_to_cpu(c_elem->value); + break; + default: + /* Ignore other tokens */ + break; + + } + c_elem++; + tkn_count++; + } + + return 0; +} + +static int audioreach_control_load(struct snd_soc_component *scomp, int index, + struct snd_kcontrol_new *kc, + struct snd_soc_tplg_ctl_hdr *hdr) +{ + struct snd_ar_control *scontrol; + struct snd_soc_dobj *dobj; + struct soc_mixer_control *sm; + int ret; + + scontrol = kzalloc(sizeof(*scontrol), GFP_KERNEL); + if (!scontrol) + return -ENOMEM; + + scontrol->scomp = scomp; + + switch (le32_to_cpu(hdr->ops.get)) { + case SND_SOC_AR_TPLG_FE_BE_GRAPH_CTL_MIX: + sm = (struct soc_mixer_control *)kc->private_value; + dobj = &sm->dobj; + ret = audioreach_control_load_mix(scomp, scontrol, kc, hdr); + break; + case SND_SOC_AR_TPLG_VOL_CTL: + sm = (struct soc_mixer_control *)kc->private_value; + dobj = &sm->dobj; + break; + default: + dev_warn(scomp->dev, "control type not supported %d:%d:%d\n", + hdr->ops.get, hdr->ops.put, hdr->ops.info); + kfree(scontrol); + return -EINVAL; + } + + dobj->private = scontrol; + return ret; +} + +static int audioreach_control_unload(struct snd_soc_component *scomp, + struct snd_soc_dobj *dobj) +{ + struct snd_ar_control *scontrol = dobj->private; + + kfree(scontrol); + + return 0; +} + +static const struct snd_soc_tplg_kcontrol_ops audioreach_io_ops[] = { + {SND_SOC_AR_TPLG_FE_BE_GRAPH_CTL_MIX, audioreach_get_audio_mixer, + audioreach_put_audio_mixer, snd_soc_info_volsw}, + {SND_SOC_AR_TPLG_VOL_CTL, audioreach_get_vol_ctrl_audio_mixer, + audioreach_put_vol_ctrl_audio_mixer, snd_soc_info_volsw}, +}; + +static struct snd_soc_tplg_ops audioreach_tplg_ops = { + .io_ops = audioreach_io_ops, + .io_ops_count = ARRAY_SIZE(audioreach_io_ops), + + .control_load = audioreach_control_load, + .control_unload = audioreach_control_unload, + + .widget_ready = audioreach_widget_ready, + .widget_unload = audioreach_widget_unload, + + .complete = audioreach_tplg_complete, + .link_load = audioreach_link_load, + + .dapm_route_load = audioreach_route_load, + .dapm_route_unload = audioreach_route_unload, +}; + +int audioreach_tplg_init(struct snd_soc_component *component) +{ + struct device *dev = component->dev; + const struct firmware *fw; + int ret; + + ret = request_firmware(&fw, "audioreach.bin", dev); + if (ret < 0) { + dev_err(dev, "tplg fw audioreach.bin load failed with %d\n", ret); + return ret; + } + + ret = snd_soc_tplg_component_load(component, &audioreach_tplg_ops, fw); + if (ret < 0) { + dev_err(dev, "tplg component load failed%d\n", ret); + release_firmware(fw); + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL_GPL(audioreach_tplg_init); From patchwork Fri Sep 3 11:20:29 2021 Content-Type: text/plain; charset="utf-8" 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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:55 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 18/21] ASoC: qdsp6: audioreach: add q6apm-dai support Date: Fri, 3 Sep 2021 12:20:29 +0100 Message-Id: <20210903112032.25834-19-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Signed-off-by: Srinivas Kandagatla --- sound/soc/qcom/Kconfig | 5 + sound/soc/qcom/qdsp6/Makefile | 1 + sound/soc/qcom/qdsp6/q6apm-dai.c | 504 +++++++++++++++++++++++++++++++ 3 files changed, 510 insertions(+) create mode 100644 sound/soc/qcom/qdsp6/q6apm-dai.c -- 2.21.0 diff --git a/sound/soc/qcom/Kconfig b/sound/soc/qcom/Kconfig index 66d8436ab0a8..fb1921889dc4 100644 --- a/sound/soc/qcom/Kconfig +++ b/sound/soc/qcom/Kconfig @@ -84,7 +84,12 @@ config SND_SOC_QDSP6_ASM_DAI select SND_SOC_COMPRESS tristate +config SND_SOC_QDSP6_APM_DAI + select SND_SOC_COMPRESS + tristate + config SND_SOC_QDSP6_APM + select SND_SOC_QDSP6_APM_DAI tristate config SND_SOC_QDSP6 diff --git a/sound/soc/qcom/qdsp6/Makefile b/sound/soc/qcom/qdsp6/Makefile index 766b824f6597..a4ec7c4d0e48 100644 --- a/sound/soc/qcom/qdsp6/Makefile +++ b/sound/soc/qcom/qdsp6/Makefile @@ -13,3 +13,4 @@ obj-$(CONFIG_SND_SOC_QDSP6_ASM) += q6asm.o obj-$(CONFIG_SND_SOC_QDSP6_ASM_DAI) += q6asm-dai.o obj-$(CONFIG_SND_SOC_QDSP6_APM) += snd-q6apm.o +obj-$(CONFIG_SND_SOC_QDSP6_APM_DAI) += q6apm-dai.o diff --git a/sound/soc/qcom/qdsp6/q6apm-dai.c b/sound/soc/qcom/qdsp6/q6apm-dai.c new file mode 100644 index 000000000000..be6dc6232290 --- /dev/null +++ b/sound/soc/qcom/qdsp6/q6apm-dai.c @@ -0,0 +1,504 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2021, Linaro Limited + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "q6apm.h" + +#define DRV_NAME "q6apm-dai" + +#define PLAYBACK_MIN_NUM_PERIODS 2 +#define PLAYBACK_MAX_NUM_PERIODS 8 +#define PLAYBACK_MAX_PERIOD_SIZE 65536 +#define PLAYBACK_MIN_PERIOD_SIZE 128 +#define CAPTURE_MIN_NUM_PERIODS 2 +#define CAPTURE_MAX_NUM_PERIODS 8 +#define CAPTURE_MAX_PERIOD_SIZE 4096 +#define CAPTURE_MIN_PERIOD_SIZE 320 +#define BUFFER_BYTES_MAX (PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE) +#define BUFFER_BYTES_MIN (PLAYBACK_MIN_NUM_PERIODS * PLAYBACK_MIN_PERIOD_SIZE) + +#define SID_MASK_DEFAULT 0xF + +enum stream_state { + Q6APM_STREAM_IDLE = 0, + Q6APM_STREAM_STOPPED, + Q6APM_STREAM_RUNNING, +}; + +struct q6apm_dai_rtd { + struct snd_pcm_substream *substream; + struct snd_compr_stream *cstream; + struct snd_compr_params codec_param; + struct snd_dma_buffer dma_buffer; + spinlock_t lock; + phys_addr_t phys; + unsigned int pcm_size; + unsigned int pcm_count; + unsigned int pcm_irq_pos; /* IRQ position */ + unsigned int periods; + unsigned int bytes_sent; + unsigned int bytes_received; + unsigned int copied_total; + uint16_t bits_per_sample; + uint16_t source; /* Encoding source bit mask */ + uint16_t session_id; + enum stream_state state; + struct q6apm_graph *graph; +}; + +struct q6apm_dai_data { + long long sid; +}; + +static struct snd_pcm_hardware q6apm_dai_hardware_capture = { + .info = (SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME), + .formats = (SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE), + .rates = SNDRV_PCM_RATE_8000_48000, + .rate_min = 8000, + .rate_max = 48000, + .channels_min = 2, + .channels_max = 4, + .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * + CAPTURE_MAX_PERIOD_SIZE, + .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, + .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE, + .periods_min = CAPTURE_MIN_NUM_PERIODS, + .periods_max = CAPTURE_MAX_NUM_PERIODS, + .fifo_size = 0, +}; + +static struct snd_pcm_hardware q6apm_dai_hardware_playback = { + .info = (SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_MMAP_VALID | + SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME), + .formats = (SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE), + .rates = SNDRV_PCM_RATE_8000_192000, + .rate_min = 8000, + .rate_max = 192000, + .channels_min = 2, + .channels_max = 8, + .buffer_bytes_max = (PLAYBACK_MAX_NUM_PERIODS * + PLAYBACK_MAX_PERIOD_SIZE), + .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, + .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE, + .periods_min = PLAYBACK_MIN_NUM_PERIODS, + .periods_max = PLAYBACK_MAX_NUM_PERIODS, + .fifo_size = 0, +}; + +static void event_handler(uint32_t opcode, uint32_t token, + uint32_t *payload, void *priv) +{ + struct q6apm_dai_rtd *prtd = priv; + struct snd_pcm_substream *substream = prtd->substream; + + switch (opcode) { + case APM_CLIENT_EVENT_CMD_EOS_DONE: + prtd->state = Q6APM_STREAM_STOPPED; + break; + case APM_CLIENT_EVENT_DATA_WRITE_DONE: { + prtd->pcm_irq_pos += prtd->pcm_count; + snd_pcm_period_elapsed(substream); + if (prtd->state == Q6APM_STREAM_RUNNING) { + q6apm_write_async(prtd->graph, + prtd->pcm_count, 0, 0, NO_TIMESTAMP); + } + + break; + } + case APM_CLIENT_EVENT_DATA_READ_DONE: + prtd->pcm_irq_pos += prtd->pcm_count; + snd_pcm_period_elapsed(substream); + if (prtd->state == Q6APM_STREAM_RUNNING) + q6apm_read(prtd->graph); + + break; + default: + break; + } +} + +static int q6apm_dai_prepare(struct snd_soc_component *component, + struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct q6apm_dai_rtd *prtd = runtime->private_data; + struct audioreach_module_config cfg; + struct q6apm_dai_data *pdata; + int ret; + + pdata = snd_soc_component_get_drvdata(component); + if (!pdata) + return -EINVAL; + + if (!prtd || !prtd->graph) { + dev_err(component->dev, "%s: private data null or audio client freed\n", + __func__); + return -EINVAL; + } + + cfg.direction = substream->stream; + cfg.sample_rate = runtime->rate; + cfg.num_channels = runtime->channels; + cfg.bit_width = prtd->bits_per_sample; + + prtd->pcm_count = snd_pcm_lib_period_bytes(substream); + prtd->pcm_irq_pos = 0; + /* rate and channels are sent to audio driver */ + ret = q6apm_graph_media_format_shmem(prtd->graph, &cfg); + if (ret < 0) { + dev_err(component->dev, "%s: q6apm_open_write failed\n", __func__); + return ret; + } + + ret = q6apm_graph_media_format_pcm(prtd->graph, &cfg); + if (ret < 0) + pr_info("%s: CMD Format block failed\n", __func__); + + ret = q6apm_map_memory_regions(prtd->graph, + substream->stream, + prtd->phys, + (prtd->pcm_size / prtd->periods), + prtd->periods); + + if (ret < 0) { + dev_err(component->dev, "Audio Start: Buffer Allocation failed rc = %d\n", + ret); + return -ENOMEM; + } + + ret = q6apm_graph_prepare(prtd->graph); + if (ret) { + dev_err(component->dev, "Failed to prepare Graph %d\n", ret); + return ret; + } + + ret = q6apm_graph_start(prtd->graph); + if (ret) { + dev_err(component->dev, "Failed to Start Graph %d\n", ret); + return ret; + } + + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + int i; + /* Queue the buffers */ + for (i = 0; i < runtime->periods; i++) + q6apm_read(prtd->graph); + + } + prtd->state = Q6APM_STREAM_RUNNING; + + return 0; +} + +static int q6apm_dai_trigger(struct snd_soc_component *component, + struct snd_pcm_substream *substream, int cmd) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct q6apm_dai_rtd *prtd = runtime->private_data; + int ret = 0; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + ret = q6apm_write_async(prtd->graph, prtd->pcm_count, 0, 0, NO_TIMESTAMP); + break; + case SNDRV_PCM_TRIGGER_STOP: + prtd->state = Q6APM_STREAM_STOPPED; + break; + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static int q6apm_dai_open(struct snd_soc_component *component, + struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct snd_soc_pcm_runtime *soc_prtd = substream->private_data; + struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(soc_prtd, 0); + struct q6apm_dai_rtd *prtd; + struct q6apm_dai_data *pdata; + struct device *dev = component->dev; + int ret; + int graph_id; + + graph_id = cpu_dai->driver->id; + + pdata = snd_soc_component_get_drvdata(component); + if (!pdata) { + dev_err(component->dev, "Drv data not found ..\n"); + return -EINVAL; + } + + prtd = kzalloc(sizeof(*prtd), GFP_KERNEL); + if (prtd == NULL) + return -ENOMEM; + + prtd->substream = substream; + + prtd->graph = q6apm_graph_open(dev, (q6apm_cb)event_handler, + prtd, graph_id); + if (IS_ERR(prtd->graph)) { + pr_info("%s: Could not allocate memory\n", __func__); + ret = PTR_ERR(prtd->graph); + kfree(prtd); + return ret; + } + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + runtime->hw = q6apm_dai_hardware_playback; + else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) + runtime->hw = q6apm_dai_hardware_capture; + + /* Ensure that buffer size is a multiple of period size */ + ret = snd_pcm_hw_constraint_integer(runtime, + SNDRV_PCM_HW_PARAM_PERIODS); + if (ret < 0) { + dev_err(dev, "snd_pcm_hw_constraint_integer failed\n"); + return ret; + } + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + ret = snd_pcm_hw_constraint_minmax(runtime, + SNDRV_PCM_HW_PARAM_BUFFER_BYTES, + BUFFER_BYTES_MIN, BUFFER_BYTES_MAX); + if (ret < 0) { + dev_err(dev, "constraint for buffer bytes min max ret = %d\n", + ret); + return ret; + } + } + + ret = snd_pcm_hw_constraint_step(runtime, 0, + SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 32); + if (ret < 0) { + dev_err(dev, "constraint for period bytes step ret = %d\n", + ret); + return ret; + } + ret = snd_pcm_hw_constraint_step(runtime, 0, + SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 32); + if (ret < 0) { + dev_err(dev, "constraint for buffer bytes step ret = %d\n", + ret); + return ret; + } + + runtime->private_data = prtd; + runtime->dma_bytes = BUFFER_BYTES_MAX; + if (pdata->sid < 0) + prtd->phys = substream->dma_buffer.addr; + else + prtd->phys = substream->dma_buffer.addr | (pdata->sid << 32); + + snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); + + return 0; +} + +static int q6apm_dai_close(struct snd_soc_component *component, + struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct q6apm_dai_rtd *prtd = runtime->private_data; + + if (prtd && prtd->graph) { + q6apm_graph_stop(prtd->graph); + + q6apm_unmap_memory_regions(prtd->graph, + substream->stream); + q6apm_graph_close(prtd->graph); + prtd->graph = NULL; + kfree(prtd); + runtime->private_data = NULL; + } + + return 0; +} + +static snd_pcm_uframes_t q6apm_dai_pointer(struct snd_soc_component *component, + struct snd_pcm_substream *substream) +{ + + struct snd_pcm_runtime *runtime = substream->runtime; + struct q6apm_dai_rtd *prtd = runtime->private_data; + + if (prtd->pcm_irq_pos >= prtd->pcm_size) + prtd->pcm_irq_pos = 0; + + return bytes_to_frames(runtime, (prtd->pcm_irq_pos)); +} + +static int q6apm_dai_mmap(struct snd_soc_component *component, + struct snd_pcm_substream *substream, + struct vm_area_struct *vma) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct device *dev = component->dev; + + return dma_mmap_coherent(dev, vma, + runtime->dma_area, runtime->dma_addr, + runtime->dma_bytes); +} + +static int q6apm_dai_hw_params(struct snd_soc_component *component, + struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct q6apm_dai_rtd *prtd = runtime->private_data; + + prtd->pcm_size = params_buffer_bytes(params); + prtd->periods = params_periods(params); + + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + prtd->bits_per_sample = 16; + break; + case SNDRV_PCM_FORMAT_S24_LE: + prtd->bits_per_sample = 24; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int q6apm_dai_pcm_new(struct snd_soc_component *component, + struct snd_soc_pcm_runtime *rtd) +{ + struct snd_pcm_substream *psubstream, *csubstream; + struct snd_pcm *pcm = rtd->pcm; + struct device *dev; + int size, ret; + + dev = component->dev; + size = BUFFER_BYTES_MAX; + psubstream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream; + if (psubstream) { + ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, dev, size, + &psubstream->dma_buffer); + if (ret) { + dev_err(dev, "Cannot allocate buffer(s)\n"); + return ret; + } + } + + csubstream = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream; + if (csubstream) { + ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, dev, size, + &csubstream->dma_buffer); + if (ret) { + dev_err(dev, "Cannot allocate buffer(s)\n"); + if (psubstream) + snd_dma_free_pages(&psubstream->dma_buffer); + return ret; + } + } + + return 0; +} + +static void q6apm_dai_pcm_free(struct snd_soc_component *component, + struct snd_pcm *pcm) +{ + struct snd_pcm_substream *substream; + int i; + + if (!pcm->streams) + return; + + for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) { + substream = pcm->streams[i].substream; + if (substream) { + snd_dma_free_pages(&substream->dma_buffer); + substream->dma_buffer.area = NULL; + substream->dma_buffer.addr = 0; + } + } +} + +static const struct snd_soc_component_driver q6apm_fe_dai_component = { + .name = DRV_NAME, + .open = q6apm_dai_open, + .close = q6apm_dai_close, + .prepare = q6apm_dai_prepare, + .pcm_construct = q6apm_dai_pcm_new, + .pcm_destruct = q6apm_dai_pcm_free, + .mmap = q6apm_dai_mmap, + .hw_params = q6apm_dai_hw_params, + .pointer = q6apm_dai_pointer, + .trigger = q6apm_dai_trigger, +}; + +static int q6apm_dai_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct of_phandle_args args; + struct q6apm_dai_data *pdata; + int rc; + + pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + rc = of_parse_phandle_with_fixed_args(node, "iommus", 1, 0, &args); + if (rc < 0) + pdata->sid = -1; + else + pdata->sid = args.args[0] & SID_MASK_DEFAULT; + + dev_set_drvdata(dev, pdata); + + return devm_snd_soc_register_component(dev, &q6apm_fe_dai_component, + NULL, 0); +} + +static const struct of_device_id q6apm_dai_device_id[] = { + { .compatible = "qcom,q6apm-dais" }, + {}, +}; +MODULE_DEVICE_TABLE(of, q6apm_dai_device_id); + +static struct platform_driver q6apm_dai_platform_driver = { + .driver = { + .name = "q6apm-dai", + .of_match_table = of_match_ptr(q6apm_dai_device_id), + }, + .probe = q6apm_dai_probe, +}; +module_platform_driver(q6apm_dai_platform_driver); + +MODULE_DESCRIPTION("Q6APM dai driver"); +MODULE_LICENSE("GPL v2"); From patchwork Fri Sep 3 11:20:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 506523 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp906682jai; Fri, 3 Sep 2021 04:22:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzRM4r+UDo7WmvWo29bw7knDOmupMNuIQCwg7mKHtVvch3yNv8qkweOyN5iIc6e5LS6VHPK X-Received: by 2002:a5e:c609:: with SMTP id f9mr2509764iok.127.1630668120515; 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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:56 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 19/21] ASoC: qdsp6: audioreach: add q6apm lpass dai support Date: Fri, 3 Sep 2021 12:20:30 +0100 Message-Id: <20210903112032.25834-20-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support to Audio port dais on LPASS Audio IP using existing common q6dsp-lpass-ports. Signed-off-by: Srinivas Kandagatla --- sound/soc/qcom/Kconfig | 4 + sound/soc/qcom/qdsp6/Makefile | 1 + sound/soc/qcom/qdsp6/q6apm-lpass-dais.c | 266 ++++++++++++++++++++++++ 3 files changed, 271 insertions(+) create mode 100644 sound/soc/qcom/qdsp6/q6apm-lpass-dais.c -- 2.21.0 diff --git a/sound/soc/qcom/Kconfig b/sound/soc/qcom/Kconfig index fb1921889dc4..51b5a173e8ed 100644 --- a/sound/soc/qcom/Kconfig +++ b/sound/soc/qcom/Kconfig @@ -88,8 +88,12 @@ config SND_SOC_QDSP6_APM_DAI select SND_SOC_COMPRESS tristate +config SND_SOC_QDSP6_APM_LPASS_DAI + tristate + config SND_SOC_QDSP6_APM select SND_SOC_QDSP6_APM_DAI + select SND_SOC_QDSP6_APM_LPASS_DAI tristate config SND_SOC_QDSP6 diff --git a/sound/soc/qcom/qdsp6/Makefile b/sound/soc/qcom/qdsp6/Makefile index a4ec7c4d0e48..bdcbfdfa9bd0 100644 --- a/sound/soc/qcom/qdsp6/Makefile +++ b/sound/soc/qcom/qdsp6/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_SND_SOC_QDSP6_ASM_DAI) += q6asm-dai.o obj-$(CONFIG_SND_SOC_QDSP6_APM) += snd-q6apm.o obj-$(CONFIG_SND_SOC_QDSP6_APM_DAI) += q6apm-dai.o +obj-$(CONFIG_SND_SOC_QDSP6_APM_LPASS_DAI) += q6apm-lpass-dais.o diff --git a/sound/soc/qcom/qdsp6/q6apm-lpass-dais.c b/sound/soc/qcom/qdsp6/q6apm-lpass-dais.c new file mode 100644 index 000000000000..25f31d425746 --- /dev/null +++ b/sound/soc/qcom/qdsp6/q6apm-lpass-dais.c @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2021, Linaro Limited + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "q6dsp-lpass-ports.h" +#include "audioreach.h" +#include "q6apm.h" + +#define AUDIOREACH_BE_PCM_BASE 16 + +struct q6apm_lpass_dai_data { + struct q6apm_graph *graph[APM_PORT_MAX]; + bool is_port_started[APM_PORT_MAX]; + struct audioreach_module_config module_config[APM_PORT_MAX]; +}; + +static int q6dma_set_channel_map(struct snd_soc_dai *dai, + unsigned int tx_num, unsigned int *tx_ch_mask, + unsigned int rx_num, unsigned int *rx_ch_mask) +{ + + struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev); + struct audioreach_module_config *cfg = &dai_data->module_config[dai->id]; + int ch_mask; + int rc = 0; + + switch (dai->id) { + case WSA_CODEC_DMA_TX_0: + case WSA_CODEC_DMA_TX_1: + case WSA_CODEC_DMA_TX_2: + case VA_CODEC_DMA_TX_0: + case VA_CODEC_DMA_TX_1: + case VA_CODEC_DMA_TX_2: + case TX_CODEC_DMA_TX_0: + case TX_CODEC_DMA_TX_1: + case TX_CODEC_DMA_TX_2: + case TX_CODEC_DMA_TX_3: + case TX_CODEC_DMA_TX_4: + case TX_CODEC_DMA_TX_5: + if (!tx_ch_mask) { + dev_err(dai->dev, "tx slot not found\n"); + return -EINVAL; + } + + if (tx_num > PCM_MAX_NUM_CHANNEL) { + dev_err(dai->dev, "invalid tx num %d\n", + tx_num); + return -EINVAL; + } + ch_mask = *tx_ch_mask; + + break; + case WSA_CODEC_DMA_RX_0: + case WSA_CODEC_DMA_RX_1: + case RX_CODEC_DMA_RX_0: + case RX_CODEC_DMA_RX_1: + case RX_CODEC_DMA_RX_2: + case RX_CODEC_DMA_RX_3: + case RX_CODEC_DMA_RX_4: + case RX_CODEC_DMA_RX_5: + case RX_CODEC_DMA_RX_6: + case RX_CODEC_DMA_RX_7: + /* rx */ + if (!rx_ch_mask) { + dev_err(dai->dev, "rx slot not found\n"); + return -EINVAL; + } + if (rx_num > APM_PORT_MAX_AUDIO_CHAN_CNT) { + dev_err(dai->dev, "invalid rx num %d\n", + rx_num); + return -EINVAL; + } + ch_mask = *rx_ch_mask; + + break; + default: + dev_err(dai->dev, "%s: invalid dai id 0x%x\n", + __func__, dai->id); + return -EINVAL; + } + + cfg->active_channels_mask = ch_mask; + + return rc; +} + +static int q6dma_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev); + struct audioreach_module_config *cfg = &dai_data->module_config[dai->id]; + + cfg->bit_width = params_width(params); + cfg->sample_rate = params_rate(params); + cfg->num_channels = params_channels(params); + + return 0; +} + +static void q6apm_lpass_dai_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev); + int rc; + + if (!dai_data->is_port_started[dai->id]) + return; + rc = q6apm_graph_stop(dai_data->graph[dai->id]); + if (rc < 0) + dev_err(dai->dev, "fail to close APM port (%d)\n", rc); + + q6apm_graph_close(dai_data->graph[dai->id]); + dai_data->is_port_started[dai->id] = false; + +} + +static int q6apm_lpass_dai_prepare(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev); + struct audioreach_module_config *cfg = &dai_data->module_config[dai->id]; + int graph_id = dai->id; + int rc; + struct q6apm_graph *graph; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + graph = q6apm_graph_open(dai->dev, NULL, dai->dev, graph_id); + if (IS_ERR(graph)) { + dev_err(dai->dev, "Failed to open graph (%d)\n", + graph_id); + rc = PTR_ERR(graph); + return rc; + } + dai_data->graph[graph_id] = graph; + } + + cfg->direction = substream->stream; + rc = q6apm_graph_media_format_pcm(dai_data->graph[dai->id], cfg); + + if (rc) { + dev_err(dai->dev, "Failed to set media format %d\n", rc); + return rc; + } + + rc = q6apm_graph_prepare(dai_data->graph[dai->id]); + if (rc) { + dev_err(dai->dev, "Failed to prepare Graph %d\n", rc); + return rc; + } + + rc = q6apm_graph_start(dai_data->graph[dai->id]); + if (rc < 0) { + dev_err(dai->dev, "fail to start APM port %x\n", dai->id); + return rc; + } + dai_data->is_port_started[dai->id] = true; + + return 0; +} + +static int q6apm_lpass_dai_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev); + int graph_id = dai->id; + struct q6apm_graph *graph; + + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + graph = q6apm_graph_open(dai->dev, NULL, dai->dev, graph_id); + if (IS_ERR(graph)) { + dev_err(dai->dev, "Failed to open graph (%d)\n", + graph_id); + return PTR_ERR(graph); + } + dai_data->graph[graph_id] = graph; + } + + return 0; +} + +static int q6i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + struct q6apm_lpass_dai_data *dai_data = dev_get_drvdata(dai->dev); + struct audioreach_module_config *cfg = &dai_data->module_config[dai->id]; + + cfg->fmt = fmt; + + return 0; +} + +static const struct snd_soc_dai_ops q6dma_ops = { + .prepare = q6apm_lpass_dai_prepare, + .startup = q6apm_lpass_dai_startup, + .shutdown = q6apm_lpass_dai_shutdown, + .set_channel_map = q6dma_set_channel_map, + .hw_params = q6dma_hw_params, +}; + +static const struct snd_soc_dai_ops q6i2s_ops = { + .prepare = q6apm_lpass_dai_prepare, + .startup = q6apm_lpass_dai_startup, + .shutdown = q6apm_lpass_dai_shutdown, + .set_channel_map = q6dma_set_channel_map, + .hw_params = q6dma_hw_params, + .set_fmt = q6i2s_set_fmt, +}; + +static const struct snd_soc_component_driver q6apm_lpass_dai_component = { + .name = "q6apm-be-dai-component", + .of_xlate_dai_name = q6dsp_audio_ports_of_xlate_dai_name, + .be_pcm_base = AUDIOREACH_BE_PCM_BASE, + .use_dai_pcm_id = true, +}; + +static int q6apm_lpass_dai_dev_probe(struct platform_device *pdev) +{ + struct q6dsp_audio_port_dai_driver_config cfg; + struct snd_soc_dai_driver *dais; + struct q6apm_lpass_dai_data *dai_data; + struct device *dev = &pdev->dev; + int num_dais; + + + dai_data = devm_kzalloc(dev, sizeof(*dai_data), GFP_KERNEL); + if (!dai_data) + return -ENOMEM; + + dev_set_drvdata(dev, dai_data); + + memset(&cfg, 0, sizeof(cfg)); + cfg.q6i2s_ops = &q6i2s_ops; + cfg.q6dma_ops = &q6dma_ops; + dais = q6dsp_audio_ports_set_config(dev, &cfg, &num_dais); + + return devm_snd_soc_register_component(dev, &q6apm_lpass_dai_component, + dais, num_dais); +} + +#ifdef CONFIG_OF +static const struct of_device_id q6apm_lpass_dai_device_id[] = { + { .compatible = "qcom,q6apm-lpass-dais" }, + {}, +}; +MODULE_DEVICE_TABLE(of, q6apm_lpass_dai_device_id); +#endif + +static struct platform_driver q6apm_lpass_dai_platform_driver = { + .driver = { + .name = "q6apm-lpass-dais", + .of_match_table = of_match_ptr(q6apm_lpass_dai_device_id), + }, + .probe = q6apm_lpass_dai_dev_probe, +}; +module_platform_driver(q6apm_lpass_dai_platform_driver); + +MODULE_DESCRIPTION("AUDIOREACH APM LPASS dai driver"); +MODULE_LICENSE("GPL"); From patchwork Fri Sep 3 11:20:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 506524 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp906702jai; Fri, 3 Sep 2021 04:22:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJycHUjAL7YOpxLf1IzSf2SUdCSZKo29yVez4W8QnYPDDGLLcqfItNhQUCEVNWnRVpbGTsmr X-Received: by 2002:a6b:e90c:: with SMTP id u12mr2544308iof.95.1630668121901; Fri, 03 Sep 2021 04:22:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1630668121; cv=none; d=google.com; s=arc-20160816; b=Lf0cl3XWZF+NpswEvcRVg8Uyr5KniXjClbMUviXoAhvZzqf8tlKmZmeWm3w4+UqWak b1tOO6U1QEDA+BnSZ+Ax50MyU+zaULziMX3zEeZO/XGVhSxQreyNabz+niK1g/uggABw jEqC+iSzYBPJkhbLrq9vw5VMvNeHcW+OaWKvF06cmeYEDS/MBMTNVm+yN6Vw53KiwRyr S/qG5+xA5Zpg1C7Pqo/j9uHIYtFZDr56wEnubbgwdLMeWghzptshnrwCAkIgxUollZCT 4r7VAPm8o4QNkKF6UnVe0DumB4piCwa7QAryyIfxKzZKOGDS6fd0eTBScCOcUhqOsi3r 3Pcw== ARC-Message-Signature: i=1; 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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:57 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 20/21] ASoC: qdsp6: audioreach: add q6prm support Date: Fri, 3 Sep 2021 12:20:31 +0100 Message-Id: <20210903112032.25834-21-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support to q6prm (Proxy Resource Manager) module used for clock resources Signed-off-by: Srinivas Kandagatla --- sound/soc/qcom/Kconfig | 4 + sound/soc/qcom/qdsp6/Makefile | 1 + sound/soc/qcom/qdsp6/q6prm.c | 256 ++++++++++++++++++++++++++++++++++ sound/soc/qcom/qdsp6/q6prm.h | 78 +++++++++++ 4 files changed, 339 insertions(+) create mode 100644 sound/soc/qcom/qdsp6/q6prm.c create mode 100644 sound/soc/qcom/qdsp6/q6prm.h -- 2.21.0 diff --git a/sound/soc/qcom/Kconfig b/sound/soc/qcom/Kconfig index 51b5a173e8ed..f4ccfe48f8f7 100644 --- a/sound/soc/qcom/Kconfig +++ b/sound/soc/qcom/Kconfig @@ -96,6 +96,9 @@ config SND_SOC_QDSP6_APM select SND_SOC_QDSP6_APM_LPASS_DAI tristate +config SND_SOC_QDSP6_PRM + tristate + config SND_SOC_QDSP6 tristate "SoC ALSA audio driver for QDSP6" depends on QCOM_APR @@ -111,6 +114,7 @@ config SND_SOC_QDSP6 select SND_SOC_QDSP6_ASM_DAI select SND_SOC_TOPOLOGY select SND_SOC_QDSP6_APM + select SND_SOC_QDSP6_PRM help To add support for MSM QDSP6 Soc Audio. This will enable sound soc platform specific diff --git a/sound/soc/qcom/qdsp6/Makefile b/sound/soc/qcom/qdsp6/Makefile index bdcbfdfa9bd0..c932f8e24b32 100644 --- a/sound/soc/qcom/qdsp6/Makefile +++ b/sound/soc/qcom/qdsp6/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_SND_SOC_QDSP6_ASM_DAI) += q6asm-dai.o obj-$(CONFIG_SND_SOC_QDSP6_APM) += snd-q6apm.o obj-$(CONFIG_SND_SOC_QDSP6_APM_DAI) += q6apm-dai.o obj-$(CONFIG_SND_SOC_QDSP6_APM_LPASS_DAI) += q6apm-lpass-dais.o +obj-$(CONFIG_SND_SOC_QDSP6_PRM) += q6prm.o diff --git a/sound/soc/qcom/qdsp6/q6prm.c b/sound/soc/qcom/qdsp6/q6prm.c new file mode 100644 index 000000000000..3ad959311205 --- /dev/null +++ b/sound/soc/qcom/qdsp6/q6prm.c @@ -0,0 +1,256 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2021, Linaro Limited + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "q6prm.h" +#include "audioreach.h" + +struct q6prm { + struct device *dev; + gpr_device_t *gdev; + wait_queue_head_t wait; + struct gpr_ibasic_rsp_result_t result; + struct mutex lock; +}; + +#define PRM_CMD_REQUEST_HW_RSC 0x0100100F +#define PRM_CMD_RSP_REQUEST_HW_RSC 0x02001002 +#define PRM_CMD_RELEASE_HW_RSC 0x01001010 +#define PRM_CMD_RSP_RELEASE_HW_RSC 0x02001003 + +#define PARAM_ID_RSC_HW_CORE 0x08001032 +#define PARAM_ID_RSC_LPASS_CORE 0x0800102B +#define PARAM_ID_RSC_AUDIO_HW_CLK 0x0800102C + +#define LPAIF_DIG_CLK 1 +#define LPAIF_BIT_CLK 2 +#define LPAIF_OSR_CLK 3 + +struct prm_cmd_request_hw_core { + struct apm_module_param_data param_data; + uint32_t hw_clk_id; +} __packed; + +struct prm_cmd_request_rsc { + struct apm_module_param_data param_data; + uint32_t num_clk_id; + struct audio_hw_clk_cfg clock_ids[1]; +} __packed; + +struct prm_cmd_release_rsc { + struct apm_module_param_data param_data; + uint32_t num_clk_id; + struct audio_hw_clk_cfg clock_ids[1]; +} __packed; + +static int q6prm_send_cmd_sync(struct q6prm *prm, struct gpr_pkt *pkt, + uint32_t rsp_opcode) +{ + gpr_device_t *gdev = prm->gdev; + struct gpr_hdr *hdr = &pkt->hdr; + int rc; + + mutex_lock(&prm->lock); + prm->result.opcode = 0; + prm->result.status = 0; + + rc = gpr_send_pkt(prm->gdev, pkt); + if (rc < 0) + goto err; + + if (rsp_opcode) + rc = wait_event_timeout(prm->wait, + (prm->result.opcode == hdr->opcode) || + (prm->result.opcode == rsp_opcode), + 5 * HZ); + else + rc = wait_event_timeout(prm->wait, + (prm->result.opcode == hdr->opcode), + 5 * HZ); + + if (!rc) { + dev_err(&gdev->dev, "CMD timeout for [%x] opcode\n", + hdr->opcode); + rc = -ETIMEDOUT; + } else if (prm->result.status > 0) { + dev_err(&gdev->dev, "DSP returned error[%x] %x\n", hdr->opcode, + prm->result.status); + rc = -EINVAL; + } else { + dev_err(&gdev->dev, "DSP returned [%x]\n", + prm->result.status); + rc = 0; + } + +err: + mutex_unlock(&prm->lock); + return rc; +} + +static int q6prm_set_hw_core_req(struct device *dev, uint32_t hw_block_id, bool enable) +{ + struct prm_cmd_request_hw_core *req; + struct apm_module_param_data *param_data; + struct gpr_pkt *pkt; + struct q6prm *prm = dev_get_drvdata(dev->parent); + gpr_device_t *gdev = prm->gdev; + void *p; + int rc = 0; + uint32_t opcode, rsp_opcode; + + if (enable) { + opcode = PRM_CMD_REQUEST_HW_RSC; + rsp_opcode = PRM_CMD_RSP_REQUEST_HW_RSC; + } else { + opcode = PRM_CMD_RELEASE_HW_RSC; + rsp_opcode = PRM_CMD_RSP_RELEASE_HW_RSC; + } + + p = audioreach_alloc_cmd_pkt(sizeof(*req), opcode, 0, gdev->svc.id, + GPR_PRM_MODULE_IID); + if (IS_ERR(p)) + return -ENOMEM; + + pkt = p; + req = p + GPR_HDR_SIZE + APM_CMD_HDR_SIZE; + + param_data = &req->param_data; + + param_data->module_instance_id = GPR_PRM_MODULE_IID; + param_data->error_code = 0; + param_data->param_id = PARAM_ID_RSC_HW_CORE; + param_data->param_size = sizeof(*req) - APM_MODULE_PARAM_DATA_SIZE; + + req->hw_clk_id = hw_block_id; + + q6prm_send_cmd_sync(prm, pkt, rsp_opcode); + + kfree(pkt); + + return rc; +} + +int q6prm_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, + const char *client_name, uint32_t *client_handle) +{ + return q6prm_set_hw_core_req(dev, hw_block_id, true); + +} +EXPORT_SYMBOL_GPL(q6prm_vote_lpass_core_hw); + +int q6prm_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, + uint32_t client_handle) +{ + return q6prm_set_hw_core_req(dev, hw_block_id, false); +} +EXPORT_SYMBOL_GPL(q6prm_unvote_lpass_core_hw); + +int q6prm_set_lpass_clock(struct device *dev, int clk_id, int clk_attr, + int clk_root, unsigned int freq) +{ + struct prm_cmd_request_rsc *req; + struct apm_module_param_data *param_data; + struct gpr_pkt *pkt; + struct q6prm *prm = dev_get_drvdata(dev->parent); + gpr_device_t *gdev = prm->gdev; + void *p; + int rc = 0; + + p = audioreach_alloc_cmd_pkt(sizeof(*req), PRM_CMD_REQUEST_HW_RSC, + 0, gdev->svc.id, GPR_PRM_MODULE_IID); + if (IS_ERR(p)) + return -ENOMEM; + + pkt = p; + req = p + GPR_HDR_SIZE + APM_CMD_HDR_SIZE; + + param_data = &req->param_data; + + param_data->module_instance_id = GPR_PRM_MODULE_IID; + param_data->error_code = 0; + param_data->param_id = PARAM_ID_RSC_AUDIO_HW_CLK; + param_data->param_size = sizeof(*req) - APM_MODULE_PARAM_DATA_SIZE; + + req->num_clk_id = 1; + req->clock_ids[0].clock_id = clk_id; + req->clock_ids[0].clock_freq = freq; + req->clock_ids[0].clock_attri = clk_attr; + req->clock_ids[0].clock_root = clk_root; + + q6prm_send_cmd_sync(prm, pkt, PRM_CMD_RSP_REQUEST_HW_RSC); + + kfree(pkt); + + return rc; +} +EXPORT_SYMBOL_GPL(q6prm_set_lpass_clock); + +static int prm_callback(struct gpr_resp_pkt *data, void *priv, int op) +{ + gpr_device_t *gdev = priv; + struct q6prm *prm = dev_get_drvdata(&gdev->dev); + struct gpr_ibasic_rsp_result_t *result; + struct gpr_hdr *hdr = &data->hdr; + + result = data->payload; + + switch (hdr->opcode) { + case PRM_CMD_RSP_REQUEST_HW_RSC: + case PRM_CMD_RSP_RELEASE_HW_RSC: + prm->result.opcode = hdr->opcode; + prm->result.status = result->status; + wake_up(&prm->wait); + break; + default: + break; + } + + return 0; +} + +static int prm_probe(gpr_device_t *gdev) +{ + struct device *dev = &gdev->dev; + struct q6prm *cc; + + cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL); + if (!cc) + return -ENOMEM; + + cc->dev = dev; + cc->gdev = gdev; + mutex_init(&cc->lock); + init_waitqueue_head(&cc->wait); + dev_set_drvdata(dev, cc); + + return devm_of_platform_populate(dev); +} + +static const struct of_device_id prm_device_id[] = { + { .compatible = "qcom,q6prm" }, + {}, +}; +MODULE_DEVICE_TABLE(of, prm_device_id); + +static gpr_driver_t prm_driver = { + .probe = prm_probe, + .gpr_callback = prm_callback, + .driver = { + .name = "qcom-prm", + .of_match_table = of_match_ptr(prm_device_id), + }, +}; + +module_gpr_driver(prm_driver); +MODULE_DESCRIPTION("Audio Process Manager"); +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/qcom/qdsp6/q6prm.h b/sound/soc/qcom/qdsp6/q6prm.h new file mode 100644 index 000000000000..fea4d1954bc1 --- /dev/null +++ b/sound/soc/qcom/qdsp6/q6prm.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __Q6PRM_H__ +#define __Q6PRM_H__ + +/* Clock ID for Primary I2S IBIT */ +#define Q6PRM_LPASS_CLK_ID_PRI_MI2S_IBIT 0x100 +/* Clock ID for Primary I2S EBIT */ +#define Q6PRM_LPASS_CLK_ID_PRI_MI2S_EBIT 0x101 +/* Clock ID for Secondary I2S IBIT */ +#define Q6PRM_LPASS_CLK_ID_SEC_MI2S_IBIT 0x102 +/* Clock ID for Secondary I2S EBIT */ +#define Q6PRM_LPASS_CLK_ID_SEC_MI2S_EBIT 0x103 +/* Clock ID for Tertiary I2S IBIT */ +#define Q6PRM_LPASS_CLK_ID_TER_MI2S_IBIT 0x104 +/* Clock ID for Tertiary I2S EBIT */ +#define Q6PRM_LPASS_CLK_ID_TER_MI2S_EBIT 0x105 +/* Clock ID for Quartnery I2S IBIT */ +#define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_IBIT 0x106 +/* Clock ID for Quartnery I2S EBIT */ +#define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_EBIT 0x107 +/* Clock ID for Speaker I2S IBIT */ +#define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_IBIT 0x108 +/* Clock ID for Speaker I2S EBIT */ +#define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_EBIT 0x109 +/* Clock ID for Speaker I2S OSR */ +#define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_OSR 0x10A + +/* Clock ID for QUINARY I2S IBIT */ +#define Q6PRM_LPASS_CLK_ID_QUI_MI2S_IBIT 0x10B +/* Clock ID for QUINARY I2S EBIT */ +#define Q6PRM_LPASS_CLK_ID_QUI_MI2S_EBIT 0x10C +/* Clock ID for SENARY I2S IBIT */ +#define Q6PRM_LPASS_CLK_ID_SEN_MI2S_IBIT 0x10D +/* Clock ID for SENARY I2S EBIT */ +#define Q6PRM_LPASS_CLK_ID_SEN_MI2S_EBIT 0x10E +/* Clock ID for INT0 I2S IBIT */ +#define Q6PRM_LPASS_CLK_ID_INT0_MI2S_IBIT 0x10F +/* Clock ID for INT1 I2S IBIT */ +#define Q6PRM_LPASS_CLK_ID_INT1_MI2S_IBIT 0x110 +/* Clock ID for INT2 I2S IBIT */ +#define Q6PRM_LPASS_CLK_ID_INT2_MI2S_IBIT 0x111 +/* Clock ID for INT3 I2S IBIT */ +#define Q6PRM_LPASS_CLK_ID_INT3_MI2S_IBIT 0x112 +/* Clock ID for INT4 I2S IBIT */ +#define Q6PRM_LPASS_CLK_ID_INT4_MI2S_IBIT 0x113 +/* Clock ID for INT5 I2S IBIT */ +#define Q6PRM_LPASS_CLK_ID_INT5_MI2S_IBIT 0x114 +/* Clock ID for INT6 I2S IBIT */ +#define Q6PRM_LPASS_CLK_ID_INT6_MI2S_IBIT 0x115 + +/* Clock ID for QUINARY MI2S OSR CLK */ +#define Q6PRM_LPASS_CLK_ID_QUI_MI2S_OSR 0x116 + +#define Q6PRM_LPASS_CLK_ID_WSA_CORE_MCLK 0x305 +#define Q6PRM_LPASS_CLK_ID_WSA_CORE_NPL_MCLK 0x306 + +#define Q6PRM_LPASS_CLK_ID_VA_CORE_MCLK 0x307 +#define Q6PRM_LPASS_CLK_ID_VA_CORE_2X_MCLK 0x308 + +#define Q6PRM_LPASS_CLK_ID_TX_CORE_MCLK 0x30c +#define Q6PRM_LPASS_CLK_ID_TX_CORE_NPL_MCLK 0x30d + +#define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK 0x30e +#define Q6PRM_LPASS_CLK_ID_RX_CORE_NPL_MCLK 0x30f + +#define Q6PRM_LPASS_CLK_SRC_INTERNAL 1 +#define Q6PRM_LPASS_CLK_ROOT_DEFAULT 0 +#define Q6PRM_HW_CORE_ID_LPASS 1 +#define Q6PRM_HW_CORE_ID_DCODEC 2 + +int q6prm_set_lpass_clock(struct device *dev, int clk_id, int clk_attr, + int clk_root, unsigned int freq); +int q6prm_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, + const char *client_name, uint32_t *client_handle); +int q6prm_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, + uint32_t client_handle); +#endif /* __Q6PRM_H__ */ From patchwork Fri Sep 3 11:20:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 506525 Delivered-To: patch@linaro.org Received: by 2002:a02:8629:0:0:0:0:0 with SMTP id e38csp906720jai; Fri, 3 Sep 2021 04:22:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxpjhc0wEUtJp275A8jlHMq/7U29XSVQaYMUJI30YS8FftnqywW0gdwHHxKftc6Erdc3g2i X-Received: by 2002:a92:b711:: with SMTP id k17mr2198419ili.247.1630668122883; Fri, 03 Sep 2021 04:22:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1630668122; cv=none; d=google.com; s=arc-20160816; b=QuPoovq1QoO5W6PvIj99UTOAmrKI7oLWSqM/GHJP6aMFZkieiAF3K/6jXAN2lmyW3X /1Fz3ma1kSs2mo34LFzuUIbYbsvRguf4dg0q2twtR3hnNcdJ3ukGY10eBN2iwsAxHcRk hqK2OYY0/wI0k+pZzDo6Xd9qbziLSSI5bfWhgpN8I0W9/wPuuSDJlx52VCni2N3HKzwO PdVG5jMbIkePdzEJtNfA6HlsdcZUeTV9fBxDM5wL6mP17MMirh6o5oExuZNGxZRk0Tm+ dCmJknrdhXaw0Na3V3RzZ8ccKwrVH86l1eHHLF/RiZkDmYXAG+jMitrYnHJssRIluecf +5Ug== ARC-Message-Signature: i=1; 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[92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:59 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 21/21] ASoC: qdsp6: audioreach: add support for q6prm-clocks Date: Fri, 3 Sep 2021 12:20:32 +0100 Message-Id: <20210903112032.25834-22-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add q6prm clocks using existing qdsp6-audio-clock driver Signed-off-by: Srinivas Kandagatla --- sound/soc/qcom/Kconfig | 4 ++ sound/soc/qcom/qdsp6/Makefile | 1 + sound/soc/qcom/qdsp6/q6prm-clocks.c | 85 +++++++++++++++++++++++++++++ 3 files changed, 90 insertions(+) create mode 100644 sound/soc/qcom/qdsp6/q6prm-clocks.c -- 2.21.0 diff --git a/sound/soc/qcom/Kconfig b/sound/soc/qcom/Kconfig index f4ccfe48f8f7..25beb0d40eb5 100644 --- a/sound/soc/qcom/Kconfig +++ b/sound/soc/qcom/Kconfig @@ -96,7 +96,11 @@ config SND_SOC_QDSP6_APM select SND_SOC_QDSP6_APM_LPASS_DAI tristate +config SND_SOC_QDSP6_PRM_LPASS_CLOCKS + tristate + config SND_SOC_QDSP6_PRM + select SND_SOC_QDSP6_PRM_LPASS_CLOCKS tristate config SND_SOC_QDSP6 diff --git a/sound/soc/qcom/qdsp6/Makefile b/sound/soc/qcom/qdsp6/Makefile index c932f8e24b32..3963bf234664 100644 --- a/sound/soc/qcom/qdsp6/Makefile +++ b/sound/soc/qcom/qdsp6/Makefile @@ -16,3 +16,4 @@ obj-$(CONFIG_SND_SOC_QDSP6_APM) += snd-q6apm.o obj-$(CONFIG_SND_SOC_QDSP6_APM_DAI) += q6apm-dai.o obj-$(CONFIG_SND_SOC_QDSP6_APM_LPASS_DAI) += q6apm-lpass-dais.o obj-$(CONFIG_SND_SOC_QDSP6_PRM) += q6prm.o +obj-$(CONFIG_SND_SOC_QDSP6_PRM_LPASS_CLOCKS) += q6prm-clocks.o diff --git a/sound/soc/qcom/qdsp6/q6prm-clocks.c b/sound/soc/qcom/qdsp6/q6prm-clocks.c new file mode 100644 index 000000000000..a1d9522b2bd2 --- /dev/null +++ b/sound/soc/qcom/qdsp6/q6prm-clocks.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2021, Linaro Limited + +#include +#include +#include +#include +#include +#include +#include +#include "q6dsp-lpass-clocks.h" +#include "q6prm.h" + +#define Q6PRM_CLK(id) { \ + .clk_id = id, \ + .q6dsp_clk_id = Q6PRM_##id, \ + .name = #id, \ + .rate = 19200000, \ + } + +static const struct q6dsp_clk_init q6prm_clks[] = { + Q6PRM_CLK(LPASS_CLK_ID_PRI_MI2S_IBIT), + Q6PRM_CLK(LPASS_CLK_ID_PRI_MI2S_EBIT), + Q6PRM_CLK(LPASS_CLK_ID_SEC_MI2S_IBIT), + Q6PRM_CLK(LPASS_CLK_ID_SEC_MI2S_EBIT), + Q6PRM_CLK(LPASS_CLK_ID_TER_MI2S_IBIT), + Q6PRM_CLK(LPASS_CLK_ID_TER_MI2S_EBIT), + Q6PRM_CLK(LPASS_CLK_ID_QUAD_MI2S_IBIT), + Q6PRM_CLK(LPASS_CLK_ID_QUAD_MI2S_EBIT), + Q6PRM_CLK(LPASS_CLK_ID_SPEAKER_I2S_IBIT), + Q6PRM_CLK(LPASS_CLK_ID_SPEAKER_I2S_EBIT), + Q6PRM_CLK(LPASS_CLK_ID_SPEAKER_I2S_OSR), + Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_IBIT), + Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_EBIT), + Q6PRM_CLK(LPASS_CLK_ID_SEN_MI2S_IBIT), + Q6PRM_CLK(LPASS_CLK_ID_SEN_MI2S_EBIT), + Q6PRM_CLK(LPASS_CLK_ID_INT0_MI2S_IBIT), + Q6PRM_CLK(LPASS_CLK_ID_INT1_MI2S_IBIT), + Q6PRM_CLK(LPASS_CLK_ID_INT2_MI2S_IBIT), + Q6PRM_CLK(LPASS_CLK_ID_INT3_MI2S_IBIT), + Q6PRM_CLK(LPASS_CLK_ID_INT4_MI2S_IBIT), + Q6PRM_CLK(LPASS_CLK_ID_INT5_MI2S_IBIT), + Q6PRM_CLK(LPASS_CLK_ID_INT6_MI2S_IBIT), + Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_OSR), + Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_MCLK), + Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_NPL_MCLK), + Q6PRM_CLK(LPASS_CLK_ID_VA_CORE_MCLK), + Q6PRM_CLK(LPASS_CLK_ID_TX_CORE_MCLK), + Q6PRM_CLK(LPASS_CLK_ID_TX_CORE_NPL_MCLK), + Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_MCLK), + Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_NPL_MCLK), + Q6PRM_CLK(LPASS_CLK_ID_VA_CORE_2X_MCLK), + Q6DSP_VOTE_CLK(LPASS_HW_MACRO_VOTE, Q6PRM_HW_CORE_ID_LPASS, + "LPASS_HW_MACRO"), + Q6DSP_VOTE_CLK(LPASS_HW_DCODEC_VOTE, Q6PRM_HW_CORE_ID_DCODEC, + "LPASS_HW_DCODEC"), +}; + +static const struct q6dsp_clk_desc q6dsp_clk_q6prm = { + .clks = q6prm_clks, + .num_clks = ARRAY_SIZE(q6prm_clks), + .lpass_set_clk = q6prm_set_lpass_clock, + .lpass_vote_clk = q6prm_vote_lpass_core_hw, + .lpass_unvote_clk = q6prm_unvote_lpass_core_hw, +}; + +#ifdef CONFIG_OF +static const struct of_device_id q6prm_clock_device_id[] = { + { .compatible = "qcom,q6prm-lpass-clocks", .data = &q6dsp_clk_q6prm }, + {}, +}; +MODULE_DEVICE_TABLE(of, q6prm_clock_device_id); +#endif + +static struct platform_driver q6prm_clock_platform_driver = { + .driver = { + .name = "q6prm-lpass-clock", + .of_match_table = of_match_ptr(q6prm_clock_device_id), + }, + .probe = q6dsp_clock_dev_probe, +}; +module_platform_driver(q6prm_clock_platform_driver); + +MODULE_DESCRIPTION("Q6 Proxy Resource Manager LPASS clock driver"); +MODULE_LICENSE("GPL v2");