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[131.252.210.177]) by mx.google.com with ESMTPS id s10-v6si18508037pgf.434.2018.10.17.07.04.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 Oct 2018 07:04:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 19CE189688; Wed, 17 Oct 2018 14:04:10 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-lj1-x243.google.com (mail-lj1-x243.google.com [IPv6:2a00:1450:4864:20::243]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2664189688 for ; Wed, 17 Oct 2018 14:04:09 +0000 (UTC) Received: by mail-lj1-x243.google.com with SMTP id r83-v6so24439183ljr.7 for ; Wed, 17 Oct 2018 07:04:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=hHHIaxeolEmAdLP47lfePR9e5YDrThygl2UEkXqOjeM=; b=RtHN5eXCjpVn2chB98f/MmaJrGNwgu3P99KsdEOxJhhJc0vTSdmoBogwmoXcllHjVu w36amWxltHYc4zxhzVGMTR/p4QWBYX9gsMSEG0xKPEUu1Lk8Yqa7/pO6NfqB0XmTW77o 2SjFhL+uP2+V/+DokmKyuB6co73Xsl/xi3Ye/aEfu3wr5OxD52WpBS6O+s16zzcLs3L4 tfXX9IwYsWnZtIBuBi8COtbpqg1XBeSby7KdMsZQ+yq4dxm5bJA6uj48aBoOtNPfpSy+ qIagGt2kiix2vnLl07g1ziikQp1BJIi8vi2532AzbhXJxJa/n0zIfs8WPdSBVq3gCL3U WbVQ== X-Gm-Message-State: ABuFfohHvXirwjacwO9slth2e2keRR81WuyJtLgXizYj7kvP0MvrfF3G 5FKjs9PXSoBEjFUIfDQM+PDAxw== X-Received: by 2002:a2e:5159:: with SMTP id b25-v6mr18446263lje.156.1539785047494; Wed, 17 Oct 2018 07:04:07 -0700 (PDT) Received: from genomnajs.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id z195-v6sm2313345lff.82.2018.10.17.07.04.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 17 Oct 2018 07:04:05 -0700 (PDT) From: Linus Walleij To: Thierry Reding , dri-devel@lists.freedesktop.org Subject: [PATCH] drm: dsi: Add lane clock rate fields to DSI device Date: Wed, 17 Oct 2018 16:04:01 +0200 Message-Id: <20181017140401.29296-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.2 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The DSI devices have a maximum operating frequency specified in their data sheet per the MIPI specification, and DSI hosts that can scale their frequency need this information to set their clock dividers right. As current panel drivers often lack this information, specify that setting it to zero will make the DSI host use some reasonable default. Cc: Andrzej Hajda Signed-off-by: Linus Walleij --- include/drm/drm_mipi_dsi.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index 4fef19064b0f..a57105776e08 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -168,6 +168,10 @@ struct mipi_dsi_device_info { * @format: pixel format for video mode * @lanes: number of active data lanes * @mode_flags: DSI operation mode related flags + * @hs_rate_hz: Maximum lane frequency for high speed operation, if zero + * the driver can assume some safe default + * @lp_rate_hz: Maximum lane frequency for low power operation, if zero + * the driver can assume some safe default */ struct mipi_dsi_device { struct mipi_dsi_host *host; @@ -178,6 +182,8 @@ struct mipi_dsi_device { unsigned int lanes; enum mipi_dsi_pixel_format format; unsigned long mode_flags; + unsigned long hs_rate_hz; + unsigned long lp_rate_hz; }; #define MIPI_DSI_MODULE_PREFIX "mipi-dsi:"