From patchwork Thu Sep 2 22:57:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 505836 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42D33C433EF for ; Thu, 2 Sep 2021 22:58:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2808E610FB for ; Thu, 2 Sep 2021 22:58:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347918AbhIBW7E (ORCPT ); Thu, 2 Sep 2021 18:59:04 -0400 Received: from wnew1-smtp.messagingengine.com ([64.147.123.26]:47113 "EHLO wnew1-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347912AbhIBW64 (ORCPT ); Thu, 2 Sep 2021 18:58:56 -0400 Received: from compute2.internal (compute2.nyi.internal [10.202.2.42]) by mailnew.west.internal (Postfix) with ESMTP id 0692B2B0004F; Thu, 2 Sep 2021 18:57:56 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute2.internal (MEProxy); Thu, 02 Sep 2021 18:57:57 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm3; bh=4O/6AKT6OT51h gMCAL5YGVG9wbdi8gB/Srj+y+pJsPM=; b=neLRzjc1NRd58tc8OKTKalQLEj6Jj i4js/08kAkQiIRwG/RbaKPA2IsIFNyPE/cNZk6atxGY5VJ3AFM3Uy2YmCdpDoQ8W BevacnhlkegPau6rUORu0CcFXgmhxh849g/xzieortOjsFQS2mrpgbTQ9xRH0+QN 7GRSOsmHhA2ylO7kkOMmaaN6SYSQ1VimEbLALgZ0jux12r/KWJyEYRfyocPpmuld Cd/PGQba3ZZy04ZmecdJXCCe/r2tEvsv6AIZPM1QTs6nXuLKcAmkzoj4aKajC6VE w/A8hc2pNv15eCL/yZztLLvnmeWpBhcqi9HXBJ8iPpV43+ID+GfQylX3A== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm3; bh=4O/6AKT6OT51hgMCAL5YGVG9wbdi8gB/Srj+y+pJsPM=; b=leNLtN1c tUsIdEh9+ms+KZT3+jnhyZ4AI/BOITVp/rVejbsHpwJuNwNJXQvT80TJHDwWdHvC /8eDRwK2qDbMHzSnU+jK4dQsZ+Mu1brSN9OxnVBduCPqwuL8xIgjxXrmI5e3eE0u ErL+pszmt12FHIuTl/yE/2Ahkxix3EWnG1Rxs6lSEpgbIOvZHs+sVvmM7U0cl96A RIjP53VEiSJ46HWyFUgiqLzT0h7cp3yan6FBcqjxeM5WCb+rXcxj/QdWa3qzjxTN OfeC7GYE7gpGnQbytMcrUyEzznnemruSxvub2EqexKzYs2sYlsb0FKmiAtLX/10p pGcvO4/5/ZO8FA== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddruddviedgudejucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefurghmuhgv lhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenucggtf frrghtthgvrhhnpeduhfejfedvhffgfeehtefghfeiiefgfeehgfdvvdevfeegjeehjedv gfejheeuieenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhroh hmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Thu, 2 Sep 2021 18:57:54 -0400 (EDT) From: Samuel Holland To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: Icenowy Zheng , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org, Samuel Holland Subject: [PATCH v3 1/3] dt-bindings: watchdog: sunxi: Add compatibles for R329 Date: Thu, 2 Sep 2021 17:57:48 -0500 Message-Id: <20210902225750.29313-2-samuel@sholland.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210902225750.29313-1-samuel@sholland.org> References: <20210902225750.29313-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On existing SoCs, the watchdog has a single clock input: HOSC (OSC24M) divided by 750. However, starting with R329, LOSC (OSC32k) is added as an alternative clock source, with a bit to switch between them. Since 24 MHz / 750 == 32 kHz, not 32.768 kHz, the hardware adjusts the cycle counts to keep the timeouts independent of the clock source. This keeps the programming interface backward-compatible. Furthermore, the R329 has two watchdogs: one for use by the ARM CPUs at 0x20000a0, and a second one for use by the DSPs at 0x7020400. The first of these adds two more new registers, to allow software to immediately assert the SoC reset signal. Add an additional "-reset" suffix to signify the presence of this feature. Signed-off-by: Samuel Holland Acked-by: Maxime Ripard Reviewed-by: Rob Herring --- Changes v2 to v3: - Add else case - Add additional allwinner,sun50i-r329-wdt-reset compatible Changes v1 to v2: - Switch clock-names from enum to const - Add descriptions to "clocks" items .../watchdog/allwinner,sun4i-a10-wdt.yaml | 42 ++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml index 9aa3c313c49f..877f47759814 100644 --- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml @@ -24,6 +24,8 @@ properties: - allwinner,sun50i-a100-wdt - allwinner,sun50i-h6-wdt - allwinner,sun50i-h616-wdt + - allwinner,sun50i-r329-wdt + - allwinner,sun50i-r329-wdt-reset - const: allwinner,sun6i-a31-wdt - items: - const: allwinner,suniv-f1c100s-wdt @@ -33,7 +35,18 @@ properties: maxItems: 1 clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 + items: + - description: High-frequency oscillator input, divided internally + - description: Low-frequency oscillator input, only found on some variants + + clock-names: + minItems: 1 + maxItems: 2 + items: + - const: hosc + - const: losc interrupts: maxItems: 1 @@ -44,6 +57,33 @@ required: - clocks - interrupts +if: + properties: + compatible: + contains: + enum: + - allwinner,sun50i-r329-wdt + - allwinner,sun50i-r329-wdt-reset + +then: + properties: + clocks: + minItems: 2 + + clock-names: + minItems: 2 + + required: + - clock-names + +else: + properties: + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + unevaluatedProperties: false examples: From patchwork Thu Sep 2 22:57:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 506711 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BBB9C4332F for ; Thu, 2 Sep 2021 22:58:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 621F7610FC for ; Thu, 2 Sep 2021 22:58:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347924AbhIBW7G (ORCPT ); Thu, 2 Sep 2021 18:59:06 -0400 Received: from wnew1-smtp.messagingengine.com ([64.147.123.26]:42679 "EHLO wnew1-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232013AbhIBW67 (ORCPT ); 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Thu, 2 Sep 2021 18:57:58 -0400 (EDT) From: Samuel Holland To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: Icenowy Zheng , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org, Samuel Holland Subject: [PATCH v3 2/3] dt-bindings: watchdog: sunxi: Add compatibles for D1 Date: Thu, 2 Sep 2021 17:57:49 -0500 Message-Id: <20210902225750.29313-3-samuel@sholland.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210902225750.29313-1-samuel@sholland.org> References: <20210902225750.29313-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org D1 keeps the same register layout and clock sources as the R329, but it adds a key field which must be set to update the watchdog's "CFG" and "MODE" registers. Therefore it is not backward-compatible. Similarly to the R329, the D1 has three watchdog instances, and only one of them has the "soft reset" registers. So that instance needs an extra compatible string. Signed-off-by: Samuel Holland Acked-by: Guenter Roeck --- Changes v2 to v3: - Add additional allwinner,sun20i-d1-wdt-reset compatible Changes v1 to v2: - None .../bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml index 877f47759814..44cad9427ae6 100644 --- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml @@ -30,6 +30,10 @@ properties: - items: - const: allwinner,suniv-f1c100s-wdt - const: allwinner,sun4i-a10-wdt + - const: allwinner,sun20i-d1-wdt + - items: + - const: allwinner,sun20i-d1-wdt-reset + - const: allwinner,sun20i-d1-wdt reg: maxItems: 1 @@ -62,6 +66,8 @@ if: compatible: contains: enum: + - allwinner,sun20i-d1-wdt + - allwinner,sun20i-d1-wdt-reset - allwinner,sun50i-r329-wdt - allwinner,sun50i-r329-wdt-reset From patchwork Thu Sep 2 22:57:50 2021 Content-Type: text/plain; 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Thu, 2 Sep 2021 18:58:00 -0400 (EDT) From: Samuel Holland To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Maxime Ripard , Chen-Yu Tsai , Jernej Skrabec Cc: Icenowy Zheng , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org, Samuel Holland , Maxime Ripard Subject: [PATCH v3 3/3] watchdog: sunxi_wdt: Add support for D1 Date: Thu, 2 Sep 2021 17:57:50 -0500 Message-Id: <20210902225750.29313-4-samuel@sholland.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210902225750.29313-1-samuel@sholland.org> References: <20210902225750.29313-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org D1 adds a key field to the "CFG" and "MODE" registers, that must be set to change the other bits. Add logic to set the key when updating those registers. Acked-by: Maxime Ripard Reviewed-by: Guenter Roeck Signed-off-by: Samuel Holland --- Changes v2 to v3: - None Changes v1 to v2: - None drivers/watchdog/sunxi_wdt.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c index b50757882a98..6cf82922d3fb 100644 --- a/drivers/watchdog/sunxi_wdt.c +++ b/drivers/watchdog/sunxi_wdt.c @@ -48,6 +48,7 @@ struct sunxi_wdt_reg { u8 wdt_timeout_shift; u8 wdt_reset_mask; u8 wdt_reset_val; + u32 wdt_key_val; }; struct sunxi_wdt_dev { @@ -91,12 +92,14 @@ static int sunxi_wdt_restart(struct watchdog_device *wdt_dev, val = readl(wdt_base + regs->wdt_cfg); val &= ~(regs->wdt_reset_mask); val |= regs->wdt_reset_val; + val |= regs->wdt_key_val; writel(val, wdt_base + regs->wdt_cfg); /* Set lowest timeout and enable watchdog */ val = readl(wdt_base + regs->wdt_mode); val &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift); val |= WDT_MODE_EN; + val |= regs->wdt_key_val; writel(val, wdt_base + regs->wdt_mode); /* @@ -109,6 +112,7 @@ static int sunxi_wdt_restart(struct watchdog_device *wdt_dev, mdelay(5); val = readl(wdt_base + regs->wdt_mode); val |= WDT_MODE_EN; + val |= regs->wdt_key_val; writel(val, wdt_base + regs->wdt_mode); } return 0; @@ -141,6 +145,7 @@ static int sunxi_wdt_set_timeout(struct watchdog_device *wdt_dev, reg = readl(wdt_base + regs->wdt_mode); reg &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift); reg |= wdt_timeout_map[timeout] << regs->wdt_timeout_shift; + reg |= regs->wdt_key_val; writel(reg, wdt_base + regs->wdt_mode); sunxi_wdt_ping(wdt_dev); @@ -154,7 +159,7 @@ static int sunxi_wdt_stop(struct watchdog_device *wdt_dev) void __iomem *wdt_base = sunxi_wdt->wdt_base; const struct sunxi_wdt_reg *regs = sunxi_wdt->wdt_regs; - writel(0, wdt_base + regs->wdt_mode); + writel(regs->wdt_key_val, wdt_base + regs->wdt_mode); return 0; } @@ -176,11 +181,13 @@ static int sunxi_wdt_start(struct watchdog_device *wdt_dev) reg = readl(wdt_base + regs->wdt_cfg); reg &= ~(regs->wdt_reset_mask); reg |= regs->wdt_reset_val; + reg |= regs->wdt_key_val; writel(reg, wdt_base + regs->wdt_cfg); /* Enable watchdog */ reg = readl(wdt_base + regs->wdt_mode); reg |= WDT_MODE_EN; + reg |= regs->wdt_key_val; writel(reg, wdt_base + regs->wdt_mode); return 0; @@ -220,9 +227,20 @@ static const struct sunxi_wdt_reg sun6i_wdt_reg = { .wdt_reset_val = 0x01, }; +static const struct sunxi_wdt_reg sun20i_wdt_reg = { + .wdt_ctrl = 0x10, + .wdt_cfg = 0x14, + .wdt_mode = 0x18, + .wdt_timeout_shift = 4, + .wdt_reset_mask = 0x03, + .wdt_reset_val = 0x01, + .wdt_key_val = 0x16aa0000, +}; + static const struct of_device_id sunxi_wdt_dt_ids[] = { { .compatible = "allwinner,sun4i-a10-wdt", .data = &sun4i_wdt_reg }, { .compatible = "allwinner,sun6i-a31-wdt", .data = &sun6i_wdt_reg }, + { .compatible = "allwinner,sun20i-d1-wdt", .data = &sun20i_wdt_reg }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sunxi_wdt_dt_ids);