From patchwork Wed Sep 1 12:30:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 505209 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B054BC4320E for ; Wed, 1 Sep 2021 12:31:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8F15161106 for ; Wed, 1 Sep 2021 12:31:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244969AbhIAMcF (ORCPT ); Wed, 1 Sep 2021 08:32:05 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:27508 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244764AbhIAMbZ (ORCPT ); Wed, 1 Sep 2021 08:31:25 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1630499428; x=1662035428; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=X8q1BEpaua/HH2cC3dulzG6TmzCuYyUWyJH4PW2xp7A=; b=ANoGlB02VuK9vc5Z8GxT8mxssLHDSTD0zX9qjgi63l6e4+QAbhcI1A1X b9dPHSTGesk44NU6OnrB9xRlp2OLY+03NI41L0TTzN43VCdmZPKnqxXoo VbxBLbVLHobPnHGq3D5/ZJ1VlA6upmjs4F7d3Pdy2LYFgDdoGQzwR02bG se1CbPaFQf3QdMCbHgUfjS8iM0xT5tTOJ7z1fPmy+SxaAgGCVYie/JaMk HWHb7y++BVEnDoNaUcNB+e+onfpHbvoFXc6D3JbcUgH+DqrPHCB1pRzIC dbEpcv/wXv04mFOSu2OiwJWjqk3Jw9/TuVGNIMguQrgwWNY6YngK4ngCd Q==; IronPort-SDR: OQBabRmA9RyquKBzdfsrVjxzFAB9kgyMtkTcjeIrIRIy5IUZgPKwNdM3NTCl8ZPnI5Y/4n26x8 uRt/3oyRzToO8PtrAcF1eGQ6oYC59cBm2rZklX0KlczlzuarXkhIZ3L/nlxt+GnmzVaR07y/yb 7qXYfMPI84pJUBDwM1dDOCKf+PHWeVltrriGXo5b+CO3tqpYHencz0C3H5nG18ZUgK0polH8TL ++NsNZD6On+6d06TkiKnloo5R/53EDlit3Clup/YqGQeX5Ud0eDXh1BeC/Y232cwp48UcGPJ8o 3d5NNGs+gW80bqr+e51tiEnt X-IronPort-AV: E=Sophos;i="5.84,369,1620716400"; d="scan'208";a="130318327" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Sep 2021 05:30:28 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Wed, 1 Sep 2021 05:30:27 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Wed, 1 Sep 2021 05:30:24 -0700 From: Eugen Hristev To: , , , CC: , , , , Eugen Hristev , Rob Herring Subject: [PATCH v3 01/10] dt-bindings: iio: adc: at91-sama5d2: add compatible for sama7g5-adc Date: Wed, 1 Sep 2021 15:30:04 +0300 Message-ID: <20210901123013.329792-2-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210901123013.329792-1-eugen.hristev@microchip.com> References: <20210901123013.329792-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add compatible for microchip,sama7g5-adc device. Acked-by: Rob Herring Signed-off-by: Eugen Hristev --- Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml b/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml index 79c13b408eda..efed361215b4 100644 --- a/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml @@ -15,6 +15,7 @@ properties: enum: - atmel,sama5d2-adc - microchip,sam9x60-adc + - microchip,sama7g5-adc reg: maxItems: 1 From patchwork Wed Sep 1 12:30:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 505208 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A04ECC19F38 for ; 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IronPort-SDR: CQvGiX9JeozmbXPUQv3AIxtSNTeSI5dMHynVwK7b+RdaeT08BPaLXSS4RMA9+gI/hdcQZl+PM6 hEa4yxiNLLPted1+/638/eYrDSqHtVzrClZc5vR42wofkaErR2nGGiqaXu9Uw2w4Gah2M7KLLb 0A2P0mZ3HpcSqQeb+z+Yc26UVVAMldbtG1h2jzsl3jWFv0e8CiPrnZYrEU+eSwN0KMEr4x4vfN gE4ZIacDszIc8UPzKUQFCduLuryvxXliQ8Tm19Omhm96vT1ZF9ARX1+q1dF838q53+lCbK5vMq 0nsySnN6b/avlfnjc3dUX88m X-IronPort-AV: E=Sophos;i="5.84,369,1620716400"; d="scan'208";a="134969777" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Sep 2021 05:30:32 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Wed, 1 Sep 2021 05:30:32 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Wed, 1 Sep 2021 05:30:30 -0700 From: Eugen Hristev To: , , , CC: , , , , Eugen Hristev Subject: [PATCH v3 03/10] iio: adc: at91-sama5d2_adc: remove unused definition Date: Wed, 1 Sep 2021 15:30:06 +0300 Message-ID: <20210901123013.329792-4-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210901123013.329792-1-eugen.hristev@microchip.com> References: <20210901123013.329792-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Remove unused register definition Signed-off-by: Eugen Hristev --- drivers/iio/adc/at91-sama5d2_adc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index 1f4d461c2c18..9d71dcffcf93 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -143,8 +143,6 @@ #define AT91_SAMA5D2_COR 0x4c #define AT91_SAMA5D2_COR_DIFF_OFFSET 16 -/* Channel Data Register 0 */ -#define AT91_SAMA5D2_CDR0 0x50 /* Analog Control Register */ #define AT91_SAMA5D2_ACR 0x94 /* Analog Control Register - Pen detect sensitivity mask */ From patchwork Wed Sep 1 12:30:08 2021 Content-Type: text/plain; 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d="scan'208";a="130318387" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Sep 2021 05:30:39 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Wed, 1 Sep 2021 05:30:38 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Wed, 1 Sep 2021 05:30:35 -0700 From: Eugen Hristev To: , , , CC: , , , , Eugen Hristev Subject: [PATCH v3 05/10] iio: adc: at91-sama5d2_adc: add support for separate end of conversion registers Date: Wed, 1 Sep 2021 15:30:08 +0300 Message-ID: <20210901123013.329792-6-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210901123013.329792-1-eugen.hristev@microchip.com> References: <20210901123013.329792-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some platforms have separated the end-of-conversion information from the usual ISR/IMR/IER/IDR registers, into EOC_ISR/EOC_IMR/EOC_IER/EOC_IDR. To cope with both variants, helpers are being added, that will make code more clear and more easy to read. Signed-off-by: Eugen Hristev --- Changes in v3: - subject at91-sama5d2-adc -> at91-sama5d2_adc drivers/iio/adc/at91-sama5d2_adc.c | 66 ++++++++++++++++++++++++++---- 1 file changed, 59 insertions(+), 7 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index d81e16f13b3b..c227a0865a31 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -117,6 +117,14 @@ struct at91_adc_reg_layout { u16 IMR; /* Interrupt Status Register */ u16 ISR; +/* End of Conversion Interrupt Enable Register */ + u16 EOC_IER; +/* End of Conversion Interrupt Disable Register */ + u16 EOC_IDR; +/* End of Conversion Interrupt Mask Register */ + u16 EOC_IMR; +/* End of Conversion Interrupt Status Register */ + u16 EOC_ISR; /* Interrupt Status Register - Pen touching sense status */ #define AT91_SAMA5D2_ISR_PENS BIT(31) /* Last Channel Trigger Mode Register */ @@ -586,6 +594,44 @@ static unsigned int at91_adc_active_scan_mask_to_reg(struct iio_dev *indio_dev) return mask & GENMASK(st->soc_info.platform->nr_channels, 0); } +static void at91_adc_irq_status(struct at91_adc_state *st, u32 *status, + u32 *eoc) +{ + *status = at91_adc_readl(st, ISR); + if (st->soc_info.platform->layout->EOC_ISR) + *eoc = at91_adc_readl(st, EOC_ISR); + else + *eoc = *status; +} + +static void at91_adc_irq_mask(struct at91_adc_state *st, u32 *status, u32 *eoc) +{ + *status = at91_adc_readl(st, IMR); + if (st->soc_info.platform->layout->EOC_IMR) + *eoc = at91_adc_readl(st, EOC_IMR); + else + *eoc = *status; +} + +static void at91_adc_eoc_dis(struct at91_adc_state *st, unsigned int channel) +{ + /* + * On some products having the EOC bits in a separate register, + * errata recommends not writing this register (EOC_IDR). + * On products having the EOC bits in the IDR register, it's fine to write it. + */ + if (!st->soc_info.platform->layout->EOC_IDR) + at91_adc_writel(st, IDR, BIT(channel)); +} + +static void at91_adc_eoc_ena(struct at91_adc_state *st, unsigned int channel) +{ + if (!st->soc_info.platform->layout->EOC_IDR) + at91_adc_writel(st, IER, BIT(channel)); + else + at91_adc_writel(st, EOC_IER, BIT(channel)); +} + static void at91_adc_config_emr(struct at91_adc_state *st) { /* configure the extended mode register */ @@ -1105,13 +1151,15 @@ static void at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev, u8 bit; u32 mask = at91_adc_active_scan_mask_to_reg(indio_dev); unsigned int timeout = 50; + u32 status, imr, eoc = 0, eoc_imr; /* * Check if the conversion is ready. If not, wait a little bit, and * in case of timeout exit with an error. */ - while ((at91_adc_readl(st, ISR) & mask) != mask && - timeout) { + while (((eoc & mask) != mask) && timeout) { + at91_adc_irq_status(st, &status, &eoc); + at91_adc_irq_mask(st, &imr, &eoc_imr); usleep_range(50, 100); timeout--; } @@ -1347,12 +1395,14 @@ static irqreturn_t at91_adc_interrupt(int irq, void *private) { struct iio_dev *indio = private; struct at91_adc_state *st = iio_priv(indio); - u32 status = at91_adc_readl(st, ISR); - u32 imr = at91_adc_readl(st, IMR); + u32 status, eoc, imr, eoc_imr; u32 rdy_mask = AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY | AT91_SAMA5D2_IER_PRDY; - if (!(status & imr)) + at91_adc_irq_status(st, &status, &eoc); + at91_adc_irq_mask(st, &imr, &eoc_imr); + + if (!(status & imr) && !(eoc & eoc_imr)) return IRQ_NONE; if (status & AT91_SAMA5D2_IER_PEN) { /* pen detected IRQ */ @@ -1446,7 +1496,7 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev, at91_adc_writel(st, COR, cor); at91_adc_writel(st, CHER, BIT(chan->channel)); - at91_adc_writel(st, IER, BIT(chan->channel)); + at91_adc_eoc_ena(st, chan->channel); at91_adc_writel(st, CR, AT91_SAMA5D2_CR_START); ret = wait_event_interruptible_timeout(st->wq_data_available, @@ -1463,7 +1513,7 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev, st->conversion_done = false; } - at91_adc_writel(st, IDR, BIT(chan->channel)); + at91_adc_eoc_dis(st, st->chan->channel); at91_adc_writel(st, CHDR, BIT(chan->channel)); /* Needed to ACK the DRDY interruption */ @@ -1681,6 +1731,8 @@ static void at91_adc_hw_init(struct iio_dev *indio_dev) struct at91_adc_state *st = iio_priv(indio_dev); at91_adc_writel(st, CR, AT91_SAMA5D2_CR_SWRST); + if (st->soc_info.platform->layout->EOC_IDR) + at91_adc_writel(st, EOC_IDR, 0xffffffff); at91_adc_writel(st, IDR, 0xffffffff); /* * Transfer field must be set to 2 according to the datasheet and From patchwork Wed Sep 1 12:30:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 505206 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55C21C43214 for ; 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IronPort-SDR: jM7m808igBDFP9TJjjxUJhfJRH81oUCHINuOKmlKjyzqvfc4GEYaGL81SakFfOlXATCEjeN85C GA1Axyrg+9YzaW4xi0fl71LW342hMEMDAWqa2ONhSit4ShFoOB+6UI29P+WxSmsRBLTX5Zo3zC 5LgsnV4LmWizFk+eemmMEcZjsdlZXfJReF4rbCHGgIvB4cxfzv1kwvXW5yQwgMib/aQZ8Ahgrc BbKepe23GTDnORW0CWP3/iLSpSM1VUNN5mwL5lZjl3Ow+ELySRA6t8B59hUIR/BjzAdyOy9XS7 LOWUNjfK8R5hnti5AMOHZxDu X-IronPort-AV: E=Sophos;i="5.84,369,1620716400"; d="scan'208";a="127848042" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Sep 2021 05:30:46 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Wed, 1 Sep 2021 05:30:46 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Wed, 1 Sep 2021 05:30:43 -0700 From: Eugen Hristev To: , , , CC: , , , , Eugen Hristev Subject: [PATCH v3 08/10] iio: adc: at91-sama5d2_adc: update copyright and authors information Date: Wed, 1 Sep 2021 15:30:11 +0300 Message-ID: <20210901123013.329792-9-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210901123013.329792-1-eugen.hristev@microchip.com> References: <20210901123013.329792-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update copyright and authors information (corrected e-mail address), and add myself as one of the authors. Signed-off-by: Eugen Hristev --- drivers/iio/adc/at91-sama5d2_adc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index 8a95310e8f64..2fc0c5d05d54 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -4,6 +4,8 @@ * * Copyright (C) 2015 Atmel, * 2015 Ludovic Desroches + * 2021 Microchip Technology, Inc. and its subsidiaries + * 2021 Eugen Hristev */ #include @@ -2194,6 +2196,7 @@ static struct platform_driver at91_adc_driver = { }; module_platform_driver(at91_adc_driver) -MODULE_AUTHOR("Ludovic Desroches "); +MODULE_AUTHOR("Ludovic Desroches "); +MODULE_AUTHOR("Eugen Hristev X-Patchwork-Id: 505205 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2875C4320E for ; Wed, 1 Sep 2021 12:31:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C6F7C610F7 for ; Wed, 1 Sep 2021 12:31:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244914AbhIAMcp (ORCPT ); Wed, 1 Sep 2021 08:32:45 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:61597 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244923AbhIAMbt (ORCPT ); Wed, 1 Sep 2021 08:31:49 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1630499452; x=1662035452; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=solFwV4JTQfjT1p/kr3lKPxhmPtCyWwDUzcwzBiiHAo=; b=sS7rnzZDzYGS79TbId3bQ5CxB/ElJBZqk5kYIi8S6kkfvmspd06KFhVy mDDqoSYVdFeDArMrz9UnSlTzjUJ3vnmqd8EdpAHRbV/NuGq9xZTWLeGy3 uD0Qt1IOF+AZTUNeQVB9Ixje66/GAXPuPFAWn5PnO6MQF4n1oYgG4kT72 AintL4epFfsfGm96E8P8Z/AA6n8lYraoIEicF+pIyrBOEgfDYVpT+PY0G cvhKJAp3mo/3y5xk5TcG0D2P/M3sZfrGSMFjDO8n8jXQXItVgbu4mVl5I xXwUEAwcA3/T6XTV6NUp9fKoCKLyrYR3wk8796uGQXLmwTM8Cqq/jOcMl Q==; IronPort-SDR: GNeBo18az5P2D2SIfssYe+RWQitxbKxnuINk85HUxCuee08lWDJZRUFq6Ki9imiTZoXbF0Huq8 wYPAzR/u456tUeekDJZZsc5EqUs7sZYyA5+OYcvB0a4PXmYAgW2extWpICe+i+dyjpn28No4gc i1ObCIvZu0MdxSIhjYzZ6fsFsHHCuYE5Hn3DsL+nCTBfE4Hh7OqgtxwYCcbCG33UvCqUH8j+r8 I2JFtdvx75BiE4CVx+zMDpu3WVbi2rVfy9dOMzgh5EwRBfJH4CNB1fg7Hhs1EX6eJQwYAOVRFL 9bk34D3pAj154OKqFTD0MifT X-IronPort-AV: E=Sophos;i="5.84,369,1620716400"; d="scan'208";a="67859488" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Sep 2021 05:30:51 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Wed, 1 Sep 2021 05:30:51 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Wed, 1 Sep 2021 05:30:49 -0700 From: Eugen Hristev To: , , , CC: , , , , Eugen Hristev Subject: [PATCH v3 10/10] ARM: dts: at91: sama7g5ek: enable ADC on the board Date: Wed, 1 Sep 2021 15:30:13 +0300 Message-ID: <20210901123013.329792-11-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210901123013.329792-1-eugen.hristev@microchip.com> References: <20210901123013.329792-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The ADC controller on the board is fed by a 2.5V reference voltage. By default the channels #14 and #15 are dedicated to analog input (marked AN on the board), on the connectors mikrobus1 and mikrobus2. Signed-off-by: Eugen Hristev Acked-by: Nicolas Ferre --- arch/arm/boot/dts/at91-sama7g5ek.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts index 4cbed98cc2f4..c46be165f2ba 100644 --- a/arch/arm/boot/dts/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/at91-sama7g5ek.dts @@ -122,6 +122,14 @@ spdif_out: spdif-out { }; }; +&adc { + vddana-supply = <&vddout25>; + vref-supply = <&vddout25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mikrobus1_an_default &pinctrl_mikrobus2_an_default>; + status = "okay"; +}; + &cpu0 { cpu-supply = <&vddcpu>; };