From patchwork Wed Sep 1 23:53:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kieran Bingham X-Patchwork-Id: 505162 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10F15C43214 for ; Wed, 1 Sep 2021 23:53:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E294360FC4 for ; Wed, 1 Sep 2021 23:53:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234223AbhIAXyi (ORCPT ); Wed, 1 Sep 2021 19:54:38 -0400 Received: from perceval.ideasonboard.com ([213.167.242.64]:53848 "EHLO perceval.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231137AbhIAXyh (ORCPT ); Wed, 1 Sep 2021 19:54:37 -0400 Received: from Monstersaurus.local (cpc89244-aztw30-2-0-cust3082.18-1.cable.virginm.net [86.31.172.11]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 683451544; Thu, 2 Sep 2021 01:53:36 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1630540416; bh=NbhF6WzQJ9BKxrEgoIvu6phF4AkR/Rg1lsS5nZtesiA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oM/M31prNq/HZdff/YRxYqFQI1yCe1oMw0mDfcVO4QuHULl1hbEnN2tt9BKi7XI1S tNcni2I8wl8FVP4jSzuKEsXwyCVUyNLf78oAGkMZxCg9/z/t/AxfhHFY+KlOot+b5W 02UTnG2bel0KkPELCqAb5F43AU39k9GfG/ry3HII= From: Kieran Bingham To: Laurent Pinchart , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org Cc: Kieran Bingham , Geert Uytterhoeven , Magnus Damm , Rob Herring , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 2/3] arm64: dts: renesas: r8a779a0: Add DSI encoders Date: Thu, 2 Sep 2021 00:53:29 +0100 Message-Id: <20210901235330.1611086-3-kieran.bingham@ideasonboard.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210901235330.1611086-1-kieran.bingham@ideasonboard.com> References: <20210901235330.1611086-1-kieran.bingham@ideasonboard.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kieran Bingham Provide the two MIPI DSI encoders on the V3U and connect them to the DU accordingly. Signed-off-by: Kieran Bingham Reviewed-by: Laurent Pinchart --- v2 - Fixup indentation arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 60 +++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 3241f7e7c01e..1ce9884ea527 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -1161,12 +1161,72 @@ ports { port@0 { reg = <0>; du_out_dsi0: endpoint { + remote-endpoint = <&dsi0_in>; }; }; port@1 { reg = <1>; du_out_dsi1: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + + dsi0: dsi-encoder@fed80000 { + compatible = "renesas,r8a779a0-dsi-csi2-tx"; + reg = <0 0xfed80000 0 0x10000>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 415>, + <&cpg CPG_CORE R8A779A0_CLK_DSI>; + clock-names = "fck", "dsi"; + resets = <&cpg 415>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&du_out_dsi0>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi1: dsi-encoder@fed90000 { + compatible = "renesas,r8a779a0-dsi-csi2-tx"; + reg = <0 0xfed90000 0 0x10000>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 416>, + <&cpg CPG_CORE R8A779A0_CLK_DSI>; + clock-names = "fck", "dsi"; + resets = <&cpg 416>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&du_out_dsi1>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { }; }; }; From patchwork Wed Sep 1 23:53:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kieran Bingham X-Patchwork-Id: 505161 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBB48C432BE for ; Wed, 1 Sep 2021 23:53:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9AAEB610CF for ; Wed, 1 Sep 2021 23:53:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235750AbhIAXyi (ORCPT ); Wed, 1 Sep 2021 19:54:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233214AbhIAXyi (ORCPT ); Wed, 1 Sep 2021 19:54:38 -0400 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [IPv6:2001:4b98:dc2:55:216:3eff:fef7:d647]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B3B0FC061575; Wed, 1 Sep 2021 16:53:40 -0700 (PDT) Received: from Monstersaurus.local (cpc89244-aztw30-2-0-cust3082.18-1.cable.virginm.net [86.31.172.11]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 07C8B18F9; Thu, 2 Sep 2021 01:53:36 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1630540417; bh=r4Kc4gwJEr7RgyM2A9nibVhkYspAI6L1Ihzyx0kFhKo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eF50aG/qKZthW+eoGXNHSKobu+8GRsFv3QfMVL3ua4Adjb0mMXJUnx+w9XHEEhAUs 3UvHrIZ/arck846fXIyLSOrS7I8EQnhgVc0QbxZqUnD+lUjX/Ks8+E3nrzW3jiST5u pnPZ4mH0iT02Z5ffkdpvVSmv9yYIKgfxlGTslE/o= From: Kieran Bingham To: Laurent Pinchart , Geert Uytterhoeven , linux-renesas-soc@vger.kernel.org Cc: Kieran Bingham , Geert Uytterhoeven , Magnus Damm , Rob Herring , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 3/3] arm64: dts: renesas: falcon-cpu: Add DSI display output Date: Thu, 2 Sep 2021 00:53:30 +0100 Message-Id: <20210901235330.1611086-4-kieran.bingham@ideasonboard.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210901235330.1611086-1-kieran.bingham@ideasonboard.com> References: <20210901235330.1611086-1-kieran.bingham@ideasonboard.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Kieran Bingham Provide the display output using the sn65dsi86 MIPI DSI bridge. Signed-off-by: Kieran Bingham Reviewed-by: Laurent Pinchart --- .../boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi index a0a1a1da0d87..5530bb82de6b 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi @@ -66,6 +66,15 @@ memory@700000000 { reg = <0x7 0x00000000 0x0 0x80000000>; }; + reg_1p2v: regulator-1p2v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.2V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; @@ -83,6 +92,46 @@ reg_3p3v: regulator-3p3v { regulator-boot-on; regulator-always-on; }; + + mini-dp-con { + compatible = "dp-connector"; + label = "CN5"; + type = "mini"; + + port { + mini_dp_con_in: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + + sn65dsi86_refclk: sn65dsi86-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; +}; + +&dsi0 { + status = "okay"; + + clocks = <&cpg CPG_MOD 415>, + <&cpg CPG_CORE R8A779A0_CLK_DSI>, + <&extal_clk>; + clock-names = "fck", "dsi", "extal"; + + ports { + port@1 { + endpoint { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&du { + status = "okay"; }; &extal_clk { @@ -114,6 +163,41 @@ &i2c1 { status = "okay"; clock-frequency = <400000>; + + sn65dsi86@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + + clocks = <&sn65dsi86_refclk>; + clock-names = "refclk"; + + interrupt-parent = <&gpio1>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; + + vccio-supply = <®_1p8v>; + vpll-supply = <®_1p8v>; + vcca-supply = <®_1p2v>; + vcc-supply = <®_1p2v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sn65dsi86_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + sn65dsi86_out: endpoint { + remote-endpoint = <&mini_dp_con_in>; + }; + }; + }; + }; }; &i2c6 {