From patchwork Mon Oct 15 18:40:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 148881 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp4134549lji; Mon, 15 Oct 2018 11:40:55 -0700 (PDT) X-Google-Smtp-Source: ACcGV60jAuHJ99LYAwcIg/cMbLCd7aXfoal12040InVuSbABp3pZ/U4xKylPepCa6MFFVKCySp4W X-Received: by 2002:a62:e80c:: with SMTP id c12-v6mr18869854pfi.124.1539628854890; Mon, 15 Oct 2018 11:40:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539628854; cv=none; d=google.com; s=arc-20160816; b=MH2m++YkuYa2zDhk4QELLLN/1f1srb4jh+fG7/Vn+jHtNd+Z4S8OC+22vTXEhtGOvs efR98/vsuDc+xc9VUwpz40t4eVBHI/j7kJ7tH3gdhcx8MsTDXDgog58lK611d9wcFXS6 OZbRE2rZobjYQPaexbPCB7xx1rHUBi8T0ayE8Onm1RncuQwHNLCZ9j+pqblQmZHTV3X7 1YidjENXnhKOQsBnbqI917sgV2Ph1m2Iho000xcmmbClimffgTggDy5kUs5wAa4qIY8h En0TftMkS184j/Dc6brmUzjCfknsBBdUZMGLZHygme/iWy9WHo9KvYt/oR/LfrBHxcpx hOvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=YLsDhg5zmRoRd2nq9v4jijpwo9apn3dlm8tarNuMuio=; b=r+UnTmJ8JY3OzN0EBpE3/cD5XX1JGRK/5pblZ/iwIf1fTJOvqjz8rkIsvfD475bZx+ MPQ5uoHozcRa1jJHJVqBZMmsKl1nVD1lhj01dCDWrTOAF3bcSss+Kz9ILsO63hCtP7Ef XWwPqeernEg+ESQBaEOamhcjItxmKj+dRf5uedJaf/tB/BLZceJWef9IKH6JpWAWNe3k +sLW9FwvqktVumGImYUi8HQVixjAyhii9QhSmGWnzvR8ioI5+f7XwDGMQvmEgwWE87uA UhTQYF1xj9L5foh1oqdIrCeLUvb76fuqFqUato9244bIgthhKJMo4FUt2Yy3KlONqs4q 5Ajg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eG7AyAl4; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m12-v6si10899735pll.105.2018.10.15.11.40.54; Mon, 15 Oct 2018 11:40:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eG7AyAl4; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726810AbeJPC1U (ORCPT + 13 others); Mon, 15 Oct 2018 22:27:20 -0400 Received: from mail-pl1-f196.google.com ([209.85.214.196]:43494 "EHLO mail-pl1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726703AbeJPC1U (ORCPT ); Mon, 15 Oct 2018 22:27:20 -0400 Received: by mail-pl1-f196.google.com with SMTP id 30-v6so9710097plb.10 for ; Mon, 15 Oct 2018 11:40:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=YLsDhg5zmRoRd2nq9v4jijpwo9apn3dlm8tarNuMuio=; b=eG7AyAl4mvM3K+g92MiM9uUWKlk4f3gpgxEDtc878UxFv09ypwwc7laEsEYU2dNAEx xLlbJyQp1Q2+pQNua5/b7I8ujrdOUVhXZ5u6dQ9WkIJA2oWFJRXpMTEFBeA2SYyk9si1 UB8+AryDuYy7sC0nUNIAOVvVCKI40LQCVR/OE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=YLsDhg5zmRoRd2nq9v4jijpwo9apn3dlm8tarNuMuio=; b=atMP5jrDTSBoSL/c22ERDfmf0wccISIrwqr8zJ0RNJ+xVaLI/Y/W5y27eVVoxo75tz wjq/KVSU5V6tj+0g+NTbjF9yMROVW4Vi0BVOGNjIul4BT8ks/fjrcieZJXVGervQVxPm AlY8ZAgmjiUE9TNy+zXYBXXWGlxqj4e0CcdMY1u+CcUSpT89NUy70J11fPD41g8cLvBb icL7IItDD6CuA8/RYsF24C6PAu+nNZ0GGrYl3SF78fGbCT+F2QV1PrGrsv20a7LggH/G jHBNCwLAu11pBflr9NZUveXZkdUE8u5LRgTeh5d+kt3CGTbKw7gtsDYR0V6Dfq1iYP8L j5pw== X-Gm-Message-State: ABuFfoggBdtjdLE20hZVwBEX50oBcnv30oHBJeMLc2t0w+1KN0X/Fb3d mZyCKFaNyzl23IoquAijIAq+Yw== X-Received: by 2002:a17:902:a7:: with SMTP id a36-v6mr5207898pla.87.1539628853369; Mon, 15 Oct 2018 11:40:53 -0700 (PDT) Received: from localhost ([49.248.168.189]) by smtp.gmail.com with ESMTPSA id r73-v6sm18627774pfk.157.2018.10.15.11.40.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 15 Oct 2018 11:40:52 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, vkoul@kernel.org, Zhang Rui , Daniel Lezcano , Rob Herring , Mark Rutland Subject: [PATCH v1 1/4] dt: thermal: tsens: Add bindings for qcs404 Date: Tue, 16 Oct 2018 00:10:40 +0530 Message-Id: <102083e3ea93f48085b93f8df307967689ea18d6.1539627762.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org qcs404 uses v1 of the TSENS IP block. Create a fallback DT property "qcom,tsens-v1" to gather common code. Signed-off-by: Amit Kucheria --- Documentation/devicetree/bindings/thermal/qcom-tsens.txt | 3 +++ 1 file changed, 3 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt index 1d9e8cf61018..799de3062352 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.txt +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.txt @@ -8,9 +8,12 @@ Required properties: - "qcom,msm8996-tsens" (MSM8996) - "qcom,msm8998-tsens", "qcom,tsens-v2" (MSM8998) - "qcom,sdm845-tsens", "qcom,tsens-v2" (SDM845) + - "qcom,qcs404-tsens", "qcom,tsens-v1" (QCS404) The generic "qcom,tsens-v2" property must be used as a fallback for any SoC with version 2 of the TSENS IP. MSM8996 is the only exception because the generic property did not exist when support was added. + Similarly, the generic "qcom,tsens-v1" property must be used as a fallback for + any SoC with version 1 of the TSENS IP. - reg: Address range of the thermal registers. New platforms containing v2.x.y of the TSENS IP must specify the SROT and TM From patchwork Mon Oct 15 18:40:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 148884 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp4134819lji; Mon, 15 Oct 2018 11:41:09 -0700 (PDT) X-Google-Smtp-Source: ACcGV6374TSoiAN2yMQTeGdrMaGzhagJoROKzEf97+/HI6Zu9Rs/CgPbXRErC3/AlJVi3CNJoNQE X-Received: by 2002:a17:902:7b84:: with SMTP id w4-v6mr17654772pll.32.1539628869490; Mon, 15 Oct 2018 11:41:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539628869; cv=none; d=google.com; s=arc-20160816; b=hV2j7rsqnEcO6wym3g3hTBNZXtt+rI3AvwB40DAPBBo2U2nYcBV+qK8mDUtjxWQr8E I7Eyx+iMNE3Q2dTyZPLY3zCPeJ/CnKlVnZSgXsJAZyDr8DDoJ6CMXwr4n0EGrkQ+tNtp 7msXMyTh0wC+XynBZrx1oXod1qUUNKmUepCyWZO5DYCFlT1R5PTxYPc7wCt7LjgAMhrT pnqeyI9PFF1G9Egmn/hY3V4rvi3QlZS4xbZaSEMS3E4XYS3xivaaANgBMAPnckqtcfY6 nfy5nTguhPWuJCycb3vHN8mZg3YwhpTvYs43AvbZYgjU1P6qaeqGGbV/vHMHQa2X2RyY 0nKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=bFmpkKZBQAbbZS/QFSkahIqwskTA5OAWzb+7WJWC4Ak=; b=Vz6d0t31NIxbJL+gThOoh/xuBTNDR0xMOCcorVMD0Cjsws1QQTxIyd3QisxtHeJULj a9q0LjNc15LnkMajcyi14OGdEMq+BDVlgPK7FVL5+/f//y0GKjd/T/ELKkPtm7qO0grr gwbff20Y1fSt25n8L5zq9KcgKUNFiiZU1ZRgG2VRomzuOfQgJGPsRAd4GN1UkphaDt/k 5yo0G7uowky57UvJkVfuF+Y1Xpke9CGGI+UPNkD2hUbyvdzhbH7N6T1hOlLy7TwmWzq5 rSBQNHx4s1D9JwWodS1g+J34VJWK7YLI2Mynf8pqvkM0SKLi/9p92qGV2Ok7HfdQAd8O WrnQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ACYsj79Z; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v32-v6si11672316pgk.16.2018.10.15.11.41.09; Mon, 15 Oct 2018 11:41:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ACYsj79Z; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727031AbeJPC1f (ORCPT + 13 others); Mon, 15 Oct 2018 22:27:35 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:34468 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726798AbeJPC1e (ORCPT ); Mon, 15 Oct 2018 22:27:34 -0400 Received: by mail-pg1-f196.google.com with SMTP id g12-v6so9580991pgs.1 for ; Mon, 15 Oct 2018 11:41:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=bFmpkKZBQAbbZS/QFSkahIqwskTA5OAWzb+7WJWC4Ak=; b=ACYsj79ZN7/1tmPHStu1S/GzpFncJaRgzF2auSIcWuMe4YTEXTXXu3+oUpkuAFcOOC GFvh5L1x8ywdDGWGBOOKe4tcnLTg7JIlZP9M7EDyqlzI3n89+u8XUnmRC3iTzJae2fJx 94Zu4PSWORdx7VeQCfRmWZXRro4J3jqD5APS0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=bFmpkKZBQAbbZS/QFSkahIqwskTA5OAWzb+7WJWC4Ak=; b=nCp/i7i7vGIW8sGDhYh447dm2uzNFeW5P/sk/9GS7t3XIcaesFJ1mEzCsfIK47+/YT TUnBK/IZmkfwhHNprkgDsZkW4zfFXZE+2TpHX88TBHJZ4686Q1k1kshqKgTZw1AxVmtr qVtp4HoPXgJefxmTYMHnq9QpVrXuq8UeAJFF709k7taub41G6q0RgSVuuuJZg6RgERQD 44bfDI3kppKW19we4ZN0DpEqrJKLvtcPOOSYYa3bTdx2s0D9BjbvR0BhNy3Znk3ukorW iBkMXGKXEfw38WLyaz14nmZq1Sa8wSpDquwqBVfmqoMbL/7kTAhAoHL64RvVfPBgk27D UYmQ== X-Gm-Message-State: ABuFfoiElS22ZnyXhvbBHhqzheYTNJmrwjChMWuE3iRHyOq9ziZQmio2 l7Sn+eWp5sVaCJX/07qfm6jP8A== X-Received: by 2002:a62:8a91:: with SMTP id o17-v6mr18843627pfk.184.1539628867423; Mon, 15 Oct 2018 11:41:07 -0700 (PDT) Received: from localhost ([49.248.168.189]) by smtp.gmail.com with ESMTPSA id m11-v6sm13170474pgn.39.2018.10.15.11.41.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 15 Oct 2018 11:41:06 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, vkoul@kernel.org, David Brown , Rob Herring , Mark Rutland Subject: [PATCH v1 4/4] arm64: dts: qcom: qcs404: Add thermal zones for each sensor Date: Tue, 16 Oct 2018 00:10:43 +0530 Message-Id: <7a0c3d8b7a751d6549b063efee718cdb1741f473.1539627762.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org qcs404 has 10 sensors connected to the single TSENS IP. Define a thermal zone for each of those sensors to expose the temperature of each zone. Signed-off-by: Amit Kucheria --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 206 +++++++++++++++++++++++++++ 1 file changed, 206 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index dfd65c53cf5f..ea882a9ce6e3 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -69,6 +69,7 @@ reg = <0x100>; enable-method = "psci"; next-level-cache = <&L2_0>; + #cooling-cells= <2>; }; CPU1: cpu@1 { @@ -77,6 +78,7 @@ reg = <0x101>; enable-method = "psci"; next-level-cache = <&L2_0>; + #cooling-cells= <2>; }; CPU2: cpu@2 { @@ -85,6 +87,7 @@ reg = <0x102>; enable-method = "psci"; next-level-cache = <&L2_0>; + #cooling-cells= <2>; }; CPU3: cpu@3 { @@ -93,6 +96,7 @@ reg = <0x100>; enable-method = "psci"; next-level-cache = <&L2_0>; + #cooling-cells= <2>; }; L2_0: l2-cache { @@ -484,4 +488,206 @@ label = "wcss"; }; }; + + thermal-zones { + aoss-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 0>; + + trips { + aoss_alert: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + aoss_crit: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + dsp-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 1>; + + trips { + dsp_alert: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + dsp_crit: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + lpass-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 2>; + + trips { + lpass_alert: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + lpass_crit: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + wlan-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 3>; + + trips { + wlan_alert: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + wlan_crit: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cluster-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 4>; + + trips { + cluster_alert: cluster_alert { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cluster_crit: cluster_crit { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 5>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: cpu_crit0 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 6>; + + trips { + cpu_alert1: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 7>; + + trips { + cpu_alert2: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit2: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 8>; + + trips { + cpu_alert3: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit3: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 9>; + + trips { + gpu_alert: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; };