From patchwork Sun Aug 29 18:24:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "A, Rashmi" X-Patchwork-Id: 504195 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52030C432BE for ; Sun, 29 Aug 2021 18:24:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2A5C660F5D for ; Sun, 29 Aug 2021 18:24:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235751AbhH2SZr (ORCPT ); Sun, 29 Aug 2021 14:25:47 -0400 Received: from mga12.intel.com ([192.55.52.136]:63344 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230010AbhH2SZq (ORCPT ); Sun, 29 Aug 2021 14:25:46 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10091"; a="197736749" X-IronPort-AV: E=Sophos;i="5.84,361,1620716400"; d="scan'208";a="197736749" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2021 11:24:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,361,1620716400"; d="scan'208";a="445519089" Received: from coresw01.iind.intel.com ([10.106.46.194]) by orsmga002.jf.intel.com with ESMTP; 29 Aug 2021 11:24:49 -0700 From: rashmi.a@intel.com To: michal.simek@xilinx.com, ulf.hansson@linaro.org, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kishon@ti.com, vkoul@kernel.org, andriy.shevchenko@linux.intel.com, linux-phy@lists.infradead.org Cc: mgross@linux.intel.com, kris.pan@linux.intel.com, furong.zhou@intel.com, mallikarjunappa.sangannavar@intel.com, adrian.hunter@intel.com, mahesh.r.vaidya@intel.com, nandhini.srikandan@intel.com, rashmi.a@intel.com Subject: [PATCH v2 1/4] mmc: sdhci-of-arasan: Add intel Thunder Bay SOC support to the arasan eMMC driver Date: Sun, 29 Aug 2021 23:54:40 +0530 Message-Id: <20210829182443.30802-2-rashmi.a@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210829182443.30802-1-rashmi.a@intel.com> References: <20210829182443.30802-1-rashmi.a@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Rashmi A Intel Thunder Bay SoC eMMC controller is based on Arasan eMMC 5.1 host controller IP Signed-off-by: Rashmi A Reviewed-by: Adrian Hunter --- drivers/mmc/host/sdhci-of-arasan.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index 839965f7c717..6f202fb7a546 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -185,6 +185,13 @@ static const struct sdhci_arasan_soc_ctl_map intel_lgm_sdxc_soc_ctl_map = { .hiword_update = false, }; +static const struct sdhci_arasan_soc_ctl_map thunderbay_soc_ctl_map = { + .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 }, + .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 }, + .support64b = { .reg = 0x4, .width = 1, .shift = 24 }, + .hiword_update = false, +}; + static const struct sdhci_arasan_soc_ctl_map intel_keembay_soc_ctl_map = { .baseclkfreq = { .reg = 0x0, .width = 8, .shift = 14 }, .clockmultiplier = { .reg = 0x4, .width = 8, .shift = 14 }, @@ -430,6 +437,15 @@ static const struct sdhci_pltfm_data sdhci_arasan_cqe_pdata = { SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, }; +static const struct sdhci_pltfm_data sdhci_arasan_thunderbay_pdata = { + .ops = &sdhci_arasan_cqe_ops, + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | + SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN | + SDHCI_QUIRK2_STOP_WITH_TC | + SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400, +}; + #ifdef CONFIG_PM_SLEEP /** * sdhci_arasan_suspend - Suspend method for the driver @@ -1098,6 +1114,12 @@ static struct sdhci_arasan_of_data sdhci_arasan_generic_data = { .clk_ops = &arasan_clk_ops, }; +static const struct sdhci_arasan_of_data sdhci_arasan_thunderbay_data = { + .soc_ctl_map = &thunderbay_soc_ctl_map, + .pdata = &sdhci_arasan_thunderbay_pdata, + .clk_ops = &arasan_clk_ops, +}; + static const struct sdhci_pltfm_data sdhci_keembay_emmc_pdata = { .ops = &sdhci_arasan_cqe_ops, .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | @@ -1231,6 +1253,10 @@ static const struct of_device_id sdhci_arasan_of_match[] = { .compatible = "intel,keembay-sdhci-5.1-sdio", .data = &intel_keembay_sdio_data, }, + { + .compatible = "intel,thunderbay-sdhci-5.1", + .data = &sdhci_arasan_thunderbay_data, + }, /* Generic compatible below here */ { .compatible = "arasan,sdhci-8.9a", @@ -1582,7 +1608,8 @@ static int sdhci_arasan_probe(struct platform_device *pdev) if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") || of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") || - of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) { + of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio") || + of_device_is_compatible(np, "intel,thunderbay-sdhci-5.1")) { sdhci_arasan_update_clockmultiplier(host, 0x0); sdhci_arasan_update_support64b(host, 0x0); From patchwork Sun Aug 29 18:24:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "A, Rashmi" X-Patchwork-Id: 504194 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BBB8C432BE for ; Sun, 29 Aug 2021 18:25:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2EF6A6023D for ; Sun, 29 Aug 2021 18:25:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235868AbhH2SZ4 (ORCPT ); Sun, 29 Aug 2021 14:25:56 -0400 Received: from mga12.intel.com ([192.55.52.136]:63344 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230010AbhH2SZz (ORCPT ); Sun, 29 Aug 2021 14:25:55 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10091"; a="197736758" X-IronPort-AV: E=Sophos;i="5.84,361,1620716400"; d="scan'208";a="197736758" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Aug 2021 11:25:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,361,1620716400"; d="scan'208";a="445519103" Received: from coresw01.iind.intel.com ([10.106.46.194]) by orsmga002.jf.intel.com with ESMTP; 29 Aug 2021 11:24:59 -0700 From: rashmi.a@intel.com To: michal.simek@xilinx.com, ulf.hansson@linaro.org, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kishon@ti.com, vkoul@kernel.org, andriy.shevchenko@linux.intel.com, linux-phy@lists.infradead.org Cc: mgross@linux.intel.com, kris.pan@linux.intel.com, furong.zhou@intel.com, mallikarjunappa.sangannavar@intel.com, adrian.hunter@intel.com, mahesh.r.vaidya@intel.com, nandhini.srikandan@intel.com, rashmi.a@intel.com Subject: [PATCH v2 3/4] dt-bindings: phy: intel: Add Thunder Bay eMMC PHY bindings Date: Sun, 29 Aug 2021 23:54:42 +0530 Message-Id: <20210829182443.30802-4-rashmi.a@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210829182443.30802-1-rashmi.a@intel.com> References: <20210829182443.30802-1-rashmi.a@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Rashmi A Binding description for Intel Thunder Bay eMMC PHY. Added the newly introduced files into MAINTAINERS file-list Signed-off-by: Rashmi A --- .../phy/intel,phy-thunderbay-emmc.yaml | 46 +++++++++++++++++++ MAINTAINERS | 7 +++ 2 files changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/intel,phy-thunderbay-emmc.yaml diff --git a/Documentation/devicetree/bindings/phy/intel,phy-thunderbay-emmc.yaml b/Documentation/devicetree/bindings/phy/intel,phy-thunderbay-emmc.yaml new file mode 100644 index 000000000000..34bdb5c4cae8 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/intel,phy-thunderbay-emmc.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/intel,phy-thunderbay-emmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Thunder Bay eMMC PHY bindings + +maintainers: + - Srikandan Nandhini + +properties: + compatible: + const: intel,thunderbay-emmc-phy + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: emmcclk + +required: + - "#phy-cells" + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + mmc_phy@80440800 { + #phy-cells = <0x0>; + compatible = "intel,thunderbay-emmc-phy"; + status = "okay"; + reg = <0x80440800 0x100>; + clocks = <&emmc>; + clock-names = "emmcclk"; + }; diff --git a/MAINTAINERS b/MAINTAINERS index bd7aff0c120f..44533319c900 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9278,6 +9278,13 @@ F: drivers/crypto/keembay/keembay-ocs-hcu-core.c F: drivers/crypto/keembay/ocs-hcu.c F: drivers/crypto/keembay/ocs-hcu.h +INTEL THUNDER BAY EMMC PHY DRIVER +M: Nandhini Srikandan +M: Rashmi A +S: Maintained +F: Documentation/devicetree/bindings/phy/intel,phy-thunderbay-emmc.yaml +F: drivers/phy/intel/phy-intel-thunderbay-emmc.c + INTEL MANAGEMENT ENGINE (mei) M: Tomas Winkler L: linux-kernel@vger.kernel.org