From patchwork Fri Aug 27 01:34:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 503901 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D354CC4320A for ; Fri, 27 Aug 2021 01:37:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B9FA960FD7 for ; Fri, 27 Aug 2021 01:37:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243962AbhH0Bip (ORCPT ); Thu, 26 Aug 2021 21:38:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243942AbhH0Bip (ORCPT ); Thu, 26 Aug 2021 21:38:45 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBA65C0613C1; Thu, 26 Aug 2021 18:37:56 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id x27so10991639lfu.5; Thu, 26 Aug 2021 18:37:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mNDPFfJoz12hFjDc4vGNuTAE2kgagxC+anlHBzhNgsQ=; b=tsiC4xKXBeIsfvwuKpWI/WiJvKSXZ/XfBwPt/3wYfrcKOWhxsEX2EINvFbfLNA9r1P 21qBc/o7l3Zh3lmITdU9Mkj4p7CfhtBlc0phouJmD3nH/w+cTiVU8HkJX6RYSphEv6uW ELXig5fiPpAJYHrk/aO6oKa/GgSZOq+RfA+mV/HYA1lAgy/VsxzBj/phNSSwqudtmH3F 6sDa4D6dx0qE/rtgkGtqz+nPRJOSgVqrEjivpFXv3Fknb5jwYfHyOx1xmXTxwk3Ep6li 3XYlP0fSAdZsixFe5+kOxCewUrdQ+hZIRkcKg3cIiY+YocZIC3tt+Mkp3B6S5346JHWN JOYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mNDPFfJoz12hFjDc4vGNuTAE2kgagxC+anlHBzhNgsQ=; b=qoqmEjjny1o8RMo64b+RHT94eHS/ABgKsrL0MLqqIIcz0ypswTkekf1p3klPQvlIoS kxeVppsdsXr+7IDvkM+IsD+4kMjCFsY15nxuVTRxwzCzsHj5iDSfNOPun5NWw7fGAAc3 SavpcYqXB3APxP7Mf3pTZZP6jsF+T9tKyw+X3AIwLChj8I83WrRZrSmbXXizjamXCI7V 6/U4FDQtirPltJBUE+T/vNYe2S6nBNI+NYs6EByucmtj3A/PglALdRzUiysd6TpyEl3D y7Ebp3Q3mQnlJesBCf4SZIodc+Yi2FhHm4QVSOA/wp6Q2AihSaVyuftZDS4pnfcPpoaK jC/Q== X-Gm-Message-State: AOAM530/xkWG08Va3So9g1AAgF/PUplSQYDALXy14ftNFKWmyGbxGYzC JextG7espYOMpeNPgy2TjOepbebeG08= X-Google-Smtp-Source: ABdhPJwzpjsWEmQfij6d+BF6RWlYMJi3ECUYnQE34njtgRn8H0T4PpitRelV4QV1Ml5lftzoswvsFw== X-Received: by 2002:ac2:562f:: with SMTP id b15mr1651077lff.604.1630028275255; Thu, 26 Aug 2021 18:37:55 -0700 (PDT) Received: from localhost.localdomain (94-29-17-251.dynamic.spd-mgts.ru. [94.29.17.251]) by smtp.gmail.com with ESMTPSA id y3sm494289lfa.240.2021.08.26.18.37.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 18:37:55 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Ulf Hansson , "Rafael J. Wysocki" , Kevin Hilman , Viresh Kumar , Stephen Boyd , Nishanth Menon Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v9 1/8] opp: Add dev_pm_opp_from_clk_rate() Date: Fri, 27 Aug 2021 04:34:08 +0300 Message-Id: <20210827013415.24027-2-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210827013415.24027-1-digetx@gmail.com> References: <20210827013415.24027-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add dev_pm_opp_from_clk_rate() helper that returns OPP corresponding to the current clock rate of a device. Signed-off-by: Dmitry Osipenko --- drivers/opp/core.c | 42 +++++++++++++++++++++++++++++++++++++++--- include/linux/pm_opp.h | 6 ++++++ 2 files changed, 45 insertions(+), 3 deletions(-) diff --git a/drivers/opp/core.c b/drivers/opp/core.c index 04b4691a8aac..fae5267f5218 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -939,7 +939,8 @@ static int _set_required_opps(struct device *dev, return ret; } -static void _find_current_opp(struct device *dev, struct opp_table *opp_table) +static struct dev_pm_opp * +_find_current_opp(struct device *dev, struct opp_table *opp_table) { struct dev_pm_opp *opp = ERR_PTR(-ENODEV); unsigned long freq; @@ -961,7 +962,7 @@ static void _find_current_opp(struct device *dev, struct opp_table *opp_table) mutex_unlock(&opp_table->lock); } - opp_table->current_opp = opp; + return opp; } static int _disable_opp_table(struct device *dev, struct opp_table *opp_table) @@ -1003,7 +1004,7 @@ static int _set_opp(struct device *dev, struct opp_table *opp_table, /* Find the currently set OPP if we don't know already */ if (unlikely(!opp_table->current_opp)) - _find_current_opp(dev, opp_table); + opp_table->current_opp = _find_current_opp(dev, opp_table); old_opp = opp_table->current_opp; @@ -2931,3 +2932,38 @@ int dev_pm_opp_sync_regulators(struct device *dev) return ret; } EXPORT_SYMBOL_GPL(dev_pm_opp_sync_regulators); + +/** + * dev_pm_opp_from_clk_rate() - Get OPP from current clock rate + * @dev: device for which we do this operation + * + * Get OPP which corresponds to the current clock rate of a device. + * + * Return: pointer to 'struct dev_pm_opp' on success and errorno otherwise. + */ +struct dev_pm_opp *dev_pm_opp_from_clk_rate(struct device *dev) +{ + struct dev_pm_opp *opp = ERR_PTR(-ENOENT); + struct opp_table *opp_table; + unsigned long freq; + + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) + return ERR_CAST(opp_table); + + if (IS_ERR(opp_table->clk)) { + opp = ERR_CAST(opp_table->clk); + goto put_table; + } + + if (opp_table->clk) { + freq = clk_get_rate(opp_table->clk); + opp = _find_freq_ceil(opp_table, &freq); + } +put_table: + /* Drop reference taken by _find_opp_table() */ + dev_pm_opp_put_opp_table(opp_table); + + return opp; +} +EXPORT_SYMBOL_GPL(dev_pm_opp_from_clk_rate); diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h index 84150a22fd7c..57e75144dd88 100644 --- a/include/linux/pm_opp.h +++ b/include/linux/pm_opp.h @@ -168,6 +168,7 @@ int dev_pm_opp_get_sharing_cpus(struct device *cpu_dev, struct cpumask *cpumask) void dev_pm_opp_remove_table(struct device *dev); void dev_pm_opp_cpumask_remove_table(const struct cpumask *cpumask); int dev_pm_opp_sync_regulators(struct device *dev); +struct dev_pm_opp *dev_pm_opp_from_clk_rate(struct device *dev); #else static inline struct opp_table *dev_pm_opp_get_opp_table(struct device *dev) { @@ -434,6 +435,11 @@ static inline int dev_pm_opp_sync_regulators(struct device *dev) return -EOPNOTSUPP; } +static struct inline dev_pm_opp *dev_pm_opp_from_clk_rate(struct device *dev) +{ + return ERR_PTR(-EOPNOTSUPP); +} + #endif /* CONFIG_PM_OPP */ #if defined(CONFIG_PM_OPP) && defined(CONFIG_OF) From patchwork Fri Aug 27 01:34:09 2021 Content-Type: text/plain; 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[94.29.17.251]) by smtp.gmail.com with ESMTPSA id y3sm494289lfa.240.2021.08.26.18.37.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 18:37:55 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Ulf Hansson , "Rafael J. Wysocki" , Kevin Hilman , Viresh Kumar , Stephen Boyd , Nishanth Menon Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v9 2/8] opp: Allow dev_pm_opp_set_clkname() to replace released clock Date: Fri, 27 Aug 2021 04:34:09 +0300 Message-Id: <20210827013415.24027-3-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210827013415.24027-1-digetx@gmail.com> References: <20210827013415.24027-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The opp_table->clk is set to error once clock is released by dev_pm_opp_put_clkname(). This doesn't allow to set clock again, until OPP table is re-created from scratch. Check opp_table->clk for both NULL and ERR_PTR to allow clock replacement. This is needed now by NVIDIA Tegra 3d driver for initializing performance state of multiple power domains, where PD driver sets and unsets OPP table clock while OPP table reference is held outside of PD. Signed-off-by: Dmitry Osipenko --- drivers/opp/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/opp/core.c b/drivers/opp/core.c index fae5267f5218..e26da1d4d6be 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -2136,7 +2136,7 @@ struct opp_table *dev_pm_opp_set_clkname(struct device *dev, const char *name) } /* clk shouldn't be initialized at this point */ - if (WARN_ON(opp_table->clk)) { + if (WARN_ON(!IS_ERR_OR_NULL(opp_table->clk))) { ret = -EBUSY; goto err; } From patchwork Fri Aug 27 01:34:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 503900 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EAF4C25AE9 for ; Fri, 27 Aug 2021 01:38:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8A5F460FD8 for ; Fri, 27 Aug 2021 01:38:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243990AbhH0Bir (ORCPT ); Thu, 26 Aug 2021 21:38:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243979AbhH0Biq (ORCPT ); Thu, 26 Aug 2021 21:38:46 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20DE2C061757; Thu, 26 Aug 2021 18:37:58 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id bq28so10938959lfb.7; Thu, 26 Aug 2021 18:37:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DqOLBs3Nwyu81nR7iG6dy0Zgt3vhXrekmHkbrh0BHsc=; b=AXFhQ7PtFQcCfglLz4K5e3Z12xgItnECaCKjR31sF97ooC4qWRhHhIf1sZEo/k++K0 +x4lJlpTWGlncypKT9nipNZ90fk3DzbnZ3GTD5HujO/S1wTzbITB5NojUlgyd9YgYUCG chrgvRsSuNO/sDrXgTy36poq1FsdjV5GPc+Ov8PnrbBVdPHonFmmui48yq5Xfmp6fLUW L9gVMJ7LWZS+ExqyvpAqZgN/jv75Cm9LJGu5dOKdOPIEANdXNkvnIpXRZX66IOt8ep2u mG0ry9HFTYH0nYs42JZNepQOJ5OnufLTeKvzrwYABey5+FdtOUgYel/1PoP3fR2CPFGC Kt9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DqOLBs3Nwyu81nR7iG6dy0Zgt3vhXrekmHkbrh0BHsc=; b=SgGFNEx1ETNh2SuJhbAdqW18tldmI19BwHxGNL7fUSRRPzV9ACIH/FneAZ++lzSlTV t283vBStgoDpZGKi+Dupw7YFWwzy0QtMCrXlXe9iP0H6JensPoKrIGTv67UE62AWWXy3 +g02clLE+Wnlqov8+4c+Znx9s+lYi6Fl07QBrOHdam5Ic0G4LwtN3LPklqBTv/0v2T6W d0opXNL/a8i0uEW8sRVr0ttyr4dw/Q6dyWP3EjH1cv3f/7bwxeVy6A9kA0o+PrNpYh79 Qk+osm8Po0zFmqRcP98QMOY+vFwCeVe9D4O0aTbgYdJ213MAKnO0YO/Ez3/lXMqEdCTF OyVw== X-Gm-Message-State: AOAM533XYCSF4gcXknpMP9tmwscTayl+BsnAeSkx5CHKmePP7ng+FAkT ORvIUbUIPYhNxiOMmTu5Ldc= X-Google-Smtp-Source: ABdhPJzrovdEiZXHdZ3lJ/SUptA05WOZqAu9/vuHUcdKVVyHj54n8AMOgirYyNgJ5Xr8HItW7a0WXA== X-Received: by 2002:a05:6512:3d13:: with SMTP id d19mr4621658lfv.607.1630028276540; Thu, 26 Aug 2021 18:37:56 -0700 (PDT) Received: from localhost.localdomain (94-29-17-251.dynamic.spd-mgts.ru. [94.29.17.251]) by smtp.gmail.com with ESMTPSA id y3sm494289lfa.240.2021.08.26.18.37.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 18:37:56 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Ulf Hansson , "Rafael J. Wysocki" , Kevin Hilman , Viresh Kumar , Stephen Boyd , Nishanth Menon Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v9 3/8] opp: Change type of dev_pm_opp_attach_genpd(names) argument Date: Fri, 27 Aug 2021 04:34:10 +0300 Message-Id: <20210827013415.24027-4-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210827013415.24027-1-digetx@gmail.com> References: <20210827013415.24027-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Elements of the 'names' array are not changed by the code, constify them for consistency. Signed-off-by: Dmitry Osipenko --- drivers/opp/core.c | 6 +++--- include/linux/pm_opp.h | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/opp/core.c b/drivers/opp/core.c index e26da1d4d6be..8d947e4f8c68 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -2349,12 +2349,12 @@ static void _opp_detach_genpd(struct opp_table *opp_table) * "required-opps" are added in DT. */ struct opp_table *dev_pm_opp_attach_genpd(struct device *dev, - const char **names, struct device ***virt_devs) + const char * const *names, struct device ***virt_devs) { struct opp_table *opp_table; struct device *virt_dev; int index = 0, ret = -EINVAL; - const char **name = names; + const char * const *name = names; opp_table = _add_opp_table(dev, false); if (IS_ERR(opp_table)) @@ -2458,7 +2458,7 @@ static void devm_pm_opp_detach_genpd(void *data) * * Return: 0 on success and errorno otherwise. */ -int devm_pm_opp_attach_genpd(struct device *dev, const char **names, +int devm_pm_opp_attach_genpd(struct device *dev, const char * const *names, struct device ***virt_devs) { struct opp_table *opp_table; diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h index 57e75144dd88..b77f2b41c30b 100644 --- a/include/linux/pm_opp.h +++ b/include/linux/pm_opp.h @@ -156,9 +156,9 @@ int devm_pm_opp_set_clkname(struct device *dev, const char *name); struct opp_table *dev_pm_opp_register_set_opp_helper(struct device *dev, int (*set_opp)(struct dev_pm_set_opp_data *data)); void dev_pm_opp_unregister_set_opp_helper(struct opp_table *opp_table); int devm_pm_opp_register_set_opp_helper(struct device *dev, int (*set_opp)(struct dev_pm_set_opp_data *data)); -struct opp_table *dev_pm_opp_attach_genpd(struct device *dev, const char **names, struct device ***virt_devs); +struct opp_table *dev_pm_opp_attach_genpd(struct device *dev, const char * const *names, struct device ***virt_devs); void dev_pm_opp_detach_genpd(struct opp_table *opp_table); -int devm_pm_opp_attach_genpd(struct device *dev, const char **names, struct device ***virt_devs); +int devm_pm_opp_attach_genpd(struct device *dev, const char * const *names, struct device ***virt_devs); struct dev_pm_opp *dev_pm_opp_xlate_required_opp(struct opp_table *src_table, struct opp_table *dst_table, struct dev_pm_opp *src_opp); int dev_pm_opp_xlate_performance_state(struct opp_table *src_table, struct opp_table *dst_table, unsigned int pstate); int dev_pm_opp_set_rate(struct device *dev, unsigned long target_freq); @@ -377,7 +377,7 @@ static inline int devm_pm_opp_set_clkname(struct device *dev, const char *name) return -EOPNOTSUPP; } -static inline struct opp_table *dev_pm_opp_attach_genpd(struct device *dev, const char **names, struct device ***virt_devs) +static inline struct opp_table *dev_pm_opp_attach_genpd(struct device *dev, const char * const *names, struct device ***virt_devs) { return ERR_PTR(-EOPNOTSUPP); } @@ -385,7 +385,7 @@ static inline struct opp_table *dev_pm_opp_attach_genpd(struct device *dev, cons static inline void dev_pm_opp_detach_genpd(struct opp_table *opp_table) {} static inline int devm_pm_opp_attach_genpd(struct device *dev, - const char **names, + const char * const *names, struct device ***virt_devs) { return -EOPNOTSUPP; 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[94.29.17.251]) by smtp.gmail.com with ESMTPSA id y3sm494289lfa.240.2021.08.26.18.37.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 18:37:56 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Ulf Hansson , "Rafael J. Wysocki" , Kevin Hilman , Viresh Kumar , Stephen Boyd , Nishanth Menon Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v9 4/8] PM: domains: Add get_performance_state() callback Date: Fri, 27 Aug 2021 04:34:11 +0300 Message-Id: <20210827013415.24027-5-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210827013415.24027-1-digetx@gmail.com> References: <20210827013415.24027-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add get_performance_state() callback that retrieves and initializes performance state of a device attached to a power domain. This removes inconsistency of the performance state with hardware state. Signed-off-by: Dmitry Osipenko --- drivers/base/power/domain.c | 32 +++++++++++++++++++++++++++++--- include/linux/pm_domain.h | 2 ++ 2 files changed, 31 insertions(+), 3 deletions(-) diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c index 3a13a942d012..8b828dcdf7f8 100644 --- a/drivers/base/power/domain.c +++ b/drivers/base/power/domain.c @@ -2700,15 +2700,41 @@ static int __genpd_dev_pm_attach(struct device *dev, struct device *base_dev, goto err; } else if (pstate > 0) { ret = dev_pm_genpd_set_performance_state(dev, pstate); - if (ret) + if (ret) { + dev_err(dev, "failed to set required performance state for power-domain %s: %d\n", + pd->name, ret); goto err; + } dev_gpd_data(dev)->default_pstate = pstate; } + + if (pd->get_performance_state && !dev_gpd_data(dev)->default_pstate) { + bool dev_suspended = false; + + ret = pd->get_performance_state(pd, base_dev, &dev_suspended); + if (ret < 0) { + dev_err(dev, "failed to get performance state for power-domain %s: %d\n", + pd->name, ret); + goto err; + } + + pstate = ret; + + if (dev_suspended) { + dev_gpd_data(dev)->rpm_pstate = pstate; + } else if (pstate > 0) { + ret = dev_pm_genpd_set_performance_state(dev, pstate); + if (ret) { + dev_err(dev, "failed to set required performance state for power-domain %s: %d\n", + pd->name, ret); + goto err; + } + } + } + return 1; err: - dev_err(dev, "failed to set required performance state for power-domain %s: %d\n", - pd->name, ret); genpd_remove_device(pd, dev); return ret; } diff --git a/include/linux/pm_domain.h b/include/linux/pm_domain.h index 67017c9390c8..4f78b31791ae 100644 --- a/include/linux/pm_domain.h +++ b/include/linux/pm_domain.h @@ -133,6 +133,8 @@ struct generic_pm_domain { struct dev_pm_opp *opp); int (*set_performance_state)(struct generic_pm_domain *genpd, unsigned int state); + int (*get_performance_state)(struct generic_pm_domain *genpd, + struct device *dev, bool *dev_suspended); struct gpd_dev_ops dev_ops; s64 max_off_time_ns; /* Maximum allowed "suspended" time. */ ktime_t next_wakeup; /* Maintained by the domain governor */ From patchwork Fri Aug 27 01:34:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 503898 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84CA9C4320A for ; Fri, 27 Aug 2021 01:38:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6B7AC60FD8 for ; Fri, 27 Aug 2021 01:38:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244018AbhH0Biu (ORCPT ); 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[94.29.17.251]) by smtp.gmail.com with ESMTPSA id y3sm494289lfa.240.2021.08.26.18.37.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 18:37:57 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Ulf Hansson , "Rafael J. Wysocki" , Kevin Hilman , Viresh Kumar , Stephen Boyd , Nishanth Menon Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v9 5/8] soc/tegra: pmc: Implement get_performance_state() callback Date: Fri, 27 Aug 2021 04:34:12 +0300 Message-Id: <20210827013415.24027-6-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210827013415.24027-1-digetx@gmail.com> References: <20210827013415.24027-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Implement get_performance_state() callback of power domains to initialize theirs performance state in accordance to the clock rate of attached device. Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/pmc.c | 86 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 50091c4ec948..ea552f7ed922 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -505,6 +505,90 @@ static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value, writel(value, pmc->scratch + offset); } +static const char * const tegra_pd_no_perf_compats[] = { + "nvidia,tegra20-sclk", + "nvidia,tegra30-sclk", + "nvidia,tegra30-pllc", + "nvidia,tegra30-plle", + "nvidia,tegra30-pllm", + "nvidia,tegra20-dc", + "nvidia,tegra30-dc", + "nvidia,tegra20-emc", + "nvidia,tegra30-emc", + NULL, +}; + +static int tegra_pmc_pd_get_performance_state(struct generic_pm_domain *genpd, + struct device *dev, + bool *dev_suspended) +{ + struct opp_table *hw_opp_table, *clk_opp_table; + struct dev_pm_opp *opp; + u32 hw_version; + int ret; + + /* + * The EMC devices are a special case because we have a protection + * from non-EMC drivers getting clock handle before EMC driver is + * fully initialized. The goal of the protection is to prevent + * devfreq driver from getting failures if it will try to change + * EMC clock rate until clock is fully initialized. The EMC drivers + * will initialize the performance state by themselves. + * + * Display controller also is a special case because only controller + * driver could get the clock rate based on configuration of internal + * divider. + * + * Clock driver uses its own state syncing. + */ + if (of_device_compatible_match(dev->of_node, tegra_pd_no_perf_compats)) + return 0; + + if (of_machine_is_compatible("nvidia,tegra20")) + hw_version = BIT(tegra_sku_info.soc_process_id); + else + hw_version = BIT(tegra_sku_info.soc_speedo_id); + + hw_opp_table = dev_pm_opp_set_supported_hw(dev, &hw_version, 1); + if (IS_ERR(hw_opp_table)) { + dev_err(dev, "failed to set OPP supported HW: %pe\n", + hw_opp_table); + return PTR_ERR(hw_opp_table); + } + + clk_opp_table = dev_pm_opp_set_clkname(dev, NULL); + if (IS_ERR(clk_opp_table)) { + dev_err(dev, "failed to set OPP clk: %pe\n", clk_opp_table); + ret = PTR_ERR(clk_opp_table); + goto put_hw; + } + + ret = devm_pm_opp_of_add_table(dev); + if (ret) { + dev_err(dev, "failed to add OPP table: %d\n", ret); + goto put_clk; + } + + opp = dev_pm_opp_from_clk_rate(dev); + if (IS_ERR(opp)) { + dev_err(dev, "failed to get current OPP: %pe\n", opp); + ret = PTR_ERR(opp); + } else { + ret = dev_pm_opp_get_required_pstate(opp, 0); + dev_pm_opp_put(opp); + } + + *dev_suspended = true; + + dev_pm_opp_of_remove_table(dev); +put_clk: + dev_pm_opp_put_clkname(clk_opp_table); +put_hw: + dev_pm_opp_put_supported_hw(hw_opp_table); + + return ret; +} + /* * TODO Figure out a way to call this with the struct tegra_pmc * passed in. * This currently doesn't work because readx_poll_timeout() can only operate @@ -1237,6 +1321,7 @@ static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) pg->id = id; pg->genpd.name = np->name; + pg->genpd.get_performance_state = tegra_pmc_pd_get_performance_state; pg->genpd.power_off = tegra_genpd_power_off; pg->genpd.power_on = tegra_genpd_power_on; pg->pmc = pmc; @@ -1353,6 +1438,7 @@ static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np) return -ENOMEM; genpd->name = np->name; + genpd->get_performance_state = tegra_pmc_pd_get_performance_state; genpd->set_performance_state = tegra_pmc_core_pd_set_performance_state; genpd->opp_to_performance_state = tegra_pmc_core_pd_opp_to_performance_state; From patchwork Fri Aug 27 01:34:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 503899 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ACCF8C00143 for ; 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[94.29.17.251]) by smtp.gmail.com with ESMTPSA id y3sm494289lfa.240.2021.08.26.18.37.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 18:37:58 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Ulf Hansson , "Rafael J. Wysocki" , Kevin Hilman , Viresh Kumar , Stephen Boyd , Nishanth Menon Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v9 6/8] soc/tegra: Add devm_tegra_core_dev_init_opp_table_simple() Date: Fri, 27 Aug 2021 04:34:13 +0300 Message-Id: <20210827013415.24027-7-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210827013415.24027-1-digetx@gmail.com> References: <20210827013415.24027-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Only couple drivers need to get the -ENODEV error code and explicitly initialize the performance state. Add new helper that allows to avoid the extra boilerplate code in majority of drivers. Signed-off-by: Dmitry Osipenko --- include/soc/tegra/common.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/soc/tegra/common.h b/include/soc/tegra/common.h index af41ad80ec21..265ad90e45a2 100644 --- a/include/soc/tegra/common.h +++ b/include/soc/tegra/common.h @@ -39,4 +39,17 @@ devm_tegra_core_dev_init_opp_table(struct device *dev, } #endif +static inline int +devm_tegra_core_dev_init_opp_table_simple(struct device *dev) +{ + struct tegra_core_opp_params params = {}; + int err; + + err = devm_tegra_core_dev_init_opp_table(dev, ¶ms); + if (err != -ENODEV) + return err; + + return 0; +} + #endif /* __SOC_TEGRA_COMMON_H__ */ From patchwork Fri Aug 27 01:34:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 503562 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74E3BC41537 for ; Fri, 27 Aug 2021 01:38:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 585E560F4F for ; Fri, 27 Aug 2021 01:38:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243997AbhH0Bix (ORCPT ); Thu, 26 Aug 2021 21:38:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43056 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243999AbhH0Bit (ORCPT ); Thu, 26 Aug 2021 21:38:49 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13BD2C0613CF; Thu, 26 Aug 2021 18:38:01 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id m28so10939033lfj.6; Thu, 26 Aug 2021 18:38:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yDP03amDwCEY6IiivIbDG+60+C+xV/Pv6sR1LEywSYo=; b=KD9YiLyI59N6auovPD9EdqECBN8+LG+i4emXwai8UV2vfa71wjQcqWMU1LGGppM4TA kOQTl7LG3rjCi5fAIo6Z/T/qDkoofGwxkYVQzCdEbmEwF8ObgqZkXTosKH6UDE1ocF83 XtGDL0yCVVXZm8yz2vXjfaNeD7321FEVaaF7MmtVj1V5i55/rKQ4x+OamlSHXyLfd/aA /EMV44ML829jByGmcbdy6sDd/Ql7sd7hFcXl3Yvn2umHRx50eU1QMKHiqrrk+be1hk4T huC8yZfrO6uk5HCSTv82M6nhc75IqQrex9AEaP7PeVFl6Bd3FNsVZ36EnwUg7Eer4ODS 5I3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yDP03amDwCEY6IiivIbDG+60+C+xV/Pv6sR1LEywSYo=; b=qwqTakq27D4FerUFg16ZEaKgDCLCiO59vJqjYQyiQ2bsfP3SJ5bGVAci7XWNGlNRRa q6d+uCVhig5O9cI6E9F2phd6E0O5eHamGPGRhVQ3WvqxQWSLJsLMkuVjbjcJhVfBnHis C0BVKsv471rezKIp3l67fgkt7XNeOBuQJBak4w0HpJ+jaIqPkOcD+IwTSGeMNio3GpOj cZmZsMMIQMCcSarKdKAMvzHErv3abzA9GRQbYzPrfi534AvDLjV4zlImgXlqp+oQhQBl IyCDb8hqTWqW/MvVztbsdh7ld816RARLbKo3cOA72o2XAZN198+bG5qqxta6BgUfq+8V aoDg== X-Gm-Message-State: AOAM533I/0Ez1TA1Wyo6awfCyIWRc+/qmyugLg1OiY0mOrXS9AR+AnvU UmA2IZnudMEZ4uhH8x2nqOA= X-Google-Smtp-Source: ABdhPJwIbBLsghNnVtkXQivhW6qOj3L046ZS0fPLnhAv7OSgju+ZxjHhCHr6g0fVcsrjKbelLKvkwQ== X-Received: by 2002:a05:6512:ac9:: with SMTP id n9mr4703705lfu.635.1630028279416; Thu, 26 Aug 2021 18:37:59 -0700 (PDT) Received: from localhost.localdomain (94-29-17-251.dynamic.spd-mgts.ru. [94.29.17.251]) by smtp.gmail.com with ESMTPSA id y3sm494289lfa.240.2021.08.26.18.37.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 18:37:59 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Ulf Hansson , "Rafael J. Wysocki" , Kevin Hilman , Viresh Kumar , Stephen Boyd , Nishanth Menon Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v9 7/8] gpu: host1x: Add host1x_channel_stop() Date: Fri, 27 Aug 2021 04:34:14 +0300 Message-Id: <20210827013415.24027-8-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210827013415.24027-1-digetx@gmail.com> References: <20210827013415.24027-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add host1x_channel_stop() which waits till channel becomes idle and then stops the channel hardware. This is needed for supporting suspend/resume by host1x drivers since the hardware state is lost after power-gating, thus the channel needs to be stopped before client enters into suspend. Tested-by: Peter Geis # Ouya T30 Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar # Ouya T30 Signed-off-by: Dmitry Osipenko --- drivers/gpu/host1x/channel.c | 8 ++++++++ include/linux/host1x.h | 1 + 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/host1x/channel.c b/drivers/gpu/host1x/channel.c index 4cd212bb570d..2a9a3a8d5931 100644 --- a/drivers/gpu/host1x/channel.c +++ b/drivers/gpu/host1x/channel.c @@ -75,6 +75,14 @@ struct host1x_channel *host1x_channel_get_index(struct host1x *host, return ch; } +void host1x_channel_stop(struct host1x_channel *channel) +{ + struct host1x *host = dev_get_drvdata(channel->dev->parent); + + host1x_hw_cdma_stop(host, &channel->cdma); +} +EXPORT_SYMBOL(host1x_channel_stop); + static void release_channel(struct kref *kref) { struct host1x_channel *channel = diff --git a/include/linux/host1x.h b/include/linux/host1x.h index 7bccf589aba7..66473b5be0af 100644 --- a/include/linux/host1x.h +++ b/include/linux/host1x.h @@ -181,6 +181,7 @@ struct host1x_job; struct host1x_channel *host1x_channel_request(struct host1x_client *client); struct host1x_channel *host1x_channel_get(struct host1x_channel *channel); +void host1x_channel_stop(struct host1x_channel *channel); void host1x_channel_put(struct host1x_channel *channel); int host1x_job_submit(struct host1x_job *job); From patchwork Fri Aug 27 01:34:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 503561 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C50DC25AEC for ; Fri, 27 Aug 2021 01:38:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 59D2F60FDA for ; Fri, 27 Aug 2021 01:38:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243979AbhH0Bix (ORCPT ); Thu, 26 Aug 2021 21:38:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43062 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244016AbhH0Biu (ORCPT ); Thu, 26 Aug 2021 21:38:50 -0400 Received: from mail-lj1-x230.google.com (mail-lj1-x230.google.com [IPv6:2a00:1450:4864:20::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C6EEDC0613D9; Thu, 26 Aug 2021 18:38:01 -0700 (PDT) Received: by mail-lj1-x230.google.com with SMTP id q21so8577535ljj.6; Thu, 26 Aug 2021 18:38:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2xnbiR8WOpQFvteKUmC+0aA2JAMzFJwrKrlTihtzzZw=; b=sEA7/5OrehzioBZBTc4S+MQ3rwVn/CjevJEBIB8YXmwkkc6aVlWbqyIbm/l195H3TC of6XngCmx4LmolqMSuSDq9lh+kboAoxttXNwSSmhhKJjv0EKQfUSgRZm7aPCYj5RsOcN giTGbJIj0KLot4lHVSjb1Zodztp4DjpGIr4YFymixuC9f0Hur5fVp2h7Bgi2OY3CFBlF CJg5RxJf3HoJyiqyC36lhvw+hzeGK/xXZSaEhj/nrwlhxaBQLufC1xy6gS8JNiPceDMX qWWa44c9/RJLgqNWV3TWBqS0+nPuePMVeNRaz191iDGZeLV21+XrTE/Q3mTf3Xg1czuJ +qAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2xnbiR8WOpQFvteKUmC+0aA2JAMzFJwrKrlTihtzzZw=; b=SxypJST7XzH9sgK2SNuTCT/OD7MS1gKOLBKQi+KI6gDVG/IQvrYrlv1PGm2XbYKGMW fk/0kBXsjrndvoOARe/gOY+I90w0omBZA3tObb3/Zb8KKPzg9awZ3TOz/oC6BAYWHp2E suDp8CybAX3uJ9GSgEOgzHcEG95TiAmMGYOtFqrlvRnyHGaENdp2jBmni0aLbjWsEhkA 0cP2K+BJtK/U6ASTuR7uD1LrMmdEQ9X3pPksAM9wO94mV9Y8JloUFF2SOSmsXW0Wt9Hc zhPrI6LZlL+3k3FJCaY23XeepSlAiRaGzs7DnKzRqIMNhAC3wOfC5UFJg1ujKnIqw2ov +rFw== X-Gm-Message-State: AOAM530bUueLPAtUY1hvJeJFyuM+E2LGiyuB1SGd8tqdNff7yGHbreqq tVkSXD8yrH3v27xNH5TrmKo= X-Google-Smtp-Source: ABdhPJx7SQDrw5X2iYEeD9j3nnOSXMdpPVZQtyOKYkWv1VCs4syWMb1gkgCRCvxhGgjqgwP+3+Vg0A== X-Received: by 2002:a2e:93c3:: with SMTP id p3mr5504590ljh.226.1630028280136; Thu, 26 Aug 2021 18:38:00 -0700 (PDT) Received: from localhost.localdomain (94-29-17-251.dynamic.spd-mgts.ru. [94.29.17.251]) by smtp.gmail.com with ESMTPSA id y3sm494289lfa.240.2021.08.26.18.37.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 18:37:59 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Ulf Hansson , "Rafael J. Wysocki" , Kevin Hilman , Viresh Kumar , Stephen Boyd , Nishanth Menon Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v9 8/8] drm/tegra: gr3d: Support generic power domain and runtime PM Date: Fri, 27 Aug 2021 04:34:15 +0300 Message-Id: <20210827013415.24027-9-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210827013415.24027-1-digetx@gmail.com> References: <20210827013415.24027-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add power management and support generic power domains. Tested-by: Peter Geis # Ouya T30 Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar # Ouya T30 Signed-off-by: Dmitry Osipenko --- drivers/gpu/drm/tegra/gr3d.c | 384 ++++++++++++++++++++++++++++++----- 1 file changed, 330 insertions(+), 54 deletions(-) diff --git a/drivers/gpu/drm/tegra/gr3d.c b/drivers/gpu/drm/tegra/gr3d.c index 24442ade0da3..545eb4005a96 100644 --- a/drivers/gpu/drm/tegra/gr3d.c +++ b/drivers/gpu/drm/tegra/gr3d.c @@ -5,32 +5,47 @@ */ #include +#include #include #include #include #include #include +#include +#include +#include #include +#include #include #include "drm.h" #include "gem.h" #include "gr3d.h" +enum { + RST_MC, + RST_GR3D, + RST_MC2, + RST_GR3D2, + RST_GR3D_MAX, +}; + struct gr3d_soc { unsigned int version; + unsigned int num_clocks; + unsigned int num_resets; }; struct gr3d { struct tegra_drm_client client; struct host1x_channel *channel; - struct clk *clk_secondary; - struct clk *clk; - struct reset_control *rst_secondary; - struct reset_control *rst; const struct gr3d_soc *soc; + struct clk_bulk_data *clocks; + unsigned int nclocks; + struct reset_control_bulk_data resets[RST_GR3D_MAX]; + unsigned int nresets; DECLARE_BITMAP(addr_regs, GR3D_NUM_REGS); }; @@ -109,16 +124,24 @@ static int gr3d_open_channel(struct tegra_drm_client *client, struct tegra_drm_context *context) { struct gr3d *gr3d = to_gr3d(client); + int err; context->channel = host1x_channel_get(gr3d->channel); if (!context->channel) return -ENOMEM; + err = pm_runtime_resume_and_get(client->base.dev); + if (err) { + host1x_channel_put(context->channel); + return err; + } + return 0; } static void gr3d_close_channel(struct tegra_drm_context *context) { + pm_runtime_put_sync(context->client->base.dev); host1x_channel_put(context->channel); } @@ -155,14 +178,20 @@ static const struct tegra_drm_client_ops gr3d_ops = { static const struct gr3d_soc tegra20_gr3d_soc = { .version = 0x20, + .num_clocks = 1, + .num_resets = 2, }; static const struct gr3d_soc tegra30_gr3d_soc = { .version = 0x30, + .num_clocks = 2, + .num_resets = 4, }; static const struct gr3d_soc tegra114_gr3d_soc = { .version = 0x35, + .num_clocks = 1, + .num_resets = 2, }; static const struct of_device_id tegra_gr3d_match[] = { @@ -278,9 +307,211 @@ static const u32 gr3d_addr_regs[] = { GR3D_GLOBAL_SAMP23SURFADDR(15), }; +static int gr3d_power_up_legacy_domain(struct device *dev, const char *name, + unsigned int id) +{ + struct gr3d *gr3d = dev_get_drvdata(dev); + struct reset_control *reset; + struct clk *clk; + unsigned int i; + int err; + + /* + * Tegra20 device-tree doesn't specify 3d clock name and there is only + * one clock for Tegra20. Tegra30+ device-trees always specified names + * for the clocks. + */ + if (gr3d->nclocks == 1) { + if (id == TEGRA_POWERGATE_3D1) + return 0; + + clk = gr3d->clocks[0].clk; + } else { + for (i = 0; i < gr3d->nclocks; i++) { + if (WARN_ON(!gr3d->clocks[i].id)) + continue; + + if (!strcmp(gr3d->clocks[i].id, name)) { + clk = gr3d->clocks[i].clk; + break; + } + } + + if (WARN_ON(i == gr3d->nclocks)) + return -EINVAL; + } + + /* + * We use array of resets, which includes MC resets, and MC + * reset shouldn't be asserted while hardware is gated because + * MC flushing will fail for gated hardware. Hence for legacy + * PD we request the individual reset separately. + */ + reset = reset_control_get_exclusive_released(dev, name); + if (IS_ERR(reset)) + return PTR_ERR(reset); + + err = reset_control_acquire(reset); + if (err) { + dev_err(dev, "failed to acquire %s reset: %d\n", name, err); + } else { + err = tegra_powergate_sequence_power_up(id, clk, reset); + reset_control_release(reset); + } + + reset_control_put(reset); + if (err) + return err; + + /* + * tegra_powergate_sequence_power_up() leaves clocks enabled + * while GENPD not, hence keep clock-enable balanced. + */ + clk_disable_unprepare(clk); + + return 0; +} + +static void gr3d_del_link(void *link) +{ + device_link_del(link); +} + +static int gr3d_init_power(struct device *dev, struct gr3d *gr3d) +{ + static const char * const opp_genpd_names[] = { "3d0", "3d1", NULL }; + const u32 link_flags = DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME; + struct device **opp_virt_devs, *pd_dev; + struct device_link *link; + unsigned int i; + int err; + + err = of_count_phandle_with_args(dev->of_node, "power-domains", + "#power-domain-cells"); + if (err < 0) { + if (err != -ENOENT) + return err; + + /* + * Older device-trees don't use GENPD. In this case we should + * toggle power domain manually. + */ + err = gr3d_power_up_legacy_domain(dev, "3d", + TEGRA_POWERGATE_3D); + if (err) + return err; + + err = gr3d_power_up_legacy_domain(dev, "3d2", + TEGRA_POWERGATE_3D1); + if (err) + return err; + + return 0; + } + + /* + * The PM domain core automatically attaches a single power domain, + * otherwise it skips attaching completely. We have a single domain + * on Tegra20 and two domains on Tegra30+. + */ + if (dev->pm_domain) + return 0; + + err = devm_pm_opp_attach_genpd(dev, opp_genpd_names, &opp_virt_devs); + if (err) + return err; + + for (i = 0; opp_genpd_names[i]; i++) { + pd_dev = opp_virt_devs[i]; + if (!pd_dev) { + dev_err(dev, "failed to get %s power domain\n", + opp_genpd_names[i]); + return -EINVAL; + } + + link = device_link_add(dev, pd_dev, link_flags); + if (!link) { + dev_err(dev, "failed to link to %s\n", dev_name(pd_dev)); + return -EINVAL; + } + + err = devm_add_action_or_reset(dev, gr3d_del_link, link); + if (err) + return err; + } + + return 0; +} + +static int gr3d_set_opp(struct dev_pm_set_opp_data *data) +{ + struct gr3d *gr3d = dev_get_drvdata(data->dev); + unsigned int i; + int err; + + for (i = 0; i < gr3d->nclocks; i++) { + err = clk_set_rate(gr3d->clocks[i].clk, data->new_opp.rate); + if (err) { + dev_err(data->dev, "failed to set %s rate to %lu: %d\n", + gr3d->clocks[i].id, data->new_opp.rate, err); + goto restore; + } + } + + return 0; + +restore: + while (i--) + clk_set_rate(gr3d->clocks[i].clk, data->old_opp.rate); + + return err; +} + +static int gr3d_get_clocks(struct device *dev, struct gr3d *gr3d) +{ + int err; + + err = devm_clk_bulk_get_all(dev, &gr3d->clocks); + if (err < 0) { + dev_err(dev, "failed to get clock: %d\n", err); + return err; + } + gr3d->nclocks = err; + + if (gr3d->nclocks != gr3d->soc->num_clocks) { + dev_err(dev, "invalid number of clocks: %u\n", gr3d->nclocks); + return -ENOENT; + } + + return 0; +} + +static int gr3d_get_resets(struct device *dev, struct gr3d *gr3d) +{ + int err; + + gr3d->resets[RST_MC].id = "mc"; + gr3d->resets[RST_MC2].id = "mc2"; + gr3d->resets[RST_GR3D].id = "3d"; + gr3d->resets[RST_GR3D2].id = "3d2"; + gr3d->nresets = gr3d->soc->num_resets; + + err = devm_reset_control_bulk_get_optional_exclusive_released( + dev, gr3d->nresets, gr3d->resets); + if (err) { + dev_err(dev, "failed to get reset: %d\n", err); + return err; + } + + if (WARN_ON(!gr3d->resets[RST_GR3D].rstc) || + WARN_ON(!gr3d->resets[RST_GR3D2].rstc && gr3d->nresets == 4)) + return -ENOENT; + + return 0; +} + static int gr3d_probe(struct platform_device *pdev) { - struct device_node *np = pdev->dev.of_node; struct host1x_syncpt **syncpts; struct gr3d *gr3d; unsigned int i; @@ -290,56 +521,33 @@ static int gr3d_probe(struct platform_device *pdev) if (!gr3d) return -ENOMEM; + platform_set_drvdata(pdev, gr3d); + gr3d->soc = of_device_get_match_data(&pdev->dev); syncpts = devm_kzalloc(&pdev->dev, sizeof(*syncpts), GFP_KERNEL); if (!syncpts) return -ENOMEM; - gr3d->clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(gr3d->clk)) { - dev_err(&pdev->dev, "cannot get clock\n"); - return PTR_ERR(gr3d->clk); - } - - gr3d->rst = devm_reset_control_get(&pdev->dev, "3d"); - if (IS_ERR(gr3d->rst)) { - dev_err(&pdev->dev, "cannot get reset\n"); - return PTR_ERR(gr3d->rst); - } + err = gr3d_get_clocks(&pdev->dev, gr3d); + if (err) + return err; - if (of_device_is_compatible(np, "nvidia,tegra30-gr3d")) { - gr3d->clk_secondary = devm_clk_get(&pdev->dev, "3d2"); - if (IS_ERR(gr3d->clk_secondary)) { - dev_err(&pdev->dev, "cannot get secondary clock\n"); - return PTR_ERR(gr3d->clk_secondary); - } + err = gr3d_get_resets(&pdev->dev, gr3d); + if (err) + return err; - gr3d->rst_secondary = devm_reset_control_get(&pdev->dev, - "3d2"); - if (IS_ERR(gr3d->rst_secondary)) { - dev_err(&pdev->dev, "cannot get secondary reset\n"); - return PTR_ERR(gr3d->rst_secondary); - } - } + err = gr3d_init_power(&pdev->dev, gr3d); + if (err) + return err; - err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D, gr3d->clk, - gr3d->rst); - if (err < 0) { - dev_err(&pdev->dev, "failed to power up 3D unit\n"); + err = devm_pm_opp_register_set_opp_helper(&pdev->dev, gr3d_set_opp); + if (err) return err; - } - if (gr3d->clk_secondary) { - err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_3D1, - gr3d->clk_secondary, - gr3d->rst_secondary); - if (err < 0) { - dev_err(&pdev->dev, - "failed to power up secondary 3D unit\n"); - return err; - } - } + err = devm_tegra_core_dev_init_opp_table_simple(&pdev->dev); + if (err) + return err; INIT_LIST_HEAD(&gr3d->client.base.list); gr3d->client.base.ops = &gr3d_client_ops; @@ -352,20 +560,28 @@ static int gr3d_probe(struct platform_device *pdev) gr3d->client.version = gr3d->soc->version; gr3d->client.ops = &gr3d_ops; + pm_runtime_enable(&pdev->dev); + pm_runtime_use_autosuspend(&pdev->dev); + pm_runtime_set_autosuspend_delay(&pdev->dev, 200); + err = host1x_client_register(&gr3d->client.base); if (err < 0) { dev_err(&pdev->dev, "failed to register host1x client: %d\n", err); - return err; + goto disable_rpm; } /* initialize address register map */ for (i = 0; i < ARRAY_SIZE(gr3d_addr_regs); i++) set_bit(gr3d_addr_regs[i], gr3d->addr_regs); - platform_set_drvdata(pdev, gr3d); - return 0; + +disable_rpm: + pm_runtime_dont_use_autosuspend(&pdev->dev); + pm_runtime_disable(&pdev->dev); + + return err; } static int gr3d_remove(struct platform_device *pdev) @@ -380,23 +596,83 @@ static int gr3d_remove(struct platform_device *pdev) return err; } - if (gr3d->clk_secondary) { - reset_control_assert(gr3d->rst_secondary); - tegra_powergate_power_off(TEGRA_POWERGATE_3D1); - clk_disable_unprepare(gr3d->clk_secondary); + pm_runtime_dont_use_autosuspend(&pdev->dev); + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static int __maybe_unused gr3d_runtime_suspend(struct device *dev) +{ + struct gr3d *gr3d = dev_get_drvdata(dev); + int err; + + host1x_channel_stop(gr3d->channel); + + err = reset_control_bulk_assert(gr3d->nresets, gr3d->resets); + if (err) { + dev_err(dev, "failed to assert reset: %d\n", err); + return err; + } + + usleep_range(10, 20); + + /* + * Older device-trees don't specify MC resets and power-gating can't + * be done safely in that case. Hence we will keep the power ungated + * for older DTBs. For newer DTBs, GENPD will perform the power-gating. + */ + + clk_bulk_disable_unprepare(gr3d->nclocks, gr3d->clocks); + reset_control_bulk_release(gr3d->nresets, gr3d->resets); + + return 0; +} + +static int __maybe_unused gr3d_runtime_resume(struct device *dev) +{ + struct gr3d *gr3d = dev_get_drvdata(dev); + int err; + + err = reset_control_bulk_acquire(gr3d->nresets, gr3d->resets); + if (err) { + dev_err(dev, "failed to acquire reset: %d\n", err); + return err; + } + + err = clk_bulk_prepare_enable(gr3d->nclocks, gr3d->clocks); + if (err) { + dev_err(dev, "failed to enable clock: %d\n", err); + goto release_reset; } - reset_control_assert(gr3d->rst); - tegra_powergate_power_off(TEGRA_POWERGATE_3D); - clk_disable_unprepare(gr3d->clk); + err = reset_control_bulk_deassert(gr3d->nresets, gr3d->resets); + if (err) { + dev_err(dev, "failed to deassert reset: %d\n", err); + goto disable_clk; + } return 0; + +disable_clk: + clk_bulk_disable_unprepare(gr3d->nclocks, gr3d->clocks); +release_reset: + reset_control_bulk_release(gr3d->nresets, gr3d->resets); + + return err; } +static const struct dev_pm_ops tegra_gr3d_pm = { + SET_RUNTIME_PM_OPS(gr3d_runtime_suspend, gr3d_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; + struct platform_driver tegra_gr3d_driver = { .driver = { .name = "tegra-gr3d", .of_match_table = tegra_gr3d_match, + .pm = &tegra_gr3d_pm, }, .probe = gr3d_probe, .remove = gr3d_remove,