From patchwork Fri Aug 27 17:15:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Kettenis X-Patchwork-Id: 503848 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65EDAC432BE for ; Fri, 27 Aug 2021 17:15:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 45DE460FD9 for ; Fri, 27 Aug 2021 17:15:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239513AbhH0RQn (ORCPT ); Fri, 27 Aug 2021 13:16:43 -0400 Received: from lb1-smtp-cloud8.xs4all.net ([194.109.24.21]:38261 "EHLO lb1-smtp-cloud8.xs4all.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238836AbhH0RQj (ORCPT ); Fri, 27 Aug 2021 13:16:39 -0400 Received: from cust-df1d398c ([IPv6:fc0c:c1f5:9ac0:c45f:1583:5c5b:91fa:2436]) by smtp-cloud8.xs4all.net with ESMTPA id JfS3mDfw9JWNeJfSDm6c3h; Fri, 27 Aug 2021 19:15:46 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xs4all.nl; s=s2; t=1630084546; bh=dV4tRmJ5z8UQ8vCAPACt05N5ZSm5ssASld+lbfZlIJQ=; h=From:To:Subject:Date:Message-Id:MIME-Version:From:Subject; b=Ypp9ykoXUTKiwYdod2H6rRl1UFcycfJLv5ciwtTB/TKDpWdsO32/gMrmsIt4tdY4l Hzfwl6sHlhsKOSdiJNfBBJE9IaaDjH0vctjhVwAWbOaFvekIkKzvhnX/WS2GijRROD NanyG+3wzo76pBfUOVnzCO7yHBGhPAx9RS6TEXHpPJfeDDSZyu5VdDKblXQ5yaYKSd 3p4xvBJh9Cf2v6KTnNi5SAnd0gHoSil0SU41gqkj/NB2qPLkmQC1xTGa3UTFzJ1bGW PhA/TaMggkAjb9mCpnpzGtfVyLGXgZ2TD+vt+6rCdkdicFaZS6vLirauzpNY7V2/vH 2jW3RYDWXn16Q== From: Mark Kettenis To: devicetree@vger.kernel.org Cc: alyssa@rosenzweig.io, Mark Kettenis , Thomas Gleixner , Marc Zyngier , Rob Herring , Hector Martin , Bjorn Helgaas , Nicolas Saenz Julienne , Florian Fainelli , bcm-kernel-feedback-list@broadcom.com, Jim Quinlan , Daire McNamara , Saenz Julienne , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-rpi-kernel@lists.infradead.org Subject: [PATCH v4 1/4] dt-bindings: interrupt-controller: Convert MSI controller to json-schema Date: Fri, 27 Aug 2021 19:15:26 +0200 Message-Id: <20210827171534.62380-2-mark.kettenis@xs4all.nl> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210827171534.62380-1-mark.kettenis@xs4all.nl> References: <20210827171534.62380-1-mark.kettenis@xs4all.nl> MIME-Version: 1.0 X-CMAE-Envelope: MS4xfEM2JDAnX6AANU9YyG5nNUjDjBfhHMBb9vhc+ykvvD4fBFpcXLUhPgqqGN0q3CustNsvfvm5kpvwyHDaGzXDq5K6r1WFkqwTQqvpC3TZw7v+sQvO+jdl T7Q1oLXYB/cyOnhOj2j/CMkhJonw+sDUTbAK6agj/tc6k27PaKEGumUa35Uuf6gUgMka1wmxVj1jbWFQ5cOT09f5FpwNB2CVAWoSVIuZBSyctM63oVH9aeBp 6LB5K6w0Hn4lib7syfMtjKZYKUK6fM2Phq0iUNuRNTld/8EsbNS+5nJVX0E+bqn3EaCv+SEOliOd558GNmJf5e4Wgj9hh6cLih4KBnNECQR5BcGJZ3IZGYlm fMbRwquxo/p9BiS3mgR40mca2eer8OpkW+JMtX+EWOjB+BSePGiAxelT7GgF9WqtCKe8cQRY/Pj8acYyxu/t+rj87jD6Q42LRSTzN/wy96X/1L5193eN1DoH Wx+GRIHzqd2BaqErrtOv0KShvZ7Tyo4QTDtIfVJL5SRDo/QmINP4yNKPTFwH2Ek4W5HK1JTw01Y083HZQafyWCVh+ZL6eXvYlTS2jatAKMY7bK4ZifEizDBd tPY50P1d3Vk272wKBDplyVv6aRmxdEmciwLGauVtoTPxwsxyn0/6GFt5zv7SyjSIFVjs5/tWV/yruHfpTNcJWPkp6OGNWazEbAMQfwF0wGEH8hbqTba2OPUR y/HObJxzas6Uay9obkVc1zdvx6fDXcV+tTqnlTG2Bby9VYGAewOxJoNePkJEvnocr9UHPNiyUizqu3h6JuLAh1RSy5B3YMJKkBU3vIE0AYtDLJUe/Y0ik/vH 2fpaK2NeE1RPVqCavNc= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Mark Kettenis Split the MSI controller bindings from the MSI binding document into DT schema format using json-schema. Signed-off-by: Mark Kettenis --- .../interrupt-controller/msi-controller.yaml | 34 +++++++++++++++++++ .../bindings/pci/brcm,stb-pcie.yaml | 1 + .../bindings/pci/microchip,pcie-host.yaml | 1 + 3 files changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/msi-controller.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/msi-controller.yaml b/Documentation/devicetree/bindings/interrupt-controller/msi-controller.yaml new file mode 100644 index 000000000000..5ed6cd46e2e0 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/msi-controller.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/msi-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MSI controller + +maintainers: + - Marc Zyngier + +description: | + An MSI controller signals interrupts to a CPU when a write is made + to an MMIO address by some master. An MSI controller may feature a + number of doorbells. + +properties: + "#msi-cells": + description: | + The number of cells in an msi-specifier, required if not zero. + + Typically this will encode information related to sideband data, + and will not encode doorbells or payloads as these can be + configured dynamically. + + The meaning of the msi-specifier is defined by the device tree + binding of the specific MSI controller. + + msi-controller: + description: + Identifies the node as an MSI controller. + $ref: /schemas/types.yaml#/definitions/flag + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index b9589a0daa5c..5c67976a8dc2 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -88,6 +88,7 @@ required: allOf: - $ref: /schemas/pci/pci-bus.yaml# + - $ref: ../interrupt-controller/msi-controller.yaml# - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index fb95c276a986..684d9d036f48 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -11,6 +11,7 @@ maintainers: allOf: - $ref: /schemas/pci/pci-bus.yaml# + - $ref: ../interrupt-controller/msi-controller.yaml# properties: compatible: From patchwork Fri Aug 27 17:15:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Kettenis X-Patchwork-Id: 503466 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 843E2C432BE for ; Fri, 27 Aug 2021 17:15:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6893460FD9 for ; Fri, 27 Aug 2021 17:15:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239329AbhH0RQp (ORCPT ); Fri, 27 Aug 2021 13:16:45 -0400 Received: from lb1-smtp-cloud8.xs4all.net ([194.109.24.21]:36585 "EHLO lb1-smtp-cloud8.xs4all.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239233AbhH0RQo (ORCPT ); Fri, 27 Aug 2021 13:16:44 -0400 Received: from cust-df1d398c ([IPv6:fc0c:c1f5:9ac0:c45f:1583:5c5b:91fa:2436]) by smtp-cloud8.xs4all.net with ESMTPA id JfS3mDfw9JWNeJfSJm6c4S; Fri, 27 Aug 2021 19:15:52 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xs4all.nl; s=s2; t=1630084552; bh=k7m/qqndabCmHEUUSTpBJLvDRdJ6wDBdYGC4IJcEHqg=; h=From:To:Subject:Date:Message-Id:MIME-Version:From:Subject; b=kEbW7hGntzF5Jlc+nLLJpOxFMAKouHLlgl0hBGZKaj0cnM4odo2965rDZT3HnLY9M VdfK2+7mZxvMGoinDLNLXAi0gsdMNbIITnxVvL8pBW2Q/QTDJ6HvXzxBpL9TJFswDY bDWeadawJTkZ8aVicQxgx3+N5DIhjF5TkXDApI/5gAydSoxxyqvB/f/6qZAx1q6bdb m2ix4iL3RZnmzoCfp87FHVVyQwNcK6tFrY9wG2TMvX15Xd4TGhb8cxnme/m5KAfrhK ZE7zqM/dUhWTMH2LNvkMd3cyAu0VnkVpsNdomw81GT6Sd8szBfPjHVZNtqhjp8XTbE Zd1AA4AAIph+A== From: Mark Kettenis To: devicetree@vger.kernel.org Cc: alyssa@rosenzweig.io, Mark Kettenis , Thomas Gleixner , Marc Zyngier , Rob Herring , Hector Martin , Bjorn Helgaas , Jim Quinlan , Nicolas Saenz Julienne , Florian Fainelli , bcm-kernel-feedback-list@broadcom.com, Daire McNamara , Saenz Julienne , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-rpi-kernel@lists.infradead.org Subject: [PATCH v4 2/4] dt-bindings: interrupt-controller: msi: Add msi-ranges property Date: Fri, 27 Aug 2021 19:15:27 +0200 Message-Id: <20210827171534.62380-3-mark.kettenis@xs4all.nl> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210827171534.62380-1-mark.kettenis@xs4all.nl> References: <20210827171534.62380-1-mark.kettenis@xs4all.nl> MIME-Version: 1.0 X-CMAE-Envelope: MS4xfAn0dMlyco3EFhBT6OCPQR7eqkcBtarYOztGBW8b0eEglHGVTauot96M2GTJzoTMcwq4lLkI6NhvhS9anrWKYUAvMdEs8hq5zjSj7KpUQp5RwCbV7Scr 74Xe9WRBxAUrTxzeJ5HRAybCQx9k7VLnZ9UGg6++B8FvXyhO0uRlkrpBRC6F5v/iRlAP8gkSJz4WlOIeKviCHiSqokisoui1Tr8BrvNm6Z6FpzMc7auw2jaX C7Z+9gi1T4wIMvahiBCScSgudcUGyzsieRQNrEGp+gdITWyX5BQovLZPUXTEmGx6LFmg73ZBQeETR+VnLpFmfZmMbuiOsBeEaXy5eGHkxexTQl6XFjSiFC2G rW4yMrfRUzDGICii6cNX3atrc3O1nkb2eaUYAaG6Jzgf5FLhlpN7RNmeJ7K2dN3Plg8xoPS0P0Sb2gbchoZLPn/CXy4+/6nQeUCjEYkkuroLtWtdRcOYjV6i mFQ6cfM9pvFl689bf/eiA0nscv0WP1qyr564IdhZyg4COIe4/CAswcKbuXygynN8K5bFK5Y+dMqUk1nU/CruO4g/HKTx6hu3fI4Wgkaoxm82A6KbxiXb8yed BQFnI42m5tb1urUh191NsRd/hdB6p6WMdms2nt8EPOVIUE3TAVB6gc74Q7CsneQttK7ojn8mAK/tm0fSmlFNkINB65K8naBa7P90p47+jHg7eIe/wRtAZlaT BatW6a+ES93YciTBxwIS7toyqKVlfc5xl4hgzsnULwhwQiXGPDoiH8jih7tCVhgJLzgsOot1ZOFl2BffR8uJVfxlNEgWl1CMnbDObZY0JfzFa0uCdQxMsPrv u0QiLI4GgIzHbC5GvWg= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Mark Kettenis Update the MSI controller binding to add an msi-ranges property that specifies how MSIs map onto regular interrupts on some other interrupt controller. Signed-off-by: Mark Kettenis --- .../bindings/interrupt-controller/msi-controller.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/msi-controller.yaml b/Documentation/devicetree/bindings/interrupt-controller/msi-controller.yaml index 5ed6cd46e2e0..bf8b8a7dba09 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/msi-controller.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/msi-controller.yaml @@ -31,4 +31,12 @@ properties: Identifies the node as an MSI controller. $ref: /schemas/types.yaml#/definitions/flag + msi-ranges: + description: + A list of pairs , where "intid" is the specification + of the first interrupt (including the phandle for the interrupt + controller) that can be used as an MSI, and "span" the size of + that range. Multiple ranges can be provided. + $ref: /schemas/types.yaml#/definitions/phandle-array + additionalProperties: true From patchwork Fri Aug 27 17:15:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Kettenis X-Patchwork-Id: 503847 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-23.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B1EDC432BE for ; Fri, 27 Aug 2021 17:16:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 35AA860F5B for ; Fri, 27 Aug 2021 17:16:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232649AbhH0RQu (ORCPT ); Fri, 27 Aug 2021 13:16:50 -0400 Received: from lb2-smtp-cloud8.xs4all.net ([194.109.24.25]:55917 "EHLO lb2-smtp-cloud8.xs4all.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237387AbhH0RQs (ORCPT ); Fri, 27 Aug 2021 13:16:48 -0400 Received: from cust-df1d398c ([IPv6:fc0c:c1f5:9ac0:c45f:1583:5c5b:91fa:2436]) by smtp-cloud8.xs4all.net with ESMTPA id JfS3mDfw9JWNeJfSPm6c5G; Fri, 27 Aug 2021 19:15:57 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xs4all.nl; s=s2; t=1630084557; bh=Uz8+b1QNzCpdFU82TySBiAwuag28IbzRbqJyuly6XeQ=; h=From:To:Subject:Date:Message-Id:MIME-Version:From:Subject; b=KOcTJdPoscNbp+Vy0HL4GjCty++SjNJqWehflgdnYf+I8gtkMiofXtglRQFhoDuQd uScYPaKF1V8gcSK2/QKJTuwFQitdrB1RIgKb3FPIuzlxIzjfQiJoK1AftTTlVzBL2U hO2DsRpBPXKCCA+lwWXx/TNUnYgv/v1pP8WjD/Dr40Jwlii8J0JmM+rhQYIFo06kaq 5Gu32ezXupJKnwbuosfH35CAwqcLEFZxTC4T30YEEJhelIS5ThOvYsrXkcFQYjRgIE 24pK1fU/LeZyfoJJXqz5/u4OaR7VeWi4Ka+ee0XEL1mhj0pHnevxx0kE399YbnwmA+ 7s0chd3pjtIPA== From: Mark Kettenis To: devicetree@vger.kernel.org Cc: alyssa@rosenzweig.io, Mark Kettenis , Thomas Gleixner , Marc Zyngier , Rob Herring , Hector Martin , Bjorn Helgaas , Jim Quinlan , Nicolas Saenz Julienne , Florian Fainelli , bcm-kernel-feedback-list@broadcom.com, Daire McNamara , Saenz Julienne , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-rpi-kernel@lists.infradead.org Subject: [PATCH v4 3/4] dt-bindings: pci: Add DT bindings for apple,pcie Date: Fri, 27 Aug 2021 19:15:28 +0200 Message-Id: <20210827171534.62380-4-mark.kettenis@xs4all.nl> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210827171534.62380-1-mark.kettenis@xs4all.nl> References: <20210827171534.62380-1-mark.kettenis@xs4all.nl> MIME-Version: 1.0 X-CMAE-Envelope: MS4xfHUwGkgju7STnLF2OOvJyhiYbu3MW7/VD0w7cOrLxJ4yEZRiqmKcfm7383j1gUCxeQ4buUzHKiFquo0vvpzW8Bblpa5VteOv2zTB7nlHXPBUhXa8hD9j jn6reyALKre8dc3VV/vUYM3I8mNz6s483Gjr3v0Fw+0wlNHhwXqppxErEzGEvWdbjaZzXSZdoqjU7ocdG5/LA5xdYaeC4bYLqHGj7G4GWt1w+0lCdVRbXFP4 pSkURt18WmNq5qaTyvp2YwuVmmtPIPhOMbjw4jarKziy+n1MCafXWRnm9b2cDYyq6QrEcIPq6/wSlOMkba1d0CyIPTOjFwrjs6NLnteLFesvYIQZlYm1hCPV ISHtofm1Mqm9OmcnMyaCXxHP/drkEh2XdbfYO/NIQRbU8Aaoizp0u7OG8nM4DbeLX41sdib19faem5WjUOrxizrhLSk+3QvNVMarmsG6jmavhztSCqYSW9Jy L7MxTXRoXwqK1S+CpOnYxhgU3nEI4EcHGbIPcXnY0/R9fdB3fPlddzHxv2iJIET0HBaB85D2p02xoFOnfz+oTBGORgDWKiLafVJCDTslvcL4G9wj9T1zXTmB mhv5BiRlC+J3CUg2uJg+ExeaOagNZCLGzODQnQb0emSfzZ2VxNKASeBCTwvrFpllHusdLfy1KwlcOhX4brnpmv7S11OeuLph709w8nxmlzfkwXAJtd7f4Etg PnnSTtFd47AADSKIX+0lT/6cas3KUHRw4JgcIeoeYoTG+L+PoqVpr8Lz4FRylrzf5AIFo3HxVaxaZQwdn58Q6DYS1ekz346MCuF/1IlviRg0cih52GsgC2m7 SxoqvEmrI/J6bE/ePWI= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Mark Kettenis The Apple PCIe host controller is a PCIe host controller with multiple root ports present in Apple ARM SoC platforms, including various iPhone and iPad devices and the "Apple Silicon" Macs. Signed-off-by: Mark Kettenis --- .../devicetree/bindings/pci/apple,pcie.yaml | 165 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 166 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/apple,pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/apple,pcie.yaml b/Documentation/devicetree/bindings/pci/apple,pcie.yaml new file mode 100644 index 000000000000..97a126db935a --- /dev/null +++ b/Documentation/devicetree/bindings/pci/apple,pcie.yaml @@ -0,0 +1,165 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/apple,pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple PCIe host controller + +maintainers: + - Mark Kettenis + +description: | + The Apple PCIe host controller is a PCIe host controller with + multiple root ports present in Apple ARM SoC platforms, including + various iPhone and iPad devices and the "Apple Silicon" Macs. + The controller incorporates Synopsys DesigWare PCIe logic to + implements its root ports. But the ATU found on most DesignWare + PCIe host bridges is absent. + + All root ports share a single ECAM space, but separate GPIOs are + used to take the PCI devices on those ports out of reset. Therefore + the standard "reset-gpios" and "max-link-speed" properties appear on + the child nodes that represent the PCI bridges that correspond to + the individual root ports. + + MSIs are handled by the PCIe controller and translated into regular + interrupts. A range of 32 MSIs is provided. These 32 MSIs can be + distributed over the root ports as the OS sees fit by programming + the PCIe controller's port registers. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: ../interrupt-controller/msi-controller.yaml# + +properties: + compatible: + items: + - const: apple,t8103-pcie + - const: apple,pcie + + reg: + minItems: 3 + maxItems: 5 + + reg-names: + minItems: 3 + maxItems: 5 + items: + - const: config + - const: rc + - const: port0 + - const: port1 + - const: port2 + + ranges: + minItems: 2 + maxItems: 2 + + interrupts: + description: + Interrupt specifiers, one for each root port. + minItems: 1 + maxItems: 3 + + msi-parent: true + +# msi-ranges: +# description: +# A list of pairs , where "intid" is the first +# interrupt number that can be used as an MSI, and "span" the size +# of that range. +# $ref: /schemas/types.yaml#/definitions/phandle-array + + iommu-map: true + iommu-map-mask: true + +required: + - compatible + - reg + - reg-names + - bus-range + - interrupts + - msi-controller + - msi-parent + - msi-ranges + +unevaluatedProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie0: pcie@690000000 { + compatible = "apple,t8103-pcie", "apple,pcie"; + device_type = "pci"; + + reg = <0x6 0x90000000 0x0 0x1000000>, + <0x6 0x80000000 0x0 0x4000>, + <0x6 0x81000000 0x0 0x8000>, + <0x6 0x82000000 0x0 0x8000>, + <0x6 0x83000000 0x0 0x8000>; + reg-names = "config", "rc", "port0", "port1", "port2"; + + interrupt-parent = <&aic>; + interrupts = , + , + ; + + msi-controller; + msi-parent = <&pcie0>; + msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; + + iommu-map = <0x100 &dart0 1 1>, + <0x200 &dart1 1 1>, + <0x300 &dart2 1 1>; + iommu-map-mask = <0xff00>; + + bus-range = <0 3>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, + <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; + + clocks = <&pcie_core_clk>, <&pcie_aux_clk>, <&pcie_ref_clk>; + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + + pci@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 152 0>; + max-link-speed = <2>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pci@1,0 { + device_type = "pci"; + reg = <0x800 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 153 0>; + max-link-speed = <2>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pci@2,0 { + device_type = "pci"; + reg = <0x1000 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 33 0>; + max-link-speed = <1>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index c6b8a720c0bc..30bea4042e7e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1694,6 +1694,7 @@ C: irc://chat.freenode.net/asahi-dev T: git https://github.com/AsahiLinux/linux.git F: Documentation/devicetree/bindings/arm/apple.yaml F: Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +F: Documentation/devicetree/bindings/pci/apple,pcie.yaml F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml F: arch/arm64/boot/dts/apple/ F: drivers/irqchip/irq-apple-aic.c From patchwork Fri Aug 27 17:15:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Kettenis X-Patchwork-Id: 503465 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C558CC4320E for ; Fri, 27 Aug 2021 17:16:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A723360F6C for ; Fri, 27 Aug 2021 17:16:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239695AbhH0RRJ (ORCPT ); Fri, 27 Aug 2021 13:17:09 -0400 Received: from lb2-smtp-cloud8.xs4all.net ([194.109.24.25]:55917 "EHLO lb2-smtp-cloud8.xs4all.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236929AbhH0RRC (ORCPT ); Fri, 27 Aug 2021 13:17:02 -0400 Received: from cust-df1d398c ([IPv6:fc0c:c1f5:9ac0:c45f:1583:5c5b:91fa:2436]) by smtp-cloud8.xs4all.net with ESMTPA id JfS3mDfw9JWNeJfSVm6c64; Fri, 27 Aug 2021 19:16:03 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xs4all.nl; s=s2; t=1630084563; bh=3E/gvqQmnwptUkUosq0Zx0aa7ySj/6pZFQ+5JuWSIY8=; h=From:To:Subject:Date:Message-Id:MIME-Version:From:Subject; b=L56qYnRbmqbbPEXYGq/+9I3iH3O3K3WVRr0WMl6Hu2Fext0OZvrPClb4Qq0VkCj1L Dj2sI6H/eSSdhTB2PEBs0n/46QwwWSUkN6TH2BURbp1SxsVfgbixIlWEAKB4rYSmt3 Xj8cQeRGgwrnGTSCVPBOELpIp8rlnNEfeOIylJV73C+wFa8qxX2y6wiUHF/R6ZhFtL hW1AtyDq4/rqTIMWtfD1Nr0RbXspGPxUmgvxqIi61cqC7PiBmZ7irLDapLJsGPynXn BHyklO2MaOpzabXayNc53FsYbqeqCI3/i36NXiWUzYLBnDcmjfkbU7uTr4jwWPgsrN 248OakVyg8L/w== From: Mark Kettenis To: devicetree@vger.kernel.org Cc: alyssa@rosenzweig.io, Mark Kettenis , Thomas Gleixner , Marc Zyngier , Rob Herring , Hector Martin , Bjorn Helgaas , Nicolas Saenz Julienne , Jim Quinlan , Florian Fainelli , bcm-kernel-feedback-list@broadcom.com, Daire McNamara , Saenz Julienne , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-rpi-kernel@lists.infradead.org Subject: [PATCH v4 4/4] arm64: apple: Add PCIe node Date: Fri, 27 Aug 2021 19:15:29 +0200 Message-Id: <20210827171534.62380-5-mark.kettenis@xs4all.nl> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210827171534.62380-1-mark.kettenis@xs4all.nl> References: <20210827171534.62380-1-mark.kettenis@xs4all.nl> MIME-Version: 1.0 X-CMAE-Envelope: MS4xfHq2O0XF3viQNnbchOr5vWvKYVWvSOO6J+kWWin2NGiihPhSI6+JDn4rXZGRPpYD91LgjUny7riMTGLq9DzAcRjLCIHYFbfkJWmimc79d0jUyEZp/OG4 d+TKn6olM6BC2Z+oQbzSLvEFky2EaR64QyCTjChZea/2Tbo3je/qT9PYs1wJqrnnJx2hv6qif0jqz32rqpFKNFuPoWBs8tnFwas0nhwqp/zVC95vGLUayBpb upOuBsnU+C0O/XKE9x3CxWzr/SjE5wfoXdZ1cajZpEW1FeLz0ssRo9DpDv99ikCxGcVOr38q4a8MBE3tJ2QKX8Wr/ItBrHXC0XEFFlWczKSYY2TnSzViLml6 BJ0VjuNNRxxcOf4iaFZspHa1TPYWFUEQxbswaK+OVc9YM8U4Pu+i/Qvsip37XNkXc8r4QD+nAHvMEunKW/hEfbYr//nE8as1Z2HFiuIIjbt/iX17ydeaZYXt oFq94MhjVcSSZwH8e8jCWYnlMDIbAFzVRMOd0RK2NapuZDud/t9UADm7clgQpQ1bbIYGAkK7N9chgCsJRxAdj+4W9bEBN1eHhUgHnxMrhVt0g4GngXbfbIgf 8bCKPlGgE8OdK3Emg0p3BIdYDBpmJAZ4upzA8r8KwnxGmizkYaPtWR6ihnIsHD+GMaEo+fCCU8KFeO5JBgDmFEFY3M2VwQJbWtHnauMwyW7/SJbu5JOfj0cJ 3oJYWeQMUr0+/QolSdvEdsEpsYqXhc8IU1eqRB1wmZLsECYaYSuqBqj/KEogyUWeGN3ep8Tamf2CqlBL2emAfpG9t3sRjPl237sFS1OWIGsic92cSt0D+R1C 5CWfltWgr0dBa5I/AvE= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Mark Kettenis Add node corresponding to the apcie,t8103 node in the Apple device tree for the Mac mini (M1, 2020). Clock references and DART (IOMMU) references are left out at the moment and will be added once the appropriate bindings have been settled upon. Signed-off-by: Mark Kettenis Reviewed-by: Marc Zyngier --- arch/arm64/boot/dts/apple/t8103.dtsi | 63 ++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi index 503a76fc30e6..6e4677bdef44 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -214,5 +214,68 @@ pinctrl_smc: pinctrl@23e820000 { , ; }; + + pcie0: pcie@690000000 { + compatible = "apple,t8103-pcie", "apple,pcie"; + device_type = "pci"; + + reg = <0x6 0x90000000 0x0 0x1000000>, + <0x6 0x80000000 0x0 0x4000>, + <0x6 0x81000000 0x0 0x8000>, + <0x6 0x82000000 0x0 0x8000>, + <0x6 0x83000000 0x0 0x8000>; + reg-names = "config", "rc", "port0", "port1", "port2"; + + interrupt-parent = <&aic>; + interrupts = , + , + ; + + msi-controller; + msi-parent = <&pcie0>; + msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; + + bus-range = <0 3>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, + <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; + + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + + pci@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 152 0>; + max-link-speed = <2>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pci@1,0 { + device_type = "pci"; + reg = <0x800 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 153 0>; + max-link-speed = <2>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pci@2,0 { + device_type = "pci"; + reg = <0x1000 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 33 0>; + max-link-speed = <1>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + }; }; };