From patchwork Wed Oct 10 16:31:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 148572 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp1071540lji; Wed, 10 Oct 2018 09:31:59 -0700 (PDT) X-Google-Smtp-Source: ACcGV62lEyx9jg4AG1wbhNED5j8k9ant2lBcONBjhnD5W8ATiHfxMOE7auW/SHWXV3Uu9+4AU7sl X-Received: by 2002:a63:480e:: with SMTP id v14-v6mr30192849pga.308.1539189119267; Wed, 10 Oct 2018 09:31:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539189119; cv=none; d=google.com; s=arc-20160816; b=sqTm+V8kbwnNa3nuo+b1nYMsPzpn0YvxEs/kXoNxMBTG46bU3ShkS4xviG72lNX+a6 m1UrR9EqfiPNoiEbfJNlkRT0xCSMKNFEMJXLxDz5r3ZE0N1nXrdMrqfJ6UpzNnLTyhTL wchAzRPTHPXdBNYvS+srZoYgyjHNwdNc9JaaJDM2Din+ZfyR2xVbpzey9WhxJIPqkO7B 6A1DGice6awMgvr+Tj5RtO4i5vEWuXDqUWzTf+yk53ATMJ5s+6qLuZLK/fC4Vj4ieyfA UBnvtUyqbBmyUsVCiwOkuLoqxCb/dLjVIBc0eYMt9EAk2xbnskwRkhP5HTVvXX3eDV+g vSJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=Pt9VoeTTN78FggttQe9onkfdjAccDoNbS5GzKj8vDMM=; b=vwbPEsNOBxmpQmInjQOXfOAkUXlw4fXN0LZ/j/4dw+m8/zcaXpFZI7aZGr5YGtJRrO 6uXiFmvn2TZR+Bb2jQwpHOnBHq1fLVm6zxwZVvtLe3yUC90BmP34PRuerKO5zXfHmd10 7TOZ4HpcoxrRQyFIo651Bizqw+uwoCtHRg35OSXeo6XfEHKU+Tr/bWghEzRmzZ+maYCK Rs93xO9L/mekbyvqGrAGiGGSDh1DfewcF7q1kj/gQLNmfuOeOGle6wvUEGnWGv/l5GHq nLqSmNUqC+FVyxUcDxCly4yxX6ATc88rFKDp0um8uKdFK3yTFT6r6RQoPcFzmi+d2Y5l LRaQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s59-v6si26340799plb.341.2018.10.10.09.31.58; Wed, 10 Oct 2018 09:31:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726798AbeJJXyx (ORCPT + 14 others); Wed, 10 Oct 2018 19:54:53 -0400 Received: from foss.arm.com ([217.140.101.70]:55064 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726794AbeJJXyw (ORCPT ); Wed, 10 Oct 2018 19:54:52 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 54939ED1; Wed, 10 Oct 2018 09:31:57 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 25F6A3F740; Wed, 10 Oct 2018 09:31:57 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id CC7CF1AE07A7; Wed, 10 Oct 2018 17:31:56 +0100 (BST) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: mark.rutland@arm.com, suzuki.poulose@arm.com, Ganapatrao.Kulkarni@cavium.com, Will Deacon , Subject: [PATCH 1/6] arm64: perf: Reject stand-alone CHAIN events for PMUv3 Date: Wed, 10 Oct 2018 17:31:50 +0100 Message-Id: <1539189115-16221-2-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1539189115-16221-1-git-send-email-will.deacon@arm.com> References: <1539189115-16221-1-git-send-email-will.deacon@arm.com> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org It doesn't make sense for a perf event to be configured as a CHAIN event in isolation, so extend the arm_pmu structure with a ->filter_match() function to allow the backend PMU implementation to reject CHAIN events early. Cc: Signed-off-by: Will Deacon --- arch/arm64/kernel/perf_event.c | 7 +++++++ drivers/perf/arm_pmu.c | 8 +++++++- include/linux/perf/arm_pmu.h | 1 + 3 files changed, 15 insertions(+), 1 deletion(-) -- 2.1.4 Reviewed-by: Suzuki K Poulose diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 8e38d5267f22..e213f8e867f6 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -966,6 +966,12 @@ static int armv8pmu_set_event_filter(struct hw_perf_event *event, return 0; } +static int armv8pmu_filter_match(struct perf_event *event) +{ + unsigned long evtype = event->hw.config_base & ARMV8_PMU_EVTYPE_EVENT; + return evtype != ARMV8_PMUV3_PERFCTR_CHAIN; +} + static void armv8pmu_reset(void *info) { struct arm_pmu *cpu_pmu = (struct arm_pmu *)info; @@ -1114,6 +1120,7 @@ static int armv8_pmu_init(struct arm_pmu *cpu_pmu) cpu_pmu->stop = armv8pmu_stop, cpu_pmu->reset = armv8pmu_reset, cpu_pmu->set_event_filter = armv8pmu_set_event_filter; + cpu_pmu->filter_match = armv8pmu_filter_match; return 0; } diff --git a/drivers/perf/arm_pmu.c b/drivers/perf/arm_pmu.c index 7f01f6f60b87..d0b7dd8fb184 100644 --- a/drivers/perf/arm_pmu.c +++ b/drivers/perf/arm_pmu.c @@ -485,7 +485,13 @@ static int armpmu_filter_match(struct perf_event *event) { struct arm_pmu *armpmu = to_arm_pmu(event->pmu); unsigned int cpu = smp_processor_id(); - return cpumask_test_cpu(cpu, &armpmu->supported_cpus); + int ret; + + ret = cpumask_test_cpu(cpu, &armpmu->supported_cpus); + if (ret && armpmu->filter_match) + return armpmu->filter_match(event); + + return ret; } static ssize_t armpmu_cpumask_show(struct device *dev, diff --git a/include/linux/perf/arm_pmu.h b/include/linux/perf/arm_pmu.h index 10f92e1d8e7b..bf309ff6f244 100644 --- a/include/linux/perf/arm_pmu.h +++ b/include/linux/perf/arm_pmu.h @@ -99,6 +99,7 @@ struct arm_pmu { void (*stop)(struct arm_pmu *); void (*reset)(void *); int (*map_event)(struct perf_event *event); + int (*filter_match)(struct perf_event *event); int num_events; bool secure_access; /* 32-bit ARM only */ #define ARMV8_PMUV3_MAX_COMMON_EVENTS 0x40