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[209.132.180.67]) by mx.google.com with ESMTP id d35-v6si20469740pla.116.2018.10.08.16.50.46; Mon, 08 Oct 2018 16:50:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=YHDTg8OE; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727246AbeJIHEy (ORCPT + 32 others); Tue, 9 Oct 2018 03:04:54 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:59164 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726761AbeJIHEJ (ORCPT ); Tue, 9 Oct 2018 03:04:09 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id w98Nnq6R074788; Mon, 8 Oct 2018 18:49:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1539042592; bh=O2+B9ZyS4qEEL4pahdJEhkZn9FK377JlFf1+Tyq5uW8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=YHDTg8OE4FAVezLbct5fi86T6mSyoYjJ3eEO8b9yDBW3a3KknuqYiUbWSZNUvd1L6 BHNCZyVq81liX0myG3Buq4/1rppj53QvESzXDH+ei4YfxjzSfiyKcraGlf4xB8FIaz rD9WTuD7pb0PuTS1RS8zqVdSLnrV28uAaZwJdyWM= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w98NnqmW023941; Mon, 8 Oct 2018 18:49:52 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Mon, 8 Oct 2018 18:49:51 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Mon, 8 Oct 2018 18:49:51 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w98Nnp7q027737; Mon, 8 Oct 2018 18:49:51 -0500 Received: from localhost (uda0226610.dhcp.ti.com [128.247.59.147]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id w98Nnpx25212; Mon, 8 Oct 2018 18:49:51 -0500 (CDT) From: Grygorii Strashko To: "David S. Miller" , , Tony Lindgren , Rob Herring , Kishon Vijay Abraham I CC: Sekhar Nori , , , , Grygorii Strashko Subject: [RFC PATCH 01/11] phy: core add phy_set_netif_mode() api Date: Mon, 8 Oct 2018 18:49:39 -0500 Message-ID: <20181008234949.15416-2-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.10.5 In-Reply-To: <20181008234949.15416-1-grygorii.strashko@ti.com> References: <20181008234949.15416-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add new API phy_set_netif_mode(struct phy *phy, phy_interface_t mode) and new PHY operation callback .set_netif_mode() which intended to be implemnte by PHY drivers which supports Network interrfaces mode selection. Both accepts phy_interface_t vlaue as input parameter. Cc: Kishon Vijay Abraham I Cc: Tony Lindgren Signed-off-by: Grygorii Strashko --- drivers/phy/phy-core.c | 15 +++++++++++++++ include/linux/phy/phy.h | 12 ++++++++++++ 2 files changed, 27 insertions(+) -- 2.10.5 diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c index 35fd38c..d9aba1a 100644 --- a/drivers/phy/phy-core.c +++ b/drivers/phy/phy-core.c @@ -377,6 +377,21 @@ int phy_set_mode(struct phy *phy, enum phy_mode mode) } EXPORT_SYMBOL_GPL(phy_set_mode); +int phy_set_netif_mode(struct phy *phy, phy_interface_t mode) +{ + int ret; + + if (!phy || !phy->ops->set_netif_mode) + return 0; + + mutex_lock(&phy->mutex); + ret = phy->ops->set_netif_mode(phy, mode); + mutex_unlock(&phy->mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(phy_set_netif_mode); + int phy_reset(struct phy *phy) { int ret; diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index 9713aeb..bc73d2b 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -49,6 +50,7 @@ enum phy_mode { * @power_on: powering on the phy * @power_off: powering off the phy * @set_mode: set the mode of the phy + * @set_netif_mode: set the mode of the net interface phy * @reset: resetting the phy * @calibrate: calibrate the phy * @owner: the module owner containing the ops @@ -59,6 +61,7 @@ struct phy_ops { int (*power_on)(struct phy *phy); int (*power_off)(struct phy *phy); int (*set_mode)(struct phy *phy, enum phy_mode mode); + int (*set_netif_mode)(struct phy *phy, phy_interface_t mode); int (*reset)(struct phy *phy); int (*calibrate)(struct phy *phy); struct module *owner; @@ -163,6 +166,7 @@ int phy_exit(struct phy *phy); int phy_power_on(struct phy *phy); int phy_power_off(struct phy *phy); int phy_set_mode(struct phy *phy, enum phy_mode mode); +int phy_set_netif_mode(struct phy *phy, phy_interface_t mode); static inline enum phy_mode phy_get_mode(struct phy *phy) { return phy->attrs.mode; @@ -283,6 +287,14 @@ static inline int phy_set_mode(struct phy *phy, enum phy_mode mode) return -ENOSYS; } +static inline int phy_set_netif_mode(struct phy *phy, + phy_interface_t mode) +{ + if (!phy) + return 0; + return -ENOTSUPP; +} + static inline enum phy_mode phy_get_mode(struct phy *phy) { return PHY_MODE_INVALID; From patchwork Mon Oct 8 23:49:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 148474 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp4243906lji; Mon, 8 Oct 2018 16:51:21 -0700 (PDT) X-Google-Smtp-Source: ACcGV61KDhbvJLZ1KO5sihLp80GBtf93IoD6aNMvUGU3c67TJyk8P2qivEUytbaav6BvIt7LUCjs X-Received: by 2002:a63:6445:: with SMTP id y66-v6mr23710713pgb.443.1539042680864; Mon, 08 Oct 2018 16:51:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539042680; cv=none; d=google.com; s=arc-20160816; b=z04TvYn/wmV/CwZ9mNJ9o+790OhM0Kf3T2iUdcnn9d2pCpF3ylR5HkOIxpdEvi+XtO I289ZkL6kC9jdVJayNEj9Nff9hVSXyRsvq3W5jbxu/8LxHicTLZxaorbqZSfwdoCryZy ip1HtEmen9YHtQ7kXuvodJJuv9HnspX+H8AKE5bpB4agKYBBm5O91NEXEzvEDp7X1Wg1 WsLYTyChQgbZ10lJzN8dbwMx0wE+F6+lFzIGcwBWe3mMjJYFjhqZpcUgHNW7tWfnYR29 b76goAg8XxL6M2E9aeUHU83egaDr6Mknq+i2lB3av6KfMR0di5Jm2l96q3LthGI5lSz9 NPTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=3uC4YX3i2GahEKMhydzhXXxO77zZOflGn5HPNJiU2+k=; b=cFaRinXy2ZQXAkheXHrC2ej32K5salamDP2Buyz07W4Ri9lPqp5qjPqS+miPIbz0fn 9d40HsZyuK8p0XpHHKRrV3clTPzS/y4WHC92+x0HYBJy2gb+m2FZpNklSZGNuSfHtyD7 8oI+MP7GkTug9gSoXmuk+ciUHp94bY+//NeuNRtDvLtJYqti2+SoDrOXYGagjFuaaICK cr/ZZaKOWJpw1EEA3esw/1PgFhmiPT8icqWXvHm4paQvythgXoUhCIDU1Qg7EQt0HrEf uCvvm/CRJ3MvMDNAI8MS2UQ812qLtHzvv8RaMiGluSBPG1Wx6MYk8cGPAVHDLXa4sROh 8c4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ThZ9KEoW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a10-v6si18315389pgk.365.2018.10.08.16.51.20; Mon, 08 Oct 2018 16:51:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ThZ9KEoW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726697AbeJIHEH (ORCPT + 32 others); Tue, 9 Oct 2018 03:04:07 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:42952 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725794AbeJIHEG (ORCPT ); Tue, 9 Oct 2018 03:04:06 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id w98Nnqvo126361; Mon, 8 Oct 2018 18:49:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1539042592; bh=3uC4YX3i2GahEKMhydzhXXxO77zZOflGn5HPNJiU2+k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ThZ9KEoWRoHFh1u+FOaUoxtuPmwMM90arV6T1MoPQ/ALIZQHtp5TpxXQ0J9wlsUoh xw3NoQNsh3+VBoN1ViU2aFWH3W24FXU5CHHjVvzPCykMsTNNpi9k2/n0MBOD91ZT2N PtUD7z0eeMvyv64wyqAJn1ONyQN2BuEneLqi7uls= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w98NnqXu023944; Mon, 8 Oct 2018 18:49:52 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Mon, 8 Oct 2018 18:49:52 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Mon, 8 Oct 2018 18:49:51 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w98Nnp7m023110; Mon, 8 Oct 2018 18:49:51 -0500 Received: from localhost (uda0226610.dhcp.ti.com [128.247.59.147]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id w98Nnpx25216; Mon, 8 Oct 2018 18:49:51 -0500 (CDT) From: Grygorii Strashko To: "David S. Miller" , , Tony Lindgren , Rob Herring , Kishon Vijay Abraham I CC: Sekhar Nori , , , , Grygorii Strashko Subject: [RFC PATCH 02/11] dt-bindings: phy: add cpsw port interface mode selection phy bindings Date: Mon, 8 Oct 2018 18:49:40 -0500 Message-ID: <20181008234949.15416-3-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.10.5 In-Reply-To: <20181008234949.15416-1-grygorii.strashko@ti.com> References: <20181008234949.15416-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add CPSW Port's Interface Mode Selection PHY (phy-gmii-sel) DT Bindings Cc: Kishon Vijay Abraham I Cc: Tony Lindgren Signed-off-by: Grygorii Strashko --- .../devicetree/bindings/phy/ti-phy-gmii-sel.txt | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt -- 2.10.5 diff --git a/Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt b/Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt new file mode 100644 index 0000000..fd81421 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt @@ -0,0 +1,68 @@ +CPSW Port's Interface Mode Selection PHY Tree Bindings +----------------------------------------------- + +TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports +two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces. +The interface mode is selected by configuring the MII mode selection register(s) +(GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and +bit fields placement in SCM are different between SoCs while fields meaning +is the same. + +--------------+ + +-------------------------------+ |SCM | + | CPSW | | +---------+ | + | +--------------------------------+gmii_sel | | + | | | | +---------+ | + | +----v---+ +--------+ | +--------------+ + | |Port 1..<--+-->GMII/MII<-------> + | | | | | | | + | +--------+ | +--------+ | + | | | + | | +--------+ | + | | | RMII <-------> + | +--> | | + | | +--------+ | + | | | + | | +--------+ | + | | | RGMII <-------> + | +--> | | + | +--------+ | + +-------------------------------+ + +CPSW Port's Interface Mode Selection PHY describes MII interface mode between +CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration. + +CPSW Port's Interface Mode Selection PHY device should defined as child device +of SCM node (scm_conf) and can be attached to each CPSW port node using standard +PHY bindings (See phy/phy-bindings.txt). + +Required properties: +- compatible : Should be "ti,am3352-phy-gmii-sel" for am335x platform + "ti,dra7xx-phy-gmii-sel" for dra7xx/am57xx platform + "ti,am43xx-phy-gmii-sel" for am43xx platform + "ti,dm814-phy-gmii-sel" for dm814x platform +- #phy-cells : must be 2. + cell 1 - CPSW port number (starting from 1) + cell 2 - RMII refclk mode +- syscon-scm : phandle on SCM node (mfd/syscon.txt) + +Examples: + phy_gmii_sel: phy-gmii-sel { + compatible = "ti,am3352-phy-gmii-sel"; + syscon-scm = <&scm_conf>; + #phy-cells = <2>; + }; + + mac: ethernet@4a100000 { + compatible = "ti,am335x-cpsw","ti,cpsw"; + ... + + cpsw_emac0: slave@4a100200 { + ... + phys = <&phy_gmii_sel 1 1>; + }; + + cpsw_emac1: slave@4a100300 { + ... + phys = <&phy_gmii_sel 2 1>; + }; + }; From patchwork Mon Oct 8 23:49:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 148469 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp4243092lji; Mon, 8 Oct 2018 16:50:07 -0700 (PDT) X-Google-Smtp-Source: ACcGV63vRH0bgRhm15ND0zA5qVO2CmZ6L9yL4ft4JCVMr4FpLftHYx+4GVhGptW1CGCYsBqDpugy X-Received: by 2002:a63:8f09:: with SMTP id n9-v6mr22815452pgd.222.1539042607326; Mon, 08 Oct 2018 16:50:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539042607; cv=none; d=google.com; s=arc-20160816; b=mIbbo5bqaXXTzxZy8osQ0gxoTk0c4+3mV31aLJi+6nXuwGcnGjC5sfZd9vTiwYDOyk c+Kfah01WbdnYymtRYw+abCV/RToBVL9NY0GXRrf0Mdf28aHPZaxKKOWfzMNrJPuxcoq ldPMcA4NLlh1exRD8c2mxMRy2IFLMjT3l77wzMRBQ+w7cu2lPMlQE06ofjxCKNJNVMnE 5Uu1dFEuZovmVok8WzCqSCrkruAfXs+9ghEp1GIO5bM84tG2mdePZnIJRQZC1ohJKyDg Bm+E0n1PsSUSb6HKbzIkFjWS6c+kKDsYtwQ8LB8jrGyIH4c4E0gS4ppWG2XO00x318b8 ie5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=1MLc6uK8ga7tgU6hXX5r/Nx9hLnMbXXXaWdHd27QlvM=; b=ZcQbp7ZvUZTeyhGBC1pGVe7PQjAuyLw6GgfTyu6WYc3vSxWq2tbiCNlwJQOLgSdwpV kLElueJ1yxnQGlMnX2RdGlyCiNRV7pJmQfZoD6hCF+phW4awR7zEjsZ7Pn9QY6XlsTRR VzMpVVhK314P171xRPDT+ufO0dxRylOPWRFK8tGGsqEB+i8UBsFsnJwtnTQsLQunxcvp MGU1X4DPFf0TSNgYWyRseE6DOq5bUODcom/khQ5wgSQfEjQQqJPPDV9lrpLcp3gWdeIL vZfx5CWtt2dDF1BtFRFlK7y1KK/RA60a3QgezSU9PCz14QyhWtRFBo/8XXHW5afUxqsE BHGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=lm4aRRYc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , , Tony Lindgren , Rob Herring , Kishon Vijay Abraham I CC: Sekhar Nori , , , , Grygorii Strashko Subject: [RFC PATCH 03/11] phy: ti: introduce phy-gmii-sel driver Date: Mon, 8 Oct 2018 18:49:41 -0500 Message-ID: <20181008234949.15416-4-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.10.5 In-Reply-To: <20181008234949.15416-1-grygorii.strashko@ti.com> References: <20181008234949.15416-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces. The interface mode is selected by configuring the MII mode selection register(s) (GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and bit fields placement in SCM are different between SoCs while fields meaning is the same. Historically CPSW external Port's interface mode selection configuartion was introduced using custom API and driver cpsw-phy-sel.c. This leads to unnecessary driver, DT binding and custom API support effort. This patch introduces CPSW Port's PHY Interface Mode selection Driver (phy-gmii-sel) which implements standard Linux PHY interface and proposed as a replacement for TI's specific driver cpsw-phy-sel.c and coresponding custom API. Cc: Kishon Vijay Abraham I Cc: Tony Lindgren Signed-off-by: Grygorii Strashko --- drivers/phy/ti/Kconfig | 10 ++ drivers/phy/ti/Makefile | 1 + drivers/phy/ti/phy-gmii-sel.c | 345 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 356 insertions(+) create mode 100644 drivers/phy/ti/phy-gmii-sel.c -- 2.10.5 diff --git a/drivers/phy/ti/Kconfig b/drivers/phy/ti/Kconfig index 2050356..f137e01 100644 --- a/drivers/phy/ti/Kconfig +++ b/drivers/phy/ti/Kconfig @@ -76,3 +76,13 @@ config TWL4030_USB family chips (including the TWL5030 and TPS659x0 devices). This transceiver supports high and full speed devices plus, in host mode, low speed. + +config PHY_TI_GMII_SEL + tristate + default y if TI_CPSW=y + depends on TI_CPSW || COMPILE_TEST + select GENERIC_PHY + default m + help + This driver supports configuring of the TI CPSW Port mode depending on + the Ethernet PHY connected to the CPSW Port. diff --git a/drivers/phy/ti/Makefile b/drivers/phy/ti/Makefile index 9f36175..bea8f25 100644 --- a/drivers/phy/ti/Makefile +++ b/drivers/phy/ti/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o obj-$(CONFIG_TI_PIPE3) += phy-ti-pipe3.o obj-$(CONFIG_PHY_TUSB1210) += phy-tusb1210.o obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o +obj-$(CONFIG_PHY_TI_GMII_SEL) += phy-gmii-sel.o diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c new file mode 100644 index 0000000..61a3aa1 --- /dev/null +++ b/drivers/phy/ti/phy-gmii-sel.c @@ -0,0 +1,345 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Texas Instruments CPSW Port's PHY Interface Mode selection Driver + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * + * Based on cpsw-phy-sel.c driver created by Mugunthan V N + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* AM33xx SoC specific definitions for the CONTROL port */ +#define AM33XX_GMII_SEL_MODE_MII 0 +#define AM33XX_GMII_SEL_MODE_RMII 1 +#define AM33XX_GMII_SEL_MODE_RGMII 2 + +enum { + PHY_GMII_SEL_PORT_MODE, + PHY_GMII_SEL_RGMII_ID_MODE, + PHY_GMII_SEL_RMII_IO_CLK_EN, + PHY_GMII_SEL_LAST, +}; + +struct phy_gmii_sel_phy_priv { + struct phy_gmii_sel_priv *priv; + u32 id; + struct phy *if_phy; + int rmii_clock_external; + int phy_if_mode; + struct regmap_field *fields[PHY_GMII_SEL_LAST]; +}; + +struct phy_gmii_sel_soc_data { + u32 num_ports; + u32 features; + const struct reg_field (*regfields)[PHY_GMII_SEL_LAST]; +}; + +struct phy_gmii_sel_priv { + struct device *dev; + const struct phy_gmii_sel_soc_data *soc_data; + struct regmap *regmap; + struct phy_provider *phy_provider; + + struct phy_gmii_sel_phy_priv *if_phys; +}; + +static int phy_gmii_sel_mode(struct phy *phy, phy_interface_t intf_mode) +{ + struct phy_gmii_sel_phy_priv *if_phy = phy_get_drvdata(phy); + const struct phy_gmii_sel_soc_data *soc_data = if_phy->priv->soc_data; + struct device *dev = if_phy->priv->dev; + struct regmap_field *regfield; + int ret, rgmii_id = 0; + u32 mode = 0; + + if_phy->phy_if_mode = intf_mode; + + switch (if_phy->phy_if_mode) { + case PHY_INTERFACE_MODE_RMII: + mode = AM33XX_GMII_SEL_MODE_RMII; + break; + + case PHY_INTERFACE_MODE_RGMII: + mode = AM33XX_GMII_SEL_MODE_RGMII; + break; + + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + mode = AM33XX_GMII_SEL_MODE_RGMII; + rgmii_id = 1; + break; + + default: + dev_warn(dev, + "port%u: unsupported mode: \"%s\". Defaulting to MII.\n", + if_phy->id, phy_modes(rgmii_id)); + /* fall through */ + case PHY_INTERFACE_MODE_MII: + mode = AM33XX_GMII_SEL_MODE_MII; + break; + }; + + dev_dbg(dev, "%s id:%u mode:%u rgmii_id:%d rmii_clk_ext:%d\n", + __func__, if_phy->id, mode, rgmii_id, + if_phy->rmii_clock_external); + + regfield = if_phy->fields[PHY_GMII_SEL_PORT_MODE]; + ret = regmap_field_write(regfield, mode); + + if (soc_data->features & BIT(PHY_GMII_SEL_RGMII_ID_MODE) && + if_phy->fields[PHY_GMII_SEL_RGMII_ID_MODE]) { + regfield = if_phy->fields[PHY_GMII_SEL_RGMII_ID_MODE]; + ret |= regmap_field_write(regfield, rgmii_id); + } + + if (soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN) && + if_phy->fields[PHY_GMII_SEL_RMII_IO_CLK_EN]) { + regfield = if_phy->fields[PHY_GMII_SEL_RMII_IO_CLK_EN]; + ret |= regmap_field_write(regfield, + if_phy->rmii_clock_external); + } + + if (ret) { + dev_err(dev, "port%u: set mode fail %d", if_phy->id, ret); + return -EIO; + } + + return 0; +} + +static const +struct reg_field phy_gmii_sel_fields_am33xx[][PHY_GMII_SEL_LAST] = { + { + [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x650, 0, 1), + [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x650, 4, 4), + [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD(0x650, 6, 6), + }, + { + [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x650, 2, 3), + [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x650, 5, 5), + [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD(0x650, 7, 7), + }, +}; + +static const +struct phy_gmii_sel_soc_data phy_gmii_sel_soc_am33xx = { + .num_ports = 2, + .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE) | + BIT(PHY_GMII_SEL_RMII_IO_CLK_EN), + .regfields = phy_gmii_sel_fields_am33xx, +}; + +static const +struct reg_field phy_gmii_sel_fields_dra7[][PHY_GMII_SEL_LAST] = { + { + [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x554, 0, 1), + [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD((~0), 0, 0), + [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD((~0), 0, 0), + }, + { + [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x554, 4, 5), + [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD((~0), 0, 0), + [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD((~0), 0, 0), + }, +}; + +static const +struct phy_gmii_sel_soc_data phy_gmii_sel_soc_dra7 = { + .num_ports = 2, + .regfields = phy_gmii_sel_fields_dra7, +}; + +static const +struct phy_gmii_sel_soc_data phy_gmii_sel_soc_dm814 = { + .num_ports = 2, + .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE), + .regfields = phy_gmii_sel_fields_am33xx, +}; + +static const struct of_device_id phy_gmii_sel_id_table[] = { + { + .compatible = "ti,am3352-phy-gmii-sel", + .data = &phy_gmii_sel_soc_am33xx, + }, + { + .compatible = "ti,dra7xx-phy-gmii-sel", + .data = &phy_gmii_sel_soc_dra7, + }, + { + .compatible = "ti,am43xx-phy-gmii-sel", + .data = &phy_gmii_sel_soc_am33xx, + }, + { + .compatible = "ti,dm814-phy-gmii-sel", + .data = &phy_gmii_sel_soc_dm814, + }, + {} +}; +MODULE_DEVICE_TABLE(of, phy_gmii_sel_id_table); + +static const struct phy_ops phy_gmii_sel_ops = { + .set_netif_mode = phy_gmii_sel_mode, + .owner = THIS_MODULE, +}; + +static struct phy *phy_gmii_sel_of_xlate(struct device *dev, + struct of_phandle_args *args) +{ + struct phy_gmii_sel_priv *priv = dev_get_drvdata(dev); + int phy_id = args->args[0]; + + if (args->args_count < 1) + return ERR_PTR(-EINVAL); + if (priv->soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN) && + args->args_count < 2) + return ERR_PTR(-EINVAL); + if (!priv || !priv->if_phys) + return ERR_PTR(-ENODEV); + if (phy_id > priv->soc_data->num_ports) + return ERR_PTR(-EINVAL); + if (phy_id != priv->if_phys[phy_id - 1].id) + return ERR_PTR(-EINVAL); + + phy_id--; + if (priv->soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN)) + priv->if_phys[phy_id].rmii_clock_external = args->args[1]; + dev_dbg(dev, "%s id:%u ext:%d\n", __func__, + priv->if_phys[phy_id].id, args->args[1]); + + return priv->if_phys[phy_id].if_phy; +} + +static int phy_gmii_sel_init_ports(struct phy_gmii_sel_priv *priv) +{ + const struct phy_gmii_sel_soc_data *soc_data = priv->soc_data; + struct device *dev = priv->dev; + struct phy_gmii_sel_phy_priv *if_phys; + int i, num_ports, ret; + + num_ports = priv->soc_data->num_ports; + + if_phys = devm_kcalloc(priv->dev, num_ports, + sizeof(*if_phys), GFP_KERNEL); + if (!if_phys) + return -ENOMEM; + dev_dbg(dev, "%s %d\n", __func__, num_ports); + + for (i = 0; i < num_ports; i++) { + const struct reg_field *field; + struct regmap_field *regfield; + + if_phys[i].id = i + 1; + if_phys[i].priv = priv; + + field = &soc_data->regfields[i][PHY_GMII_SEL_PORT_MODE]; + dev_dbg(dev, "%s field %x %d %d\n", __func__, + field->reg, field->msb, field->lsb); + + regfield = devm_regmap_field_alloc(dev, priv->regmap, *field); + if (IS_ERR(regfield)) + return PTR_ERR(regfield); + if_phys[i].fields[PHY_GMII_SEL_PORT_MODE] = regfield; + + field = &soc_data->regfields[i][PHY_GMII_SEL_RGMII_ID_MODE]; + if (field->reg != (~0)) { + regfield = devm_regmap_field_alloc(dev, + priv->regmap, + *field); + if (IS_ERR(regfield)) + return PTR_ERR(regfield); + if_phys[i].fields[PHY_GMII_SEL_RGMII_ID_MODE] = + regfield; + } + + field = &soc_data->regfields[i][PHY_GMII_SEL_RMII_IO_CLK_EN]; + if (field->reg != (~0)) { + regfield = devm_regmap_field_alloc(dev, + priv->regmap, + *field); + if (IS_ERR(regfield)) + return PTR_ERR(regfield); + if_phys[i].fields[PHY_GMII_SEL_RMII_IO_CLK_EN] = + regfield; + } + + if_phys[i].if_phy = devm_phy_create(dev, + priv->dev->of_node, + &phy_gmii_sel_ops); + if (IS_ERR(if_phys[i].if_phy)) { + ret = PTR_ERR(if_phys[i].if_phy); + dev_err(dev, "Failed to create phy%d %d\n", i, ret); + return ret; + } + phy_set_drvdata(if_phys[i].if_phy, &if_phys[i]); + } + + priv->if_phys = if_phys; + return 0; +} + +static int phy_gmii_sel_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + const struct of_device_id *of_id; + struct phy_gmii_sel_priv *priv; + int ret; + + of_id = of_match_node(phy_gmii_sel_id_table, pdev->dev.of_node); + if (!of_id) + return -EINVAL; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = &pdev->dev; + priv->soc_data = of_id->data; + + priv->regmap = syscon_regmap_lookup_by_phandle(node, "syscon-scm"); + if (IS_ERR(priv->regmap)) { + ret = PTR_ERR(priv->regmap); + dev_err(dev, "Failed to get syscon %d\n", ret); + return ret; + } + + ret = phy_gmii_sel_init_ports(priv); + if (ret) + return ret; + + dev_set_drvdata(&pdev->dev, priv); + + priv->phy_provider = + devm_of_phy_provider_register(dev, + phy_gmii_sel_of_xlate); + if (IS_ERR(priv->phy_provider)) { + ret = PTR_ERR(priv->phy_provider); + dev_err(dev, "Failed to create phy provider %d\n", ret); + return ret; + } + + return 0; +} + +static struct platform_driver phy_gmii_sel_driver = { + .probe = phy_gmii_sel_probe, + .driver = { + .name = "phy-gmii-sel", + .of_match_table = phy_gmii_sel_id_table, + }, +}; +module_platform_driver(phy_gmii_sel_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Grygorii Strashko "); +MODULE_DESCRIPTION("TI CPSW Port's PHY Interface Mode selection Driver"); From patchwork Mon Oct 8 23:49:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 148466 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp4243030lji; Mon, 8 Oct 2018 16:50:02 -0700 (PDT) X-Google-Smtp-Source: ACcGV61s3AU3jNJqClbKjWRAZlTp1cHaqq3m98yZ09sSl8cJT2AQd+EY9Dc4MWXWnDfZ8P901BCa X-Received: by 2002:a63:184a:: with SMTP id 10-v6mr22771768pgy.81.1539042602002; Mon, 08 Oct 2018 16:50:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539042601; cv=none; d=google.com; s=arc-20160816; b=IXlVz3yoQe3kMWpIEePAX82qw8xfrcVMLzrFI0NjvVdX/JdAIJYBMSND/XZEaSfM4s cxaBo7/b1TXuDkx/8jwOdN3uVPk+ItNgKgPPvpa3Eb20QBJ+I9tIaasCcUtpMd6k2lWo 76jxfmW752QTeF5cIwqW01IwdA+TC83/8KJ2a7trWaJupBL+qrFYEaenPaN2uwqMNk84 6e7iUl/QMbloQEhnuQdiwSYKyQAxs829ntNN9brcXeJn7Ts4Ocwrhsb3D0fO/QQ+bHUa 7lhEwok9QEHRse7gJ2F/J5kbJqZZDhE9DV+cu3AksJzkxi3Rr6k6YHKJrQaX6UZdBdzu jVaA== ARC-Message-Signature: i=1; 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Miller" , , Tony Lindgren , Rob Herring , Kishon Vijay Abraham I CC: Sekhar Nori , , , , Grygorii Strashko Subject: [RFC PATCH 05/11] net: ethernet: ti: cpsw: add support for port interface mode selection phy Date: Mon, 8 Oct 2018 18:49:43 -0500 Message-ID: <20181008234949.15416-6-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.10.5 In-Reply-To: <20181008234949.15416-1-grygorii.strashko@ti.com> References: <20181008234949.15416-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add support for port interface mode selection phy (phy-gmii-sel): - try to request interface mode selection phy from Port DT node and fail silently if not defined and old CONFIG_TI_CPSW_PHY_SEL driver enabled. - use new phy if requested successfully. Cc: Kishon Vijay Abraham I Cc: Tony Lindgren Signed-off-by: Grygorii Strashko --- drivers/net/ethernet/ti/cpsw.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) -- 2.10.5 diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c index 832bce0..4607de2 100644 --- a/drivers/net/ethernet/ti/cpsw.c +++ b/drivers/net/ethernet/ti/cpsw.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -387,6 +388,7 @@ struct cpsw_slave_data { int phy_if; u8 mac_addr[ETH_ALEN]; u16 dual_emac_res_vlan; /* Reserved VLAN for DualEMAC */ + struct phy *ifphy; }; struct cpsw_platform_data { @@ -1502,7 +1504,11 @@ static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) phy_start(slave->phy); /* Configure GMII_SEL register */ - cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num); + if (!IS_ERR(slave->data->ifphy)) + phy_set_netif_mode(slave->data->ifphy, slave->data->phy_if); + else + cpsw_phy_sel(cpsw->dev, slave->phy->interface, + slave->slave_num); } static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) @@ -3135,6 +3141,16 @@ static int cpsw_probe_dt(struct cpsw_platform_data *data, if (strcmp(slave_node->name, "slave")) continue; + slave_data->ifphy = devm_of_phy_get(&pdev->dev, slave_node, + NULL); + if (!IS_ENABLED(CONFIG_TI_CPSW_PHY_SEL) && + IS_ERR(slave_data->ifphy)) { + ret = PTR_ERR(slave_data->ifphy); + dev_err(&pdev->dev, + "%d: Error retrieving port phy: %d\n", i, ret); + return ret; + } + slave_data->phy_node = of_parse_phandle(slave_node, "phy-handle", 0); parp = of_get_property(slave_node, "phy_id", &lenp); From patchwork Mon Oct 8 23:49:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 148473 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp4243635lji; Mon, 8 Oct 2018 16:50:54 -0700 (PDT) X-Google-Smtp-Source: ACcGV60Rtp3UHiVbd3/cbXB5OfEZtfUVShzHgHIPn8qV+oTHDzyp35bOLmIsbxrPG5SKcma7Suj9 X-Received: by 2002:a62:d206:: with SMTP id c6-v6mr7262401pfg.8.1539042654425; Mon, 08 Oct 2018 16:50:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539042654; cv=none; d=google.com; s=arc-20160816; b=xQLpjAXLydJ51BHgt/kRKCUtyk+ZJ24zk+FrE0UGVLYvIeOVBDVvw6tI3C2Kfao8l1 D12Tg4wgK4zFYeeAX60KA5POKckDb4IkUzGo0SHH8VxNbNz4LjKUnAKBQ57ZK+GjqnDA +3LflRcgIcznarVtsUHbpRiqIilRq3zXaeqUblmZvqrSdT2czez8qOOCC6LcQrOIftSc z23mcnj/mHnRFRQlm8wYY+VKjYiZCUwHvSWfvTjxhrJV7HLXvT5FXJI09Hmay+aLIW/G VdRJms5rOckbmY7UaznVvMnsIfxiwrPDRtqsjg+92wXVLM1BDjn1i2bNFcH3c2rywoDu LcQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=9cZr7Nn2/H3Cn+hGCY3taoQux5m7n9inHKQE01z0P+o=; b=LcoBX8vrH5DVFqQQ1EZGuwwEOAebOq7fuwCSzAzLmrVRAJtJu8pciP+xvdRumdkR6w mPhvvG3ME+GfioBFrLWQFLbC9YYGIY4Lq5XhMKVz1Qtlzc4TOkG54eYjOY6BBT1iXnkg d4MB9eYiw5FKQ6ZFXI+njencQ3HCjnAPsRKCYyHTvxLto4Zmjo9epl71HxZK33w5agvN WHKmuSXGTCCb7LJEY0EemhOqwFXZDnSOz9KrwFtvgJ0YsXWbi+j6BLVcTDO6XZF+JK4s HFYJ9wSqPbCS+095rsM0llyQf/TSEGZoAguZCDKT8wUMjHVzTxoO07ktqCIL4bMmA27d ycDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=xDuWurKl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , , Tony Lindgren , Rob Herring , Kishon Vijay Abraham I CC: Sekhar Nori , , , , Grygorii Strashko Subject: [RFC PATCH 06/11] ARM: dts: dra7: switch to use phy-gmii-sel Date: Mon, 8 Oct 2018 18:49:44 -0500 Message-ID: <20181008234949.15416-7-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.10.5 In-Reply-To: <20181008234949.15416-1-grygorii.strashko@ti.com> References: <20181008234949.15416-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Switch to use phy-gmii-sel PHY instead of cpsw-phy-sel. Cc: Kishon Vijay Abraham I Cc: Tony Lindgren Signed-off-by: Grygorii Strashko --- arch/arm/boot/dts/dra7.dtsi | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) -- 2.10.5 diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index a0ddf49..07a0edf 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -187,6 +187,12 @@ }; }; + phy_gmii_sel: phy-gmii-sel { + compatible = "ti,dra7xx-phy-gmii-sel"; + syscon-scm = <&scm_conf>; + #phy-cells = <1>; + }; + scm_conf_clocks: clocks { #address-cells = <1>; #size-cells = <0>; @@ -1879,17 +1885,13 @@ cpsw_emac0: slave@48480200 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1>; }; cpsw_emac1: slave@48480300 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; - }; - - phy_sel: cpsw-phy-sel@4a002554 { - compatible = "ti,dra7xx-cpsw-phy-sel"; - reg= <0x4a002554 0x4>; - reg-names = "gmii-sel"; + phys = <&phy_gmii_sel 2>; }; }; From patchwork Mon Oct 8 23:49:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 148475 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp4244016lji; Mon, 8 Oct 2018 16:51:30 -0700 (PDT) X-Google-Smtp-Source: ACcGV61vOqkhfsvo6s8Cvx705EH9wy+4JSMigc6zCF9WWmEdrWobrj9V934dQnHcPV5w5x0syIJ+ X-Received: by 2002:a63:3507:: with SMTP id c7-v6mr22865162pga.158.1539042690640; Mon, 08 Oct 2018 16:51:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539042690; cv=none; d=google.com; s=arc-20160816; b=AbDZgrer47o6yA5xHt7fiYn9cibkHli05ntuuI94HNVCbM/dknI237nj23Zg+CmOTF 0XlqnBsJUcZRaWaCuCebhGa2+fwW/77uS7hBMJQl7/f8fib1Lqjf6qGFrU9uA7COrROi NztyQNfWrhV161G7sRw/R87NMghtJvDqJoJJBM1tedXiIrBFrPZCSQ5HJt3O/r91X7Zi r8Ek8WRi5U4qMybhO6PRdXUfS/8ZhJUMzrPWUIpDPWBygBoBvBzzWp1ktarMB6BeeWpK KsA7zb6A7AN7WjNpC/PSNkY+kexLOuIO3vOc5SeKvDGJmRS8UjYfIICEy//bpupOG4aA cU5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=rp9yeZQyHs0zKorGtui/WZyQj6Qvx1sg2vu+2CFPDMU=; b=IQ+MxTgTc2ZqOG7L4Ap55xiDCU01doTntR1lSTc1F0IWrxuPVes6KZkM7tyY3oBba8 YZIxcXPgnZOWDRif8jSi1CEtT5a0lojuL9EWOPmpB3f4TL8PTQ4k5e7tKtTV+wkW2ODd 6I2gL+fB40x96qAPWD/WlzCWH9rQxddvK/AMBZoJbVP/N86o/braFCmnjVHhCXudEFA0 y+LWPyo/THVArzLvIjvUZeSIgGskOANbuXQU+V4Mq8fpBY/Nu/ctWuVivGTaww8t5ATP URyv4q0/RH25MpvufsKAgzwcf1vke1sNFsTrKm3BY2LQHpf4OOmAskqXlNstqPM/uP8L kWJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=AtUbDIpl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , , Tony Lindgren , Rob Herring , Kishon Vijay Abraham I CC: Sekhar Nori , , , , Grygorii Strashko Subject: [RFC PATCH 08/11] ARM: dts: am4372: switch to use phy-gmii-sel Date: Mon, 8 Oct 2018 18:49:46 -0500 Message-ID: <20181008234949.15416-9-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.10.5 In-Reply-To: <20181008234949.15416-1-grygorii.strashko@ti.com> References: <20181008234949.15416-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Switch to use phy-gmii-sel PHY instead of cpsw-phy-sel. Cc: Kishon Vijay Abraham I Cc: Tony Lindgren Signed-off-by: Grygorii Strashko --- arch/arm/boot/dts/am4372.dtsi | 16 +++++++++------- arch/arm/boot/dts/am43x-epos-evm.dts | 5 +---- 2 files changed, 10 insertions(+), 11 deletions(-) -- 2.10.5 diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index d4b7c59..3dd6d2e 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -212,11 +212,17 @@ }; scm_conf: scm_conf@0 { - compatible = "syscon"; + compatible = "syscon", "simple-bus"; reg = <0x0 0x800>; #address-cells = <1>; #size-cells = <1>; + phy_gmii_sel: phy-gmii-sel { + compatible = "ti,am43xx-phy-gmii-sel"; + syscon-scm = <&scm_conf>; + #phy-cells = <2>; + }; + scm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; @@ -714,17 +720,13 @@ cpsw_emac0: slave@4a100200 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1 0>; }; cpsw_emac1: slave@4a100300 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; - }; - - phy_sel: cpsw-phy-sel@44e10650 { - compatible = "ti,am43xx-cpsw-phy-sel"; - reg= <0x44e10650 0x4>; - reg-names = "gmii-sel"; + phys = <&phy_gmii_sel 2 0>; }; }; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 6502d33..8677f4a 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -580,10 +580,7 @@ &cpsw_emac0 { phy_id = <&davinci_mdio>, <16>; phy-mode = "rmii"; -}; - -&phy_sel { - rmii-clock-ext; + phys = <&phy_gmii_sel 1 1>; }; &i2c0 { From patchwork Mon Oct 8 23:49:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grygorii Strashko X-Patchwork-Id: 148465 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp4243021lji; Mon, 8 Oct 2018 16:50:01 -0700 (PDT) X-Google-Smtp-Source: ACcGV60VO8jMQwI1EufTPH4c/9p//fY7tnWo2FDYffRhU6Ngd2QjVEHJDqKQLqzPscx0/X6IkeK+ X-Received: by 2002:aa7:8281:: with SMTP id s1-v6mr26979213pfm.63.1539042601371; Mon, 08 Oct 2018 16:50:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539042601; cv=none; d=google.com; s=arc-20160816; b=pJNPJr5s2RcJiPhQYVJFA8Ys8TKMA/docQw7Dn+oJHn2XsOuQl+J7yW9sjyd/WSrUV DHrhp/63KEwMFgQRBk6gnRjjCZyq5DW+xHKnkZ1JKNCSej2y/0LkHmhatfIq6NWv4xK6 pRjKg6Hy5Q2Tccx3z99AQ1KAtJtpozDtuSLCVBmHRQ0I//y+kxRE/et4f6LZUjN4AR4B f3y7BmGGolwkDWujIcp6P2D37tDZsLsSn8SdBhgxXGq4KFS38FBI6ZDkJ2WLg8eQEVvD zm9qIBwXth68Bmx1GFjgCe9wJud1dJbGiLOTK+NrpWQW0jm+KhkgTo1zfwMsc/4mEz7g NR4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=wL/p1xowDla28x2ETkZQaanZgPfzVV7FK2duJyx2Hj8=; b=DaO294Sbj18UEpbhPN3f9bRhk1Yma3DwBBidVeuHG0bnHRegVVBreGQ1vu2xgcg8yq 2R2/XbHCTEL+PLfnVXWAHM06RWonromR2N9DoY5jooLOKWALwCcY+M+BbvJN19Q+R8n4 ZtnAWzStXZ94VInHcYAZuksJyaI0ckvQs+ecTKRe7ttGzCNvpQF6P4IomFnLbF7R/vWZ ExeK3OtMv9jJrzbjAaIaqA8TEVmA1lDUkF+POTMDq0JT5/BzJiA5vXDru1NXVmLEFyae 6CeIVqe+9TvL8e+df4WOl4AU7Luauv8H79048w71taKMmSkUkzoA8SDcepjy4Yoq0eR9 x80g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=QUoLjsty; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Miller" , , Tony Lindgren , Rob Herring , Kishon Vijay Abraham I CC: Sekhar Nori , , , , Grygorii Strashko Subject: [RFC PATCH 09/11] ARM: dts: am335x: switch to use phy-gmii-sel Date: Mon, 8 Oct 2018 18:49:47 -0500 Message-ID: <20181008234949.15416-10-grygorii.strashko@ti.com> X-Mailer: git-send-email 2.10.5 In-Reply-To: <20181008234949.15416-1-grygorii.strashko@ti.com> References: <20181008234949.15416-1-grygorii.strashko@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Switch to use phy-gmii-sel PHY instead of cpsw-phy-sel. Cc: Kishon Vijay Abraham I Cc: Tony Lindgren Signed-off-by: Grygorii Strashko --- arch/arm/boot/dts/am335x-baltos-ir2110.dts | 4 ---- arch/arm/boot/dts/am335x-baltos-ir3220.dts | 3 --- arch/arm/boot/dts/am335x-baltos-ir5221.dts | 3 --- arch/arm/boot/dts/am335x-chiliboard.dts | 3 --- arch/arm/boot/dts/am335x-icev2.dts | 4 ---- arch/arm/boot/dts/am335x-igep0033.dtsi | 3 --- arch/arm/boot/dts/am335x-lxm.dts | 3 --- arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts | 5 ----- arch/arm/boot/dts/am335x-phycore-som.dtsi | 3 --- arch/arm/boot/dts/am33xx.dtsi | 14 ++++++++------ 10 files changed, 8 insertions(+), 37 deletions(-) -- 2.10.5 diff --git a/arch/arm/boot/dts/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/am335x-baltos-ir2110.dts index 75de1e7..50dcf12 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir2110.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir2110.dts @@ -72,7 +72,3 @@ dual_emac_res_vlan = <2>; phy-handle = <&phy1>; }; - -&phy_sel { - rmii-clock-ext = <1>; -}; diff --git a/arch/arm/boot/dts/am335x-baltos-ir3220.dts b/arch/arm/boot/dts/am335x-baltos-ir3220.dts index 1b215c4..44f7858 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir3220.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir3220.dts @@ -115,6 +115,3 @@ phy-handle = <&phy1>; }; -&phy_sel { - rmii-clock-ext = <1>; -}; diff --git a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/am335x-baltos-ir5221.dts index 832ead8..1e10813 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir5221.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir5221.dts @@ -133,9 +133,6 @@ phy-handle = <&phy1>; }; -&phy_sel { - rmii-clock-ext = <1>; -}; &dcan1 { pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/am335x-chiliboard.dts b/arch/arm/boot/dts/am335x-chiliboard.dts index 59431b2..7b77315 100644 --- a/arch/arm/boot/dts/am335x-chiliboard.dts +++ b/arch/arm/boot/dts/am335x-chiliboard.dts @@ -147,9 +147,6 @@ phy-mode = "rmii"; }; -&phy_sel { - rmii-clock-ext; -}; /* USB */ &usb { diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts index f2005ec..9ac775c 100644 --- a/arch/arm/boot/dts/am335x-icev2.dts +++ b/arch/arm/boot/dts/am335x-icev2.dts @@ -484,10 +484,6 @@ dual_emac; }; -&phy_sel { - rmii-clock-ext; -}; - &davinci_mdio { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi index a5769a8..2bc8456 100644 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ b/arch/arm/boot/dts/am335x-igep0033.dtsi @@ -114,9 +114,6 @@ phy-mode = "rmii"; }; -&phy_sel { - rmii-clock-ext; -}; &elm { status = "okay"; diff --git a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/am335x-lxm.dts index 1d6c6fa..56b354b1 100644 --- a/arch/arm/boot/dts/am335x-lxm.dts +++ b/arch/arm/boot/dts/am335x-lxm.dts @@ -328,9 +328,6 @@ dual_emac_res_vlan = <3>; }; -&phy_sel { - rmii-clock-ext; -}; &mac { pinctrl-names = "default", "sleep"; diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts index f82233c..5563e92 100644 --- a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts +++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts @@ -438,11 +438,6 @@ dual_emac_res_vlan = <2>; }; -&phy_sel { - reg= <0x44e10650 0xf5>; - rmii-clock-ext; -}; - &sham { status = "okay"; }; diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/am335x-phycore-som.dtsi index 428a25e..cf40a2b 100644 --- a/arch/arm/boot/dts/am335x-phycore-som.dtsi +++ b/arch/arm/boot/dts/am335x-phycore-som.dtsi @@ -100,9 +100,6 @@ status = "okay"; }; -&phy_sel { - rmii-clock-ext; -}; /* I2C Busses */ &am33xx_pinmux { diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index d3dd6a1..3179b24 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -222,6 +222,12 @@ #size-cells = <1>; ranges = <0 0 0x800>; + phy_gmii_sel: phy-gmii-sel { + compatible = "ti,am3352-phy-gmii-sel"; + syscon-scm = <&scm_conf>; + #phy-cells = <2>; + }; + scm_clocks: clocks { #address-cells = <1>; #size-cells = <0>; @@ -890,17 +896,13 @@ cpsw_emac0: slave@4a100200 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; + phys = <&phy_gmii_sel 1 1>; }; cpsw_emac1: slave@4a100300 { /* Filled in by U-Boot */ mac-address = [ 00 00 00 00 00 00 ]; - }; - - phy_sel: cpsw-phy-sel@44e10650 { - compatible = "ti,am3352-cpsw-phy-sel"; - reg= <0x44e10650 0x4>; - reg-names = "gmii-sel"; + phys = <&phy_gmii_sel 2 1>; }; };