From patchwork Tue Aug 24 11:54:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 501893 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D89D7C4320A for ; Tue, 24 Aug 2021 11:55:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C018F611F0 for ; Tue, 24 Aug 2021 11:55:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236670AbhHXL4O (ORCPT ); Tue, 24 Aug 2021 07:56:14 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:20919 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236650AbhHXL4O (ORCPT ); Tue, 24 Aug 2021 07:56:14 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1629806131; x=1661342131; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nvQXMiaPy2VuNQO50RLteRfILBr98vNnCM+YLfLiMik=; b=GXAI3+YUqRs7Sndc+mBBMy3orUyeGQEz9ik/h1vwaCazN9FgWcSxiMj1 DPrG07NjYRqmiHfv4AxdfO2e6SMg+vd6ZDxoe4eTTQVVl7sucl63QMFoK AvdaaStsUoPQbKZD9nw+GhonlZ04wBcpYxBeAzPiTfqAGBpIiV4QrIgSA Vmj5z+eDPn/RcKFQsGaRqajg1MYXR5/Q4Z9IzY01uFdkK76KQMu60pZ3L eYz+GbZ+WkxeS8VmEeZcTn2O9zMNwyxXn5TdCy2hFzk5Y8q63919P2jhF C3AbjWJ/6Z6IZlMManjoOZvORmuJcNlBGytJlBsSjEDMBh3+Wf4kIi+kX Q==; IronPort-SDR: 6nPG1Al6NEDaXSpPdGdoVRRm6Hi4pWaBvvs6si5FpIn+sJSk/P6n4jbLO1f2vgB4Edld59Va2K 3LAgxeMLWOw/huylvtwDj8zSVrPfPqWTiZSSEdXv65nGffvxP0M7DSaPfSDa7lDPsyKVzfZZaF 4pGLEkzzeYrORjjwTx5zgbEHQquYFEW4c+t/4y/eCXmwx6LzIY0Riq+eboTIjqkK8eNcu+Neto bj071yJsx50L34yivs1QsdYqbuqH9SmjnWBsPyanNgSGO3RkO1Ltyzvg0QuFkhSApEgrZNHxai JWtd9X7OFfQOW2j2sWwWN/aV X-IronPort-AV: E=Sophos;i="5.84,347,1620716400"; d="scan'208";a="133408028" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 24 Aug 2021 04:55:30 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 24 Aug 2021 04:55:29 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 24 Aug 2021 04:55:18 -0700 From: Eugen Hristev To: , , , CC: , , , , Eugen Hristev Subject: [PATCH v2 02/10] iio: adc: at91-sama5d2_adc: initialize hardware after clock is started Date: Tue, 24 Aug 2021 14:54:33 +0300 Message-ID: <20210824115441.681253-3-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210824115441.681253-1-eugen.hristev@microchip.com> References: <20210824115441.681253-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The hw_init hardware init call must happen after the clock is prepared and enabled. Otherwise, writing to the registers might lead to a block or external abort. Signed-off-by: Eugen Hristev --- drivers/iio/adc/at91-sama5d2_adc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index ea5ca163d879..1f4d461c2c18 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -1833,12 +1833,12 @@ static int at91_adc_probe(struct platform_device *pdev) goto vref_disable; } - at91_adc_hw_init(indio_dev); - ret = clk_prepare_enable(st->per_clk); if (ret) goto vref_disable; + at91_adc_hw_init(indio_dev); + platform_set_drvdata(pdev, indio_dev); ret = at91_adc_buffer_and_trigger_init(&pdev->dev, indio_dev); From patchwork Tue Aug 24 11:54:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 501892 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC3CFC4320A for ; Tue, 24 Aug 2021 11:56:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D59E260EE0 for ; Tue, 24 Aug 2021 11:56:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237055AbhHXL44 (ORCPT ); Tue, 24 Aug 2021 07:56:56 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:23272 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237095AbhHXL4u (ORCPT ); Tue, 24 Aug 2021 07:56:50 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1629806167; x=1661342167; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qW8KAnZWqVWyEk8YWpmG05BOTuKIoV+MBdVsrB4eYEI=; b=lKro4fc7LK8/ouizPWs5YJIu+F9J3Vr5+7TUs64943c/Ma7T/ZoTwT+7 vWU9EKb60BcNhci4svBbuMAiBMtKZcT6k2j09ekgDg7Xllm4TZMc3lJwd rOzHIUtsr1Pi6eLg72uDHLhld266Mu4snF05sI0Ynl9bVUP0RoKd7a86Z kbwqX32WqxjzfoOKReUduGYmq7jUFq6mMlW20uPxoS8QuuWRRZYcSbHDm 8nqXib8EC82mDI4xn1FM0GBX7g3lo4kyEHAYhxpuEFPATsubr758JkPxw CCc95OH5XUIxYcA9z0QXXPZI3fO4rE/QccrLZNk6A1KyaUIfTee3qx6Dl Q==; IronPort-SDR: Hrk2LLzY/eHEwtHW+yRZLI6Gy9f8o987RkgHU7lcFxGNvguHfYwOIwIHILYzUWl6lEk+CbgU2R Us9sT+/Zrb8yL+hbsjzv5BWoZq9nBSrNxZfhUoZqlNNEZ9xkpdJTTle0NAFAzoA+PivMbpr59o OMlImnf7uLK/NVGo603yMzx+z2xkDlEKhONZo2WLobmFIyPovjUuSRKUpfwRIHHfenrX+4jMLj AW1g2jhiBu6uaHoM0j7OauOy4IptcLBzqR2cAq3pRXCUoMTflV22T3fUu7v8/K1rOPJ/Q2I5Ph +iLfVPXrJXgit6N/tot/cCb3 X-IronPort-AV: E=Sophos;i="5.84,347,1620716400"; d="scan'208";a="126884960" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 24 Aug 2021 04:56:02 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 24 Aug 2021 04:56:02 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 24 Aug 2021 04:55:47 -0700 From: Eugen Hristev To: , , , CC: , , , , Eugen Hristev Subject: [PATCH v2 05/10] iio: adc: at91-sama5d2-adc: add support for separate end of conversion registers Date: Tue, 24 Aug 2021 14:54:36 +0300 Message-ID: <20210824115441.681253-6-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210824115441.681253-1-eugen.hristev@microchip.com> References: <20210824115441.681253-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some platforms have separated the end-of-conversion information from the usual ISR/IMR/IER/IDR registers, into EOC_ISR/EOC_IMR/EOC_IER/EOC_IDR. To cope with both variants, helpers are being added, that will make code more clear and more easy to read. Signed-off-by: Eugen Hristev --- drivers/iio/adc/at91-sama5d2_adc.c | 66 ++++++++++++++++++++++++++---- 1 file changed, 59 insertions(+), 7 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index 8ede18b8d789..23be7cec063e 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -117,6 +117,14 @@ struct at91_adc_reg_layout { u16 IMR; /* Interrupt Status Register */ u16 ISR; +/* End of Conversion Interrupt Enable Register */ + u16 EOC_IER; +/* End of Conversion Interrupt Disable Register */ + u16 EOC_IDR; +/* End of Conversion Interrupt Mask Register */ + u16 EOC_IMR; +/* End of Conversion Interrupt Status Register */ + u16 EOC_ISR; /* Interrupt Status Register - Pen touching sense status */ #define AT91_SAMA5D2_ISR_PENS BIT(31) /* Last Channel Trigger Mode Register */ @@ -581,6 +589,44 @@ static unsigned int at91_adc_active_scan_mask_to_reg(struct iio_dev *indio_dev) return mask & GENMASK(st->soc_info.platform->nr_channels, 0); } +static void at91_adc_irq_status(struct at91_adc_state *st, u32 *status, + u32 *eoc) +{ + *status = at91_adc_readl(st, ISR); + if (st->soc_info.platform->layout->EOC_ISR) + *eoc = at91_adc_readl(st, EOC_ISR); + else + *eoc = *status; +} + +static void at91_adc_irq_mask(struct at91_adc_state *st, u32 *status, u32 *eoc) +{ + *status = at91_adc_readl(st, IMR); + if (st->soc_info.platform->layout->EOC_IMR) + *eoc = at91_adc_readl(st, EOC_IMR); + else + *eoc = *status; +} + +static void at91_adc_eoc_dis(struct at91_adc_state *st, unsigned int channel) +{ + /* + * On some products having the EOC bits in a separate register, + * errata recommends not writing this register (EOC_IDR). + * On products having the EOC bits in the IDR register, it's fine to write it. + */ + if (!st->soc_info.platform->layout->EOC_IDR) + at91_adc_writel(st, IDR, BIT(channel)); +} + +static void at91_adc_eoc_ena(struct at91_adc_state *st, unsigned int channel) +{ + if (!st->soc_info.platform->layout->EOC_IDR) + at91_adc_writel(st, IER, BIT(channel)); + else + at91_adc_writel(st, EOC_IER, BIT(channel)); +} + static void at91_adc_config_emr(struct at91_adc_state *st) { /* configure the extended mode register */ @@ -1100,13 +1146,15 @@ static void at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev, u8 bit; u32 mask = at91_adc_active_scan_mask_to_reg(indio_dev); unsigned int timeout = 50; + u32 status, imr, eoc = 0, eoc_imr; /* * Check if the conversion is ready. If not, wait a little bit, and * in case of timeout exit with an error. */ - while ((at91_adc_readl(st, ISR) & mask) != mask && - timeout) { + while (((eoc & mask) != mask) && timeout) { + at91_adc_irq_status(st, &status, &eoc); + at91_adc_irq_mask(st, &imr, &eoc_imr); usleep_range(50, 100); timeout--; } @@ -1342,12 +1390,14 @@ static irqreturn_t at91_adc_interrupt(int irq, void *private) { struct iio_dev *indio = private; struct at91_adc_state *st = iio_priv(indio); - u32 status = at91_adc_readl(st, ISR); - u32 imr = at91_adc_readl(st, IMR); + u32 status, eoc, imr, eoc_imr; u32 rdy_mask = AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY | AT91_SAMA5D2_IER_PRDY; - if (!(status & imr)) + at91_adc_irq_status(st, &status, &eoc); + at91_adc_irq_mask(st, &imr, &eoc_imr); + + if (!(status & imr) && !(eoc & eoc_imr)) return IRQ_NONE; if (status & AT91_SAMA5D2_IER_PEN) { /* pen detected IRQ */ @@ -1441,7 +1491,7 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev, at91_adc_writel(st, COR, cor); at91_adc_writel(st, CHER, BIT(chan->channel)); - at91_adc_writel(st, IER, BIT(chan->channel)); + at91_adc_eoc_ena(st, chan->channel); at91_adc_writel(st, CR, AT91_SAMA5D2_CR_START); ret = wait_event_interruptible_timeout(st->wq_data_available, @@ -1458,7 +1508,7 @@ static int at91_adc_read_info_raw(struct iio_dev *indio_dev, st->conversion_done = false; } - at91_adc_writel(st, IDR, BIT(chan->channel)); + at91_adc_eoc_dis(st, st->chan->channel); at91_adc_writel(st, CHDR, BIT(chan->channel)); /* Needed to ACK the DRDY interruption */ @@ -1676,6 +1726,8 @@ static void at91_adc_hw_init(struct iio_dev *indio_dev) struct at91_adc_state *st = iio_priv(indio_dev); at91_adc_writel(st, CR, AT91_SAMA5D2_CR_SWRST); + if (st->soc_info.platform->layout->EOC_IDR) + at91_adc_writel(st, EOC_IDR, 0xffffffff); at91_adc_writel(st, IDR, 0xffffffff); /* * Transfer field must be set to 2 according to the datasheet and From patchwork Tue Aug 24 11:54:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 501891 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91ED3C4320A for ; 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IronPort-SDR: HiHKPZpeRDBX4xcDtX7bINfg9KyhALmckMhKrpleMxM8yS/ls0XLbs7UxyiKxHLZnP7jiTi2NZ 35NMR+6+wX0y+NRBwu8q1bmMaACvdN+ZAgfPeVL+Lm5JlzP66+Jwq1xU4scgW7HBONNbMSLWh0 y5sfq9Bkou0aBZVdbzG9sisOiCbzjE16Gbcz+HEJgl/zaT2v/hKvbbk3QwTxlC7IVN8jHluoVI 2AG8vawf1Qv9qwFL4zNS37H8LmZEsgJ5Y2lnZvEvxQvIhH8TmfWjbaO0HZ0y+cKNgmX6rOohMn 5mu21dk9GBOBSgMERjrLkeYj X-IronPort-AV: E=Sophos;i="5.84,347,1620716400"; d="scan'208";a="66906609" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 24 Aug 2021 04:56:33 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 24 Aug 2021 04:56:33 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 24 Aug 2021 04:56:22 -0700 From: Eugen Hristev To: , , , CC: , , , , Eugen Hristev Subject: [PATCH v2 07/10] iio: adc: at91-sama5d2_adc: add support for sama7g5 device Date: Tue, 24 Aug 2021 14:54:38 +0300 Message-ID: <20210824115441.681253-8-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210824115441.681253-1-eugen.hristev@microchip.com> References: <20210824115441.681253-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support to sama7g5 ADC which is similar with sama5d2/sam9x60 device. Differences are highlighted by compatible. Main differences include 16 channels instead of 12 and missing resistive touchscreen. Signed-off-by: Eugen Hristev --- drivers/iio/adc/at91-sama5d2_adc.c | 77 ++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index bb4e5e1e3ce4..f3f5230eac54 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -261,6 +261,38 @@ static const struct at91_adc_reg_layout sama5d2_layout = { .VERSION = 0xfc, }; +static const struct at91_adc_reg_layout sama7g5_layout = { + .CR = 0x00, + .MR = 0x04, + .SEQR1 = 0x08, + .SEQR2 = 0x0c, + .CHER = 0x10, + .CHDR = 0x14, + .CHSR = 0x18, + .LCDR = 0x20, + .IER = 0x24, + .IDR = 0x28, + .IMR = 0x2c, + .ISR = 0x30, + .EOC_IER = 0x34, + .EOC_IDR = 0x38, + .EOC_IMR = 0x3c, + .EOC_ISR = 0x40, + .OVER = 0x4c, + .EMR = 0x50, + .CWR = 0x54, + .COR = 0x5c, + .COR_diff_offset = 0, + .ACR = 0xe0, + .TRGR = 0x100, + .COSR = 0x104, + .CVR = 0x108, + .CECR = 0x10c, + .WPMR = 0x118, + .WPSR = 0x11c, + .VERSION = 0x130, +}; + #define AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */ #define AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US 200 @@ -527,6 +559,34 @@ static const struct iio_chan_spec at91_sama5d2_adc_channels[] = { AT91_SAMA5D2_CHAN_PRESSURE(21, "pressure"), }; +static const struct iio_chan_spec at91_sama7g5_adc_channels[] = { + AT91_SAMA5D2_CHAN_SINGLE(0, 0, 0x60), + AT91_SAMA5D2_CHAN_SINGLE(1, 1, 0x64), + AT91_SAMA5D2_CHAN_SINGLE(2, 2, 0x68), + AT91_SAMA5D2_CHAN_SINGLE(3, 3, 0x6c), + AT91_SAMA5D2_CHAN_SINGLE(4, 4, 0x70), + AT91_SAMA5D2_CHAN_SINGLE(5, 5, 0x74), + AT91_SAMA5D2_CHAN_SINGLE(6, 6, 0x78), + AT91_SAMA5D2_CHAN_SINGLE(7, 7, 0x7c), + AT91_SAMA5D2_CHAN_SINGLE(8, 8, 0x80), + AT91_SAMA5D2_CHAN_SINGLE(9, 9, 0x84), + AT91_SAMA5D2_CHAN_SINGLE(10, 10, 0x88), + AT91_SAMA5D2_CHAN_SINGLE(11, 11, 0x8c), + AT91_SAMA5D2_CHAN_SINGLE(12, 12, 0x90), + AT91_SAMA5D2_CHAN_SINGLE(13, 13, 0x94), + AT91_SAMA5D2_CHAN_SINGLE(14, 14, 0x98), + AT91_SAMA5D2_CHAN_SINGLE(15, 15, 0x9c), + AT91_SAMA5D2_CHAN_DIFF(16, 0, 1, 0x60), + AT91_SAMA5D2_CHAN_DIFF(17, 2, 3, 0x68), + AT91_SAMA5D2_CHAN_DIFF(18, 4, 5, 0x70), + AT91_SAMA5D2_CHAN_DIFF(19, 6, 7, 0x78), + AT91_SAMA5D2_CHAN_DIFF(20, 8, 9, 0x80), + AT91_SAMA5D2_CHAN_DIFF(21, 10, 11, 0x88), + AT91_SAMA5D2_CHAN_DIFF(22, 12, 13, 0x90), + AT91_SAMA5D2_CHAN_DIFF(23, 14, 15, 0x98), + IIO_CHAN_SOFT_TIMESTAMP(24), +}; + static const struct at91_adc_platform sama5d2_platform = { .layout = &sama5d2_layout, .adc_channels = &at91_sama5d2_adc_channels, @@ -547,6 +607,20 @@ static const struct at91_adc_platform sama5d2_platform = { .hw_trig_cnt = AT91_SAMA5D2_HW_TRIG_CNT, }; +static const struct at91_adc_platform sama7g5_platform = { + .layout = &sama7g5_layout, + .adc_channels = &at91_sama7g5_adc_channels, +#define AT91_SAMA7G5_SINGLE_CHAN_CNT 16 +#define AT91_SAMA7G5_DIFF_CHAN_CNT 8 + .nr_channels = AT91_SAMA7G5_SINGLE_CHAN_CNT + + AT91_SAMA7G5_DIFF_CHAN_CNT, +#define AT91_SAMA7G5_MAX_CHAN_IDX (AT91_SAMA7G5_SINGLE_CHAN_CNT + \ + AT91_SAMA7G5_DIFF_CHAN_CNT) + .max_channels = ARRAY_SIZE(at91_sama7g5_adc_channels), +#define AT91_SAMA7G5_HW_TRIG_CNT 3 + .hw_trig_cnt = AT91_SAMA7G5_HW_TRIG_CNT, +}; + static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan) { int i; @@ -2094,6 +2168,9 @@ static const struct of_device_id at91_adc_dt_match[] = { { .compatible = "atmel,sama5d2-adc", .data = (const void *)&sama5d2_platform, + }, { + .compatible = "microchip,sama7g5-adc", + .data = (const void *)&sama7g5_platform, }, { /* sentinel */ } From patchwork Tue Aug 24 11:54:40 2021 Content-Type: text/plain; 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d="scan'208";a="66906623" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 24 Aug 2021 04:56:48 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 24 Aug 2021 04:56:48 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 24 Aug 2021 04:56:45 -0700 From: Eugen Hristev To: , , , CC: , , , , Eugen Hristev Subject: [PATCH v2 09/10] ARM: dts: at91: sama7g5: add node for the ADC Date: Tue, 24 Aug 2021 14:54:40 +0300 Message-ID: <20210824115441.681253-10-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210824115441.681253-1-eugen.hristev@microchip.com> References: <20210824115441.681253-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add node for the ADC controller in sama7g5 SoC. Signed-off-by: Eugen Hristev --- arch/arm/boot/dts/sama7g5.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index f9ad5365862f..de960519c72a 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -137,6 +137,22 @@ ps_wdt: watchdog@e001d180 { clocks = <&clk32k 0>; }; + adc: adc@e1000000 { + compatible = "microchip,sama7g5-adc"; + reg = <0xe1000000 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_GCK 26>; + assigned-clocks = <&pmc PMC_TYPE_GCK 26>; + assigned-clock-rates = <100000000>; + clock-names = "adc_clk"; + dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>; + dma-names = "rx"; + atmel,min-sample-rate-hz = <200000>; + atmel,max-sample-rate-hz = <20000000>; + atmel,startup-time-ms = <4>; + status = "disabled"; + }; + sdmmc0: mmc@e1204000 { compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci"; reg = <0xe1204000 0x4000>;