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[209.132.180.67]) by mx.google.com with ESMTP id g82-v6si24722203pfj.283.2018.10.08.12.14.40; Mon, 08 Oct 2018 12:14:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WdHU7cWW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727713AbeJIC1x (ORCPT + 32 others); Mon, 8 Oct 2018 22:27:53 -0400 Received: from mail-pg1-f182.google.com ([209.85.215.182]:45082 "EHLO mail-pg1-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727350AbeJIC1w (ORCPT ); Mon, 8 Oct 2018 22:27:52 -0400 Received: by mail-pg1-f182.google.com with SMTP id t70-v6so8231809pgd.12 for ; Mon, 08 Oct 2018 12:14:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7/25EuJDtf/QEtboufHLc/LTPTyST3xl75hOVYB9BTk=; b=WdHU7cWWZNFQDDOmHUoTkkKRLnWgezAbNmL7gEkkIgkl45DX5DOH/1GWWthrmkT7cW Pi1hVZoYBUpu13+Hb08qY57XK7jIJrEZJSj1FbYwaHZw4aFXbc6/E8KZSm/iTDdOYJWI /hpqkXrt4GBStUuC+K9beLAd1FMlH1xz9RVhg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7/25EuJDtf/QEtboufHLc/LTPTyST3xl75hOVYB9BTk=; b=Hgo/YXSJIBvstEglsKFAuB0JgUvTxWJ+TFz98/5hEIq5i/GT8G3i0xvVUdRV0M0swJ x0tW+Zt/dGHdtdxJvUNLJxdZxeJ9Y234EwuVXjrFF6hG9+4cdJLEKkwgIznWHK0oQwzG hmxu4w4qBCUxL/PWmvsxGUfA0guZ6ssB8WP/GnWQWzQzlgJpOELajda/l7g+um0IQdrF i3P1Oc5UsmX+qw1nWkroWELVpx4uZ1anIlJJJ6mdjXwzxI0bIrVivQmlze1xfuVLmp3p UUbwS7Ysd+/N11beTVsAfbqAckrd0hfYnMIdBVomRfjIwsr5eF11RtMHMV15HyJiEXyU ZhbQ== X-Gm-Message-State: ABuFfogK0QmAWZ3nceoc0BQxVStNbh5Xl/MnIkru+5EvT2U8gdrJp66j YegvZUssFNl58EEHahjY3Kc6 X-Received: by 2002:a63:141:: with SMTP id 62-v6mr21637579pgb.406.1539026076209; Mon, 08 Oct 2018 12:14:36 -0700 (PDT) Received: from localhost.localdomain ([2405:204:73c6:20ea:9fd:1785:d893:1e98]) by smtp.gmail.com with ESMTPSA id a15-v6sm15648035pff.8.2018.10.08.12.14.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 08 Oct 2018 12:14:35 -0700 (PDT) From: Manivannan Sadhasivam To: sean.wang@mediatek.com, linus.walleij@linaro.org, matthias.bgg@gmail.com, robh+dt@kernel.org Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, amit.kucheria@linaro.org, Manivannan Sadhasivam Subject: [PATCH 1/5] dt-bindings: pinctrl: Add devicetree constants for MT6797 SoC Date: Tue, 9 Oct 2018 00:44:07 +0530 Message-Id: <20181008191411.32555-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181008191411.32555-1-manivannan.sadhasivam@linaro.org> References: <20181008191411.32555-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add devicetree constants for Mediatek MT6797 SoC. Signed-off-by: Manivannan Sadhasivam --- include/dt-bindings/pinctrl/mt6797-pinfunc.h | 1368 ++++++++++++++++++ 1 file changed, 1368 insertions(+) create mode 100644 include/dt-bindings/pinctrl/mt6797-pinfunc.h -- 2.17.1 diff --git a/include/dt-bindings/pinctrl/mt6797-pinfunc.h b/include/dt-bindings/pinctrl/mt6797-pinfunc.h new file mode 100644 index 000000000000..e9813361b27c --- /dev/null +++ b/include/dt-bindings/pinctrl/mt6797-pinfunc.h @@ -0,0 +1,1368 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DTS_MT6797_PINFUNC_H +#define __DTS_MT6797_PINFUNC_H + +#include + +#define MT6797_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT6797_GPIO0__FUNC_CSI0A_L0P_T0A (MTK_PIN_NO(0) | 1) + +#define MT6797_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT6797_GPIO1__FUNC_CSI0A_L0N_T0B (MTK_PIN_NO(1) | 1) + +#define MT6797_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT6797_GPIO2__FUNC_CSI0A_L1P_T0C (MTK_PIN_NO(2) | 1) + +#define MT6797_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT6797_GPIO3__FUNC_CSI0A_L1N_T1A (MTK_PIN_NO(3) | 1) + +#define MT6797_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT6797_GPIO4__FUNC_CSI0A_L2P_T1B (MTK_PIN_NO(4) | 1) + +#define MT6797_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT6797_GPIO5__FUNC_CSI0A_L2N_T1C (MTK_PIN_NO(5) | 1) + +#define MT6797_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT6797_GPIO6__FUNC_CSI0B_L0P_T0A (MTK_PIN_NO(6) | 1) + +#define MT6797_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT6797_GPIO7__FUNC_CSI0B_L0N_T0B (MTK_PIN_NO(7) | 1) + +#define MT6797_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT6797_GPIO8__FUNC_CSI0B_L1P_T0C (MTK_PIN_NO(8) | 1) + +#define MT6797_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT6797_GPIO9__FUNC_CSI0B_L1N_T1A (MTK_PIN_NO(9) | 1) + +#define MT6797_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT6797_GPIO10__FUNC_CSI1A_L0P_T0A (MTK_PIN_NO(10) | 1) + +#define MT6797_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT6797_GPIO11__FUNC_CSI1A_L0N_T0B (MTK_PIN_NO(11) | 1) + +#define MT6797_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT6797_GPIO12__FUNC_CSI1A_L1P_T0C (MTK_PIN_NO(12) | 1) + +#define MT6797_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define MT6797_GPIO13__FUNC_CSI1A_L1N_T1A (MTK_PIN_NO(13) | 1) + +#define MT6797_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define MT6797_GPIO14__FUNC_CSI1A_L2P_T1B (MTK_PIN_NO(14) | 1) + +#define MT6797_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define MT6797_GPIO15__FUNC_CSI1A_L2N_T1C (MTK_PIN_NO(15) | 1) + +#define MT6797_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define MT6797_GPIO16__FUNC_CSI1B_L0P_T0A (MTK_PIN_NO(16) | 1) + +#define MT6797_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define MT6797_GPIO17__FUNC_CSI1B_L0N_T0B (MTK_PIN_NO(17) | 1) + +#define MT6797_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define MT6797_GPIO18__FUNC_CSI1B_L1P_T0C (MTK_PIN_NO(18) | 1) + +#define MT6797_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define MT6797_GPIO19__FUNC_CSI1B_L1N_T1A (MTK_PIN_NO(19) | 1) + +#define MT6797_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define MT6797_GPIO20__FUNC_CSI1B_L2P_T1B (MTK_PIN_NO(20) | 1) + +#define MT6797_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define MT6797_GPIO21__FUNC_CSI1B_L2N_T1C (MTK_PIN_NO(21) | 1) + +#define MT6797_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define MT6797_GPIO22__FUNC_CSI2_L0P_T0A (MTK_PIN_NO(22) | 1) + +#define MT6797_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define MT6797_GPIO23__FUNC_CSI2_L0N_T0B (MTK_PIN_NO(23) | 1) + +#define MT6797_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define MT6797_GPIO24__FUNC_CSI2_L1P_T0C (MTK_PIN_NO(24) | 1) + +#define MT6797_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define MT6797_GPIO25__FUNC_CSI2_L1N_T1A (MTK_PIN_NO(25) | 1) + +#define MT6797_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define MT6797_GPIO26__FUNC_CSI2_L2P_T1B (MTK_PIN_NO(26) | 1) + +#define MT6797_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define MT6797_GPIO27__FUNC_CSI2_L2N_T1C (MTK_PIN_NO(27) | 1) + +#define MT6797_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define MT6797_GPIO28__FUNC_SPI5_CLK_A (MTK_PIN_NO(28) | 1) +#define MT6797_GPIO28__FUNC_IRTX_OUT (MTK_PIN_NO(28) | 2) +#define MT6797_GPIO28__FUNC_UDI_TDO (MTK_PIN_NO(28) | 3) +#define MT6797_GPIO28__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(28) | 4) +#define MT6797_GPIO28__FUNC_CONN_MCU_TDO (MTK_PIN_NO(28) | 5) +#define MT6797_GPIO28__FUNC_PWM_A (MTK_PIN_NO(28) | 6) +#define MT6797_GPIO28__FUNC_C2K_DM_OTDO (MTK_PIN_NO(28) | 7) + +#define MT6797_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define MT6797_GPIO29__FUNC_SPI5_MI_A (MTK_PIN_NO(29) | 1) +#define MT6797_GPIO29__FUNC_DAP_SIB1_SWD (MTK_PIN_NO(29) | 2) +#define MT6797_GPIO29__FUNC_UDI_TMS (MTK_PIN_NO(29) | 3) +#define MT6797_GPIO29__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(29) | 4) +#define MT6797_GPIO29__FUNC_CONN_MCU_TMS (MTK_PIN_NO(29) | 5) +#define MT6797_GPIO29__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(29) | 6) +#define MT6797_GPIO29__FUNC_C2K_DM_OTMS (MTK_PIN_NO(29) | 7) + +#define MT6797_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define MT6797_GPIO30__FUNC_CMMCLK0 (MTK_PIN_NO(30) | 1) +#define MT6797_GPIO30__FUNC_MD_CLKM0 (MTK_PIN_NO(30) | 7) + +#define MT6797_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define MT6797_GPIO31__FUNC_CMMCLK1 (MTK_PIN_NO(31) | 1) +#define MT6797_GPIO31__FUNC_MD_CLKM1 (MTK_PIN_NO(31) | 7) + +#define MT6797_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define MT6797_GPIO32__FUNC_SPI5_CS_A (MTK_PIN_NO(32) | 1) +#define MT6797_GPIO32__FUNC_DAP_SIB1_SWCK (MTK_PIN_NO(32) | 2) +#define MT6797_GPIO32__FUNC_UDI_TCK_XI (MTK_PIN_NO(32) | 3) +#define MT6797_GPIO32__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(32) | 4) +#define MT6797_GPIO32__FUNC_CONN_MCU_TCK (MTK_PIN_NO(32) | 5) +#define MT6797_GPIO32__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(32) | 6) +#define MT6797_GPIO32__FUNC_C2K_DM_OTCK (MTK_PIN_NO(32) | 7) + +#define MT6797_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define MT6797_GPIO33__FUNC_SPI5_MO_A (MTK_PIN_NO(33) | 1) +#define MT6797_GPIO33__FUNC_CMFLASH (MTK_PIN_NO(33) | 2) +#define MT6797_GPIO33__FUNC_UDI_TDI (MTK_PIN_NO(33) | 3) +#define MT6797_GPIO33__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(33) | 4) +#define MT6797_GPIO33__FUNC_CONN_MCU_TDI (MTK_PIN_NO(33) | 5) +#define MT6797_GPIO33__FUNC_MD_URXD0 (MTK_PIN_NO(33) | 6) +#define MT6797_GPIO33__FUNC_C2K_DM_OTDI (MTK_PIN_NO(33) | 7) + +#define MT6797_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define MT6797_GPIO34__FUNC_CMFLASH (MTK_PIN_NO(34) | 1) +#define MT6797_GPIO34__FUNC_CLKM0 (MTK_PIN_NO(34) | 2) +#define MT6797_GPIO34__FUNC_UDI_NTRST (MTK_PIN_NO(34) | 3) +#define MT6797_GPIO34__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(34) | 4) +#define MT6797_GPIO34__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(34) | 5) +#define MT6797_GPIO34__FUNC_MD_UTXD0 (MTK_PIN_NO(34) | 6) +#define MT6797_GPIO34__FUNC_C2K_DM_JTINTP (MTK_PIN_NO(34) | 7) + +#define MT6797_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define MT6797_GPIO35__FUNC_CMMCLK3 (MTK_PIN_NO(35) | 1) +#define MT6797_GPIO35__FUNC_CLKM1 (MTK_PIN_NO(35) | 2) +#define MT6797_GPIO35__FUNC_MD_URXD1 (MTK_PIN_NO(35) | 3) +#define MT6797_GPIO35__FUNC_PTA_RXD (MTK_PIN_NO(35) | 4) +#define MT6797_GPIO35__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(35) | 5) +#define MT6797_GPIO35__FUNC_PWM_B (MTK_PIN_NO(35) | 6) +#define MT6797_GPIO35__FUNC_PCC_PPC_IO (MTK_PIN_NO(35) | 7) + +#define MT6797_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define MT6797_GPIO36__FUNC_CMMCLK2 (MTK_PIN_NO(36) | 1) +#define MT6797_GPIO36__FUNC_CLKM2 (MTK_PIN_NO(36) | 2) +#define MT6797_GPIO36__FUNC_MD_UTXD1 (MTK_PIN_NO(36) | 3) +#define MT6797_GPIO36__FUNC_PTA_TXD (MTK_PIN_NO(36) | 4) +#define MT6797_GPIO36__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(36) | 5) +#define MT6797_GPIO36__FUNC_PWM_C (MTK_PIN_NO(36) | 6) +#define MT6797_GPIO36__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(36) | 7) + +#define MT6797_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define MT6797_GPIO37__FUNC_SCL0_0 (MTK_PIN_NO(37) | 1) + +#define MT6797_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define MT6797_GPIO38__FUNC_SDA0_0 (MTK_PIN_NO(38) | 1) + +#define MT6797_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define MT6797_GPIO39__FUNC_DPI_D0 (MTK_PIN_NO(39) | 1) +#define MT6797_GPIO39__FUNC_SPI1_CLK_A (MTK_PIN_NO(39) | 2) +#define MT6797_GPIO39__FUNC_PCM0_SYNC (MTK_PIN_NO(39) | 3) +#define MT6797_GPIO39__FUNC_I2S0_LRCK (MTK_PIN_NO(39) | 4) +#define MT6797_GPIO39__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(39) | 5) +#define MT6797_GPIO39__FUNC_URXD3 (MTK_PIN_NO(39) | 6) +#define MT6797_GPIO39__FUNC_C2K_NTRST (MTK_PIN_NO(39) | 7) + +#define MT6797_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define MT6797_GPIO40__FUNC_DPI_D1 (MTK_PIN_NO(40) | 1) +#define MT6797_GPIO40__FUNC_SPI1_MI_A (MTK_PIN_NO(40) | 2) +#define MT6797_GPIO40__FUNC_PCM0_CLK (MTK_PIN_NO(40) | 3) +#define MT6797_GPIO40__FUNC_I2S0_BCK (MTK_PIN_NO(40) | 4) +#define MT6797_GPIO40__FUNC_CONN_MCU_TDO (MTK_PIN_NO(40) | 5) +#define MT6797_GPIO40__FUNC_UTXD3 (MTK_PIN_NO(40) | 6) +#define MT6797_GPIO40__FUNC_C2K_TCK (MTK_PIN_NO(40) | 7) + +#define MT6797_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define MT6797_GPIO41__FUNC_DPI_D2 (MTK_PIN_NO(41) | 1) +#define MT6797_GPIO41__FUNC_SPI1_CS_A (MTK_PIN_NO(41) | 2) +#define MT6797_GPIO41__FUNC_PCM0_DO (MTK_PIN_NO(41) | 3) +#define MT6797_GPIO41__FUNC_I2S3_DO (MTK_PIN_NO(41) | 4) +#define MT6797_GPIO41__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(41) | 5) +#define MT6797_GPIO41__FUNC_URTS3 (MTK_PIN_NO(41) | 6) +#define MT6797_GPIO41__FUNC_C2K_TDI (MTK_PIN_NO(41) | 7) + +#define MT6797_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define MT6797_GPIO42__FUNC_DPI_D3 (MTK_PIN_NO(42) | 1) +#define MT6797_GPIO42__FUNC_SPI1_MO_A (MTK_PIN_NO(42) | 2) +#define MT6797_GPIO42__FUNC_PCM0_DI (MTK_PIN_NO(42) | 3) +#define MT6797_GPIO42__FUNC_I2S0_DI (MTK_PIN_NO(42) | 4) +#define MT6797_GPIO42__FUNC_CONN_MCU_TDI (MTK_PIN_NO(42) | 5) +#define MT6797_GPIO42__FUNC_UCTS3 (MTK_PIN_NO(42) | 6) +#define MT6797_GPIO42__FUNC_C2K_TMS (MTK_PIN_NO(42) | 7) + +#define MT6797_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define MT6797_GPIO43__FUNC_DPI_D4 (MTK_PIN_NO(43) | 1) +#define MT6797_GPIO43__FUNC_SPI2_CLK_A (MTK_PIN_NO(43) | 2) +#define MT6797_GPIO43__FUNC_PCM1_SYNC (MTK_PIN_NO(43) | 3) +#define MT6797_GPIO43__FUNC_I2S2_LRCK (MTK_PIN_NO(43) | 4) +#define MT6797_GPIO43__FUNC_CONN_MCU_TMS (MTK_PIN_NO(43) | 5) +#define MT6797_GPIO43__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(43) | 6) +#define MT6797_GPIO43__FUNC_C2K_TDO (MTK_PIN_NO(43) | 7) + +#define MT6797_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define MT6797_GPIO44__FUNC_DPI_D5 (MTK_PIN_NO(44) | 1) +#define MT6797_GPIO44__FUNC_SPI2_MI_A (MTK_PIN_NO(44) | 2) +#define MT6797_GPIO44__FUNC_PCM1_CLK (MTK_PIN_NO(44) | 3) +#define MT6797_GPIO44__FUNC_I2S2_BCK (MTK_PIN_NO(44) | 4) +#define MT6797_GPIO44__FUNC_CONN_MCU_TCK (MTK_PIN_NO(44) | 5) +#define MT6797_GPIO44__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(44) | 6) +#define MT6797_GPIO44__FUNC_C2K_RTCK (MTK_PIN_NO(44) | 7) + +#define MT6797_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define MT6797_GPIO45__FUNC_DPI_D6 (MTK_PIN_NO(45) | 1) +#define MT6797_GPIO45__FUNC_SPI2_CS_A (MTK_PIN_NO(45) | 2) +#define MT6797_GPIO45__FUNC_PCM1_DI (MTK_PIN_NO(45) | 3) +#define MT6797_GPIO45__FUNC_I2S2_DI (MTK_PIN_NO(45) | 4) +#define MT6797_GPIO45__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(45) | 5) +#define MT6797_GPIO45__FUNC_MD_URXD0 (MTK_PIN_NO(45) | 6) + +#define MT6797_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define MT6797_GPIO46__FUNC_DPI_D7 (MTK_PIN_NO(46) | 1) +#define MT6797_GPIO46__FUNC_SPI2_MO_A (MTK_PIN_NO(46) | 2) +#define MT6797_GPIO46__FUNC_PCM1_DO0 (MTK_PIN_NO(46) | 3) +#define MT6797_GPIO46__FUNC_I2S1_DO (MTK_PIN_NO(46) | 4) +#define MT6797_GPIO46__FUNC_ANT_SEL0 (MTK_PIN_NO(46) | 5) +#define MT6797_GPIO46__FUNC_MD_UTXD0 (MTK_PIN_NO(46) | 6) + +#define MT6797_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define MT6797_GPIO47__FUNC_DPI_D8 (MTK_PIN_NO(47) | 1) +#define MT6797_GPIO47__FUNC_CLKM0 (MTK_PIN_NO(47) | 2) +#define MT6797_GPIO47__FUNC_PCM1_DO1 (MTK_PIN_NO(47) | 3) +#define MT6797_GPIO47__FUNC_I2S0_MCK (MTK_PIN_NO(47) | 4) +#define MT6797_GPIO47__FUNC_ANT_SEL1 (MTK_PIN_NO(47) | 5) +#define MT6797_GPIO47__FUNC_PTA_RXD (MTK_PIN_NO(47) | 6) +#define MT6797_GPIO47__FUNC_C2K_URXD0 (MTK_PIN_NO(47) | 7) + +#define MT6797_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define MT6797_GPIO48__FUNC_DPI_D9 (MTK_PIN_NO(48) | 1) +#define MT6797_GPIO48__FUNC_CLKM1 (MTK_PIN_NO(48) | 2) +#define MT6797_GPIO48__FUNC_CMFLASH (MTK_PIN_NO(48) | 3) +#define MT6797_GPIO48__FUNC_I2S2_MCK (MTK_PIN_NO(48) | 4) +#define MT6797_GPIO48__FUNC_ANT_SEL2 (MTK_PIN_NO(48) | 5) +#define MT6797_GPIO48__FUNC_PTA_TXD (MTK_PIN_NO(48) | 6) +#define MT6797_GPIO48__FUNC_C2K_UTXD0 (MTK_PIN_NO(48) | 7) + +#define MT6797_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define MT6797_GPIO49__FUNC_DPI_D10 (MTK_PIN_NO(49) | 1) +#define MT6797_GPIO49__FUNC_MD_INT1_C2K_UIM1_HOT_PLUG_IN (MTK_PIN_NO(49) | 2) +#define MT6797_GPIO49__FUNC_PWM_C (MTK_PIN_NO(49) | 3) +#define MT6797_GPIO49__FUNC_IRTX_OUT (MTK_PIN_NO(49) | 4) +#define MT6797_GPIO49__FUNC_ANT_SEL3 (MTK_PIN_NO(49) | 5) +#define MT6797_GPIO49__FUNC_MD_URXD1 (MTK_PIN_NO(49) | 6) + +#define MT6797_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define MT6797_GPIO50__FUNC_DPI_D11 (MTK_PIN_NO(50) | 1) +#define MT6797_GPIO50__FUNC_MD_INT2 (MTK_PIN_NO(50) | 2) +#define MT6797_GPIO50__FUNC_PWM_D (MTK_PIN_NO(50) | 3) +#define MT6797_GPIO50__FUNC_CLKM2 (MTK_PIN_NO(50) | 4) +#define MT6797_GPIO50__FUNC_ANT_SEL4 (MTK_PIN_NO(50) | 5) +#define MT6797_GPIO50__FUNC_MD_UTXD1 (MTK_PIN_NO(50) | 6) + +#define MT6797_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define MT6797_GPIO51__FUNC_DPI_DE (MTK_PIN_NO(51) | 1) +#define MT6797_GPIO51__FUNC_SPI4_CLK_A (MTK_PIN_NO(51) | 2) +#define MT6797_GPIO51__FUNC_IRTX_OUT (MTK_PIN_NO(51) | 3) +#define MT6797_GPIO51__FUNC_SCL0_1 (MTK_PIN_NO(51) | 4) +#define MT6797_GPIO51__FUNC_ANT_SEL5 (MTK_PIN_NO(51) | 5) +#define MT6797_GPIO51__FUNC_C2K_UTXD1 (MTK_PIN_NO(51) | 7) + +#define MT6797_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define MT6797_GPIO52__FUNC_DPI_CK (MTK_PIN_NO(52) | 1) +#define MT6797_GPIO52__FUNC_SPI4_MI_A (MTK_PIN_NO(52) | 2) +#define MT6797_GPIO52__FUNC_SPI4_MO_A (MTK_PIN_NO(52) | 3) +#define MT6797_GPIO52__FUNC_SDA0_1 (MTK_PIN_NO(52) | 4) +#define MT6797_GPIO52__FUNC_ANT_SEL6 (MTK_PIN_NO(52) | 5) +#define MT6797_GPIO52__FUNC_C2K_URXD1 (MTK_PIN_NO(52) | 7) + +#define MT6797_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define MT6797_GPIO53__FUNC_DPI_HSYNC (MTK_PIN_NO(53) | 1) +#define MT6797_GPIO53__FUNC_SPI4_CS_A (MTK_PIN_NO(53) | 2) +#define MT6797_GPIO53__FUNC_CMFLASH (MTK_PIN_NO(53) | 3) +#define MT6797_GPIO53__FUNC_SCL1_1 (MTK_PIN_NO(53) | 4) +#define MT6797_GPIO53__FUNC_ANT_SEL7 (MTK_PIN_NO(53) | 5) +#define MT6797_GPIO53__FUNC_MD_URXD2 (MTK_PIN_NO(53) | 6) +#define MT6797_GPIO53__FUNC_PCC_PPC_IO (MTK_PIN_NO(53) | 7) + +#define MT6797_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define MT6797_GPIO54__FUNC_DPI_VSYNC (MTK_PIN_NO(54) | 1) +#define MT6797_GPIO54__FUNC_SPI4_MO_A (MTK_PIN_NO(54) | 2) +#define MT6797_GPIO54__FUNC_SPI4_MI_A (MTK_PIN_NO(54) | 3) +#define MT6797_GPIO54__FUNC_SDA1_1 (MTK_PIN_NO(54) | 4) +#define MT6797_GPIO54__FUNC_PWM_A (MTK_PIN_NO(54) | 5) +#define MT6797_GPIO54__FUNC_MD_UTXD2 (MTK_PIN_NO(54) | 6) +#define MT6797_GPIO54__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(54) | 7) + +#define MT6797_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define MT6797_GPIO55__FUNC_SCL1_0 (MTK_PIN_NO(55) | 1) + +#define MT6797_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define MT6797_GPIO56__FUNC_SDA1_0 (MTK_PIN_NO(56) | 1) + +#define MT6797_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define MT6797_GPIO57__FUNC_SPI0_CLK (MTK_PIN_NO(57) | 1) +#define MT6797_GPIO57__FUNC_SCL0_2 (MTK_PIN_NO(57) | 2) +#define MT6797_GPIO57__FUNC_PWM_B (MTK_PIN_NO(57) | 3) +#define MT6797_GPIO57__FUNC_UTXD3 (MTK_PIN_NO(57) | 4) +#define MT6797_GPIO57__FUNC_PCM0_SYNC (MTK_PIN_NO(57) | 5) + +#define MT6797_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define MT6797_GPIO58__FUNC_SPI0_MI (MTK_PIN_NO(58) | 1) +#define MT6797_GPIO58__FUNC_SPI0_MO (MTK_PIN_NO(58) | 2) +#define MT6797_GPIO58__FUNC_SDA1_2 (MTK_PIN_NO(58) | 3) +#define MT6797_GPIO58__FUNC_URXD3 (MTK_PIN_NO(58) | 4) +#define MT6797_GPIO58__FUNC_PCM0_CLK (MTK_PIN_NO(58) | 5) + +#define MT6797_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define MT6797_GPIO59__FUNC_SPI0_MO (MTK_PIN_NO(59) | 1) +#define MT6797_GPIO59__FUNC_SPI0_MI (MTK_PIN_NO(59) | 2) +#define MT6797_GPIO59__FUNC_PWM_C (MTK_PIN_NO(59) | 3) +#define MT6797_GPIO59__FUNC_URTS3 (MTK_PIN_NO(59) | 4) +#define MT6797_GPIO59__FUNC_PCM0_DO (MTK_PIN_NO(59) | 5) + +#define MT6797_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define MT6797_GPIO60__FUNC_SPI0_CS (MTK_PIN_NO(60) | 1) +#define MT6797_GPIO60__FUNC_SDA0_2 (MTK_PIN_NO(60) | 2) +#define MT6797_GPIO60__FUNC_SCL1_2 (MTK_PIN_NO(60) | 3) +#define MT6797_GPIO60__FUNC_UCTS3 (MTK_PIN_NO(60) | 4) +#define MT6797_GPIO60__FUNC_PCM0_DI (MTK_PIN_NO(60) | 5) + +#define MT6797_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define MT6797_GPIO61__FUNC_EINT0 (MTK_PIN_NO(61) | 1) +#define MT6797_GPIO61__FUNC_IDDIG (MTK_PIN_NO(61) | 2) +#define MT6797_GPIO61__FUNC_SPI4_CLK_B (MTK_PIN_NO(61) | 3) +#define MT6797_GPIO61__FUNC_I2S0_LRCK (MTK_PIN_NO(61) | 4) +#define MT6797_GPIO61__FUNC_PCM0_SYNC (MTK_PIN_NO(61) | 5) +#define MT6797_GPIO61__FUNC_C2K_EINT0 (MTK_PIN_NO(61) | 7) + +#define MT6797_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define MT6797_GPIO62__FUNC_EINT1 (MTK_PIN_NO(62) | 1) +#define MT6797_GPIO62__FUNC_USB_DRVVBUS (MTK_PIN_NO(62) | 2) +#define MT6797_GPIO62__FUNC_SPI4_MI_B (MTK_PIN_NO(62) | 3) +#define MT6797_GPIO62__FUNC_I2S0_BCK (MTK_PIN_NO(62) | 4) +#define MT6797_GPIO62__FUNC_PCM0_CLK (MTK_PIN_NO(62) | 5) +#define MT6797_GPIO62__FUNC_C2K_EINT1 (MTK_PIN_NO(62) | 7) + +#define MT6797_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define MT6797_GPIO63__FUNC_EINT2 (MTK_PIN_NO(63) | 1) +#define MT6797_GPIO63__FUNC_IRTX_OUT (MTK_PIN_NO(63) | 2) +#define MT6797_GPIO63__FUNC_SPI4_MO_B (MTK_PIN_NO(63) | 3) +#define MT6797_GPIO63__FUNC_I2S0_MCK (MTK_PIN_NO(63) | 4) +#define MT6797_GPIO63__FUNC_PCM0_DI (MTK_PIN_NO(63) | 5) +#define MT6797_GPIO63__FUNC_C2K_DM_EINT0 (MTK_PIN_NO(63) | 7) + +#define MT6797_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define MT6797_GPIO64__FUNC_EINT3 (MTK_PIN_NO(64) | 1) +#define MT6797_GPIO64__FUNC_CMFLASH (MTK_PIN_NO(64) | 2) +#define MT6797_GPIO64__FUNC_SPI4_CS_B (MTK_PIN_NO(64) | 3) +#define MT6797_GPIO64__FUNC_I2S0_DI (MTK_PIN_NO(64) | 4) +#define MT6797_GPIO64__FUNC_PCM0_DO (MTK_PIN_NO(64) | 5) +#define MT6797_GPIO64__FUNC_C2K_DM_EINT1 (MTK_PIN_NO(64) | 7) + +#define MT6797_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define MT6797_GPIO65__FUNC_EINT4 (MTK_PIN_NO(65) | 1) +#define MT6797_GPIO65__FUNC_CLKM0 (MTK_PIN_NO(65) | 2) +#define MT6797_GPIO65__FUNC_SPI5_CLK_B (MTK_PIN_NO(65) | 3) +#define MT6797_GPIO65__FUNC_I2S1_LRCK (MTK_PIN_NO(65) | 4) +#define MT6797_GPIO65__FUNC_PWM_A (MTK_PIN_NO(65) | 5) +#define MT6797_GPIO65__FUNC_C2K_DM_EINT2 (MTK_PIN_NO(65) | 7) + +#define MT6797_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define MT6797_GPIO66__FUNC_EINT5 (MTK_PIN_NO(66) | 1) +#define MT6797_GPIO66__FUNC_CLKM1 (MTK_PIN_NO(66) | 2) +#define MT6797_GPIO66__FUNC_SPI5_MI_B (MTK_PIN_NO(66) | 3) +#define MT6797_GPIO66__FUNC_I2S1_BCK (MTK_PIN_NO(66) | 4) +#define MT6797_GPIO66__FUNC_PWM_B (MTK_PIN_NO(66) | 5) +#define MT6797_GPIO66__FUNC_C2K_DM_EINT3 (MTK_PIN_NO(66) | 7) + +#define MT6797_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define MT6797_GPIO67__FUNC_EINT6 (MTK_PIN_NO(67) | 1) +#define MT6797_GPIO67__FUNC_CLKM2 (MTK_PIN_NO(67) | 2) +#define MT6797_GPIO67__FUNC_SPI5_MO_B (MTK_PIN_NO(67) | 3) +#define MT6797_GPIO67__FUNC_I2S1_MCK (MTK_PIN_NO(67) | 4) +#define MT6797_GPIO67__FUNC_PWM_C (MTK_PIN_NO(67) | 5) +#define MT6797_GPIO67__FUNC_DBG_MON_A0 (MTK_PIN_NO(67) | 7) + +#define MT6797_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define MT6797_GPIO68__FUNC_EINT7 (MTK_PIN_NO(68) | 1) +#define MT6797_GPIO68__FUNC_CLKM3 (MTK_PIN_NO(68) | 2) +#define MT6797_GPIO68__FUNC_SPI5_CS_B (MTK_PIN_NO(68) | 3) +#define MT6797_GPIO68__FUNC_I2S1_DO (MTK_PIN_NO(68) | 4) +#define MT6797_GPIO68__FUNC_PWM_D (MTK_PIN_NO(68) | 5) +#define MT6797_GPIO68__FUNC_DBG_MON_A1 (MTK_PIN_NO(68) | 7) + +#define MT6797_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define MT6797_GPIO69__FUNC_I2S0_LRCK (MTK_PIN_NO(69) | 1) +#define MT6797_GPIO69__FUNC_I2S3_LRCK (MTK_PIN_NO(69) | 2) +#define MT6797_GPIO69__FUNC_I2S1_LRCK (MTK_PIN_NO(69) | 3) +#define MT6797_GPIO69__FUNC_I2S2_LRCK (MTK_PIN_NO(69) | 4) +#define MT6797_GPIO69__FUNC_DBG_MON_A2 (MTK_PIN_NO(69) | 7) + +#define MT6797_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define MT6797_GPIO70__FUNC_I2S0_BCK (MTK_PIN_NO(70) | 1) +#define MT6797_GPIO70__FUNC_I2S3_BCK (MTK_PIN_NO(70) | 2) +#define MT6797_GPIO70__FUNC_I2S1_BCK (MTK_PIN_NO(70) | 3) +#define MT6797_GPIO70__FUNC_I2S2_BCK (MTK_PIN_NO(70) | 4) +#define MT6797_GPIO70__FUNC_DBG_MON_A3 (MTK_PIN_NO(70) | 7) + +#define MT6797_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define MT6797_GPIO71__FUNC_I2S0_MCK (MTK_PIN_NO(71) | 1) +#define MT6797_GPIO71__FUNC_I2S3_MCK (MTK_PIN_NO(71) | 2) +#define MT6797_GPIO71__FUNC_I2S1_MCK (MTK_PIN_NO(71) | 3) +#define MT6797_GPIO71__FUNC_I2S2_MCK (MTK_PIN_NO(71) | 4) +#define MT6797_GPIO71__FUNC_DBG_MON_A4 (MTK_PIN_NO(71) | 7) + +#define MT6797_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +/* #define MT6797_GPIO72__FUNC_I2S0_DI (MTK_PIN_NO(72) | 1) */ +#define MT6797_GPIO72__FUNC_I2S0_DI (MTK_PIN_NO(72) | 2) +/* #define MT6797_GPIO72__FUNC_I2S2_DI (MTK_PIN_NO(72) | 3) */ +#define MT6797_GPIO72__FUNC_I2S2_DI (MTK_PIN_NO(72) | 4) +#define MT6797_GPIO72__FUNC_DBG_MON_A5 (MTK_PIN_NO(72) | 7) + +#define MT6797_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +/* #define MT6797_GPIO73__FUNC_I2S3_DO (MTK_PIN_NO(73) | 1) */ +#define MT6797_GPIO73__FUNC_I2S3_DO (MTK_PIN_NO(73) | 2) +/* #define MT6797_GPIO73__FUNC_I2S1_DO (MTK_PIN_NO(73) | 3) */ +#define MT6797_GPIO73__FUNC_I2S1_DO (MTK_PIN_NO(73) | 4) +#define MT6797_GPIO73__FUNC_DBG_MON_A6 (MTK_PIN_NO(73) | 7) + +#define MT6797_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define MT6797_GPIO74__FUNC_SCL3_0 (MTK_PIN_NO(74) | 1) +#define MT6797_GPIO74__FUNC_AUXIF_CLK1 (MTK_PIN_NO(74) | 7) + +#define MT6797_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define MT6797_GPIO75__FUNC_SDA3_0 (MTK_PIN_NO(75) | 1) +#define MT6797_GPIO75__FUNC_AUXIF_ST1 (MTK_PIN_NO(75) | 7) + +#define MT6797_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define MT6797_GPIO76__FUNC_CONN_HRST_B (MTK_PIN_NO(76) | 1) +#define MT6797_GPIO76__FUNC_C2K_DM_EINT0 (MTK_PIN_NO(76) | 7) + +#define MT6797_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define MT6797_GPIO77__FUNC_CONN_TOP_CLK (MTK_PIN_NO(77) | 1) +#define MT6797_GPIO77__FUNC_C2K_DM_EINT1 (MTK_PIN_NO(77) | 7) + +#define MT6797_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define MT6797_GPIO78__FUNC_CONN_TOP_DATA (MTK_PIN_NO(78) | 1) +#define MT6797_GPIO78__FUNC_C2K_DM_EINT2 (MTK_PIN_NO(78) | 7) + +#define MT6797_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define MT6797_GPIO79__FUNC_CONN_WB_PTA (MTK_PIN_NO(79) | 1) +#define MT6797_GPIO79__FUNC_C2K_DM_EINT3 (MTK_PIN_NO(79) | 7) + +#define MT6797_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define MT6797_GPIO80__FUNC_CONN_WF_HB0 (MTK_PIN_NO(80) | 1) +#define MT6797_GPIO80__FUNC_C2K_EINT0 (MTK_PIN_NO(80) | 7) + +#define MT6797_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define MT6797_GPIO81__FUNC_CONN_WF_HB1 (MTK_PIN_NO(81) | 1) +#define MT6797_GPIO81__FUNC_C2K_EINT1 (MTK_PIN_NO(81) | 7) + +#define MT6797_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define MT6797_GPIO82__FUNC_CONN_WF_HB2 (MTK_PIN_NO(82) | 1) +#define MT6797_GPIO82__FUNC_MD_CLKM0 (MTK_PIN_NO(82) | 7) + +#define MT6797_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define MT6797_GPIO83__FUNC_CONN_BT_CLK (MTK_PIN_NO(83) | 1) +#define MT6797_GPIO83__FUNC_MD_CLKM1 (MTK_PIN_NO(83) | 7) + +#define MT6797_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define MT6797_GPIO84__FUNC_CONN_BT_DATA (MTK_PIN_NO(84) | 1) + +#define MT6797_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define MT6797_GPIO85__FUNC_EINT8 (MTK_PIN_NO(85) | 1) +#define MT6797_GPIO85__FUNC_I2S1_LRCK (MTK_PIN_NO(85) | 2) +#define MT6797_GPIO85__FUNC_I2S2_LRCK (MTK_PIN_NO(85) | 3) +#define MT6797_GPIO85__FUNC_URXD1 (MTK_PIN_NO(85) | 4) +#define MT6797_GPIO85__FUNC_MD_URXD0 (MTK_PIN_NO(85) | 5) +#define MT6797_GPIO85__FUNC_DBG_MON_A7 (MTK_PIN_NO(85) | 7) + +#define MT6797_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define MT6797_GPIO86__FUNC_EINT9 (MTK_PIN_NO(86) | 1) +#define MT6797_GPIO86__FUNC_I2S1_BCK (MTK_PIN_NO(86) | 2) +#define MT6797_GPIO86__FUNC_I2S2_BCK (MTK_PIN_NO(86) | 3) +#define MT6797_GPIO86__FUNC_UTXD1 (MTK_PIN_NO(86) | 4) +#define MT6797_GPIO86__FUNC_MD_UTXD0 (MTK_PIN_NO(86) | 5) +#define MT6797_GPIO86__FUNC_DBG_MON_A8 (MTK_PIN_NO(86) | 7) + +#define MT6797_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define MT6797_GPIO87__FUNC_EINT10 (MTK_PIN_NO(87) | 1) +#define MT6797_GPIO87__FUNC_I2S1_MCK (MTK_PIN_NO(87) | 2) +#define MT6797_GPIO87__FUNC_I2S2_MCK (MTK_PIN_NO(87) | 3) +#define MT6797_GPIO87__FUNC_URTS1 (MTK_PIN_NO(87) | 4) +#define MT6797_GPIO87__FUNC_MD_URXD1 (MTK_PIN_NO(87) | 5) +#define MT6797_GPIO87__FUNC_DBG_MON_A9 (MTK_PIN_NO(87) | 7) + +#define MT6797_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define MT6797_GPIO88__FUNC_EINT11 (MTK_PIN_NO(88) | 1) +#define MT6797_GPIO88__FUNC_I2S1_DO (MTK_PIN_NO(88) | 2) +#define MT6797_GPIO88__FUNC_I2S2_DI (MTK_PIN_NO(88) | 3) +#define MT6797_GPIO88__FUNC_UCTS1 (MTK_PIN_NO(88) | 4) +#define MT6797_GPIO88__FUNC_MD_UTXD1 (MTK_PIN_NO(88) | 5) +#define MT6797_GPIO88__FUNC_DBG_MON_A10 (MTK_PIN_NO(88) | 7) + +#define MT6797_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define MT6797_GPIO89__FUNC_EINT12 (MTK_PIN_NO(89) | 1) +#define MT6797_GPIO89__FUNC_IRTX_OUT (MTK_PIN_NO(89) | 2) +#define MT6797_GPIO89__FUNC_CLKM0 (MTK_PIN_NO(89) | 3) +#define MT6797_GPIO89__FUNC_PCM1_SYNC (MTK_PIN_NO(89) | 4) +#define MT6797_GPIO89__FUNC_URTS0 (MTK_PIN_NO(89) | 5) +#define MT6797_GPIO89__FUNC_DBG_MON_A11 (MTK_PIN_NO(89) | 7) + +#define MT6797_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define MT6797_GPIO90__FUNC_EINT13 (MTK_PIN_NO(90) | 1) +#define MT6797_GPIO90__FUNC_CMFLASH (MTK_PIN_NO(90) | 2) +#define MT6797_GPIO90__FUNC_CLKM1 (MTK_PIN_NO(90) | 3) +#define MT6797_GPIO90__FUNC_PCM1_CLK (MTK_PIN_NO(90) | 4) +#define MT6797_GPIO90__FUNC_UCTS0 (MTK_PIN_NO(90) | 5) +#define MT6797_GPIO90__FUNC_C2K_DM_EINT0 (MTK_PIN_NO(90) | 7) + +#define MT6797_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define MT6797_GPIO91__FUNC_EINT14 (MTK_PIN_NO(91) | 1) +#define MT6797_GPIO91__FUNC_PWM_A (MTK_PIN_NO(91) | 2) +#define MT6797_GPIO91__FUNC_CLKM2 (MTK_PIN_NO(91) | 3) +#define MT6797_GPIO91__FUNC_PCM1_DI (MTK_PIN_NO(91) | 4) +#define MT6797_GPIO91__FUNC_SDA0_3 (MTK_PIN_NO(91) | 5) +#define MT6797_GPIO91__FUNC_C2K_DM_EINT1 (MTK_PIN_NO(91) | 7) + +#define MT6797_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define MT6797_GPIO92__FUNC_EINT15 (MTK_PIN_NO(92) | 1) +#define MT6797_GPIO92__FUNC_PWM_B (MTK_PIN_NO(92) | 2) +#define MT6797_GPIO92__FUNC_CLKM3 (MTK_PIN_NO(92) | 3) +#define MT6797_GPIO92__FUNC_PCM1_DO0 (MTK_PIN_NO(92) | 4) +#define MT6797_GPIO92__FUNC_SCL0_3 (MTK_PIN_NO(92) | 5) + +#define MT6797_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define MT6797_GPIO93__FUNC_EINT16 (MTK_PIN_NO(93) | 1) +#define MT6797_GPIO93__FUNC_IDDIG (MTK_PIN_NO(93) | 2) +#define MT6797_GPIO93__FUNC_CLKM4 (MTK_PIN_NO(93) | 3) +#define MT6797_GPIO93__FUNC_PCM1_DO1 (MTK_PIN_NO(93) | 4) +#define MT6797_GPIO93__FUNC_MD_INT2 (MTK_PIN_NO(93) | 5) +#define MT6797_GPIO93__FUNC_DROP_ZONE (MTK_PIN_NO(93) | 7) + +#define MT6797_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define MT6797_GPIO94__FUNC_USB_DRVVBUS (MTK_PIN_NO(94) | 1) +#define MT6797_GPIO94__FUNC_PWM_C (MTK_PIN_NO(94) | 2) +#define MT6797_GPIO94__FUNC_CLKM5 (MTK_PIN_NO(94) | 3) + +#define MT6797_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define MT6797_GPIO95__FUNC_SDA2_0 (MTK_PIN_NO(95) | 1) +#define MT6797_GPIO95__FUNC_AUXIF_ST0 (MTK_PIN_NO(95) | 7) + +#define MT6797_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define MT6797_GPIO96__FUNC_SCL2_0 (MTK_PIN_NO(96) | 1) +#define MT6797_GPIO96__FUNC_AUXIF_CLK0 (MTK_PIN_NO(96) | 7) + +#define MT6797_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define MT6797_GPIO97__FUNC_URXD0 (MTK_PIN_NO(97) | 1) +#define MT6797_GPIO97__FUNC_UTXD0 (MTK_PIN_NO(97) | 2) +#define MT6797_GPIO97__FUNC_MD_URXD0 (MTK_PIN_NO(97) | 3) +#define MT6797_GPIO97__FUNC_MD_URXD1 (MTK_PIN_NO(97) | 4) +#define MT6797_GPIO97__FUNC_MD_URXD2 (MTK_PIN_NO(97) | 5) +#define MT6797_GPIO97__FUNC_C2K_URXD0 (MTK_PIN_NO(97) | 6) +#define MT6797_GPIO97__FUNC_C2K_URXD1 (MTK_PIN_NO(97) | 7) + +#define MT6797_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define MT6797_GPIO98__FUNC_UTXD0 (MTK_PIN_NO(98) | 1) +#define MT6797_GPIO98__FUNC_URXD0 (MTK_PIN_NO(98) | 2) +#define MT6797_GPIO98__FUNC_MD_UTXD0 (MTK_PIN_NO(98) | 3) +#define MT6797_GPIO98__FUNC_MD_UTXD1 (MTK_PIN_NO(98) | 4) +#define MT6797_GPIO98__FUNC_MD_UTXD2 (MTK_PIN_NO(98) | 5) +#define MT6797_GPIO98__FUNC_C2K_UTXD0 (MTK_PIN_NO(98) | 6) +#define MT6797_GPIO98__FUNC_C2K_UTXD1 (MTK_PIN_NO(98) | 7) + +#define MT6797_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define MT6797_GPIO99__FUNC_RTC32K_CK (MTK_PIN_NO(99) | 1) + +#define MT6797_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define MT6797_GPIO100__FUNC_SRCLKENAI0 (MTK_PIN_NO(100) | 1) + +#define MT6797_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define MT6797_GPIO101__FUNC_SRCLKENAI1 (MTK_PIN_NO(101) | 1) + +#define MT6797_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define MT6797_GPIO102__FUNC_SRCLKENA0 (MTK_PIN_NO(102) | 1) + +#define MT6797_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define MT6797_GPIO103__FUNC_SRCLKENA1 (MTK_PIN_NO(103) | 1) + +#define MT6797_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define MT6797_GPIO104__FUNC_SYSRSTB (MTK_PIN_NO(104) | 1) + +#define MT6797_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define MT6797_GPIO105__FUNC_WATCHDOG (MTK_PIN_NO(105) | 1) + +#define MT6797_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define MT6797_GPIO106__FUNC_KPROW0 (MTK_PIN_NO(106) | 1) +#define MT6797_GPIO106__FUNC_CMFLASH (MTK_PIN_NO(106) | 2) +#define MT6797_GPIO106__FUNC_CLKM4 (MTK_PIN_NO(106) | 3) +#define MT6797_GPIO106__FUNC_TP_GPIO0_AO (MTK_PIN_NO(106) | 4) +#define MT6797_GPIO106__FUNC_IRTX_OUT (MTK_PIN_NO(106) | 5) + +#define MT6797_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define MT6797_GPIO107__FUNC_KPROW1 (MTK_PIN_NO(107) | 1) +#define MT6797_GPIO107__FUNC_IDDIG (MTK_PIN_NO(107) | 2) +#define MT6797_GPIO107__FUNC_CLKM5 (MTK_PIN_NO(107) | 3) +#define MT6797_GPIO107__FUNC_TP_GPIO1_AO (MTK_PIN_NO(107) | 4) +#define MT6797_GPIO107__FUNC_I2S1_BCK (MTK_PIN_NO(107) | 5) +#define MT6797_GPIO107__FUNC_DAP_SIB1_SWD (MTK_PIN_NO(107) | 7) + +#define MT6797_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define MT6797_GPIO108__FUNC_KPROW2 (MTK_PIN_NO(108) | 1) +#define MT6797_GPIO108__FUNC_USB_DRVVBUS (MTK_PIN_NO(108) | 2) +#define MT6797_GPIO108__FUNC_PWM_A (MTK_PIN_NO(108) | 3) +#define MT6797_GPIO108__FUNC_CMFLASH (MTK_PIN_NO(108) | 4) +#define MT6797_GPIO108__FUNC_I2S1_LRCK (MTK_PIN_NO(108) | 5) +#define MT6797_GPIO108__FUNC_DAP_SIB1_SWCK (MTK_PIN_NO(108) | 7) + +#define MT6797_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define MT6797_GPIO109__FUNC_KPCOL0 (MTK_PIN_NO(109) | 1) + +#define MT6797_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define MT6797_GPIO110__FUNC_KPCOL1 (MTK_PIN_NO(110) | 1) +#define MT6797_GPIO110__FUNC_SDA1_3 (MTK_PIN_NO(110) | 2) +#define MT6797_GPIO110__FUNC_PWM_B (MTK_PIN_NO(110) | 3) +#define MT6797_GPIO110__FUNC_CLKM0 (MTK_PIN_NO(110) | 4) +#define MT6797_GPIO110__FUNC_I2S1_DO (MTK_PIN_NO(110) | 5) +#define MT6797_GPIO110__FUNC_C2K_DM_EINT3 (MTK_PIN_NO(110) | 7) + +#define MT6797_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define MT6797_GPIO111__FUNC_KPCOL2 (MTK_PIN_NO(111) | 1) +#define MT6797_GPIO111__FUNC_SCL1_3 (MTK_PIN_NO(111) | 2) +#define MT6797_GPIO111__FUNC_PWM_C (MTK_PIN_NO(111) | 3) +#define MT6797_GPIO111__FUNC_DISP_PWM (MTK_PIN_NO(111) | 4) +#define MT6797_GPIO111__FUNC_I2S1_MCK (MTK_PIN_NO(111) | 5) +#define MT6797_GPIO111__FUNC_C2K_DM_EINT2 (MTK_PIN_NO(111) | 7) + +#define MT6797_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define MT6797_GPIO112__FUNC_MD_INT1_C2K_UIM1_HOT_PLUG_IN (MTK_PIN_NO(112) | 1) +#define MT6797_GPIO112__FUNC_C2K_DM_EINT1 (MTK_PIN_NO(112) | 7) + +#define MT6797_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define MT6797_GPIO113__FUNC_MD_INT0_C2K_UIM0_HOT_PLUG_IN (MTK_PIN_NO(113) | 1) +#define MT6797_GPIO113__FUNC_C2K_DM_EINT0 (MTK_PIN_NO(113) | 7) + +#define MT6797_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define MT6797_GPIO114__FUNC_MSDC0_DAT0 (MTK_PIN_NO(114) | 1) + +#define MT6797_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define MT6797_GPIO115__FUNC_MSDC0_DAT1 (MTK_PIN_NO(115) | 1) + +#define MT6797_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define MT6797_GPIO116__FUNC_MSDC0_DAT2 (MTK_PIN_NO(116) | 1) + +#define MT6797_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define MT6797_GPIO117__FUNC_MSDC0_DAT3 (MTK_PIN_NO(117) | 1) + +#define MT6797_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define MT6797_GPIO118__FUNC_MSDC0_DAT4 (MTK_PIN_NO(118) | 1) + +#define MT6797_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define MT6797_GPIO119__FUNC_MSDC0_DAT5 (MTK_PIN_NO(119) | 1) + +#define MT6797_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define MT6797_GPIO120__FUNC_MSDC0_DAT6 (MTK_PIN_NO(120) | 1) + +#define MT6797_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define MT6797_GPIO121__FUNC_MSDC0_DAT7 (MTK_PIN_NO(121) | 1) + +#define MT6797_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define MT6797_GPIO122__FUNC_MSDC0_CMD (MTK_PIN_NO(122) | 1) + +#define MT6797_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define MT6797_GPIO123__FUNC_MSDC0_CLK (MTK_PIN_NO(123) | 1) + +#define MT6797_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define MT6797_GPIO124__FUNC_MSDC0_DSL (MTK_PIN_NO(124) | 1) + +#define MT6797_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define MT6797_GPIO125__FUNC_MSDC0_RSTB (MTK_PIN_NO(125) | 1) + +#define MT6797_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define MT6797_GPIO126__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(126) | 1) +#define MT6797_GPIO126__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(126) | 2) +#define MT6797_GPIO126__FUNC_C2K_UIM0_CLK (MTK_PIN_NO(126) | 3) +#define MT6797_GPIO126__FUNC_C2K_UIM1_CLK (MTK_PIN_NO(126) | 4) + +#define MT6797_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define MT6797_GPIO127__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(127) | 1) +#define MT6797_GPIO127__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(127) | 2) +#define MT6797_GPIO127__FUNC_C2K_UIM0_RST (MTK_PIN_NO(127) | 3) +#define MT6797_GPIO127__FUNC_C2K_UIM1_RST (MTK_PIN_NO(127) | 4) + +#define MT6797_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define MT6797_GPIO128__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(128) | 1) +#define MT6797_GPIO128__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(128) | 2) +#define MT6797_GPIO128__FUNC_C2K_UIM0_IO (MTK_PIN_NO(128) | 3) +#define MT6797_GPIO128__FUNC_C2K_UIM1_IO (MTK_PIN_NO(128) | 4) + +#define MT6797_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define MT6797_GPIO129__FUNC_MSDC1_CMD (MTK_PIN_NO(129) | 1) +#define MT6797_GPIO129__FUNC_CONN_DSP_JMS (MTK_PIN_NO(129) | 2) +#define MT6797_GPIO129__FUNC_LTE_JTAG_TMS (MTK_PIN_NO(129) | 3) +#define MT6797_GPIO129__FUNC_UDI_TMS (MTK_PIN_NO(129) | 4) +#define MT6797_GPIO129__FUNC_C2K_TMS (MTK_PIN_NO(129) | 5) + +#define MT6797_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define MT6797_GPIO130__FUNC_MSDC1_DAT0 (MTK_PIN_NO(130) | 1) +#define MT6797_GPIO130__FUNC_CONN_DSP_JDI (MTK_PIN_NO(130) | 2) +#define MT6797_GPIO130__FUNC_LTE_JTAG_TDI (MTK_PIN_NO(130) | 3) +#define MT6797_GPIO130__FUNC_UDI_TDI (MTK_PIN_NO(130) | 4) +#define MT6797_GPIO130__FUNC_C2K_TDI (MTK_PIN_NO(130) | 5) + +#define MT6797_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define MT6797_GPIO131__FUNC_MSDC1_DAT1 (MTK_PIN_NO(131) | 1) +#define MT6797_GPIO131__FUNC_CONN_DSP_JDO (MTK_PIN_NO(131) | 2) +#define MT6797_GPIO131__FUNC_LTE_JTAG_TDO (MTK_PIN_NO(131) | 3) +#define MT6797_GPIO131__FUNC_UDI_TDO (MTK_PIN_NO(131) | 4) +#define MT6797_GPIO131__FUNC_C2K_TDO (MTK_PIN_NO(131) | 5) + +#define MT6797_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define MT6797_GPIO132__FUNC_MSDC1_DAT2 (MTK_PIN_NO(132) | 1) +#define MT6797_GPIO132__FUNC_C2K_RTCK (MTK_PIN_NO(132) | 5) + +#define MT6797_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define MT6797_GPIO133__FUNC_MSDC1_DAT3 (MTK_PIN_NO(133) | 1) +#define MT6797_GPIO133__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(133) | 2) +#define MT6797_GPIO133__FUNC_LTE_JTAG_TRSTN (MTK_PIN_NO(133) | 3) +#define MT6797_GPIO133__FUNC_UDI_NTRST (MTK_PIN_NO(133) | 4) +#define MT6797_GPIO133__FUNC_C2K_NTRST (MTK_PIN_NO(133) | 5) + +#define MT6797_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define MT6797_GPIO134__FUNC_MSDC1_CLK (MTK_PIN_NO(134) | 1) +#define MT6797_GPIO134__FUNC_CONN_DSP_JCK (MTK_PIN_NO(134) | 2) +#define MT6797_GPIO134__FUNC_LTE_JTAG_TCK (MTK_PIN_NO(134) | 3) +#define MT6797_GPIO134__FUNC_UDI_TCK_XI (MTK_PIN_NO(134) | 4) +#define MT6797_GPIO134__FUNC_C2K_TCK (MTK_PIN_NO(134) | 5) + +#define MT6797_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define MT6797_GPIO135__FUNC_TDM_LRCK (MTK_PIN_NO(135) | 1) +#define MT6797_GPIO135__FUNC_I2S0_LRCK (MTK_PIN_NO(135) | 2) +#define MT6797_GPIO135__FUNC_CLKM0 (MTK_PIN_NO(135) | 3) +#define MT6797_GPIO135__FUNC_PCM1_SYNC (MTK_PIN_NO(135) | 4) +#define MT6797_GPIO135__FUNC_PWM_A (MTK_PIN_NO(135) | 5) +#define MT6797_GPIO135__FUNC_DBG_MON_A12 (MTK_PIN_NO(135) | 7) + +#define MT6797_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define MT6797_GPIO136__FUNC_TDM_BCK (MTK_PIN_NO(136) | 1) +#define MT6797_GPIO136__FUNC_I2S0_BCK (MTK_PIN_NO(136) | 2) +#define MT6797_GPIO136__FUNC_CLKM1 (MTK_PIN_NO(136) | 3) +#define MT6797_GPIO136__FUNC_PCM1_CLK (MTK_PIN_NO(136) | 4) +#define MT6797_GPIO136__FUNC_PWM_B (MTK_PIN_NO(136) | 5) +#define MT6797_GPIO136__FUNC_DBG_MON_A13 (MTK_PIN_NO(136) | 7) + +#define MT6797_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define MT6797_GPIO137__FUNC_TDM_MCK (MTK_PIN_NO(137) | 1) +#define MT6797_GPIO137__FUNC_I2S0_MCK (MTK_PIN_NO(137) | 2) +#define MT6797_GPIO137__FUNC_CLKM2 (MTK_PIN_NO(137) | 3) +#define MT6797_GPIO137__FUNC_PCM1_DI (MTK_PIN_NO(137) | 4) +#define MT6797_GPIO137__FUNC_IRTX_OUT (MTK_PIN_NO(137) | 5) +#define MT6797_GPIO137__FUNC_DBG_MON_A14 (MTK_PIN_NO(137) | 7) + +#define MT6797_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define MT6797_GPIO138__FUNC_TDM_DATA0 (MTK_PIN_NO(138) | 1) +#define MT6797_GPIO138__FUNC_I2S0_DI (MTK_PIN_NO(138) | 2) +#define MT6797_GPIO138__FUNC_CLKM3 (MTK_PIN_NO(138) | 3) +#define MT6797_GPIO138__FUNC_PCM1_DO0 (MTK_PIN_NO(138) | 4) +#define MT6797_GPIO138__FUNC_PWM_C (MTK_PIN_NO(138) | 5) +#define MT6797_GPIO138__FUNC_SDA3_1 (MTK_PIN_NO(138) | 6) +#define MT6797_GPIO138__FUNC_DBG_MON_A15 (MTK_PIN_NO(138) | 7) + +#define MT6797_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define MT6797_GPIO139__FUNC_TDM_DATA1 (MTK_PIN_NO(139) | 1) +#define MT6797_GPIO139__FUNC_I2S3_DO (MTK_PIN_NO(139) | 2) +#define MT6797_GPIO139__FUNC_CLKM4 (MTK_PIN_NO(139) | 3) +#define MT6797_GPIO139__FUNC_PCM1_DO1 (MTK_PIN_NO(139) | 4) +#define MT6797_GPIO139__FUNC_ANT_SEL2 (MTK_PIN_NO(139) | 5) +#define MT6797_GPIO139__FUNC_SCL3_1 (MTK_PIN_NO(139) | 6) +#define MT6797_GPIO139__FUNC_DBG_MON_A16 (MTK_PIN_NO(139) | 7) + +#define MT6797_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define MT6797_GPIO140__FUNC_TDM_DATA2 (MTK_PIN_NO(140) | 1) +#define MT6797_GPIO140__FUNC_DISP_PWM (MTK_PIN_NO(140) | 2) +#define MT6797_GPIO140__FUNC_CLKM5 (MTK_PIN_NO(140) | 3) +#define MT6797_GPIO140__FUNC_SDA1_4 (MTK_PIN_NO(140) | 4) +#define MT6797_GPIO140__FUNC_ANT_SEL1 (MTK_PIN_NO(140) | 5) +#define MT6797_GPIO140__FUNC_URXD3 (MTK_PIN_NO(140) | 6) +#define MT6797_GPIO140__FUNC_DBG_MON_A17 (MTK_PIN_NO(140) | 7) + +#define MT6797_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define MT6797_GPIO141__FUNC_TDM_DATA3 (MTK_PIN_NO(141) | 1) +#define MT6797_GPIO141__FUNC_CMFLASH (MTK_PIN_NO(141) | 2) +#define MT6797_GPIO141__FUNC_IRTX_OUT (MTK_PIN_NO(141) | 3) +#define MT6797_GPIO141__FUNC_SCL1_4 (MTK_PIN_NO(141) | 4) +#define MT6797_GPIO141__FUNC_ANT_SEL0 (MTK_PIN_NO(141) | 5) +#define MT6797_GPIO141__FUNC_UTXD3 (MTK_PIN_NO(141) | 6) +#define MT6797_GPIO141__FUNC_DBG_MON_A18 (MTK_PIN_NO(141) | 7) + +#define MT6797_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define MT6797_GPIO142__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(142) | 1) +#define MT6797_GPIO142__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(142) | 2) + +#define MT6797_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define MT6797_GPIO143__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(143) | 1) +#define MT6797_GPIO143__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(143) | 2) + +#define MT6797_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define MT6797_GPIO144__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(144) | 1) + +#define MT6797_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define MT6797_GPIO145__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(145) | 1) + +#define MT6797_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define MT6797_GPIO146__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(146) | 1) + +#define MT6797_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define MT6797_GPIO147__FUNC_AUD_DAT_MISO (MTK_PIN_NO(147) | 1) +#define MT6797_GPIO147__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(147) | 2) +#define MT6797_GPIO147__FUNC_VOW_DAT_MISO (MTK_PIN_NO(147) | 3) + +#define MT6797_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define MT6797_GPIO148__FUNC_AUD_DAT_MOSI (MTK_PIN_NO(148) | 1) +#define MT6797_GPIO148__FUNC_AUD_DAT_MISO (MTK_PIN_NO(148) | 2) + +#define MT6797_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define MT6797_GPIO149__FUNC_VOW_CLK_MISO (MTK_PIN_NO(149) | 1) + +#define MT6797_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define MT6797_GPIO150__FUNC_ANC_DAT_MOSI (MTK_PIN_NO(150) | 1) + +#define MT6797_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define MT6797_GPIO151__FUNC_SCL6_0 (MTK_PIN_NO(151) | 1) + +#define MT6797_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define MT6797_GPIO152__FUNC_SDA6_0 (MTK_PIN_NO(152) | 1) + +#define MT6797_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define MT6797_GPIO153__FUNC_SCL7_0 (MTK_PIN_NO(153) | 1) + +#define MT6797_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define MT6797_GPIO154__FUNC_SDA7_0 (MTK_PIN_NO(154) | 1) + +#define MT6797_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define MT6797_GPIO155__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(155) | 1) +#define MT6797_GPIO155__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(155) | 2) +#define MT6797_GPIO155__FUNC_C2K_UIM0_CLK (MTK_PIN_NO(155) | 3) +#define MT6797_GPIO155__FUNC_C2K_UIM1_CLK (MTK_PIN_NO(155) | 4) + +#define MT6797_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define MT6797_GPIO156__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(156) | 1) +#define MT6797_GPIO156__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(156) | 2) +#define MT6797_GPIO156__FUNC_C2K_UIM0_RST (MTK_PIN_NO(156) | 3) +#define MT6797_GPIO156__FUNC_C2K_UIM1_RST (MTK_PIN_NO(156) | 4) + +#define MT6797_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define MT6797_GPIO157__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(157) | 1) +#define MT6797_GPIO157__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(157) | 2) +#define MT6797_GPIO157__FUNC_C2K_UIM0_IO (MTK_PIN_NO(157) | 3) +#define MT6797_GPIO157__FUNC_C2K_UIM1_IO (MTK_PIN_NO(157) | 4) + +#define MT6797_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define MT6797_GPIO158__FUNC_MIPI_TDP0 (MTK_PIN_NO(158) | 1) + +#define MT6797_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define MT6797_GPIO159__FUNC_MIPI_TDN0 (MTK_PIN_NO(159) | 1) + +#define MT6797_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define MT6797_GPIO160__FUNC_MIPI_TDP1 (MTK_PIN_NO(160) | 1) + +#define MT6797_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define MT6797_GPIO161__FUNC_MIPI_TDN1 (MTK_PIN_NO(161) | 1) + +#define MT6797_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define MT6797_GPIO162__FUNC_MIPI_TCP (MTK_PIN_NO(162) | 1) + +#define MT6797_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define MT6797_GPIO163__FUNC_MIPI_TCN (MTK_PIN_NO(163) | 1) + +#define MT6797_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define MT6797_GPIO164__FUNC_MIPI_TDP2 (MTK_PIN_NO(164) | 1) + +#define MT6797_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +#define MT6797_GPIO165__FUNC_MIPI_TDN2 (MTK_PIN_NO(165) | 1) + +#define MT6797_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +#define MT6797_GPIO166__FUNC_MIPI_TDP3 (MTK_PIN_NO(166) | 1) + +#define MT6797_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +#define MT6797_GPIO167__FUNC_MIPI_TDN3 (MTK_PIN_NO(167) | 1) + +#define MT6797_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +#define MT6797_GPIO168__FUNC_MIPI_TDP0_A (MTK_PIN_NO(168) | 1) + +#define MT6797_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define MT6797_GPIO169__FUNC_MIPI_TDN0_A (MTK_PIN_NO(169) | 1) + +#define MT6797_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define MT6797_GPIO170__FUNC_MIPI_TDP1_A (MTK_PIN_NO(170) | 1) + +#define MT6797_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define MT6797_GPIO171__FUNC_MIPI_TDN1_A (MTK_PIN_NO(171) | 1) + +#define MT6797_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +#define MT6797_GPIO172__FUNC_MIPI_TCP_A (MTK_PIN_NO(172) | 1) + +#define MT6797_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +#define MT6797_GPIO173__FUNC_MIPI_TCN_A (MTK_PIN_NO(173) | 1) + +#define MT6797_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +#define MT6797_GPIO174__FUNC_MIPI_TDP2_A (MTK_PIN_NO(174) | 1) + +#define MT6797_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +#define MT6797_GPIO175__FUNC_MIPI_TDN2_A (MTK_PIN_NO(175) | 1) + +#define MT6797_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +#define MT6797_GPIO176__FUNC_MIPI_TDP3_A (MTK_PIN_NO(176) | 1) + +#define MT6797_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +#define MT6797_GPIO177__FUNC_MIPI_TDN3_A (MTK_PIN_NO(177) | 1) + +#define MT6797_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +#define MT6797_GPIO178__FUNC_DISP_PWM (MTK_PIN_NO(178) | 1) +#define MT6797_GPIO178__FUNC_PWM_D (MTK_PIN_NO(178) | 2) +#define MT6797_GPIO178__FUNC_CLKM5 (MTK_PIN_NO(178) | 3) +#define MT6797_GPIO178__FUNC_DBG_MON_A19 (MTK_PIN_NO(178) | 7) + +#define MT6797_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +#define MT6797_GPIO179__FUNC_DSI_TE0 (MTK_PIN_NO(179) | 1) +#define MT6797_GPIO179__FUNC_DBG_MON_A20 (MTK_PIN_NO(179) | 7) + +#define MT6797_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +#define MT6797_GPIO180__FUNC_LCM_RST (MTK_PIN_NO(180) | 1) +#define MT6797_GPIO180__FUNC_DSI_TE1 (MTK_PIN_NO(180) | 2) +#define MT6797_GPIO180__FUNC_DBG_MON_A21 (MTK_PIN_NO(180) | 7) + +#define MT6797_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +#define MT6797_GPIO181__FUNC_IDDIG (MTK_PIN_NO(181) | 1) +#define MT6797_GPIO181__FUNC_DSI_TE1 (MTK_PIN_NO(181) | 2) +#define MT6797_GPIO181__FUNC_DBG_MON_A22 (MTK_PIN_NO(181) | 7) + +#define MT6797_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +#define MT6797_GPIO182__FUNC_TESTMODE (MTK_PIN_NO(182) | 1) + +#define MT6797_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +#define MT6797_GPIO183__FUNC_RFIC0_BSI_CK (MTK_PIN_NO(183) | 1) +#define MT6797_GPIO183__FUNC_SPM_BSI_CK (MTK_PIN_NO(183) | 2) +#define MT6797_GPIO183__FUNC_DBG_MON_B27 (MTK_PIN_NO(183) | 7) + +#define MT6797_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +#define MT6797_GPIO184__FUNC_RFIC0_BSI_EN (MTK_PIN_NO(184) | 1) +#define MT6797_GPIO184__FUNC_SPM_BSI_EN (MTK_PIN_NO(184) | 2) +#define MT6797_GPIO184__FUNC_DBG_MON_B28 (MTK_PIN_NO(184) | 7) + +#define MT6797_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) +#define MT6797_GPIO185__FUNC_RFIC0_BSI_D0 (MTK_PIN_NO(185) | 1) +#define MT6797_GPIO185__FUNC_SPM_BSI_D0 (MTK_PIN_NO(185) | 2) +#define MT6797_GPIO185__FUNC_DBG_MON_B29 (MTK_PIN_NO(185) | 7) + +#define MT6797_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) +#define MT6797_GPIO186__FUNC_RFIC0_BSI_D1 (MTK_PIN_NO(186) | 1) +#define MT6797_GPIO186__FUNC_SPM_BSI_D1 (MTK_PIN_NO(186) | 2) +#define MT6797_GPIO186__FUNC_DBG_MON_B30 (MTK_PIN_NO(186) | 7) + +#define MT6797_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) +#define MT6797_GPIO187__FUNC_RFIC0_BSI_D2 (MTK_PIN_NO(187) | 1) +#define MT6797_GPIO187__FUNC_SPM_BSI_D2 (MTK_PIN_NO(187) | 2) +#define MT6797_GPIO187__FUNC_DBG_MON_B31 (MTK_PIN_NO(187) | 7) + +#define MT6797_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) +#define MT6797_GPIO188__FUNC_MIPI0_SCLK (MTK_PIN_NO(188) | 1) +#define MT6797_GPIO188__FUNC_DBG_MON_B32 (MTK_PIN_NO(188) | 7) + +#define MT6797_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) +#define MT6797_GPIO189__FUNC_MIPI0_SDATA (MTK_PIN_NO(189) | 1) + +#define MT6797_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) +#define MT6797_GPIO190__FUNC_MIPI1_SCLK (MTK_PIN_NO(190) | 1) + +#define MT6797_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) +#define MT6797_GPIO191__FUNC_MIPI1_SDATA (MTK_PIN_NO(191) | 1) + +#define MT6797_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) +#define MT6797_GPIO192__FUNC_BPI_BUS4 (MTK_PIN_NO(192) | 1) + +#define MT6797_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) +#define MT6797_GPIO193__FUNC_BPI_BUS5 (MTK_PIN_NO(193) | 1) +#define MT6797_GPIO193__FUNC_DBG_MON_B0 (MTK_PIN_NO(193) | 7) + +#define MT6797_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) +#define MT6797_GPIO194__FUNC_BPI_BUS6 (MTK_PIN_NO(194) | 1) +#define MT6797_GPIO194__FUNC_DBG_MON_B1 (MTK_PIN_NO(194) | 7) + +#define MT6797_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) +#define MT6797_GPIO195__FUNC_BPI_BUS7 (MTK_PIN_NO(195) | 1) +#define MT6797_GPIO195__FUNC_DBG_MON_B2 (MTK_PIN_NO(195) | 7) + +#define MT6797_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) +#define MT6797_GPIO196__FUNC_BPI_BUS8 (MTK_PIN_NO(196) | 1) +#define MT6797_GPIO196__FUNC_DBG_MON_B3 (MTK_PIN_NO(196) | 7) + +#define MT6797_GPIO197__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) +#define MT6797_GPIO197__FUNC_BPI_BUS9 (MTK_PIN_NO(197) | 1) +#define MT6797_GPIO197__FUNC_DBG_MON_B4 (MTK_PIN_NO(197) | 7) + +#define MT6797_GPIO198__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) +#define MT6797_GPIO198__FUNC_BPI_BUS10 (MTK_PIN_NO(198) | 1) +#define MT6797_GPIO198__FUNC_DBG_MON_B5 (MTK_PIN_NO(198) | 7) + +#define MT6797_GPIO199__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) +#define MT6797_GPIO199__FUNC_BPI_BUS11 (MTK_PIN_NO(199) | 1) +#define MT6797_GPIO199__FUNC_DBG_MON_B6 (MTK_PIN_NO(199) | 7) + +#define MT6797_GPIO200__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) +#define MT6797_GPIO200__FUNC_BPI_BUS12 (MTK_PIN_NO(200) | 1) +#define MT6797_GPIO200__FUNC_DBG_MON_B7 (MTK_PIN_NO(200) | 7) + +#define MT6797_GPIO201__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) +#define MT6797_GPIO201__FUNC_BPI_BUS13 (MTK_PIN_NO(201) | 1) +#define MT6797_GPIO201__FUNC_DBG_MON_B8 (MTK_PIN_NO(201) | 7) + +#define MT6797_GPIO202__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) +#define MT6797_GPIO202__FUNC_BPI_BUS14 (MTK_PIN_NO(202) | 1) +#define MT6797_GPIO202__FUNC_DBG_MON_B9 (MTK_PIN_NO(202) | 7) + +#define MT6797_GPIO203__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) +#define MT6797_GPIO203__FUNC_BPI_BUS15 (MTK_PIN_NO(203) | 1) +#define MT6797_GPIO203__FUNC_DBG_MON_B10 (MTK_PIN_NO(203) | 7) + +#define MT6797_GPIO204__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) +#define MT6797_GPIO204__FUNC_BPI_BUS16 (MTK_PIN_NO(204) | 1) +#define MT6797_GPIO204__FUNC_PA_VM0 (MTK_PIN_NO(204) | 2) +#define MT6797_GPIO204__FUNC_DBG_MON_B11 (MTK_PIN_NO(204) | 7) + +#define MT6797_GPIO205__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) +#define MT6797_GPIO205__FUNC_BPI_BUS17 (MTK_PIN_NO(205) | 1) +#define MT6797_GPIO205__FUNC_PA_VM1 (MTK_PIN_NO(205) | 2) +#define MT6797_GPIO205__FUNC_DBG_MON_B12 (MTK_PIN_NO(205) | 7) + +#define MT6797_GPIO206__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) +#define MT6797_GPIO206__FUNC_BPI_BUS18 (MTK_PIN_NO(206) | 1) +#define MT6797_GPIO206__FUNC_TX_SWAP0 (MTK_PIN_NO(206) | 2) +#define MT6797_GPIO206__FUNC_DBG_MON_B13 (MTK_PIN_NO(206) | 7) + +#define MT6797_GPIO207__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) +#define MT6797_GPIO207__FUNC_BPI_BUS19 (MTK_PIN_NO(207) | 1) +#define MT6797_GPIO207__FUNC_TX_SWAP1 (MTK_PIN_NO(207) | 2) +#define MT6797_GPIO207__FUNC_DBG_MON_B14 (MTK_PIN_NO(207) | 7) + +#define MT6797_GPIO208__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) +#define MT6797_GPIO208__FUNC_BPI_BUS20 (MTK_PIN_NO(208) | 1) +#define MT6797_GPIO208__FUNC_TX_SWAP2 (MTK_PIN_NO(208) | 2) +#define MT6797_GPIO208__FUNC_DBG_MON_B15 (MTK_PIN_NO(208) | 7) + +#define MT6797_GPIO209__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) +#define MT6797_GPIO209__FUNC_BPI_BUS21 (MTK_PIN_NO(209) | 1) +#define MT6797_GPIO209__FUNC_TX_SWAP3 (MTK_PIN_NO(209) | 2) +#define MT6797_GPIO209__FUNC_DBG_MON_B16 (MTK_PIN_NO(209) | 7) + +#define MT6797_GPIO210__FUNC_GPIO210 (MTK_PIN_NO(210) | 0) +#define MT6797_GPIO210__FUNC_BPI_BUS22 (MTK_PIN_NO(210) | 1) +#define MT6797_GPIO210__FUNC_DET_BPI0 (MTK_PIN_NO(210) | 2) +#define MT6797_GPIO210__FUNC_DBG_MON_B17 (MTK_PIN_NO(210) | 7) + +#define MT6797_GPIO211__FUNC_GPIO211 (MTK_PIN_NO(211) | 0) +#define MT6797_GPIO211__FUNC_BPI_BUS23 (MTK_PIN_NO(211) | 1) +#define MT6797_GPIO211__FUNC_DET_BPI1 (MTK_PIN_NO(211) | 2) +#define MT6797_GPIO211__FUNC_DBG_MON_B18 (MTK_PIN_NO(211) | 7) + +#define MT6797_GPIO212__FUNC_GPIO212 (MTK_PIN_NO(212) | 0) +#define MT6797_GPIO212__FUNC_BPI_BUS0 (MTK_PIN_NO(212) | 1) +#define MT6797_GPIO212__FUNC_DBG_MON_B19 (MTK_PIN_NO(212) | 7) + +#define MT6797_GPIO213__FUNC_GPIO213 (MTK_PIN_NO(213) | 0) +#define MT6797_GPIO213__FUNC_BPI_BUS1 (MTK_PIN_NO(213) | 1) +#define MT6797_GPIO213__FUNC_DBG_MON_B20 (MTK_PIN_NO(213) | 7) + +#define MT6797_GPIO214__FUNC_GPIO214 (MTK_PIN_NO(214) | 0) +#define MT6797_GPIO214__FUNC_BPI_BUS2 (MTK_PIN_NO(214) | 1) +#define MT6797_GPIO214__FUNC_DBG_MON_B21 (MTK_PIN_NO(214) | 7) + +#define MT6797_GPIO215__FUNC_GPIO215 (MTK_PIN_NO(215) | 0) +#define MT6797_GPIO215__FUNC_BPI_BUS3 (MTK_PIN_NO(215) | 1) +#define MT6797_GPIO215__FUNC_DBG_MON_B22 (MTK_PIN_NO(215) | 7) + +#define MT6797_GPIO216__FUNC_GPIO216 (MTK_PIN_NO(216) | 0) +#define MT6797_GPIO216__FUNC_MIPI2_SCLK (MTK_PIN_NO(216) | 1) +#define MT6797_GPIO216__FUNC_DBG_MON_B23 (MTK_PIN_NO(216) | 7) + +#define MT6797_GPIO217__FUNC_GPIO217 (MTK_PIN_NO(217) | 0) +#define MT6797_GPIO217__FUNC_MIPI2_SDATA (MTK_PIN_NO(217) | 1) +#define MT6797_GPIO217__FUNC_DBG_MON_B24 (MTK_PIN_NO(217) | 7) + +#define MT6797_GPIO218__FUNC_GPIO218 (MTK_PIN_NO(218) | 0) +#define MT6797_GPIO218__FUNC_MIPI3_SCLK (MTK_PIN_NO(218) | 1) +#define MT6797_GPIO218__FUNC_DBG_MON_B25 (MTK_PIN_NO(218) | 7) + +#define MT6797_GPIO219__FUNC_GPIO219 (MTK_PIN_NO(219) | 0) +#define MT6797_GPIO219__FUNC_MIPI3_SDATA (MTK_PIN_NO(219) | 1) +#define MT6797_GPIO219__FUNC_DBG_MON_B26 (MTK_PIN_NO(219) | 7) + +#define MT6797_GPIO220__FUNC_GPIO220 (MTK_PIN_NO(220) | 0) +#define MT6797_GPIO220__FUNC_CONN_WF_IP (MTK_PIN_NO(220) | 1) + +#define MT6797_GPIO221__FUNC_GPIO221 (MTK_PIN_NO(221) | 0) +#define MT6797_GPIO221__FUNC_CONN_WF_IN (MTK_PIN_NO(221) | 1) + +#define MT6797_GPIO222__FUNC_GPIO222 (MTK_PIN_NO(222) | 0) +#define MT6797_GPIO222__FUNC_CONN_WF_QP (MTK_PIN_NO(222) | 1) + +#define MT6797_GPIO223__FUNC_GPIO223 (MTK_PIN_NO(223) | 0) +#define MT6797_GPIO223__FUNC_CONN_WF_QN (MTK_PIN_NO(223) | 1) + +#define MT6797_GPIO224__FUNC_GPIO224 (MTK_PIN_NO(224) | 0) +#define MT6797_GPIO224__FUNC_CONN_BT_IP (MTK_PIN_NO(224) | 1) + +#define MT6797_GPIO225__FUNC_GPIO225 (MTK_PIN_NO(225) | 0) +#define MT6797_GPIO225__FUNC_CONN_BT_IN (MTK_PIN_NO(225) | 1) + +#define MT6797_GPIO226__FUNC_GPIO226 (MTK_PIN_NO(226) | 0) +#define MT6797_GPIO226__FUNC_CONN_BT_QP (MTK_PIN_NO(226) | 1) + +#define MT6797_GPIO227__FUNC_GPIO227 (MTK_PIN_NO(227) | 0) +#define MT6797_GPIO227__FUNC_CONN_BT_QN (MTK_PIN_NO(227) | 1) + +#define MT6797_GPIO228__FUNC_GPIO228 (MTK_PIN_NO(228) | 0) +#define MT6797_GPIO228__FUNC_CONN_GPS_IP (MTK_PIN_NO(228) | 1) + +#define MT6797_GPIO229__FUNC_GPIO229 (MTK_PIN_NO(229) | 0) +#define MT6797_GPIO229__FUNC_CONN_GPS_IN (MTK_PIN_NO(229) | 1) + +#define MT6797_GPIO230__FUNC_GPIO230 (MTK_PIN_NO(230) | 0) +#define MT6797_GPIO230__FUNC_CONN_GPS_QP (MTK_PIN_NO(230) | 1) + +#define MT6797_GPIO231__FUNC_GPIO231 (MTK_PIN_NO(231) | 0) +#define MT6797_GPIO231__FUNC_CONN_GPS_QN (MTK_PIN_NO(231) | 1) + +#define MT6797_GPIO232__FUNC_GPIO232 (MTK_PIN_NO(232) | 0) +#define MT6797_GPIO232__FUNC_URXD1 (MTK_PIN_NO(232) | 1) +#define MT6797_GPIO232__FUNC_UTXD1 (MTK_PIN_NO(232) | 2) +#define MT6797_GPIO232__FUNC_MD_URXD0 (MTK_PIN_NO(232) | 3) +#define MT6797_GPIO232__FUNC_MD_URXD1 (MTK_PIN_NO(232) | 4) +#define MT6797_GPIO232__FUNC_MD_URXD2 (MTK_PIN_NO(232) | 5) +#define MT6797_GPIO232__FUNC_C2K_URXD0 (MTK_PIN_NO(232) | 6) +#define MT6797_GPIO232__FUNC_C2K_URXD1 (MTK_PIN_NO(232) | 7) + +#define MT6797_GPIO233__FUNC_GPIO233 (MTK_PIN_NO(233) | 0) +#define MT6797_GPIO233__FUNC_UTXD1 (MTK_PIN_NO(233) | 1) +#define MT6797_GPIO233__FUNC_URXD1 (MTK_PIN_NO(233) | 2) +#define MT6797_GPIO233__FUNC_MD_UTXD0 (MTK_PIN_NO(233) | 3) +#define MT6797_GPIO233__FUNC_MD_UTXD1 (MTK_PIN_NO(233) | 4) +#define MT6797_GPIO233__FUNC_MD_UTXD2 (MTK_PIN_NO(233) | 5) +#define MT6797_GPIO233__FUNC_C2K_UTXD0 (MTK_PIN_NO(233) | 6) +#define MT6797_GPIO233__FUNC_C2K_UTXD1 (MTK_PIN_NO(233) | 7) + +#define MT6797_GPIO234__FUNC_GPIO234 (MTK_PIN_NO(234) | 0) +#define MT6797_GPIO234__FUNC_SPI1_CLK_B (MTK_PIN_NO(234) | 1) +#define MT6797_GPIO234__FUNC_TP_UTXD1_AO (MTK_PIN_NO(234) | 2) +#define MT6797_GPIO234__FUNC_SCL4_1 (MTK_PIN_NO(234) | 3) +#define MT6797_GPIO234__FUNC_UTXD0 (MTK_PIN_NO(234) | 4) +#define MT6797_GPIO234__FUNC_PWM_A (MTK_PIN_NO(234) | 6) +#define MT6797_GPIO234__FUNC_DBG_MON_A23 (MTK_PIN_NO(234) | 7) + +#define MT6797_GPIO235__FUNC_GPIO235 (MTK_PIN_NO(235) | 0) +#define MT6797_GPIO235__FUNC_SPI1_MI_B (MTK_PIN_NO(235) | 1) +#define MT6797_GPIO235__FUNC_SPI1_MO_B (MTK_PIN_NO(235) | 2) +#define MT6797_GPIO235__FUNC_SDA4_1 (MTK_PIN_NO(235) | 3) +#define MT6797_GPIO235__FUNC_URXD0 (MTK_PIN_NO(235) | 4) +#define MT6797_GPIO235__FUNC_CLKM0 (MTK_PIN_NO(235) | 6) +#define MT6797_GPIO235__FUNC_DBG_MON_A24 (MTK_PIN_NO(235) | 7) + +#define MT6797_GPIO236__FUNC_GPIO236 (MTK_PIN_NO(236) | 0) +#define MT6797_GPIO236__FUNC_SPI1_MO_B (MTK_PIN_NO(236) | 1) +#define MT6797_GPIO236__FUNC_SPI1_MI_B (MTK_PIN_NO(236) | 2) +#define MT6797_GPIO236__FUNC_SCL5_1 (MTK_PIN_NO(236) | 3) +#define MT6797_GPIO236__FUNC_URTS0 (MTK_PIN_NO(236) | 4) +#define MT6797_GPIO236__FUNC_PWM_B (MTK_PIN_NO(236) | 6) +#define MT6797_GPIO236__FUNC_DBG_MON_A25 (MTK_PIN_NO(236) | 7) + +#define MT6797_GPIO237__FUNC_GPIO237 (MTK_PIN_NO(237) | 0) +#define MT6797_GPIO237__FUNC_SPI1_CS_B (MTK_PIN_NO(237) | 1) +#define MT6797_GPIO237__FUNC_TP_URXD1_AO (MTK_PIN_NO(237) | 2) +#define MT6797_GPIO237__FUNC_SDA5_1 (MTK_PIN_NO(237) | 3) +#define MT6797_GPIO237__FUNC_UCTS0 (MTK_PIN_NO(237) | 4) +#define MT6797_GPIO237__FUNC_CLKM1 (MTK_PIN_NO(237) | 6) +#define MT6797_GPIO237__FUNC_DBG_MON_A26 (MTK_PIN_NO(237) | 7) + +#define MT6797_GPIO238__FUNC_GPIO238 (MTK_PIN_NO(238) | 0) +#define MT6797_GPIO238__FUNC_SDA4_0 (MTK_PIN_NO(238) | 1) + +#define MT6797_GPIO239__FUNC_GPIO239 (MTK_PIN_NO(239) | 0) +#define MT6797_GPIO239__FUNC_SCL4_0 (MTK_PIN_NO(239) | 1) + +#define MT6797_GPIO240__FUNC_GPIO240 (MTK_PIN_NO(240) | 0) +#define MT6797_GPIO240__FUNC_SDA5_0 (MTK_PIN_NO(240) | 1) + +#define MT6797_GPIO241__FUNC_GPIO241 (MTK_PIN_NO(241) | 0) +#define MT6797_GPIO241__FUNC_SCL5_0 (MTK_PIN_NO(241) | 1) + +#define MT6797_GPIO242__FUNC_GPIO242 (MTK_PIN_NO(242) | 0) +#define MT6797_GPIO242__FUNC_SPI2_CLK_B (MTK_PIN_NO(242) | 1) +#define MT6797_GPIO242__FUNC_TP_UTXD2_AO (MTK_PIN_NO(242) | 2) +#define MT6797_GPIO242__FUNC_SCL4_2 (MTK_PIN_NO(242) | 3) +#define MT6797_GPIO242__FUNC_UTXD1 (MTK_PIN_NO(242) | 4) +#define MT6797_GPIO242__FUNC_URTS3 (MTK_PIN_NO(242) | 5) +#define MT6797_GPIO242__FUNC_PWM_C (MTK_PIN_NO(242) | 6) +#define MT6797_GPIO242__FUNC_DBG_MON_A27 (MTK_PIN_NO(242) | 7) + +#define MT6797_GPIO243__FUNC_GPIO243 (MTK_PIN_NO(243) | 0) +#define MT6797_GPIO243__FUNC_SPI2_MI_B (MTK_PIN_NO(243) | 1) +#define MT6797_GPIO243__FUNC_SPI2_MO_B (MTK_PIN_NO(243) | 2) +#define MT6797_GPIO243__FUNC_SDA4_2 (MTK_PIN_NO(243) | 3) +#define MT6797_GPIO243__FUNC_URXD1 (MTK_PIN_NO(243) | 4) +#define MT6797_GPIO243__FUNC_UCTS3 (MTK_PIN_NO(243) | 5) +#define MT6797_GPIO243__FUNC_CLKM2 (MTK_PIN_NO(243) | 6) +#define MT6797_GPIO243__FUNC_DBG_MON_A28 (MTK_PIN_NO(243) | 7) + +#define MT6797_GPIO244__FUNC_GPIO244 (MTK_PIN_NO(244) | 0) +#define MT6797_GPIO244__FUNC_SPI2_MO_B (MTK_PIN_NO(244) | 1) +#define MT6797_GPIO244__FUNC_SPI2_MI_B (MTK_PIN_NO(244) | 2) +#define MT6797_GPIO244__FUNC_SCL5_2 (MTK_PIN_NO(244) | 3) +#define MT6797_GPIO244__FUNC_URTS1 (MTK_PIN_NO(244) | 4) +#define MT6797_GPIO244__FUNC_UTXD3 (MTK_PIN_NO(244) | 5) +#define MT6797_GPIO244__FUNC_PWM_D (MTK_PIN_NO(244) | 6) +#define MT6797_GPIO244__FUNC_DBG_MON_A29 (MTK_PIN_NO(244) | 7) + +#define MT6797_GPIO245__FUNC_GPIO245 (MTK_PIN_NO(245) | 0) +#define MT6797_GPIO245__FUNC_SPI2_CS_B (MTK_PIN_NO(245) | 1) +#define MT6797_GPIO245__FUNC_TP_URXD2_AO (MTK_PIN_NO(245) | 2) +#define MT6797_GPIO245__FUNC_SDA5_2 (MTK_PIN_NO(245) | 3) +#define MT6797_GPIO245__FUNC_UCTS1 (MTK_PIN_NO(245) | 4) +#define MT6797_GPIO245__FUNC_URXD3 (MTK_PIN_NO(245) | 5) +#define MT6797_GPIO245__FUNC_CLKM3 (MTK_PIN_NO(245) | 6) +#define MT6797_GPIO245__FUNC_DBG_MON_A30 (MTK_PIN_NO(245) | 7) + +#define MT6797_GPIO246__FUNC_GPIO246 (MTK_PIN_NO(246) | 0) +#define MT6797_GPIO246__FUNC_I2S1_LRCK (MTK_PIN_NO(246) | 1) +#define MT6797_GPIO246__FUNC_I2S2_LRCK (MTK_PIN_NO(246) | 2) +#define MT6797_GPIO246__FUNC_I2S0_LRCK (MTK_PIN_NO(246) | 3) +#define MT6797_GPIO246__FUNC_I2S3_LRCK (MTK_PIN_NO(246) | 4) +#define MT6797_GPIO246__FUNC_PCM0_SYNC (MTK_PIN_NO(246) | 5) +#define MT6797_GPIO246__FUNC_SPI5_CLK_C (MTK_PIN_NO(246) | 6) +#define MT6797_GPIO246__FUNC_DBG_MON_A31 (MTK_PIN_NO(246) | 7) + +#define MT6797_GPIO247__FUNC_GPIO247 (MTK_PIN_NO(247) | 0) +#define MT6797_GPIO247__FUNC_I2S1_BCK (MTK_PIN_NO(247) | 1) +#define MT6797_GPIO247__FUNC_I2S2_BCK (MTK_PIN_NO(247) | 2) +#define MT6797_GPIO247__FUNC_I2S0_BCK (MTK_PIN_NO(247) | 3) +#define MT6797_GPIO247__FUNC_I2S3_BCK (MTK_PIN_NO(247) | 4) +#define MT6797_GPIO247__FUNC_PCM0_CLK (MTK_PIN_NO(247) | 5) +#define MT6797_GPIO247__FUNC_SPI5_MI_C (MTK_PIN_NO(247) | 6) +#define MT6797_GPIO247__FUNC_DBG_MON_A32 (MTK_PIN_NO(247) | 7) + +#define MT6797_GPIO248__FUNC_GPIO248 (MTK_PIN_NO(248) | 0) +/* #define MT6797_GPIO248__FUNC_I2S2_DI (MTK_PIN_NO(248) | 1) */ +#define MT6797_GPIO248__FUNC_I2S2_DI (MTK_PIN_NO(248) | 2) +/* #define MT6797_GPIO248__FUNC_I2S0_DI (MTK_PIN_NO(248) | 3) */ +#define MT6797_GPIO248__FUNC_I2S0_DI (MTK_PIN_NO(248) | 4) +#define MT6797_GPIO248__FUNC_PCM0_DI (MTK_PIN_NO(248) | 5) +#define MT6797_GPIO248__FUNC_SPI5_CS_C (MTK_PIN_NO(248) | 6) + +#define MT6797_GPIO249__FUNC_GPIO249 (MTK_PIN_NO(249) | 0) +/* #define MT6797_GPIO249__FUNC_I2S1_DO (MTK_PIN_NO(249) | 1) */ +#define MT6797_GPIO249__FUNC_I2S1_DO (MTK_PIN_NO(249) | 2) +/* #define MT6797_GPIO249__FUNC_I2S3_DO (MTK_PIN_NO(249) | 3) */ +#define MT6797_GPIO249__FUNC_I2S3_DO (MTK_PIN_NO(249) | 4) +#define MT6797_GPIO249__FUNC_PCM0_DO (MTK_PIN_NO(249) | 5) +#define MT6797_GPIO249__FUNC_SPI5_MO_C (MTK_PIN_NO(249) | 6) +#define MT6797_GPIO249__FUNC_TRAP_SRAM_PWR_BYPASS (MTK_PIN_NO(249) | 7) + +#define MT6797_GPIO250__FUNC_GPIO250 (MTK_PIN_NO(250) | 0) +#define MT6797_GPIO250__FUNC_SPI3_MI (MTK_PIN_NO(250) | 1) +#define MT6797_GPIO250__FUNC_SPI3_MO (MTK_PIN_NO(250) | 2) +#define MT6797_GPIO250__FUNC_IRTX_OUT (MTK_PIN_NO(250) | 3) +#define MT6797_GPIO250__FUNC_TP_URXD1_AO (MTK_PIN_NO(250) | 6) +#define MT6797_GPIO250__FUNC_DROP_ZONE (MTK_PIN_NO(250) | 7) + +#define MT6797_GPIO251__FUNC_GPIO251 (MTK_PIN_NO(251) | 0) +#define MT6797_GPIO251__FUNC_SPI3_MO (MTK_PIN_NO(251) | 1) +#define MT6797_GPIO251__FUNC_SPI3_MI (MTK_PIN_NO(251) | 2) +#define MT6797_GPIO251__FUNC_CMFLASH (MTK_PIN_NO(251) | 3) +#define MT6797_GPIO251__FUNC_TP_UTXD1_AO (MTK_PIN_NO(251) | 6) +#define MT6797_GPIO251__FUNC_C2K_RTCK (MTK_PIN_NO(251) | 7) + +#define MT6797_GPIO252__FUNC_GPIO252 (MTK_PIN_NO(252) | 0) +#define MT6797_GPIO252__FUNC_SPI3_CLK (MTK_PIN_NO(252) | 1) +#define MT6797_GPIO252__FUNC_SCL0_4 (MTK_PIN_NO(252) | 2) +#define MT6797_GPIO252__FUNC_PWM_D (MTK_PIN_NO(252) | 3) +#define MT6797_GPIO252__FUNC_C2K_TMS (MTK_PIN_NO(252) | 7) + +#define MT6797_GPIO253__FUNC_GPIO253 (MTK_PIN_NO(253) | 0) +#define MT6797_GPIO253__FUNC_SPI3_CS (MTK_PIN_NO(253) | 1) +#define MT6797_GPIO253__FUNC_SDA0_4 (MTK_PIN_NO(253) | 2) +#define MT6797_GPIO253__FUNC_PWM_A (MTK_PIN_NO(253) | 3) +#define MT6797_GPIO253__FUNC_C2K_TCK (MTK_PIN_NO(253) | 7) + +#define MT6797_GPIO254__FUNC_GPIO254 (MTK_PIN_NO(254) | 0) +#define MT6797_GPIO254__FUNC_I2S1_MCK (MTK_PIN_NO(254) | 1) +#define MT6797_GPIO254__FUNC_I2S2_MCK (MTK_PIN_NO(254) | 2) +#define MT6797_GPIO254__FUNC_I2S0_MCK (MTK_PIN_NO(254) | 3) +#define MT6797_GPIO254__FUNC_I2S3_MCK (MTK_PIN_NO(254) | 4) +#define MT6797_GPIO254__FUNC_CLKM0 (MTK_PIN_NO(254) | 5) +#define MT6797_GPIO254__FUNC_C2K_TDI (MTK_PIN_NO(254) | 7) + +#define MT6797_GPIO255__FUNC_GPIO255 (MTK_PIN_NO(255) | 0) +#define MT6797_GPIO255__FUNC_CLKM1 (MTK_PIN_NO(255) | 1) +#define MT6797_GPIO255__FUNC_DISP_PWM (MTK_PIN_NO(255) | 2) +#define MT6797_GPIO255__FUNC_PWM_B (MTK_PIN_NO(255) | 3) +#define MT6797_GPIO255__FUNC_TP_GPIO1_AO (MTK_PIN_NO(255) | 6) +#define MT6797_GPIO255__FUNC_C2K_TDO (MTK_PIN_NO(255) | 7) + +#define MT6797_GPIO256__FUNC_GPIO256 (MTK_PIN_NO(256) | 0) +#define MT6797_GPIO256__FUNC_CLKM2 (MTK_PIN_NO(256) | 1) +#define MT6797_GPIO256__FUNC_IRTX_OUT (MTK_PIN_NO(256) | 2) +#define MT6797_GPIO256__FUNC_PWM_C (MTK_PIN_NO(256) | 3) +#define MT6797_GPIO256__FUNC_TP_GPIO0_AO (MTK_PIN_NO(256) | 6) +#define MT6797_GPIO256__FUNC_C2K_NTRST (MTK_PIN_NO(256) | 7) + +#define MT6797_GPIO257__FUNC_GPIO257 (MTK_PIN_NO(257) | 0) +#define MT6797_GPIO257__FUNC_IO_JTAG_TMS (MTK_PIN_NO(257) | 1) +#define MT6797_GPIO257__FUNC_LTE_JTAG_TMS (MTK_PIN_NO(257) | 2) +#define MT6797_GPIO257__FUNC_DFD_TMS (MTK_PIN_NO(257) | 3) +#define MT6797_GPIO257__FUNC_DAP_SIB1_SWD (MTK_PIN_NO(257) | 4) +#define MT6797_GPIO257__FUNC_ANC_JTAG_TMS (MTK_PIN_NO(257) | 5) +#define MT6797_GPIO257__FUNC_SCP_JTAG_TMS (MTK_PIN_NO(257) | 6) +#define MT6797_GPIO257__FUNC_C2K_DM_OTMS (MTK_PIN_NO(257) | 7) + +#define MT6797_GPIO258__FUNC_GPIO258 (MTK_PIN_NO(258) | 0) +#define MT6797_GPIO258__FUNC_IO_JTAG_TCK (MTK_PIN_NO(258) | 1) +#define MT6797_GPIO258__FUNC_LTE_JTAG_TCK (MTK_PIN_NO(258) | 2) +#define MT6797_GPIO258__FUNC_DFD_TCK_XI (MTK_PIN_NO(258) | 3) +#define MT6797_GPIO258__FUNC_DAP_SIB1_SWCK (MTK_PIN_NO(258) | 4) +#define MT6797_GPIO258__FUNC_ANC_JTAG_TCK (MTK_PIN_NO(258) | 5) +#define MT6797_GPIO258__FUNC_SCP_JTAG_TCK (MTK_PIN_NO(258) | 6) +#define MT6797_GPIO258__FUNC_C2K_DM_OTCK (MTK_PIN_NO(258) | 7) + +#define MT6797_GPIO259__FUNC_GPIO259 (MTK_PIN_NO(259) | 0) +#define MT6797_GPIO259__FUNC_IO_JTAG_TDI (MTK_PIN_NO(259) | 1) +#define MT6797_GPIO259__FUNC_LTE_JTAG_TDI (MTK_PIN_NO(259) | 2) +#define MT6797_GPIO259__FUNC_DFD_TDI (MTK_PIN_NO(259) | 3) +#define MT6797_GPIO259__FUNC_ANC_JTAG_TDI (MTK_PIN_NO(259) | 5) +#define MT6797_GPIO259__FUNC_SCP_JTAG_TDI (MTK_PIN_NO(259) | 6) +#define MT6797_GPIO259__FUNC_C2K_DM_OTDI (MTK_PIN_NO(259) | 7) + +#define MT6797_GPIO260__FUNC_GPIO260 (MTK_PIN_NO(260) | 0) +#define MT6797_GPIO260__FUNC_IO_JTAG_TDO (MTK_PIN_NO(260) | 1) +#define MT6797_GPIO260__FUNC_LTE_JTAG_TDO (MTK_PIN_NO(260) | 2) +#define MT6797_GPIO260__FUNC_DFD_TDO (MTK_PIN_NO(260) | 3) +#define MT6797_GPIO260__FUNC_ANC_JTAG_TDO (MTK_PIN_NO(260) | 5) +#define MT6797_GPIO260__FUNC_SCP_JTAG_TDO (MTK_PIN_NO(260) | 6) +#define MT6797_GPIO260__FUNC_C2K_DM_OTDO (MTK_PIN_NO(260) | 7) + +#define MT6797_GPIO261__FUNC_GPIO261 (MTK_PIN_NO(261) | 0) +#define MT6797_GPIO261__FUNC_LTE_JTAG_TRSTN (MTK_PIN_NO(261) | 2) +#define MT6797_GPIO261__FUNC_DFD_NTRST (MTK_PIN_NO(261) | 3) +#define MT6797_GPIO261__FUNC_ANC_JTAG_TRSTN (MTK_PIN_NO(261) | 5) +#define MT6797_GPIO261__FUNC_SCP_JTAG_TRSTN (MTK_PIN_NO(261) | 6) +#define MT6797_GPIO261__FUNC_C2K_DM_JTINTP (MTK_PIN_NO(261) | 7) + +#endif /* __DTS_MT6797_PINFUNC_H */ From patchwork Mon Oct 8 19:14:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 148440 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp4020976lji; Mon, 8 Oct 2018 12:14:47 -0700 (PDT) X-Google-Smtp-Source: ACcGV62igkVXp5ViSKXYJnW83zD2V1Oulikam1qyJURgOkBmsIi1myW8/F1ZdmWQYA56fbH12lZf X-Received: by 2002:a17:902:e012:: with SMTP id ca18-v6mr24766740plb.195.1539026087002; Mon, 08 Oct 2018 12:14:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539026086; cv=none; d=google.com; s=arc-20160816; b=PWgsiTBteDy1Rr8WfMRSnCNU2ukHyxS1PVDTNzpNjaA2XbUjkkRTBF3bbdvxPGMVzl +4NF+jnkosGt5DotK8206iXGFQrTQVpoFttExJw3tLr9ysNwlpjxtVc5Im56rlnxstYw kjWALvdLxw6a+uf1oOjSzPVKZTChkNnH7dawODaZyb1VS+KiuarnEEFQZyJ0wR9bxxVX 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Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/mediatek/mt6797.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi index 4beaa71107d7..231230d32d09 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include / { compatible = "mediatek,mt6797"; @@ -129,6 +130,19 @@ #clock-cells = <1>; }; + pio: pinctrl@10005000 { + compatible = "mediatek,mt6797-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x10002000 0 0x400>, + <0 0x10002400 0 0x400>, + <0 0x10002800 0 0x400>, + <0 0x10002C00 0 0x400>; + reg-names = "gpio", "iocfgl", "iocfgb", + "iocfgr", "iocfgt"; + gpio-controller; + #gpio-cells = <2>; + }; + scpsys: scpsys@10006000 { compatible = "mediatek,mt6797-scpsys"; #power-domain-cells = <1>; From patchwork Mon Oct 8 19:14:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 148441 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp4021045lji; Mon, 8 Oct 2018 12:14:51 -0700 (PDT) X-Google-Smtp-Source: ACcGV62y6dJtDu4znSM43j++tDTvxxrAai5Ny7fIw/6t8PhG006CBRxalr+Iq2Vq73Uxxy7PVvfU X-Received: by 2002:a63:501:: with SMTP id 1-v6mr22136693pgf.205.1539026091061; Mon, 08 Oct 2018 12:14:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539026091; cv=none; d=google.com; s=arc-20160816; b=TP5qfanUNhzAAypchMR46JCsj1k3AwyKl3ILhW51MGHiKM9QS+gM9z/Ccosj1Gsg+E E1kdNM/GF/a9qn0i0h0rITM3NOnu8rpUXswnoHJPOEJvlMo9con0N8b1vBBYG/rWACxl EtDgG0R7uugXIO8fbCwX2/l51poIDVMhq+6zuJ7V5C84yIbxeoW5egfuj5RAoRgGRGur XNnkCm+11fsYXmJ3BNuwXB4PqR+hQmu2pDW71/GxkFQ2ixdXABhwneD2UiT47aXWyGTV jmJpYLD1MKVqDlEKOUs3PpYWnT5GSKDZqUxUm1ykmAZkvHHoeVXi8EXfFaBOIaev8pRV Rv2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=v+EkBGJYgP5l8roNkAIcHxwpqxLvNbg8+WmAulqw8rE=; b=rpy/IM75CuAXgk3jVdv7/KRklRRFZIxZGnQj60Guri5ys1w37VbBOt7czfFKp4ROUf AazL3EAqXVWk7fOY2SQLg8nMVCUawSuxYzAhxdEtE4LeFVXwx+x9X43Pkkk5pO0Lk15E 4X4HxKBRLdzlhJOnqiVLyEHE10B2FF2pa18IVY4LXDnuiJnFBYAhe3ng+QyJPfyEo0k7 wBxtH8LQPU9Pkn9eLFJjOP13fRo6p2HpdrKyZS2t0bRMdMNQyIoXQQfmeWLmQeaSeG7Z tfcau1ffc1baoO/3eALo9ppOwf1DGY3sskweyzxRuT/BlMgK6KyJUGgiy79ps/k4IihF Hb3w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GsvmHcKX; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 1-v6si19809838pls.340.2018.10.08.12.14.50; Mon, 08 Oct 2018 12:14:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GsvmHcKX; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728024AbeJIC2D (ORCPT + 32 others); Mon, 8 Oct 2018 22:28:03 -0400 Received: from mail-pf1-f193.google.com ([209.85.210.193]:34487 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727852AbeJIC2C (ORCPT ); Mon, 8 Oct 2018 22:28:02 -0400 Received: by mail-pf1-f193.google.com with SMTP id k19-v6so8820055pfi.1 for ; Mon, 08 Oct 2018 12:14:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=v+EkBGJYgP5l8roNkAIcHxwpqxLvNbg8+WmAulqw8rE=; b=GsvmHcKXZLLg9D8JsGEhcSA4tY7FRDhnnZuE4crvm3+w/aW+70L1Z7AXOqjp/Xz0Qx HapGzRngWQUsqL9f3l8balsF27eU87IglMFxJacj8ZSJOEur+H6W+bquJmuAP+odSDYA 1tGnYedayjB/yL6UZQ/loQPEgmL3aoiDgtQXc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=v+EkBGJYgP5l8roNkAIcHxwpqxLvNbg8+WmAulqw8rE=; b=t4MLLC0k/8w6HGLukfkXGVVeg4RzNuV5sD1kmexRzsDeOewjrQ/kJElLEFGGQVmZaZ 6TJbyl2+QgvDlS0I4pl5AvSxgbJhKH+sSzOTgPouIFv6tYUFQxrFmqAXXPb12gtSYfjN mAoPM4u03nKUNQESEGqcDlBw8hlEWmTYNrrAyECq+eSz7rGpgXzarpPjlmZG0wUVSdOt JbhGHI4vHm89YH8mEs2rp/XuyYnc/7i5o8udPlWz/e3DCShq59hurZgC+JHSTLU/HZxR 2Vf8VwhOIrh4+tfo5bFV8876L3wAXwUzLVU0G2+O7hY0/EO+P3emXpfbpaH2+h1t8v89 eCsQ== X-Gm-Message-State: ABuFfojzFnrYDQnVnDtE8KcQB+YPqO43m7xq43Q1l4+kBg4rPGCAkCsf /Aa8heI2bj/QCjTaYvTw8awB X-Received: by 2002:a63:5816:: with SMTP id m22-v6mr22077083pgb.332.1539026087434; Mon, 08 Oct 2018 12:14:47 -0700 (PDT) Received: from localhost.localdomain ([2405:204:73c6:20ea:9fd:1785:d893:1e98]) by smtp.gmail.com with ESMTPSA id a15-v6sm15648035pff.8.2018.10.08.12.14.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 08 Oct 2018 12:14:47 -0700 (PDT) From: Manivannan Sadhasivam To: sean.wang@mediatek.com, linus.walleij@linaro.org, matthias.bgg@gmail.com, robh+dt@kernel.org Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, amit.kucheria@linaro.org, Manivannan Sadhasivam Subject: [PATCH 3/5] arm64: dts: mediatek: x20: Add pinmux support for UART1 Date: Tue, 9 Oct 2018 00:44:09 +0530 Message-Id: <20181008191411.32555-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181008191411.32555-1-manivannan.sadhasivam@linaro.org> References: <20181008191411.32555-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add pinmux support for UART1 on MediatekX20 Development board based on Mediatek MT6797 SoC. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts | 2 ++ arch/arm64/boot/dts/mediatek/mt6797.dtsi | 7 +++++++ 2 files changed, 9 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts index 742938a1a548..13939d55b85b 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts +++ b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts @@ -30,4 +30,6 @@ &uart1 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi index 231230d32d09..a64bb84bdec3 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi @@ -141,6 +141,13 @@ "iocfgr", "iocfgt"; gpio-controller; #gpio-cells = <2>; + + uart1_pins_a: uart1 { + pins1 { + pinmux = , + ; + }; + }; }; scpsys: scpsys@10006000 { From patchwork Mon Oct 8 19:14:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 148442 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp4021153lji; Mon, 8 Oct 2018 12:14:58 -0700 (PDT) X-Google-Smtp-Source: ACcGV62M/33hV3YC0Hm/5C1ag2h0fBZ5AhOV2Mi9aE2+dHTqv75ziADcHJngqf5sad39XVrKZbaq X-Received: by 2002:a17:902:6b46:: with SMTP id g6-v6mr24622133plt.19.1539026098788; Mon, 08 Oct 2018 12:14:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539026098; cv=none; d=google.com; s=arc-20160816; b=D/gfuzDMi31/CBQthbTbVWeQ5lFyLXkEuOmx0dJ6Q0DySukf1hHxTZVNemCTGtnwZn 7i60HLzelUx+PeuqT3FxXbFM3qs6A4P/scgIcbxSGj6694RF7QGewy6bCOHXJv6YlPZE ZbjnIjL5W0srbKOzNTDRwYy51naOj3QgerDYF/J9iWWVg/jCQ6CZD295mT/YYL4jqZS8 VQcw6QHEKg/DNK7PhCHrBkGawkTcY1jszRkV00wiQEJCKN+pqB4Mdyclqv/GQFZUOQG7 vZkgk0JB3BCArbQNtUCK1tYAWIFiJiaGq098h4FS3smAwYKwn8YarbrKpRXvOaYCQnnO +e2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=0DFpLkI1lNkAOGQBFjmq2KvrwZ3ezAavaUuWVCM404M=; b=DhDLh5HgLgUz9tK21UZ2qYVAaQ9fXn5ZMXxfO8A5fQWqG4H8drb4lyaupbUiGtdXMB iu+CQmYwwBxJEMRKo6wpyssyoCgI2DzNOHyXMHciJ1s6BeQ5Zgwi7fkfEQoSEq2Isi0f qYO/Pk+0I53YcIp1xYLyiaSyNE8U7aunqAKItMxuzyRpnjhksIujiY/BIv+8dwHQPiEr FeDvQupwoZsZGmnvngS2YA/tU09FAUKsEtm1cPuDgDYtDHINyQNQEFs1yLojC2JTU5xS pVm1PF/YiUXDTnK/PUfcNFv8IDw64AOdAEY2Ghdrf7oTj9CU96td0lE/lJ6TeVCLe7EK AWEg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fxqIgHHL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j16-v6si17036564pgm.501.2018.10.08.12.14.58; Mon, 08 Oct 2018 12:14:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fxqIgHHL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728135AbeJIC2K (ORCPT + 32 others); Mon, 8 Oct 2018 22:28:10 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:46646 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728039AbeJIC2J (ORCPT ); Mon, 8 Oct 2018 22:28:09 -0400 Received: by mail-pl1-f194.google.com with SMTP id v5-v6so10473346plz.13 for ; Mon, 08 Oct 2018 12:14:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0DFpLkI1lNkAOGQBFjmq2KvrwZ3ezAavaUuWVCM404M=; b=fxqIgHHLnh41AnjmBb2pMLDToDRT17Jxa32+2Cy+zp7fIx7L+N/JTOfoNEcgkrw5G5 nLpTAIvb7j2PKfuMe2N3HDUZIQXF3/Ahs/ZOxVUy4V7hXfqd5CThL4dMsHjc/tcHCpWH QSfI14FmQ5nKO3vuYZJgQ9Zaf5iG3S9yiGyFQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0DFpLkI1lNkAOGQBFjmq2KvrwZ3ezAavaUuWVCM404M=; b=PkViRPJjCGQfwAUR69ijvEBsd+lE6jNElx44Ig3TV5N+KxbOulfZ5wK7UDkesiZHdn YwVv1Q1hMz1MFch4iaxz3qcca+JIzEMAApm+oJRJa/IZiIwgnqwEM0mpb3SKbekbg7NS 9DV4iAhQhR3cUqIkb50/Sx3r4JqaYJUjsP7Q9qbCHpDjjG63+ewuRgzkldfhM8sUULWm OnNYunbtqlcyARYEk8i2mCFNNf6uPqdrGjpUAZ/rdxBPbT+MQmPwfc0uZP5Zkilo/pAD g0HsexnMNAdZUGghWJpyLx293+QajktpBvHXgCYgqBPz5C5/JKcQK22mKxdi6jmgVHPF eZvw== X-Gm-Message-State: ABuFfogrRr4M2kTGDXy1XKbvAJS0O7RSShZx8twqnZ+ADbPAJbAQfSP9 mj66tN8P7umQFVZTR1alTNI3 X-Received: by 2002:a17:902:509:: with SMTP id 9-v6mr25516482plf.155.1539026094911; Mon, 08 Oct 2018 12:14:54 -0700 (PDT) Received: from localhost.localdomain ([2405:204:73c6:20ea:9fd:1785:d893:1e98]) by smtp.gmail.com with ESMTPSA id a15-v6sm15648035pff.8.2018.10.08.12.14.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 08 Oct 2018 12:14:54 -0700 (PDT) From: Manivannan Sadhasivam To: sean.wang@mediatek.com, linus.walleij@linaro.org, matthias.bgg@gmail.com, robh+dt@kernel.org Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, amit.kucheria@linaro.org, Manivannan Sadhasivam Subject: [PATCH 4/5] pinctrl: mediatek: pinctrl-mtk-common-v2: Make eint_m u16 Date: Tue, 9 Oct 2018 00:44:10 +0530 Message-Id: <20181008191411.32555-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181008191411.32555-1-manivannan.sadhasivam@linaro.org> References: <20181008191411.32555-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For SoC's which lacks EINT support, U16_MAX is assigned to both eint_m and eint_n through macro NO_EINT_SUPPORT. This will generate integer overflow warning because eint_m is declared as u8 type. Hence modify the eint_m type to u16. Signed-off-by: Manivannan Sadhasivam --- drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 Reviewed-by: Matthias Brugger diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h index 991c1c56670c..6d24522739d9 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h @@ -154,7 +154,7 @@ struct mtk_func_desc { * @eitn_n: the eint number for this pin */ struct mtk_eint_desc { - u8 eint_m; + u16 eint_m; u16 eint_n; }; From patchwork Mon Oct 8 19:14:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 148443 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp4021379lji; Mon, 8 Oct 2018 12:15:11 -0700 (PDT) X-Google-Smtp-Source: ACcGV62on1sgo4Z9h0wiapaqeAY+JBe5T9yYCuJ9vL6EC14gLtnT7qB1cAY3VJIBJMfEu6ysB6tK X-Received: by 2002:a63:2483:: with SMTP id k125-v6mr22380370pgk.287.1539026111616; Mon, 08 Oct 2018 12:15:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539026111; cv=none; d=google.com; s=arc-20160816; b=wc7iKp6Yv7FR8/NbuGpx0aUU28rZaZgq9OYxZisPOlcwKn7gKa+HdvsDE38SVRf2sF kbTG9Yapbaz08eoP76fwm9eoiJN8u4o8LbdW0c9SN9KfWPLz09y7K5U6gu8QwDQUtDE6 5JFr2cAEMB8VXDltSsNxMBejDUP8i0//IHc5/9wdRvKlBYGvluhIzt9sMOZVOqlLHX69 rHVQUxWNMxgMA7yP7XNS/UKejYsQX5hnB7oFyquiEEuze0eVpIMg2kgdvnz3jeIW38NU jrkKMcREE4mSbp4xKB4NtdQ4z5Hklreu7nv3lZLLr9UdXWSD+/YI32eZDEnKt5M47vfK up2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=nyabq7sR4xCdV9OF5dd4/+fabWzLmX3j41WteW2pLsM=; b=l26DV6y11GARTW9YLq0CtZuNK0GiQaHqxjx4xxSQ0iD8dt/rmTibmsEmzSFnagfxjG JBU856RyKb8WkSl7xiLV8aykTC/PZeZcUEiK7h0M01/MNYPO2DZ0hFJQDMu6D/HUTN6e OHEUlYD72V2sqZZTvEE1ui34I5e81X5q71sHuUIvjp7ocAgA/24YMQZ8iesAphFqnM5P JenEATpf03H0VxNkHSp9Tn6IaM+ssJ6dAiJ4A080qqi7bUYz7G+7eoo/31NO++gRS6s3 v51zwbcfqarJ8S+EO4Xpw4WCkyQjYVHFG1g/jeXX09d2XhKjferW8h8uYwZ5JsivoG53 VLjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IZ8pegkM; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p9-v6si11835921pfh.232.2018.10.08.12.15.09; Mon, 08 Oct 2018 12:15:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IZ8pegkM; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728260AbeJIC2U (ORCPT + 32 others); Mon, 8 Oct 2018 22:28:20 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:45747 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728039AbeJIC2T (ORCPT ); Mon, 8 Oct 2018 22:28:19 -0400 Received: by mail-pl1-f195.google.com with SMTP id y15-v6so10481190plr.12 for ; Mon, 08 Oct 2018 12:15:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nyabq7sR4xCdV9OF5dd4/+fabWzLmX3j41WteW2pLsM=; b=IZ8pegkMvdla5FWsfkWdOzWWDY6fAKM7OiSMGVDMAYgklN0Ae5SB/T73PCz3NdFgSu uIPLhdAQ2E6o/2lDB+lWdgkGTBGAZQzXhonry0Lhh8AeW+Fgvw16V+m5q20o3rrFSWrT G7juLYsCkkUxTS+9iapbYu19WSqyKSx1aDXVs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nyabq7sR4xCdV9OF5dd4/+fabWzLmX3j41WteW2pLsM=; b=XAMszp/Dzq/o9emjB9FPBvoZNlJN0Xf1RwJP3dkYd51ZxcIMvHYh9DGPzmL75+vIPR XaucI+G1Yt1Dt6BlSIMqSTacQa8H6TNsmKC/W8YpMf6cWeBQKXvg0t93Me6ebh/0oLsL GkFaVfS4dEkipcQNOR/yG4Y6zS56ysjemdKpLyq0ddwWxpp8nM+lrJ3lYCdScqTojos0 fzrZzth/eT3qEcL+Ata4lmVoX36yQ2AYzSIJ42zdkK6tiD7Jfbb9xk6fIFqferaxa378 vDdIEVXj/TqlXX1OGPTLxpZKBRB1MYaSdQqIeUqiA3Cm+zP75AkraY0j7XYXHhrAo6Fi dF6A== X-Gm-Message-State: ABuFfoiRO5bEljGApP8UOo9Fiyl6BGEP8R7Z74nkZ3hlKEp43vId7vC3 garrIn4yqY1DBClXQJeGB9Oa X-Received: by 2002:a17:902:50e3:: with SMTP id c32-v6mr24974492plj.194.1539026102237; Mon, 08 Oct 2018 12:15:02 -0700 (PDT) Received: from localhost.localdomain ([2405:204:73c6:20ea:9fd:1785:d893:1e98]) by smtp.gmail.com with ESMTPSA id a15-v6sm15648035pff.8.2018.10.08.12.14.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 08 Oct 2018 12:15:01 -0700 (PDT) From: Manivannan Sadhasivam To: sean.wang@mediatek.com, linus.walleij@linaro.org, matthias.bgg@gmail.com, robh+dt@kernel.org Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, amit.kucheria@linaro.org, Manivannan Sadhasivam Subject: [PATCH 5/5] pinctrl: mediatek: Add initial pinctrl driver for MT6797 SoC Date: Tue, 9 Oct 2018 00:44:11 +0530 Message-Id: <20181008191411.32555-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181008191411.32555-1-manivannan.sadhasivam@linaro.org> References: <20181008191411.32555-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add initial pinctrl driver for Mediatek MT6797 SoC supporting only GPIO and pinmux configurations. Signed-off-by: Manivannan Sadhasivam --- drivers/pinctrl/mediatek/Kconfig | 7 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt6797.c | 82 + drivers/pinctrl/mediatek/pinctrl-mtk-mt6797.h | 2430 +++++++++++++++++ 4 files changed, 2520 insertions(+) create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6797.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6797.h -- 2.17.1 diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 05be5ddafec4..ca9b55cee3f2 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -76,6 +76,13 @@ config PINCTRL_MT6765 default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS +config PINCTRL_MT6797 + bool "Mediatek MT6797 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_PARIS + config PINCTRL_MT7622 bool "MediaTek MT7622 pin control" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 70d800054f69..e50dcf83dd07 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o +obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6797.c b/drivers/pinctrl/mediatek/pinctrl-mt6797.c new file mode 100644 index 000000000000..adebe4333ed9 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt6797.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Based on pinctrl-mt6765.c + * + * Copyright (C) 2018 MediaTek Inc. + * + * Author: ZH Chen + * + * Copyright (C) Manivannan Sadhasivam + * + */ + +#include "pinctrl-mtk-mt6797.h" +#include "pinctrl-paris.h" + +/* + * MT6797 have multiple bases to program pin configuration listed as the below: + * gpio:0x10005000, iocfg[l]:0x10002000, iocfg[b]:0x10002400, + * iocfg[r]:0x10002800, iocfg[t]:0x10002C00. + * _i_base could be used to indicate what base the pin should be mapped into. + */ + +static const struct mtk_pin_field_calc mt6797_pin_mode_range[] = { + PIN_FIELD(0, 261, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt6797_pin_dir_range[] = { + PIN_FIELD(0, 261, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6797_pin_di_range[] = { + PIN_FIELD(0, 261, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt6797_pin_do_range[] = { + PIN_FIELD(0, 261, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_reg_calc mt6797_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6797_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6797_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6797_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6797_pin_do_range), +}; + +static const char * const mt6797_pinctrl_register_base_names[] = { + "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt", +}; + +static const struct mtk_pin_soc mt6797_data = { + .reg_cal = mt6797_reg_cals, + .pins = mtk_pins_mt6797, + .npins = ARRAY_SIZE(mtk_pins_mt6797), + .ngrps = ARRAY_SIZE(mtk_pins_mt6797), + .gpio_m = 0, + .base_names = mt6797_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt6797_pinctrl_register_base_names), +}; + +static const struct of_device_id mt6797_pinctrl_of_match[] = { + { .compatible = "mediatek,mt6797-pinctrl", }, + { } +}; + +static int mt6797_pinctrl_probe(struct platform_device *pdev) +{ + return mtk_paris_pinctrl_probe(pdev, &mt6797_data); +} + +static struct platform_driver mt6797_pinctrl_driver = { + .driver = { + .name = "mt6797-pinctrl", + .of_match_table = mt6797_pinctrl_of_match, + }, + .probe = mt6797_pinctrl_probe, +}; + +static int __init mt6797_pinctrl_init(void) +{ + return platform_driver_register(&mt6797_pinctrl_driver); +} +arch_initcall(mt6797_pinctrl_init); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6797.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6797.h new file mode 100644 index 000000000000..8949d2a15c39 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6797.h @@ -0,0 +1,2430 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Based on pinctrl-mtk-mt6765.h + * + * Copyright (C) 2018 MediaTek Inc. + * + * Author: ZH Chen + * + * Copyright (c) 2018 Manivannan Sadhasivam + */ + +#ifndef __PINCTRL_MTK_MT6797_H +#define __PINCTRL_MTK_MT6797_H + +#include "pinctrl-paris.h" + +static const struct mtk_pin_desc mtk_pins_mt6797[] = { + MTK_PIN( + 0, "GPIO0", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "CSI0A_L0P_T0A") + ), + MTK_PIN( + 1, "GPIO1", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "CSI0A_L0N_T0B") + ), + MTK_PIN( + 2, "GPIO2", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "CSI0A_L1P_T0C") + ), + MTK_PIN( + 3, "GPIO3", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "CSI0A_L1N_T1A") + ), + MTK_PIN( + 4, "GPIO4", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "CSI0A_L2P_T1B") + ), + MTK_PIN( + 5, "GPIO5", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "CSI0A_L2N_T1C") + ), + MTK_PIN( + 6, "GPIO6", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "CSI0B_L0P_T0A") + ), + MTK_PIN( + 7, "GPIO7", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "CSI0B_L0N_T0B") + ), + MTK_PIN( + 8, "GPIO8", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "CSI0B_L1P_T0C") + ), + MTK_PIN( + 9, "GPIO9", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "CSI0B_L1N_T1A") + ), + MTK_PIN( + 10, "GPIO10", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "CSI1A_L0P_T0A") + ), + MTK_PIN( + 11, "GPIO11", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "CSI1A_L0N_T0B") + ), + MTK_PIN( + 12, "GPIO12", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "CSI1A_L1P_T0C") + ), + MTK_PIN( + 13, "GPIO13", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "CSI1A_L1N_T1A") + ), + MTK_PIN( + 14, "GPIO14", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "CSI1A_L2P_T1B") + ), + MTK_PIN( + 15, "GPIO15", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "CSI1A_L2N_T1C") + ), + MTK_PIN( + 16, "GPIO16", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "CSI1B_L0P_T0A") + ), + MTK_PIN( + 17, "GPIO17", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "CSI1B_L0N_T0B") + ), + MTK_PIN( + 18, "GPIO18", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "CSI1B_L1P_T0C") + ), + MTK_PIN( + 19, "GPIO19", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "CSI1B_L1N_T1A") + ), + MTK_PIN( + 20, "GPIO20", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "CSI1B_L2P_T1B") + ), + MTK_PIN( + 21, "GPIO21", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "CSI1B_L2N_T1C") + ), + MTK_PIN( + 22, "GPIO22", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "CSI2_L0P_T0A") + ), + MTK_PIN( + 23, "GPIO23", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(1, "CSI2_L0N_T0B") + ), + MTK_PIN( + 24, "GPIO24", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "CSI2_L1P_T0C") + ), + MTK_PIN( + 25, "GPIO25", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "CSI2_L1N_T1A") + ), + MTK_PIN( + 26, "GPIO26", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "CSI2_L2P_T1B") + ), + MTK_PIN( + 27, "GPIO27", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "CSI2_L2N_T1C") + ), + MTK_PIN( + 28, "GPIO28", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "SPI5_CLK_A"), + MTK_FUNCTION(2, "IRTX_OUT"), + MTK_FUNCTION(3, "UDI_TDO"), + MTK_FUNCTION(4, "SCP_JTAG_TDO"), + MTK_FUNCTION(5, "CONN_MCU_TDO"), + MTK_FUNCTION(6, "PWM_A"), + MTK_FUNCTION(7, "C2K_DM_OTDO") + ), + MTK_PIN( + 29, "GPIO29", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "SPI5_MI_A"), + MTK_FUNCTION(2, "DAP_SIB1_SWD"), + MTK_FUNCTION(3, "UDI_TMS"), + MTK_FUNCTION(4, "SCP_JTAG_TMS"), + MTK_FUNCTION(5, "CONN_MCU_TMS"), + MTK_FUNCTION(6, "CONN_MCU_AICE_TMSC"), + MTK_FUNCTION(7, "C2K_DM_OTMS") + ), + MTK_PIN( + 30, "GPIO30", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "CMMCLK0"), + MTK_FUNCTION(7, "MD_CLKM0") + ), + MTK_PIN( + 31, "GPIO31", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "CMMCLK1"), + MTK_FUNCTION(7, "MD_CLKM1") + ), + MTK_PIN( + 32, "GPIO32", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "SPI5_CS_A"), + MTK_FUNCTION(2, "DAP_SIB1_SWCK"), + MTK_FUNCTION(3, "UDI_TCK_XI"), + MTK_FUNCTION(4, "SCP_JTAG_TCK"), + MTK_FUNCTION(5, "CONN_MCU_TCK"), + MTK_FUNCTION(6, "CONN_MCU_AICE_TCKC"), + MTK_FUNCTION(7, "C2K_DM_OTCK") + ), + MTK_PIN( + 33, "GPIO33", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "SPI5_MO_A"), + MTK_FUNCTION(2, "CMFLASH"), + MTK_FUNCTION(3, "UDI_TDI"), + MTK_FUNCTION(4, "SCP_JTAG_TDI"), + MTK_FUNCTION(5, "CONN_MCU_TDI"), + MTK_FUNCTION(6, "MD_URXD0"), + MTK_FUNCTION(7, "C2K_DM_OTDI") + ), + MTK_PIN( + 34, "GPIO34", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "CMFLASH"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "UDI_NTRST"), + MTK_FUNCTION(4, "SCP_JTAG_TRSTN"), + MTK_FUNCTION(5, "CONN_MCU_TRST_B"), + MTK_FUNCTION(6, "MD_UTXD0"), + MTK_FUNCTION(7, "C2K_DM_JTINTP") + ), + MTK_PIN( + 35, "GPIO35", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "CMMCLK3"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "MD_URXD1"), + MTK_FUNCTION(4, "PTA_RXD"), + MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"), + MTK_FUNCTION(6, "PWM_B"), + MTK_FUNCTION(7, "PCC_PPC_IO") + ), + MTK_PIN( + 36, "GPIO36", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "CMMCLK2"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(3, "MD_UTXD1"), + MTK_FUNCTION(4, "PTA_TXD"), + MTK_FUNCTION(5, "CONN_MCU_DBGI_N"), + MTK_FUNCTION(6, "PWM_C"), + MTK_FUNCTION(7, "EXT_FRAME_SYNC") + ), + MTK_PIN( + 37, "GPIO37", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "SCL0_0") + ), + MTK_PIN( + 38, "GPIO38", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "SDA0_0") + ), + MTK_PIN( + 39, "GPIO39", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "DPI_D0"), + MTK_FUNCTION(2, "SPI1_CLK_A"), + MTK_FUNCTION(3, "PCM0_SYNC"), + MTK_FUNCTION(4, "I2S0_LRCK"), + MTK_FUNCTION(5, "CONN_MCU_TRST_B"), + MTK_FUNCTION(6, "URXD3"), + MTK_FUNCTION(7, "C2K_NTRST") + ), + MTK_PIN( + 40, "GPIO40", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "DPI_D1"), + MTK_FUNCTION(2, "SPI1_MI_A"), + MTK_FUNCTION(3, "PCM0_CLK"), + MTK_FUNCTION(4, "I2S0_BCK"), + MTK_FUNCTION(5, "CONN_MCU_TDO"), + MTK_FUNCTION(6, "UTXD3"), + MTK_FUNCTION(7, "C2K_TCK") + ), + MTK_PIN( + 41, "GPIO41", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "DPI_D2"), + MTK_FUNCTION(2, "SPI1_CS_A"), + MTK_FUNCTION(3, "PCM0_DO"), + MTK_FUNCTION(4, "I2S3_DO"), + MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"), + MTK_FUNCTION(6, "URTS3"), + MTK_FUNCTION(7, "C2K_TDI") + ), + MTK_PIN( + 42, "GPIO42", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "DPI_D3"), + MTK_FUNCTION(2, "SPI1_MO_A"), + MTK_FUNCTION(3, "PCM0_DI"), + MTK_FUNCTION(4, "I2S0_DI"), + MTK_FUNCTION(5, "CONN_MCU_TDI"), + MTK_FUNCTION(6, "UCTS3"), + MTK_FUNCTION(7, "C2K_TMS") + ), + MTK_PIN( + 43, "GPIO43", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "DPI_D4"), + MTK_FUNCTION(2, "SPI2_CLK_A"), + MTK_FUNCTION(3, "PCM1_SYNC"), + MTK_FUNCTION(4, "I2S2_LRCK"), + MTK_FUNCTION(5, "CONN_MCU_TMS"), + MTK_FUNCTION(6, "CONN_MCU_AICE_TMSC"), + MTK_FUNCTION(7, "C2K_TDO") + ), + MTK_PIN( + 44, "GPIO44", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "DPI_D5"), + MTK_FUNCTION(2, "SPI2_MI_A"), + MTK_FUNCTION(3, "PCM1_CLK"), + MTK_FUNCTION(4, "I2S2_BCK"), + MTK_FUNCTION(5, "CONN_MCU_TCK"), + MTK_FUNCTION(6, "CONN_MCU_AICE_TCKC"), + MTK_FUNCTION(7, "C2K_RTCK") + ), + MTK_PIN( + 45, "GPIO45", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "DPI_D6"), + MTK_FUNCTION(2, "SPI2_CS_A"), + MTK_FUNCTION(3, "PCM1_DI"), + MTK_FUNCTION(4, "I2S2_DI"), + MTK_FUNCTION(5, "CONN_MCU_DBGI_N"), + MTK_FUNCTION(6, "MD_URXD0") + ), + MTK_PIN( + 46, "GPIO46", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "DPI_D7"), + MTK_FUNCTION(2, "SPI2_MO_A"), + MTK_FUNCTION(3, "PCM1_DO0"), + MTK_FUNCTION(4, "I2S1_DO"), + MTK_FUNCTION(5, "ANT_SEL0"), + MTK_FUNCTION(6, "MD_UTXD0") + ), + MTK_PIN( + 47, "GPIO47", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "DPI_D8"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "PCM1_DO1"), + MTK_FUNCTION(4, "I2S0_MCK"), + MTK_FUNCTION(5, "ANT_SEL1"), + MTK_FUNCTION(6, "PTA_RXD"), + MTK_FUNCTION(7, "C2K_URXD0") + ), + MTK_PIN( + 48, "GPIO48", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "DPI_D9"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "CMFLASH"), + MTK_FUNCTION(4, "I2S2_MCK"), + MTK_FUNCTION(5, "ANT_SEL2"), + MTK_FUNCTION(6, "PTA_TXD"), + MTK_FUNCTION(7, "C2K_UTXD0") + ), + MTK_PIN( + 49, "GPIO49", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "DPI_D10"), + MTK_FUNCTION(2, "MD_INT1_C2K_UIM1_HOT_PLUG_IN"), + MTK_FUNCTION(3, "PWM_C"), + MTK_FUNCTION(4, "IRTX_OUT"), + MTK_FUNCTION(5, "ANT_SEL3"), + MTK_FUNCTION(6, "MD_URXD1") + ), + MTK_PIN( + 50, "GPIO50", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "DPI_D11"), + MTK_FUNCTION(2, "MD_INT2"), + MTK_FUNCTION(3, "PWM_D"), + MTK_FUNCTION(4, "CLKM2"), + MTK_FUNCTION(5, "ANT_SEL4"), + MTK_FUNCTION(6, "MD_UTXD1") + ), + MTK_PIN( + 51, "GPIO51", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "DPI_DE"), + MTK_FUNCTION(2, "SPI4_CLK_A"), + MTK_FUNCTION(3, "IRTX_OUT"), + MTK_FUNCTION(4, "SCL0_1"), + MTK_FUNCTION(5, "ANT_SEL5"), + MTK_FUNCTION(7, "C2K_UTXD1") + ), + MTK_PIN( + 52, "GPIO52", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "DPI_CK"), + MTK_FUNCTION(2, "SPI4_MI_A"), + MTK_FUNCTION(3, "SPI4_MO_A"), + MTK_FUNCTION(4, "SDA0_1"), + MTK_FUNCTION(5, "ANT_SEL6"), + MTK_FUNCTION(7, "C2K_URXD1") + ), + MTK_PIN( + 53, "GPIO53", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "DPI_HSYNC"), + MTK_FUNCTION(2, "SPI4_CS_A"), + MTK_FUNCTION(3, "CMFLASH"), + MTK_FUNCTION(4, "SCL1_1"), + MTK_FUNCTION(5, "ANT_SEL7"), + MTK_FUNCTION(6, "MD_URXD2"), + MTK_FUNCTION(7, "PCC_PPC_IO") + ), + MTK_PIN( + 54, "GPIO54", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "DPI_VSYNC"), + MTK_FUNCTION(2, "SPI4_MO_A"), + MTK_FUNCTION(3, "SPI4_MI_A"), + MTK_FUNCTION(4, "SDA1_1"), + MTK_FUNCTION(5, "PWM_A"), + MTK_FUNCTION(6, "MD_UTXD2"), + MTK_FUNCTION(7, "EXT_FRAME_SYNC") + ), + MTK_PIN( + 55, "GPIO55", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "SCL1_0") + ), + MTK_PIN( + 56, "GPIO56", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "SDA1_0") + ), + MTK_PIN( + 57, "GPIO57", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "SPI0_CLK"), + MTK_FUNCTION(2, "SCL0_2"), + MTK_FUNCTION(3, "PWM_B"), + MTK_FUNCTION(4, "UTXD3"), + MTK_FUNCTION(5, "PCM0_SYNC") + ), + MTK_PIN( + 58, "GPIO58", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "SPI0_MI"), + MTK_FUNCTION(2, "SPI0_MO"), + MTK_FUNCTION(3, "SDA1_2"), + MTK_FUNCTION(4, "URXD3"), + MTK_FUNCTION(5, "PCM0_CLK") + ), + MTK_PIN( + 59, "GPIO59", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "SPI0_MO"), + MTK_FUNCTION(2, "SPI0_MI"), + MTK_FUNCTION(3, "PWM_C"), + MTK_FUNCTION(4, "URTS3"), + MTK_FUNCTION(5, "PCM0_DO") + ), + MTK_PIN( + 60, "GPIO60", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "SPI0_CS"), + MTK_FUNCTION(2, "SDA0_2"), + MTK_FUNCTION(3, "SCL1_2"), + MTK_FUNCTION(4, "UCTS3"), + MTK_FUNCTION(5, "PCM0_DI") + ), + MTK_PIN( + 61, "GPIO61", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "EINT0"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "SPI4_CLK_B"), + MTK_FUNCTION(4, "I2S0_LRCK"), + MTK_FUNCTION(5, "PCM0_SYNC"), + MTK_FUNCTION(7, "C2K_EINT0") + ), + MTK_PIN( + 62, "GPIO62", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "EINT1"), + MTK_FUNCTION(2, "USB_DRVVBUS"), + MTK_FUNCTION(3, "SPI4_MI_B"), + MTK_FUNCTION(4, "I2S0_BCK"), + MTK_FUNCTION(5, "PCM0_CLK"), + MTK_FUNCTION(7, "C2K_EINT1") + ), + MTK_PIN( + 63, "GPIO63", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "EINT2"), + MTK_FUNCTION(2, "IRTX_OUT"), + MTK_FUNCTION(3, "SPI4_MO_B"), + MTK_FUNCTION(4, "I2S0_MCK"), + MTK_FUNCTION(5, "PCM0_DI"), + MTK_FUNCTION(7, "C2K_DM_EINT0") + ), + MTK_PIN( + 64, "GPIO64", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "EINT3"), + MTK_FUNCTION(2, "CMFLASH"), + MTK_FUNCTION(3, "SPI4_CS_B"), + MTK_FUNCTION(4, "I2S0_DI"), + MTK_FUNCTION(5, "PCM0_DO"), + MTK_FUNCTION(7, "C2K_DM_EINT1") + ), + MTK_PIN( + 65, "GPIO65", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "EINT4"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "SPI5_CLK_B"), + MTK_FUNCTION(4, "I2S1_LRCK"), + MTK_FUNCTION(5, "PWM_A"), + MTK_FUNCTION(7, "C2K_DM_EINT2") + ), + MTK_PIN( + 66, "GPIO66", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "EINT5"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "SPI5_MI_B"), + MTK_FUNCTION(4, "I2S1_BCK"), + MTK_FUNCTION(5, "PWM_B"), + MTK_FUNCTION(7, "C2K_DM_EINT3") + ), + MTK_PIN( + 67, "GPIO67", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "EINT6"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(3, "SPI5_MO_B"), + MTK_FUNCTION(4, "I2S1_MCK"), + MTK_FUNCTION(5, "PWM_C"), + MTK_FUNCTION(7, "DBG_MON_A0") + ), + MTK_PIN( + 68, "GPIO68", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "EINT7"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(3, "SPI5_CS_B"), + MTK_FUNCTION(4, "I2S1_DO"), + MTK_FUNCTION(5, "PWM_D"), + MTK_FUNCTION(7, "DBG_MON_A1") + ), + MTK_PIN( + 69, "GPIO69", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "I2S0_LRCK"), + MTK_FUNCTION(2, "I2S3_LRCK"), + MTK_FUNCTION(3, "I2S1_LRCK"), + MTK_FUNCTION(4, "I2S2_LRCK"), + MTK_FUNCTION(7, "DBG_MON_A2") + ), + MTK_PIN( + 70, "GPIO70", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "I2S0_BCK"), + MTK_FUNCTION(2, "I2S3_BCK"), + MTK_FUNCTION(3, "I2S1_BCK"), + MTK_FUNCTION(4, "I2S2_BCK"), + MTK_FUNCTION(7, "DBG_MON_A3") + ), + MTK_PIN( + 71, "GPIO71", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO71"), + MTK_FUNCTION(1, "I2S0_MCK"), + MTK_FUNCTION(2, "I2S3_MCK"), + MTK_FUNCTION(3, "I2S1_MCK"), + MTK_FUNCTION(4, "I2S2_MCK"), + MTK_FUNCTION(7, "DBG_MON_A4") + ), + MTK_PIN( + 72, "GPIO72", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO72"), + MTK_FUNCTION(1, "I2S0_DI"), + MTK_FUNCTION(2, "I2S0_DI"), + MTK_FUNCTION(3, "I2S2_DI"), + MTK_FUNCTION(4, "I2S2_DI"), + MTK_FUNCTION(7, "DBG_MON_A5") + ), + MTK_PIN( + 73, "GPIO73", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO73"), + MTK_FUNCTION(1, "I2S3_DO"), + MTK_FUNCTION(2, "I2S3_DO"), + MTK_FUNCTION(3, "I2S1_DO"), + MTK_FUNCTION(4, "I2S1_DO"), + MTK_FUNCTION(7, "DBG_MON_A6") + ), + MTK_PIN( + 74, "GPIO74", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "SCL3_0"), + MTK_FUNCTION(7, "AUXIF_CLK1") + ), + MTK_PIN( + 75, "GPIO75", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "SDA3_0"), + MTK_FUNCTION(7, "AUXIF_ST1") + ), + MTK_PIN( + 76, "GPIO76", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "CONN_HRST_B"), + MTK_FUNCTION(7, "C2K_DM_EINT0") + ), + MTK_PIN( + 77, "GPIO77", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "CONN_TOP_CLK"), + MTK_FUNCTION(7, "C2K_DM_EINT1") + ), + MTK_PIN( + 78, "GPIO78", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "CONN_TOP_DATA"), + MTK_FUNCTION(7, "C2K_DM_EINT2") + ), + MTK_PIN( + 79, "GPIO79", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "CONN_WB_PTA"), + MTK_FUNCTION(7, "C2K_DM_EINT3") + ), + MTK_PIN( + 80, "GPIO80", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "CONN_WF_HB0"), + MTK_FUNCTION(7, "C2K_EINT0") + ), + MTK_PIN( + 81, "GPIO81", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "CONN_WF_HB1"), + MTK_FUNCTION(7, "C2K_EINT1") + ), + MTK_PIN( + 82, "GPIO82", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "CONN_WF_HB2"), + MTK_FUNCTION(7, "MD_CLKM0") + ), + MTK_PIN( + 83, "GPIO83", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "CONN_BT_CLK"), + MTK_FUNCTION(7, "MD_CLKM1") + ), + MTK_PIN( + 84, "GPIO84", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "CONN_BT_DATA") + ), + MTK_PIN( + 85, "GPIO85", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "EINT8"), + MTK_FUNCTION(2, "I2S1_LRCK"), + MTK_FUNCTION(3, "I2S2_LRCK"), + MTK_FUNCTION(4, "URXD1"), + MTK_FUNCTION(5, "MD_URXD0"), + MTK_FUNCTION(7, "DBG_MON_A7") + ), + MTK_PIN( + 86, "GPIO86", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "EINT9"), + MTK_FUNCTION(2, "I2S1_BCK"), + MTK_FUNCTION(3, "I2S2_BCK"), + MTK_FUNCTION(4, "UTXD1"), + MTK_FUNCTION(5, "MD_UTXD0"), + MTK_FUNCTION(7, "DBG_MON_A8") + ), + MTK_PIN( + 87, "GPIO87", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(1, "EINT10"), + MTK_FUNCTION(2, "I2S1_MCK"), + MTK_FUNCTION(3, "I2S2_MCK"), + MTK_FUNCTION(4, "URTS1"), + MTK_FUNCTION(5, "MD_URXD1"), + MTK_FUNCTION(7, "DBG_MON_A9") + ), + MTK_PIN( + 88, "GPIO88", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "EINT11"), + MTK_FUNCTION(2, "I2S1_DO"), + MTK_FUNCTION(3, "I2S2_DI"), + MTK_FUNCTION(4, "UCTS1"), + MTK_FUNCTION(5, "MD_UTXD1"), + MTK_FUNCTION(7, "DBG_MON_A10") + ), + MTK_PIN( + 89, "GPIO89", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "EINT12"), + MTK_FUNCTION(2, "IRTX_OUT"), + MTK_FUNCTION(3, "CLKM0"), + MTK_FUNCTION(4, "PCM1_SYNC"), + MTK_FUNCTION(5, "URTS0"), + MTK_FUNCTION(7, "DBG_MON_A11") + ), + MTK_PIN( + 90, "GPIO90", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "EINT13"), + MTK_FUNCTION(2, "CMFLASH"), + MTK_FUNCTION(3, "CLKM1"), + MTK_FUNCTION(4, "PCM1_CLK"), + MTK_FUNCTION(5, "UCTS0"), + MTK_FUNCTION(7, "C2K_DM_EINT0") + ), + MTK_PIN( + 91, "GPIO91", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO91"), + MTK_FUNCTION(1, "EINT14"), + MTK_FUNCTION(2, "PWM_A"), + MTK_FUNCTION(3, "CLKM2"), + MTK_FUNCTION(4, "PCM1_DI"), + MTK_FUNCTION(5, "SDA0_3"), + MTK_FUNCTION(7, "C2K_DM_EINT1") + ), + MTK_PIN( + 92, "GPIO92", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO92"), + MTK_FUNCTION(1, "EINT15"), + MTK_FUNCTION(2, "PWM_B"), + MTK_FUNCTION(3, "CLKM3"), + MTK_FUNCTION(4, "PCM1_DO0"), + MTK_FUNCTION(5, "SCL0_3") + ), + MTK_PIN( + 93, "GPIO93", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO93"), + MTK_FUNCTION(1, "EINT16"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "CLKM4"), + MTK_FUNCTION(4, "PCM1_DO1"), + MTK_FUNCTION(5, "MD_INT2"), + MTK_FUNCTION(7, "DROP_ZONE") + ), + MTK_PIN( + 94, "GPIO94", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO94"), + MTK_FUNCTION(1, "USB_DRVVBUS"), + MTK_FUNCTION(2, "PWM_C"), + MTK_FUNCTION(3, "CLKM5") + ), + MTK_PIN( + 95, "GPIO95", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO95"), + MTK_FUNCTION(1, "SDA2_0"), + MTK_FUNCTION(7, "AUXIF_ST0") + ), + MTK_PIN( + 96, "GPIO96", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO96"), + MTK_FUNCTION(1, "SCL2_0"), + MTK_FUNCTION(7, "AUXIF_CLK0") + ), + MTK_PIN( + 97, "GPIO97", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO97"), + MTK_FUNCTION(1, "URXD0"), + MTK_FUNCTION(2, "UTXD0"), + MTK_FUNCTION(3, "MD_URXD0"), + MTK_FUNCTION(4, "MD_URXD1"), + MTK_FUNCTION(5, "MD_URXD2"), + MTK_FUNCTION(6, "C2K_URXD0"), + MTK_FUNCTION(7, "C2K_URXD1") + ), + MTK_PIN( + 98, "GPIO98", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO98"), + MTK_FUNCTION(1, "UTXD0"), + MTK_FUNCTION(2, "URXD0"), + MTK_FUNCTION(3, "MD_UTXD0"), + MTK_FUNCTION(4, "MD_UTXD1"), + MTK_FUNCTION(5, "MD_UTXD2"), + MTK_FUNCTION(6, "C2K_UTXD0"), + MTK_FUNCTION(7, "C2K_UTXD1") + ), + MTK_PIN( + 99, "GPIO99", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO99"), + MTK_FUNCTION(1, "RTC32K_CK") + ), + MTK_PIN( + 100, "GPIO100", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO100"), + MTK_FUNCTION(1, "SRCLKENAI0") + ), + MTK_PIN( + 101, "GPIO101", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO101"), + MTK_FUNCTION(1, "SRCLKENAI1") + ), + MTK_PIN( + 102, "GPIO102", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO102"), + MTK_FUNCTION(1, "SRCLKENA0") + ), + MTK_PIN( + 103, "GPIO103", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO103"), + MTK_FUNCTION(1, "SRCLKENA1") + ), + MTK_PIN( + 104, "GPIO104", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO104"), + MTK_FUNCTION(1, "SYSRSTB") + ), + MTK_PIN( + 105, "GPIO105", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO105"), + MTK_FUNCTION(1, "WATCHDOG") + ), + MTK_PIN( + 106, "GPIO106", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO106"), + MTK_FUNCTION(1, "KPROW0"), + MTK_FUNCTION(2, "CMFLASH"), + MTK_FUNCTION(3, "CLKM4"), + MTK_FUNCTION(4, "TP_GPIO0_AO"), + MTK_FUNCTION(5, "IRTX_OUT") + ), + MTK_PIN( + 107, "GPIO107", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO107"), + MTK_FUNCTION(1, "KPROW1"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "CLKM5"), + MTK_FUNCTION(4, "TP_GPIO1_AO"), + MTK_FUNCTION(5, "I2S1_BCK"), + MTK_FUNCTION(7, "DAP_SIB1_SWD") + ), + MTK_PIN( + 108, "GPIO108", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO108"), + MTK_FUNCTION(1, "KPROW2"), + MTK_FUNCTION(2, "USB_DRVVBUS"), + MTK_FUNCTION(3, "PWM_A"), + MTK_FUNCTION(4, "CMFLASH"), + MTK_FUNCTION(5, "I2S1_LRCK"), + MTK_FUNCTION(7, "DAP_SIB1_SWCK") + ), + MTK_PIN( + 109, "GPIO109", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO109"), + MTK_FUNCTION(1, "KPCOL0") + ), + MTK_PIN( + 110, "GPIO110", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO110"), + MTK_FUNCTION(1, "KPCOL1"), + MTK_FUNCTION(2, "SDA1_3"), + MTK_FUNCTION(3, "PWM_B"), + MTK_FUNCTION(4, "CLKM0"), + MTK_FUNCTION(5, "I2S1_DO"), + MTK_FUNCTION(7, "C2K_DM_EINT3") + ), + MTK_PIN( + 111, "GPIO111", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO111"), + MTK_FUNCTION(1, "KPCOL2"), + MTK_FUNCTION(2, "SCL1_3"), + MTK_FUNCTION(3, "PWM_C"), + MTK_FUNCTION(4, "DISP_PWM"), + MTK_FUNCTION(5, "I2S1_MCK"), + MTK_FUNCTION(7, "C2K_DM_EINT2") + ), + MTK_PIN( + 112, "GPIO112", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO112"), + MTK_FUNCTION(1, "MD_INT1_C2K_UIM1_HOT_PLUG_IN"), + MTK_FUNCTION(7, "C2K_DM_EINT1") + ), + MTK_PIN( + 113, "GPIO113", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO113"), + MTK_FUNCTION(1, "MD_INT0_C2K_UIM0_HOT_PLUG_IN"), + MTK_FUNCTION(7, "C2K_DM_EINT0") + ), + MTK_PIN( + 114, "GPIO114", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO114"), + MTK_FUNCTION(1, "MSDC0_DAT0") + ), + MTK_PIN( + 115, "GPIO115", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO115"), + MTK_FUNCTION(1, "MSDC0_DAT1") + ), + MTK_PIN( + 116, "GPIO116", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO116"), + MTK_FUNCTION(1, "MSDC0_DAT2") + ), + MTK_PIN( + 117, "GPIO117", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "MSDC0_DAT3") + ), + MTK_PIN( + 118, "GPIO118", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(1, "MSDC0_DAT4") + ), + MTK_PIN( + 119, "GPIO119", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "MSDC0_DAT5") + ), + MTK_PIN( + 120, "GPIO120", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "MSDC0_DAT6") + ), + MTK_PIN( + 121, "GPIO121", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "MSDC0_DAT7") + ), + MTK_PIN( + 122, "GPIO122", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "MSDC0_CMD") + ), + MTK_PIN( + 123, "GPIO123", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(1, "MSDC0_CLK") + ), + MTK_PIN( + 124, "GPIO124", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "MSDC0_DSL") + ), + MTK_PIN( + 125, "GPIO125", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO125"), + MTK_FUNCTION(1, "MSDC0_RSTB") + ), + MTK_PIN( + 126, "GPIO126", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "MD1_SIM1_SCLK"), + MTK_FUNCTION(2, "MD1_SIM2_SCLK"), + MTK_FUNCTION(3, "C2K_UIM0_CLK"), + MTK_FUNCTION(4, "C2K_UIM1_CLK") + ), + MTK_PIN( + 127, "GPIO127", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "MD1_SIM1_SRST"), + MTK_FUNCTION(2, "MD1_SIM2_SRST"), + MTK_FUNCTION(3, "C2K_UIM0_RST"), + MTK_FUNCTION(4, "C2K_UIM1_RST") + ), + MTK_PIN( + 128, "GPIO128", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "MD1_SIM1_SIO"), + MTK_FUNCTION(2, "MD1_SIM2_SIO"), + MTK_FUNCTION(3, "C2K_UIM0_IO"), + MTK_FUNCTION(4, "C2K_UIM1_IO") + ), + MTK_PIN( + 129, "GPIO129", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "MSDC1_CMD"), + MTK_FUNCTION(2, "CONN_DSP_JMS"), + MTK_FUNCTION(3, "LTE_JTAG_TMS"), + MTK_FUNCTION(4, "UDI_TMS"), + MTK_FUNCTION(5, "C2K_TMS") + ), + MTK_PIN( + 130, "GPIO130", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(1, "MSDC1_DAT0"), + MTK_FUNCTION(2, "CONN_DSP_JDI"), + MTK_FUNCTION(3, "LTE_JTAG_TDI"), + MTK_FUNCTION(4, "UDI_TDI"), + MTK_FUNCTION(5, "C2K_TDI") + ), + MTK_PIN( + 131, "GPIO131", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "MSDC1_DAT1"), + MTK_FUNCTION(2, "CONN_DSP_JDO"), + MTK_FUNCTION(3, "LTE_JTAG_TDO"), + MTK_FUNCTION(4, "UDI_TDO"), + MTK_FUNCTION(5, "C2K_TDO") + ), + MTK_PIN( + 132, "GPIO132", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "MSDC1_DAT2"), + MTK_FUNCTION(5, "C2K_RTCK") + ), + MTK_PIN( + 133, "GPIO133", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "MSDC1_DAT3"), + MTK_FUNCTION(2, "CONN_DSP_JINTP"), + MTK_FUNCTION(3, "LTE_JTAG_TRSTN"), + MTK_FUNCTION(4, "UDI_NTRST"), + MTK_FUNCTION(5, "C2K_NTRST") + ), + MTK_PIN( + 134, "GPIO134", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "MSDC1_CLK"), + MTK_FUNCTION(2, "CONN_DSP_JCK"), + MTK_FUNCTION(3, "LTE_JTAG_TCK"), + MTK_FUNCTION(4, "UDI_TCK_XI"), + MTK_FUNCTION(5, "C2K_TCK") + ), + MTK_PIN( + 135, "GPIO135", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO135"), + MTK_FUNCTION(1, "TDM_LRCK"), + MTK_FUNCTION(2, "I2S0_LRCK"), + MTK_FUNCTION(3, "CLKM0"), + MTK_FUNCTION(4, "PCM1_SYNC"), + MTK_FUNCTION(5, "PWM_A"), + MTK_FUNCTION(7, "DBG_MON_A12") + ), + MTK_PIN( + 136, "GPIO136", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO136"), + MTK_FUNCTION(1, "TDM_BCK"), + MTK_FUNCTION(2, "I2S0_BCK"), + MTK_FUNCTION(3, "CLKM1"), + MTK_FUNCTION(4, "PCM1_CLK"), + MTK_FUNCTION(5, "PWM_B"), + MTK_FUNCTION(7, "DBG_MON_A13") + ), + MTK_PIN( + 137, "GPIO137", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO137"), + MTK_FUNCTION(1, "TDM_MCK"), + MTK_FUNCTION(2, "I2S0_MCK"), + MTK_FUNCTION(3, "CLKM2"), + MTK_FUNCTION(4, "PCM1_DI"), + MTK_FUNCTION(5, "IRTX_OUT"), + MTK_FUNCTION(7, "DBG_MON_A14") + ), + MTK_PIN( + 138, "GPIO138", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO138"), + MTK_FUNCTION(1, "TDM_DATA0"), + MTK_FUNCTION(2, "I2S0_DI"), + MTK_FUNCTION(3, "CLKM3"), + MTK_FUNCTION(4, "PCM1_DO0"), + MTK_FUNCTION(5, "PWM_C"), + MTK_FUNCTION(6, "SDA3_1"), + MTK_FUNCTION(7, "DBG_MON_A15") + ), + MTK_PIN( + 139, "GPIO139", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO139"), + MTK_FUNCTION(1, "TDM_DATA1"), + MTK_FUNCTION(2, "I2S3_DO"), + MTK_FUNCTION(3, "CLKM4"), + MTK_FUNCTION(4, "PCM1_DO1"), + MTK_FUNCTION(5, "ANT_SEL2"), + MTK_FUNCTION(6, "SCL3_1"), + MTK_FUNCTION(7, "DBG_MON_A16") + ), + MTK_PIN( + 140, "GPIO140", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO140"), + MTK_FUNCTION(1, "TDM_DATA2"), + MTK_FUNCTION(2, "DISP_PWM"), + MTK_FUNCTION(3, "CLKM5"), + MTK_FUNCTION(4, "SDA1_4"), + MTK_FUNCTION(5, "ANT_SEL1"), + MTK_FUNCTION(6, "URXD3"), + MTK_FUNCTION(7, "DBG_MON_A17") + ), + MTK_PIN( + 141, "GPIO141", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO141"), + MTK_FUNCTION(1, "TDM_DATA3"), + MTK_FUNCTION(2, "CMFLASH"), + MTK_FUNCTION(3, "IRTX_OUT"), + MTK_FUNCTION(4, "SCL1_4"), + MTK_FUNCTION(5, "ANT_SEL0"), + MTK_FUNCTION(6, "UTXD3"), + MTK_FUNCTION(7, "DBG_MON_A18") + ), + MTK_PIN( + 142, "GPIO142", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO142"), + MTK_FUNCTION(1, "PWRAP_SPI0_MI"), + MTK_FUNCTION(2, "PWRAP_SPI0_MO") + ), + MTK_PIN( + 143, "GPIO143", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO143"), + MTK_FUNCTION(1, "PWRAP_SPI0_MO"), + MTK_FUNCTION(2, "PWRAP_SPI0_MI") + ), + MTK_PIN( + 144, "GPIO144", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO144"), + MTK_FUNCTION(1, "PWRAP_SPI0_CK") + ), + MTK_PIN( + 145, "GPIO145", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO145"), + MTK_FUNCTION(1, "PWRAP_SPI0_CSN") + ), + MTK_PIN( + 146, "GPIO146", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO146"), + MTK_FUNCTION(1, "AUD_CLK_MOSI") + ), + MTK_PIN( + 147, "GPIO147", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO147"), + MTK_FUNCTION(1, "AUD_DAT_MISO"), + MTK_FUNCTION(2, "AUD_DAT_MOSI"), + MTK_FUNCTION(3, "VOW_DAT_MISO") + ), + MTK_PIN( + 148, "GPIO148", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO148"), + MTK_FUNCTION(1, "AUD_DAT_MOSI"), + MTK_FUNCTION(2, "AUD_DAT_MISO") + ), + MTK_PIN( + 149, "GPIO149", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO149"), + MTK_FUNCTION(1, "VOW_CLK_MISO") + ), + MTK_PIN( + 150, "GPIO150", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO150"), + MTK_FUNCTION(1, "ANC_DAT_MOSI") + ), + MTK_PIN( + 151, "GPIO151", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO151"), + MTK_FUNCTION(1, "SCL6_0") + ), + MTK_PIN( + 152, "GPIO152", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO152"), + MTK_FUNCTION(1, "SDA6_0") + ), + MTK_PIN( + 153, "GPIO153", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO153"), + MTK_FUNCTION(1, "SCL7_0") + ), + MTK_PIN( + 154, "GPIO154", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO154"), + MTK_FUNCTION(1, "SDA7_0") + ), + MTK_PIN( + 155, "GPIO155", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO155"), + MTK_FUNCTION(1, "MD1_SIM2_SCLK"), + MTK_FUNCTION(2, "MD1_SIM1_SCLK"), + MTK_FUNCTION(3, "C2K_UIM0_CLK"), + MTK_FUNCTION(4, "C2K_UIM1_CLK") + ), + MTK_PIN( + 156, "GPIO156", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO156"), + MTK_FUNCTION(1, "MD1_SIM2_SRST"), + MTK_FUNCTION(2, "MD1_SIM1_SRST"), + MTK_FUNCTION(3, "C2K_UIM0_RST"), + MTK_FUNCTION(4, "C2K_UIM1_RST") + ), + MTK_PIN( + 157, "GPIO157", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO157"), + MTK_FUNCTION(1, "MD1_SIM2_SIO"), + MTK_FUNCTION(2, "MD1_SIM1_SIO"), + MTK_FUNCTION(3, "C2K_UIM0_IO"), + MTK_FUNCTION(4, "C2K_UIM1_IO") + ), + MTK_PIN( + 158, "GPIO158", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO158"), + MTK_FUNCTION(1, "MIPI_TDP0") + ), + MTK_PIN( + 159, "GPIO159", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO159"), + MTK_FUNCTION(1, "MIPI_TDN0") + ), + MTK_PIN( + 160, "GPIO160", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO160"), + MTK_FUNCTION(1, "MIPI_TDP1") + ), + MTK_PIN( + 161, "GPIO161", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO161"), + MTK_FUNCTION(1, "MIPI_TDN1") + ), + MTK_PIN( + 162, "GPIO162", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO162"), + MTK_FUNCTION(1, "MIPI_TCP") + ), + MTK_PIN( + 163, "GPIO163", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO163"), + MTK_FUNCTION(1, "MIPI_TCN") + ), + MTK_PIN( + 164, "GPIO164", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO164"), + MTK_FUNCTION(1, "MIPI_TDP2") + ), + MTK_PIN( + 165, "GPIO165", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO165"), + MTK_FUNCTION(1, "MIPI_TDN2") + ), + MTK_PIN( + 166, "GPIO166", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO166"), + MTK_FUNCTION(1, "MIPI_TDP3") + ), + MTK_PIN( + 167, "GPIO167", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO167"), + MTK_FUNCTION(1, "MIPI_TDN3") + ), + MTK_PIN( + 168, "GPIO168", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO168"), + MTK_FUNCTION(1, "MIPI_TDP0_A") + ), + MTK_PIN( + 169, "GPIO169", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO169"), + MTK_FUNCTION(1, "MIPI_TDN0_A") + ), + MTK_PIN( + 170, "GPIO170", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO170"), + MTK_FUNCTION(1, "MIPI_TDP1_A") + ), + MTK_PIN( + 171, "GPIO171", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO171"), + MTK_FUNCTION(1, "MIPI_TDN1_A") + ), + MTK_PIN( + 172, "GPIO172", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO172"), + MTK_FUNCTION(1, "MIPI_TCP_A") + ), + MTK_PIN( + 173, "GPIO173", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO173"), + MTK_FUNCTION(1, "MIPI_TCN_A") + ), + MTK_PIN( + 174, "GPIO174", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO174"), + MTK_FUNCTION(1, "MIPI_TDP2_A") + ), + MTK_PIN( + 175, "GPIO175", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO175"), + MTK_FUNCTION(1, "MIPI_TDN2_A") + ), + MTK_PIN( + 176, "GPIO176", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO176"), + MTK_FUNCTION(1, "MIPI_TDP3_A") + ), + MTK_PIN( + 177, "GPIO177", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO177"), + MTK_FUNCTION(1, "MIPI_TDN3_A") + ), + MTK_PIN( + 178, "GPIO178", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO178"), + MTK_FUNCTION(1, "DISP_PWM"), + MTK_FUNCTION(2, "PWM_D"), + MTK_FUNCTION(3, "CLKM5"), + MTK_FUNCTION(7, "DBG_MON_A19") + ), + MTK_PIN( + 179, "GPIO179", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO179"), + MTK_FUNCTION(1, "DSI_TE0"), + MTK_FUNCTION(7, "DBG_MON_A20") + ), + MTK_PIN( + 180, "GPIO180", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO180"), + MTK_FUNCTION(1, "LCM_RST"), + MTK_FUNCTION(2, "DSI_TE1"), + MTK_FUNCTION(7, "DBG_MON_A21") + ), + MTK_PIN( + 181, "GPIO181", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO181"), + MTK_FUNCTION(1, "IDDIG"), + MTK_FUNCTION(2, "DSI_TE1"), + MTK_FUNCTION(7, "DBG_MON_A22") + ), + MTK_PIN( + 182, "GPIO182", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO182"), + MTK_FUNCTION(1, "TESTMODE") + ), + MTK_PIN( + 183, "GPIO183", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO183"), + MTK_FUNCTION(1, "RFIC0_BSI_CK"), + MTK_FUNCTION(2, "SPM_BSI_CK"), + MTK_FUNCTION(7, "DBG_MON_B27") + ), + MTK_PIN( + 184, "GPIO184", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO184"), + MTK_FUNCTION(1, "RFIC0_BSI_EN"), + MTK_FUNCTION(2, "SPM_BSI_EN"), + MTK_FUNCTION(7, "DBG_MON_B28") + ), + MTK_PIN( + 185, "GPIO185", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO185"), + MTK_FUNCTION(1, "RFIC0_BSI_D0"), + MTK_FUNCTION(2, "SPM_BSI_D0"), + MTK_FUNCTION(7, "DBG_MON_B29") + ), + MTK_PIN( + 186, "GPIO186", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO186"), + MTK_FUNCTION(1, "RFIC0_BSI_D1"), + MTK_FUNCTION(2, "SPM_BSI_D1"), + MTK_FUNCTION(7, "DBG_MON_B30") + ), + MTK_PIN( + 187, "GPIO187", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO187"), + MTK_FUNCTION(1, "RFIC0_BSI_D2"), + MTK_FUNCTION(2, "SPM_BSI_D2"), + MTK_FUNCTION(7, "DBG_MON_B31") + ), + MTK_PIN( + 188, "GPIO188", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO188"), + MTK_FUNCTION(1, "MIPI0_SCLK"), + MTK_FUNCTION(7, "DBG_MON_B32") + ), + MTK_PIN( + 189, "GPIO189", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO189"), + MTK_FUNCTION(1, "MIPI0_SDATA") + ), + MTK_PIN( + 190, "GPIO190", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO190"), + MTK_FUNCTION(1, "MIPI1_SCLK") + ), + MTK_PIN( + 191, "GPIO191", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO191"), + MTK_FUNCTION(1, "MIPI1_SDATA") + ), + MTK_PIN( + 192, "GPIO192", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO192"), + MTK_FUNCTION(1, "BPI_BUS4") + ), + MTK_PIN( + 193, "GPIO193", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO193"), + MTK_FUNCTION(1, "BPI_BUS5"), + MTK_FUNCTION(7, "DBG_MON_B0") + ), + MTK_PIN( + 194, "GPIO194", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO194"), + MTK_FUNCTION(1, "BPI_BUS6"), + MTK_FUNCTION(7, "DBG_MON_B1") + ), + MTK_PIN( + 195, "GPIO195", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO195"), + MTK_FUNCTION(1, "BPI_BUS7"), + MTK_FUNCTION(7, "DBG_MON_B2") + ), + MTK_PIN( + 196, "GPIO196", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO196"), + MTK_FUNCTION(1, "BPI_BUS8"), + MTK_FUNCTION(7, "DBG_MON_B3") + ), + MTK_PIN( + 197, "GPIO197", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO197"), + MTK_FUNCTION(1, "BPI_BUS9"), + MTK_FUNCTION(7, "DBG_MON_B4") + ), + MTK_PIN( + 198, "GPIO198", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO198"), + MTK_FUNCTION(1, "BPI_BUS10"), + MTK_FUNCTION(7, "DBG_MON_B5") + ), + MTK_PIN( + 199, "GPIO199", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO199"), + MTK_FUNCTION(1, "BPI_BUS11"), + MTK_FUNCTION(7, "DBG_MON_B6") + ), + MTK_PIN( + 200, "GPIO200", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO200"), + MTK_FUNCTION(1, "BPI_BUS12"), + MTK_FUNCTION(7, "DBG_MON_B7") + ), + MTK_PIN( + 201, "GPIO201", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO201"), + MTK_FUNCTION(1, "BPI_BUS13"), + MTK_FUNCTION(7, "DBG_MON_B8") + ), + MTK_PIN( + 202, "GPIO202", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO202"), + MTK_FUNCTION(1, "BPI_BUS14"), + MTK_FUNCTION(7, "DBG_MON_B9") + ), + MTK_PIN( + 203, "GPIO203", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO203"), + MTK_FUNCTION(1, "BPI_BUS15"), + MTK_FUNCTION(7, "DBG_MON_B10") + ), + MTK_PIN( + 204, "GPIO204", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO204"), + MTK_FUNCTION(1, "BPI_BUS16"), + MTK_FUNCTION(2, "PA_VM0"), + MTK_FUNCTION(7, "DBG_MON_B11") + ), + MTK_PIN( + 205, "GPIO205", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO205"), + MTK_FUNCTION(1, "BPI_BUS17"), + MTK_FUNCTION(2, "PA_VM1"), + MTK_FUNCTION(7, "DBG_MON_B12") + ), + MTK_PIN( + 206, "GPIO206", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO206"), + MTK_FUNCTION(1, "BPI_BUS18"), + MTK_FUNCTION(2, "TX_SWAP0"), + MTK_FUNCTION(7, "DBG_MON_B13") + ), + MTK_PIN( + 207, "GPIO207", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO207"), + MTK_FUNCTION(1, "BPI_BUS19"), + MTK_FUNCTION(2, "TX_SWAP1"), + MTK_FUNCTION(7, "DBG_MON_B14") + ), + MTK_PIN( + 208, "GPIO208", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO208"), + MTK_FUNCTION(1, "BPI_BUS20"), + MTK_FUNCTION(2, "TX_SWAP2"), + MTK_FUNCTION(7, "DBG_MON_B15") + ), + MTK_PIN( + 209, "GPIO209", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO209"), + MTK_FUNCTION(1, "BPI_BUS21"), + MTK_FUNCTION(2, "TX_SWAP3"), + MTK_FUNCTION(7, "DBG_MON_B16") + ), + MTK_PIN( + 210, "GPIO210", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO210"), + MTK_FUNCTION(1, "BPI_BUS22"), + MTK_FUNCTION(2, "DET_BPI0"), + MTK_FUNCTION(7, "DBG_MON_B17") + ), + MTK_PIN( + 211, "GPIO211", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO211"), + MTK_FUNCTION(1, "BPI_BUS23"), + MTK_FUNCTION(2, "DET_BPI1"), + MTK_FUNCTION(7, "DBG_MON_B18") + ), + MTK_PIN( + 212, "GPIO212", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO212"), + MTK_FUNCTION(1, "BPI_BUS0"), + MTK_FUNCTION(7, "DBG_MON_B19") + ), + MTK_PIN( + 213, "GPIO213", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO213"), + MTK_FUNCTION(1, "BPI_BUS1"), + MTK_FUNCTION(7, "DBG_MON_B20") + ), + MTK_PIN( + 214, "GPIO214", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO214"), + MTK_FUNCTION(1, "BPI_BUS2"), + MTK_FUNCTION(7, "DBG_MON_B21") + ), + MTK_PIN( + 215, "GPIO215", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO215"), + MTK_FUNCTION(1, "BPI_BUS3"), + MTK_FUNCTION(7, "DBG_MON_B22") + ), + MTK_PIN( + 216, "GPIO216", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO216"), + MTK_FUNCTION(1, "MIPI2_SCLK"), + MTK_FUNCTION(7, "DBG_MON_B23") + ), + MTK_PIN( + 217, "GPIO217", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO217"), + MTK_FUNCTION(1, "MIPI2_SDATA"), + MTK_FUNCTION(7, "DBG_MON_B24") + ), + MTK_PIN( + 218, "GPIO218", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO218"), + MTK_FUNCTION(1, "MIPI3_SCLK"), + MTK_FUNCTION(7, "DBG_MON_B25") + ), + MTK_PIN( + 219, "GPIO219", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO219"), + MTK_FUNCTION(1, "MIPI3_SDATA"), + MTK_FUNCTION(7, "DBG_MON_B26") + ), + MTK_PIN( + 220, "GPIO220", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO220"), + MTK_FUNCTION(1, "CONN_WF_IP") + ), + MTK_PIN( + 221, "GPIO221", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO221"), + MTK_FUNCTION(1, "CONN_WF_IN") + ), + MTK_PIN( + 222, "GPIO222", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO222"), + MTK_FUNCTION(1, "CONN_WF_QP") + ), + MTK_PIN( + 223, "GPIO223", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO223"), + MTK_FUNCTION(1, "CONN_WF_QN") + ), + MTK_PIN( + 224, "GPIO224", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO224"), + MTK_FUNCTION(1, "CONN_BT_IP") + ), + MTK_PIN( + 225, "GPIO225", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO225"), + MTK_FUNCTION(1, "CONN_BT_IN") + ), + MTK_PIN( + 226, "GPIO226", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO226"), + MTK_FUNCTION(1, "CONN_BT_QP") + ), + MTK_PIN( + 227, "GPIO227", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO227"), + MTK_FUNCTION(1, "CONN_BT_QN") + ), + MTK_PIN( + 228, "GPIO228", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO228"), + MTK_FUNCTION(1, "CONN_GPS_IP") + ), + MTK_PIN( + 229, "GPIO229", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO229"), + MTK_FUNCTION(1, "CONN_GPS_IN") + ), + MTK_PIN( + 230, "GPIO230", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO230"), + MTK_FUNCTION(1, "CONN_GPS_QP") + ), + MTK_PIN( + 231, "GPIO231", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO231"), + MTK_FUNCTION(1, "CONN_GPS_QN") + ), + MTK_PIN( + 232, "GPIO232", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO232"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "UTXD1"), + MTK_FUNCTION(3, "MD_URXD0"), + MTK_FUNCTION(4, "MD_URXD1"), + MTK_FUNCTION(5, "MD_URXD2"), + MTK_FUNCTION(6, "C2K_URXD0"), + MTK_FUNCTION(7, "C2K_URXD1") + ), + MTK_PIN( + 233, "GPIO233", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO233"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "URXD1"), + MTK_FUNCTION(3, "MD_UTXD0"), + MTK_FUNCTION(4, "MD_UTXD1"), + MTK_FUNCTION(5, "MD_UTXD2"), + MTK_FUNCTION(6, "C2K_UTXD0"), + MTK_FUNCTION(7, "C2K_UTXD1") + ), + MTK_PIN( + 234, "GPIO234", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO234"), + MTK_FUNCTION(1, "SPI1_CLK_B"), + MTK_FUNCTION(2, "TP_UTXD1_AO"), + MTK_FUNCTION(3, "SCL4_1"), + MTK_FUNCTION(4, "UTXD0"), + MTK_FUNCTION(6, "PWM_A"), + MTK_FUNCTION(7, "DBG_MON_A23") + ), + MTK_PIN( + 235, "GPIO235", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO235"), + MTK_FUNCTION(1, "SPI1_MI_B"), + MTK_FUNCTION(2, "SPI1_MO_B"), + MTK_FUNCTION(3, "SDA4_1"), + MTK_FUNCTION(4, "URXD0"), + MTK_FUNCTION(6, "CLKM0"), + MTK_FUNCTION(7, "DBG_MON_A24") + ), + MTK_PIN( + 236, "GPIO236", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO236"), + MTK_FUNCTION(1, "SPI1_MO_B"), + MTK_FUNCTION(2, "SPI1_MI_B"), + MTK_FUNCTION(3, "SCL5_1"), + MTK_FUNCTION(4, "URTS0"), + MTK_FUNCTION(6, "PWM_B"), + MTK_FUNCTION(7, "DBG_MON_A25") + ), + MTK_PIN( + 237, "GPIO237", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO237"), + MTK_FUNCTION(1, "SPI1_CS_B"), + MTK_FUNCTION(2, "TP_URXD1_AO"), + MTK_FUNCTION(3, "SDA5_1"), + MTK_FUNCTION(4, "UCTS0"), + MTK_FUNCTION(6, "CLKM1"), + MTK_FUNCTION(7, "DBG_MON_A26") + ), + MTK_PIN( + 238, "GPIO238", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO238"), + MTK_FUNCTION(1, "SDA4_0") + ), + MTK_PIN( + 239, "GPIO239", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO239"), + MTK_FUNCTION(1, "SCL4_0") + ), + MTK_PIN( + 240, "GPIO240", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO240"), + MTK_FUNCTION(1, "SDA5_0") + ), + MTK_PIN( + 241, "GPIO241", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO241"), + MTK_FUNCTION(1, "SCL5_0") + ), + MTK_PIN( + 242, "GPIO242", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO242"), + MTK_FUNCTION(1, "SPI2_CLK_B"), + MTK_FUNCTION(2, "TP_UTXD2_AO"), + MTK_FUNCTION(3, "SCL4_2"), + MTK_FUNCTION(4, "UTXD1"), + MTK_FUNCTION(5, "URTS3"), + MTK_FUNCTION(6, "PWM_C"), + MTK_FUNCTION(7, "DBG_MON_A27") + ), + MTK_PIN( + 243, "GPIO243", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO243"), + MTK_FUNCTION(1, "SPI2_MI_B"), + MTK_FUNCTION(2, "SPI2_MO_B"), + MTK_FUNCTION(3, "SDA4_2"), + MTK_FUNCTION(4, "URXD1"), + MTK_FUNCTION(5, "UCTS3"), + MTK_FUNCTION(6, "CLKM2"), + MTK_FUNCTION(7, "DBG_MON_A28") + ), + MTK_PIN( + 244, "GPIO244", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO244"), + MTK_FUNCTION(1, "SPI2_MO_B"), + MTK_FUNCTION(2, "SPI2_MI_B"), + MTK_FUNCTION(3, "SCL5_2"), + MTK_FUNCTION(4, "URTS1"), + MTK_FUNCTION(5, "UTXD3"), + MTK_FUNCTION(6, "PWM_D"), + MTK_FUNCTION(7, "DBG_MON_A29") + ), + MTK_PIN( + 245, "GPIO245", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO245"), + MTK_FUNCTION(1, "SPI2_CS_B"), + MTK_FUNCTION(2, "TP_URXD2_AO"), + MTK_FUNCTION(3, "SDA5_2"), + MTK_FUNCTION(4, "UCTS1"), + MTK_FUNCTION(5, "URXD3"), + MTK_FUNCTION(6, "CLKM3"), + MTK_FUNCTION(7, "DBG_MON_A30") + ), + MTK_PIN( + 246, "GPIO246", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO246"), + MTK_FUNCTION(1, "I2S1_LRCK"), + MTK_FUNCTION(2, "I2S2_LRCK"), + MTK_FUNCTION(3, "I2S0_LRCK"), + MTK_FUNCTION(4, "I2S3_LRCK"), + MTK_FUNCTION(5, "PCM0_SYNC"), + MTK_FUNCTION(6, "SPI5_CLK_C"), + MTK_FUNCTION(7, "DBG_MON_A31") + ), + MTK_PIN( + 247, "GPIO247", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO247"), + MTK_FUNCTION(1, "I2S1_BCK"), + MTK_FUNCTION(2, "I2S2_BCK"), + MTK_FUNCTION(3, "I2S0_BCK"), + MTK_FUNCTION(4, "I2S3_BCK"), + MTK_FUNCTION(5, "PCM0_CLK"), + MTK_FUNCTION(6, "SPI5_MI_C"), + MTK_FUNCTION(7, "DBG_MON_A32") + ), + MTK_PIN( + 248, "GPIO248", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO248"), + MTK_FUNCTION(1, "I2S2_DI"), + MTK_FUNCTION(2, "I2S2_DI"), + MTK_FUNCTION(3, "I2S0_DI"), + MTK_FUNCTION(4, "I2S0_DI"), + MTK_FUNCTION(5, "PCM0_DI"), + MTK_FUNCTION(6, "SPI5_CS_C") + ), + MTK_PIN( + 249, "GPIO249", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO249"), + MTK_FUNCTION(1, "I2S1_DO"), + MTK_FUNCTION(2, "I2S1_DO"), + MTK_FUNCTION(3, "I2S3_DO"), + MTK_FUNCTION(4, "I2S3_DO"), + MTK_FUNCTION(5, "PCM0_DO"), + MTK_FUNCTION(6, "SPI5_MO_C"), + MTK_FUNCTION(7, "TRAP_SRAM_PWR_BYPASS") + ), + MTK_PIN( + 250, "GPIO250", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO250"), + MTK_FUNCTION(1, "SPI3_MI"), + MTK_FUNCTION(2, "SPI3_MO"), + MTK_FUNCTION(3, "IRTX_OUT"), + MTK_FUNCTION(6, "TP_URXD1_AO"), + MTK_FUNCTION(7, "DROP_ZONE") + ), + MTK_PIN( + 251, "GPIO251", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO251"), + MTK_FUNCTION(1, "SPI3_MO"), + MTK_FUNCTION(2, "SPI3_MI"), + MTK_FUNCTION(3, "CMFLASH"), + MTK_FUNCTION(6, "TP_UTXD1_AO"), + MTK_FUNCTION(7, "C2K_RTCK") + ), + MTK_PIN( + 252, "GPIO252", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO252"), + MTK_FUNCTION(1, "SPI3_CLK"), + MTK_FUNCTION(2, "SCL0_4"), + MTK_FUNCTION(3, "PWM_D"), + MTK_FUNCTION(7, "C2K_TMS") + ), + MTK_PIN( + 253, "GPIO253", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO253"), + MTK_FUNCTION(1, "SPI3_CS"), + MTK_FUNCTION(2, "SDA0_4"), + MTK_FUNCTION(3, "PWM_A"), + MTK_FUNCTION(7, "C2K_TCK") + ), + MTK_PIN( + 254, "GPIO254", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO254"), + MTK_FUNCTION(1, "I2S1_MCK"), + MTK_FUNCTION(2, "I2S2_MCK"), + MTK_FUNCTION(3, "I2S0_MCK"), + MTK_FUNCTION(4, "I2S3_MCK"), + MTK_FUNCTION(5, "CLKM0"), + MTK_FUNCTION(7, "C2K_TDI") + ), + MTK_PIN( + 255, "GPIO255", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO255"), + MTK_FUNCTION(1, "CLKM1"), + MTK_FUNCTION(2, "DISP_PWM"), + MTK_FUNCTION(3, "PWM_B"), + MTK_FUNCTION(6, "TP_GPIO1_AO"), + MTK_FUNCTION(7, "C2K_TDO") + ), + MTK_PIN( + 256, "GPIO256", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO256"), + MTK_FUNCTION(1, "CLKM2"), + MTK_FUNCTION(2, "IRTX_OUT"), + MTK_FUNCTION(3, "PWM_C"), + MTK_FUNCTION(6, "TP_GPIO0_AO"), + MTK_FUNCTION(7, "C2K_NTRST") + ), + MTK_PIN( + 257, "GPIO257", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO257"), + MTK_FUNCTION(1, "IO_JTAG_TMS"), + MTK_FUNCTION(2, "LTE_JTAG_TMS"), + MTK_FUNCTION(3, "DFD_TMS"), + MTK_FUNCTION(4, "DAP_SIB1_SWD"), + MTK_FUNCTION(5, "ANC_JTAG_TMS"), + MTK_FUNCTION(6, "SCP_JTAG_TMS"), + MTK_FUNCTION(7, "C2K_DM_OTMS") + ), + MTK_PIN( + 258, "GPIO258", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO258"), + MTK_FUNCTION(1, "IO_JTAG_TCK"), + MTK_FUNCTION(2, "LTE_JTAG_TCK"), + MTK_FUNCTION(3, "DFD_TCK_XI"), + MTK_FUNCTION(4, "DAP_SIB1_SWCK"), + MTK_FUNCTION(5, "ANC_JTAG_TCK"), + MTK_FUNCTION(6, "SCP_JTAG_TCK"), + MTK_FUNCTION(7, "C2K_DM_OTCK") + ), + MTK_PIN( + 259, "GPIO259", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO259"), + MTK_FUNCTION(1, "IO_JTAG_TDI"), + MTK_FUNCTION(2, "LTE_JTAG_TDI"), + MTK_FUNCTION(3, "DFD_TDI"), + MTK_FUNCTION(5, "ANC_JTAG_TDI"), + MTK_FUNCTION(6, "SCP_JTAG_TDI"), + MTK_FUNCTION(7, "C2K_DM_OTDI") + ), + MTK_PIN( + 260, "GPIO260", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO260"), + MTK_FUNCTION(1, "IO_JTAG_TDO"), + MTK_FUNCTION(2, "LTE_JTAG_TDO"), + MTK_FUNCTION(3, "DFD_TDO"), + MTK_FUNCTION(5, "ANC_JTAG_TDO"), + MTK_FUNCTION(6, "SCP_JTAG_TDO"), + MTK_FUNCTION(7, "C2K_DM_OTDO") + ), + MTK_PIN( + 261, "GPIO261", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, + MTK_FUNCTION(0, "GPIO261"), + MTK_FUNCTION(2, "LTE_JTAG_TRSTN"), + MTK_FUNCTION(3, "DFD_NTRST"), + MTK_FUNCTION(5, "ANC_JTAG_TRSTN"), + MTK_FUNCTION(6, "SCP_JTAG_TRSTN"), + MTK_FUNCTION(7, "C2K_DM_JTINTP") + ), +}; + +#endif /* __PINCTRL_MTK_MT6797_H */ +