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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id 4sm3704379oil.38.2021.08.23.08.48.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Aug 2021 08:48:41 -0700 (PDT) From: Bjorn Andersson To: Bjorn Helgaas , Rob Herring , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Stanimir Varbanov Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/2] PCI: dwc: Perform host_init() before registering msi Date: Mon, 23 Aug 2021 08:49:57 -0700 Message-Id: <20210823154958.305677-1-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On the Qualcomm sc8180x platform the bootloader does something related to PCI that leaves a pending "msi" interrupt, which with the current ordering often fires before init has a chance to enable the clocks that are necessary for the interrupt handler to access the hardware. Move the host_init() call before the registration of the "msi" interrupt handler to ensure the host driver has a chance to enable the clocks. The assignment of the bridge's ops and child_ops is moved along, because at least the TI Keystone driver overwrites these in its host_init callback. Signed-off-by: Bjorn Andersson Reviewed-by: Rob Herring --- Changes since v1: - New patch, instead of enabling resources in the qcom driver before jumping to dw_pcie_host_init(), per Rob Herring's suggestion. .../pci/controller/dwc/pcie-designware-host.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) -- 2.29.2 diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index d1d9b8344ec9..f4755f3a03be 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -335,6 +335,16 @@ int dw_pcie_host_init(struct pcie_port *pp) if (pci->link_gen < 1) pci->link_gen = of_pci_get_max_link_speed(np); + /* Set default bus ops */ + bridge->ops = &dw_pcie_ops; + bridge->child_ops = &dw_child_pcie_ops; + + if (pp->ops->host_init) { + ret = pp->ops->host_init(pp); + if (ret) + return ret; + } + if (pci_msi_enabled()) { pp->has_msi_ctrl = !(pp->ops->msi_host_init || of_property_read_bool(np, "msi-parent") || @@ -388,15 +398,6 @@ int dw_pcie_host_init(struct pcie_port *pp) } } - /* Set default bus ops */ - bridge->ops = &dw_pcie_ops; - bridge->child_ops = &dw_child_pcie_ops; - - if (pp->ops->host_init) { - ret = pp->ops->host_init(pp); - if (ret) - goto err_free_msi; - } dw_pcie_iatu_detect(pci); dw_pcie_setup_rc(pp); From patchwork Mon Aug 23 15:49:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 501602 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4094FC00143 for ; Mon, 23 Aug 2021 15:48:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 29B0561414 for ; Mon, 23 Aug 2021 15:48:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231533AbhHWPt1 (ORCPT ); Mon, 23 Aug 2021 11:49:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231564AbhHWPt0 (ORCPT ); Mon, 23 Aug 2021 11:49:26 -0400 Received: from mail-oo1-xc34.google.com (mail-oo1-xc34.google.com [IPv6:2607:f8b0:4864:20::c34]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DB4CC061760 for ; Mon, 23 Aug 2021 08:48:43 -0700 (PDT) Received: by mail-oo1-xc34.google.com with SMTP id b5-20020a4ac285000000b0029038344c3dso55254ooq.8 for ; Mon, 23 Aug 2021 08:48:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AKgdb23zVQQiYBe9YRTyia8uSzqrlES/FzcZLFz+L8M=; b=QDu4K/VcDYjt1r8tIck1Xp3hIvZJjnzR5kjlmCXeKzsbzrSD2Ba7XtFJoaomDfZPUU lwOyOnb2YPOeYcwrywq47FhuMf1cbrcIGysu/Wxhrxpf3MHCwyp8/SebA3P/exJnoBIn G461r198vc/dYxxnRSgQTmiCowdLMLueaIFlfc8QcX1uhpt3L8Sqh1AUfhRCZDoF4Ugw 1E2dmbvY65IfcVfm+cfBpqXmNf+gfpMLh8bX/ZcfLMbQoVYd1TFSIJ9H1ATP5NcTDqzp 0NrYmbMbzWDJUpC6RIr5URMbIM0v+t4ZddCndOzwaFyEw6L3es5mCjjkvqcmRjrCvq9t dTJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AKgdb23zVQQiYBe9YRTyia8uSzqrlES/FzcZLFz+L8M=; b=atDL83cfu6dPjtWYoutqMweEa3JsDt4SE/yqMtlSBFmJy10VvKyp26fn3GjJYPGxrs hLOQlcCwMtxBjlOwUbL1Px+QBpCRfFQin5fTSRD7udq6uZ2YvcCcyKuH6Xs1QWW19oZd IyTSuvgQs1et+8QHHnyhqfIWjlo7zmIaYlj3ojyQa1wCv7P2TuSV151hI3G8sBwBNnyj F6qpf9ybEGqYlhAD5nJBOOBCZF0FuIqFUNgxfAb/zWvs+dnpenGbzg9NOWq5nMQy6MjF lBXW6AX/bJtC2vZ9T6KUPL/XdMQ4Orxsym3BFH1Dt6+Cgachw6hsA5V747yyAclFlo/t NP8A== X-Gm-Message-State: AOAM533HxmsimosdQWQd6kw/hQSVH571OA+EFEI1Uz9ASi7mo3XxFVtZ wMBzGkQVB9jkfQm2wrLFL5Qv+g== X-Google-Smtp-Source: ABdhPJxSoo10Ko60CXkzwxw9InfSHOFlXC8MR1nsIwYLhTY5lOrDLMeQRVu0W1kdq5sjFNUdOWjBZA== X-Received: by 2002:a4a:b402:: with SMTP id y2mr26343711oon.89.1629733722788; Mon, 23 Aug 2021 08:48:42 -0700 (PDT) Received: from localhost.localdomain (104-57-184-186.lightspeed.austtx.sbcglobal.net. [104.57.184.186]) by smtp.gmail.com with ESMTPSA id 4sm3704379oil.38.2021.08.23.08.48.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Aug 2021 08:48:42 -0700 (PDT) From: Bjorn Andersson To: Bjorn Helgaas , Rob Herring , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Stanimir Varbanov Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/2] PCI: qcom: Add sc8180x compatible Date: Mon, 23 Aug 2021 08:49:58 -0700 Message-Id: <20210823154958.305677-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210823154958.305677-1-bjorn.andersson@linaro.org> References: <20210823154958.305677-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SC8180x platform comes with 4 PCIe controllers, typically used for things such as NVME storage or connecting a SDX55 5G modem. Add a compatible for this, that just reuses the 1.9.0 ops. Link: https://lore.kernel.org/linux-arm-msm/20210725040038.3966348-4-bjorn.andersson@linaro.org/ Signed-off-by: Bjorn Andersson --- Changes since v1: - None Documentation/devicetree/bindings/pci/qcom,pcie.txt | 5 +++-- drivers/pci/controller/dwc/pcie-qcom.c | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 3f646875f8c2..a0ae024c2d0c 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -12,6 +12,7 @@ - "qcom,pcie-ipq4019" for ipq4019 - "qcom,pcie-ipq8074" for ipq8074 - "qcom,pcie-qcs404" for qcs404 + - "qcom,pcie-sc8180x" for sc8180x - "qcom,pcie-sdm845" for sdm845 - "qcom,pcie-sm8250" for sm8250 - "qcom,pcie-ipq6018" for ipq6018 @@ -156,7 +157,7 @@ - "pipe" PIPE clock - clock-names: - Usage: required for sm8250 + Usage: required for sc8180x and sm8250 Value type: Definition: Should contain the following entries - "aux" Auxiliary clock @@ -245,7 +246,7 @@ - "ahb" AHB reset - reset-names: - Usage: required for sdm845 and sm8250 + Usage: required for sc8180x, sdm845 and sm8250 Value type: Definition: Should contain the following entries - "pci" PCIe core reset diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 8a7a300163e5..f3d9e522cfab 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1554,6 +1554,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 }, { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 }, { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 }, + { .compatible = "qcom,pcie-sc8180x", .data = &ops_1_9_0 }, { .compatible = "qcom,pcie-sm8250", .data = &ops_1_9_0 }, { } };