From patchwork Sun Aug 22 12:02:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kovvuri Goutham X-Patchwork-Id: 501773 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F85FC4338F for ; Sun, 22 Aug 2021 12:02:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 13E146128A for ; Sun, 22 Aug 2021 12:02:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231157AbhHVMD1 (ORCPT ); Sun, 22 Aug 2021 08:03:27 -0400 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:28058 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229961AbhHVMDZ (ORCPT ); Sun, 22 Aug 2021 08:03:25 -0400 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.0.43) with SMTP id 17MBO8Q2012225; Sun, 22 Aug 2021 05:02:42 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=iMzgXIpRF84Lk39VFbig3OfiOEdNrgFtCTIAJjU1dDs=; b=XXFwOdZRQsQtrSZkJQW8yPGPs1KyAdbtJJwjIfySWJQOQvQ1IrAJyIaLGk4LBzcZaCeJ evnT9suyio0z9OzcmpwdXu1oCPnhAEAv/AtPEVDpxsZvtLf5hXBrTG1XUwlLlMqxmfa+ t+rQ15Zw/9Ky9p0sltdn8jB16v8Sc/RO5gtiJEbkotYYjomUnkZtaGhMngm4/3dYZquy Y8H/BuVv8JPa89U/qnc9NH3awG7QVcBt3FSOTTd/7VJ940ZpRI4sKr0fLDWFmrUwlmzb l3E5VDynbUt4lLUlj7ceJ71nXC+q2grtsS8HmS0hYm+TDCA+lXvGXktMteWodeqWphxe DQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3ak10mtr5p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 22 Aug 2021 05:02:42 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Sun, 22 Aug 2021 05:02:40 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.23 via Frontend Transport; Sun, 22 Aug 2021 05:02:40 -0700 Received: from machine421.marvell.com (unknown [10.29.37.2]) by maili.marvell.com (Postfix) with ESMTP id 8BF743F7060; Sun, 22 Aug 2021 05:02:38 -0700 (PDT) From: Sunil Goutham To: , , CC: Subbaraya Sundeep , Hariprasad Kelam , Sunil Goutham Subject: [net PATCH 01/10] octeontx2-pf: Fix NIX1_RX interface backpressure Date: Sun, 22 Aug 2021 17:32:18 +0530 Message-ID: <1629633747-22061-2-git-send-email-sgoutham@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1629633747-22061-1-git-send-email-sgoutham@marvell.com> References: <1629633747-22061-1-git-send-email-sgoutham@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: l5k2k-hzNd7SQkFdR4ETjufmzbxV049L X-Proofpoint-ORIG-GUID: l5k2k-hzNd7SQkFdR4ETjufmzbxV049L X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1, Aquarius:18.0.790, Hydra:6.0.391, FMLib:17.0.607.475 definitions=2021-08-21_11,2021-08-20_03,2020-04-07_01 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Subbaraya Sundeep 'bp_ena' in Aura context is NIX block index, setting it zero will always backpressure NIX0 block, even if NIXLF belongs to NIX1. Hence fix this by setting it appropriately based on NIX block address. Signed-off-by: Subbaraya Sundeep Signed-off-by: Hariprasad Kelam Signed-off-by: Sunil Goutham --- drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c index 70fcc1f..2112008 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c @@ -1190,7 +1190,22 @@ static int otx2_aura_init(struct otx2_nic *pfvf, int aura_id, /* Enable backpressure for RQ aura */ if (aura_id < pfvf->hw.rqpool_cnt && !is_otx2_lbkvf(pfvf->pdev)) { aq->aura.bp_ena = 0; + /* If NIX1 LF is attached then specify NIX1_RX. + * + * Below NPA_AURA_S[BP_ENA] is set according to the + * NPA_BPINTF_E enumeration given as: + * 0x0 + a*0x1 where 'a' is 0 for NIX0_RX and 1 for NIX1_RX so + * NIX0_RX is 0x0 + 0*0x1 = 0 + * NIX1_RX is 0x0 + 1*0x1 = 1 + * But in HRM it is given that + * "NPA_AURA_S[BP_ENA](w1[33:32]) - Enable aura backpressure to + * NIX-RX based on [BP] level. One bit per NIX-RX; index + * enumerated by NPA_BPINTF_E." + */ + if (pfvf->nix_blkaddr == BLKADDR_NIX1) + aq->aura.bp_ena = 1; aq->aura.nix0_bpid = pfvf->bpid[0]; + /* Set backpressure level for RQ's Aura */ aq->aura.bp = RQ_BP_LVL_AURA; } From patchwork Sun Aug 22 12:02:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kovvuri Goutham X-Patchwork-Id: 501492 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93534C432BE for ; Sun, 22 Aug 2021 12:02:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 765BB611C2 for ; Sun, 22 Aug 2021 12:02:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231388AbhHVMD3 (ORCPT ); Sun, 22 Aug 2021 08:03:29 -0400 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:41468 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229961AbhHVMD2 (ORCPT ); Sun, 22 Aug 2021 08:03:28 -0400 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.0.43) with SMTP id 17M9nI63017269; Sun, 22 Aug 2021 05:02:45 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=h/GjcaFOVREoS7h92m9EHoci3aAZup1fR4rzPYX2Ix0=; b=KLNc6BGuiSrQbrsafDGkOpY85Pf/OafOUuwB/tYeZBLOINufBsJzmsSZWOeueg7wzK/9 YllRI5E4XgAAfZZh7YmsK3hSkxpJEehPz+6iY/9W4+e2u5KCeMQlMC2ijDK/y19KSX+K 8qNi90b1bLYphX7O4tpX8ofAAAlHavJwNHEr1rcZL8X8q4aXbAhF4GiQUyQcZ5WzVJ5j GLlMiTnCWZ5KvfL9YfTc6lYSXKA4HCL/meOhuOtPRDHfAJ8dpaCtfnN6wXfScNNTy2s2 kCf0KOUXnSpqNRn1nMbJhJ8RvSxRS63ZHjEGMoVDNioFxEH63ABTZAekwAvgoclf+ihp TA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3ak10mtr5u-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 22 Aug 2021 05:02:45 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Sun, 22 Aug 2021 05:02:43 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.23 via Frontend Transport; Sun, 22 Aug 2021 05:02:43 -0700 Received: from machine421.marvell.com (unknown [10.29.37.2]) by maili.marvell.com (Postfix) with ESMTP id 126013F7060; Sun, 22 Aug 2021 05:02:41 -0700 (PDT) From: Sunil Goutham To: , , CC: Subbaraya Sundeep , Sunil Goutham Subject: [net PATCH 02/10] octeontx2-af: cn10k: Fix SDP base channel number Date: Sun, 22 Aug 2021 17:32:19 +0530 Message-ID: <1629633747-22061-3-git-send-email-sgoutham@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1629633747-22061-1-git-send-email-sgoutham@marvell.com> References: <1629633747-22061-1-git-send-email-sgoutham@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: -PDsij0FHRFcMF4uVpm4g8sHP3CYXmD- X-Proofpoint-ORIG-GUID: -PDsij0FHRFcMF4uVpm4g8sHP3CYXmD- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1, Aquarius:18.0.790, Hydra:6.0.391, FMLib:17.0.607.475 definitions=2021-08-21_11,2021-08-20_03,2020-04-07_01 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Subbaraya Sundeep As per hardware the base channel number configured for programmable channels of a block must be multiple of number of channels of that block. This condition is not met for SDP base channel currently. Hence this patch ensures all the base channel numbers of all blocks are multiple of number of channels present in the blocks. Also instead of hardcoding SDP number of channels the same is read from the NIX_AF_CONST1 register. Fixes: 242da439214b ("octeontx2-af: cn10k: Add support for programmable") Signed-off-by: Subbaraya Sundeep Signed-off-by: Sunil Goutham --- drivers/net/ethernet/marvell/octeontx2/af/common.h | 2 -- .../net/ethernet/marvell/octeontx2/af/rvu_cn10k.c | 31 +++++++++++++++------- 2 files changed, 22 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/common.h b/drivers/net/ethernet/marvell/octeontx2/af/common.h index 47f5ed0..e0b43aa 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/common.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/common.h @@ -195,8 +195,6 @@ enum nix_scheduler { #define NIX_CHAN_LBK_CHX(a, b) (0 + 0x100 * (a) + (b)) #define NIX_CHAN_SDP_CH_START (0x700ull) -#define SDP_CHANNELS 256 - /* The mask is to extract lower 10-bits of channel number * which CPT will pass to X2P. */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c index 8d48b64..28dcce7 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c @@ -212,9 +212,10 @@ void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc) int rvu_set_channels_base(struct rvu *rvu) { + u16 nr_lbk_chans, nr_sdp_chans, nr_cgx_chans, nr_cpt_chans; + u16 sdp_chan_base, cgx_chan_base, cpt_chan_base; struct rvu_hwinfo *hw = rvu->hw; - u16 cpt_chan_base; - u64 nix_const; + u64 nix_const, nix_const1; int blkaddr; blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, 0); @@ -222,6 +223,7 @@ int rvu_set_channels_base(struct rvu *rvu) return blkaddr; nix_const = rvu_read64(rvu, blkaddr, NIX_AF_CONST); + nix_const1 = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); hw->cgx = (nix_const >> 12) & 0xFULL; hw->lmac_per_cgx = (nix_const >> 8) & 0xFULL; @@ -244,14 +246,24 @@ int rvu_set_channels_base(struct rvu *rvu) * channels such that all channel numbers are contiguous * leaving no holes. This way the new CPT channels can be * accomodated. The order of channel numbers assigned is - * LBK, SDP, CGX and CPT. + * LBK, SDP, CGX and CPT. Also the base channel number + * of a block must be multiple of number of channels + * of the block. */ - hw->sdp_chan_base = hw->lbk_chan_base + hw->lbk_links * - ((nix_const >> 16) & 0xFFULL); - hw->cgx_chan_base = hw->sdp_chan_base + hw->sdp_links * SDP_CHANNELS; + nr_lbk_chans = (nix_const >> 16) & 0xFFULL; + nr_sdp_chans = nix_const1 & 0xFFFULL; + nr_cgx_chans = nix_const & 0xFFULL; + nr_cpt_chans = (nix_const >> 32) & 0xFFFULL; - cpt_chan_base = hw->cgx_chan_base + hw->cgx_links * - (nix_const & 0xFFULL); + sdp_chan_base = hw->lbk_chan_base + hw->lbk_links * nr_lbk_chans; + /* Round up base channel to multiple of number of channels */ + hw->sdp_chan_base = ALIGN(sdp_chan_base, nr_sdp_chans); + + cgx_chan_base = hw->sdp_chan_base + hw->sdp_links * nr_sdp_chans; + hw->cgx_chan_base = ALIGN(cgx_chan_base, nr_cgx_chans); + + cpt_chan_base = hw->cgx_chan_base + hw->cgx_links * nr_cgx_chans; + hw->cpt_chan_base = ALIGN(cpt_chan_base, nr_cpt_chans); /* Out of 4096 channels start CPT from 2048 so * that MSB for CPT channels is always set @@ -355,6 +367,7 @@ static void rvu_lbk_set_channels(struct rvu *rvu) static void __rvu_nix_set_channels(struct rvu *rvu, int blkaddr) { + u64 nix_const1 = rvu_read64(rvu, blkaddr, NIX_AF_CONST1); u64 nix_const = rvu_read64(rvu, blkaddr, NIX_AF_CONST); u16 cgx_chans, lbk_chans, sdp_chans, cpt_chans; struct rvu_hwinfo *hw = rvu->hw; @@ -364,7 +377,7 @@ static void __rvu_nix_set_channels(struct rvu *rvu, int blkaddr) cgx_chans = nix_const & 0xFFULL; lbk_chans = (nix_const >> 16) & 0xFFULL; - sdp_chans = SDP_CHANNELS; + sdp_chans = nix_const1 & 0xFFFULL; cpt_chans = (nix_const >> 32) & 0xFFFULL; start = hw->cgx_chan_base; From patchwork Sun Aug 22 12:02:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kovvuri Goutham X-Patchwork-Id: 501772 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26364C4338F for ; Sun, 22 Aug 2021 12:02:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0A46261284 for ; Sun, 22 Aug 2021 12:02:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231601AbhHVMDf (ORCPT ); Sun, 22 Aug 2021 08:03:35 -0400 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:61202 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231580AbhHVMDb (ORCPT ); Sun, 22 Aug 2021 08:03:31 -0400 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.0.43) with SMTP id 17MBLSwO006972; Sun, 22 Aug 2021 05:02:48 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=N9f5GZNAdvDPBo5HgALod4DU3+eTEndHl50kWYAHLEA=; b=CeHtboKS+vw4QJ1y+QacgnNRImxnXB66OT2X/0p9osI6XfVCZZJqcMaHcSpu/h6NB143 c+OGkU0sVCj4FHaMT0sVk1pgtO31RE/ZNGAD8lNf+W00R98eHyNU9dRjhPQdFku8DPo6 yMSWX///4+xui0g2an5eJLQnI6CozD0zf+Aaf14HV5eL/M+epU71bYQxTZC+SQDY+Gs+ dRZsC0Zh75mNLAjpg/L0zoO3ZjlZpHyZ7lmL4D8R9ci5htVD6L2o4EQKp+qNDpcG0/iG yqXKg4wImCAJzuFSlnDD3nAyVSYm3ed28TyAjGBjD7mrWqCueTR6drz+wDzknNtsA70F Ow== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3ak10mtr5x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 22 Aug 2021 05:02:47 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Sun, 22 Aug 2021 05:02:45 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.23 via Frontend Transport; Sun, 22 Aug 2021 05:02:45 -0700 Received: from machine421.marvell.com (unknown [10.29.37.2]) by maili.marvell.com (Postfix) with ESMTP id 3486D3F7061; Sun, 22 Aug 2021 05:02:43 -0700 (PDT) From: Sunil Goutham To: , , CC: Geetha sowjanya , Sunil Goutham Subject: [net PATCH 03/10] octeontx2-af: Handle return value in block reset. Date: Sun, 22 Aug 2021 17:32:20 +0530 Message-ID: <1629633747-22061-4-git-send-email-sgoutham@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1629633747-22061-1-git-send-email-sgoutham@marvell.com> References: <1629633747-22061-1-git-send-email-sgoutham@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: 65IvyFbS1LE8pKni0e6fBz62OSkYkrbG X-Proofpoint-ORIG-GUID: 65IvyFbS1LE8pKni0e6fBz62OSkYkrbG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1, Aquarius:18.0.790, Hydra:6.0.391, FMLib:17.0.607.475 definitions=2021-08-21_11,2021-08-20_03,2020-04-07_01 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Geetha sowjanya Print debug message if any of the RVU hardware blocks reset fails. Signed-off-by: Geetha sowjanya Signed-off-by: Sunil Goutham --- drivers/net/ethernet/marvell/octeontx2/af/rvu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c index 5fe277e..633ba6c 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c @@ -498,12 +498,15 @@ int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf) static void rvu_block_reset(struct rvu *rvu, int blkaddr, u64 rst_reg) { struct rvu_block *block = &rvu->hw->block[blkaddr]; + int err; if (!block->implemented) return; rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0)); - rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true); + err = rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true); + if (err) + dev_err(rvu->dev, "HW block:%d reset failed\n", blkaddr); } static void rvu_reset_all_blocks(struct rvu *rvu) From patchwork Sun Aug 22 12:02:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kovvuri Goutham X-Patchwork-Id: 501491 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81FD3C4338F for ; Sun, 22 Aug 2021 12:02:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 691BC6128A for ; Sun, 22 Aug 2021 12:02:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231646AbhHVMDh (ORCPT ); Sun, 22 Aug 2021 08:03:37 -0400 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:8772 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231414AbhHVMDe (ORCPT ); Sun, 22 Aug 2021 08:03:34 -0400 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.0.43) with SMTP id 17MB0KTa005798; Sun, 22 Aug 2021 05:02:51 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=hSE7RWISIMoYhRkahQcHjHPsWhNSg2EbPiwP4Vj0FLk=; b=cfcHb6YDrQGLbRQlkHqN7q8Y7SXy4OPTDJVoD1H+ASecfXC18O/EJ19yDil3xIkmXrnQ pEqQPNJ949XIeBDJ7RqRWna0p5fvc7ykbbd73tDbDjEXXMfMigitUo2pPLntMVdGaH3a Zhmf68ikMfdqqZEE4zMSg8oDx6xrwqb8YUVEaB0/c9jIo1eBq30icKcuBRJIJjaUwtxl 61Y/9SR6TkhEtwGAVyCd47XGyEDTxzwN8YmS/oEX8h99sY1DAAgFdzJylSWRohI+iDZX g+de1LdXyTPk0gQVMj3tRNM80e7rBkex2xbASTmRdqyziZySmOgZFGtylJq+wKNWp0xT Eg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3ak10mtr63-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 22 Aug 2021 05:02:50 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Sun, 22 Aug 2021 05:02:47 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.23 via Frontend Transport; Sun, 22 Aug 2021 05:02:47 -0700 Received: from machine421.marvell.com (unknown [10.29.37.2]) by maili.marvell.com (Postfix) with ESMTP id 6031A3F706C; Sun, 22 Aug 2021 05:02:46 -0700 (PDT) From: Sunil Goutham To: , , CC: Hariprasad Kelam , Sunil Goutham Subject: [net PATCH 04/10] octeontx2-pf: Don't mask out supported link modes Date: Sun, 22 Aug 2021 17:32:21 +0530 Message-ID: <1629633747-22061-5-git-send-email-sgoutham@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1629633747-22061-1-git-send-email-sgoutham@marvell.com> References: <1629633747-22061-1-git-send-email-sgoutham@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: _4FlFMwWnPGOdqx5BUyymQVPqEl6UUTa X-Proofpoint-ORIG-GUID: _4FlFMwWnPGOdqx5BUyymQVPqEl6UUTa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1, Aquarius:18.0.790, Hydra:6.0.391, FMLib:17.0.607.475 definitions=2021-08-21_11,2021-08-20_03,2020-04-07_01 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Hariprasad Kelam Supported link modes are updated by firmware in shared structure per interface. Kernel uses this value to display supported link modes via ethtool. Currently there is extra validation that firmware updated modes are validated against internal list of supported modes. As intenal list of supported modes are not updated frequently new modes supported by firmware are not updated to ethtool. Hence remove extra validation and report all firmware updated modes. Signed-off-by: Hariprasad Kelam Signed-off-by: Sunil Goutham --- drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c index b906a0e..b90decf 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c @@ -33,9 +33,6 @@ struct otx2_stat { .index = offsetof(struct otx2_dev_stats, stat) / sizeof(u64), \ } -/* Physical link config */ -#define OTX2_ETHTOOL_SUPPORTED_MODES 0x638CCBF //110001110001100110010111111 - enum link_mode { OTX2_MODE_SUPPORTED, OTX2_MODE_ADVERTISED @@ -1116,8 +1113,6 @@ static void otx2_get_link_mode_info(u64 link_mode_bmap, }; u8 bit; - link_mode_bmap = link_mode_bmap & OTX2_ETHTOOL_SUPPORTED_MODES; - for_each_set_bit(bit, (unsigned long *)&link_mode_bmap, 27) { /* SGMII mode is set */ if (bit == 0) From patchwork Sun Aug 22 12:02:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kovvuri Goutham X-Patchwork-Id: 501771 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B466C432BE for ; Sun, 22 Aug 2021 12:02:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6451361284 for ; Sun, 22 Aug 2021 12:02:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231686AbhHVMDi (ORCPT ); Sun, 22 Aug 2021 08:03:38 -0400 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:25974 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231571AbhHVMDe (ORCPT ); Sun, 22 Aug 2021 08:03:34 -0400 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.0.43) with SMTP id 17MB0KTb005798; Sun, 22 Aug 2021 05:02:51 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=qzToyglDQMprVvtHMsjaHZSxNkpUas3nIBGCae6uXo8=; b=Ze7Vy2iSEnt1WZn5s2UzEhVxtMo/WUcDX+dBiRkznJBup26grr1oYQ9QfRFJX6NpDjYT XDA/Mrr7JtbfwXHUxEQpajF4DX9FLWElZTWkvApksRNw9ZEwIbFSAi5ttp4w1mIYsfnR 3Q9P+ipIS0cLEKzLoE0UNyFK3T6kLPDRolm7oCTmHWDQW0/M6quEoiRhY/QY33WhSsi+ k0Kxy2V0ZODE5W5JoOEJCcCV9laLCSGnbMiU+RCTlSzyhOAxs1LYqXCXnTtaZ+wQ6sNP STlzcuNiMUHcpYIaj1NbmWKOQQq3fR/FLTMk33JQYxwvxNPVsXrhchmKkVRhnk1/Mz2T Ew== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3ak10mtr63-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 22 Aug 2021 05:02:51 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Sun, 22 Aug 2021 05:02:50 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.23 via Frontend Transport; Sun, 22 Aug 2021 05:02:50 -0700 Received: from machine421.marvell.com (unknown [10.29.37.2]) by maili.marvell.com (Postfix) with ESMTP id 82F7B3F7060; Sun, 22 Aug 2021 05:02:48 -0700 (PDT) From: Sunil Goutham To: , , CC: Naveen Mamindlapalli , Sunil Goutham Subject: [net PATCH 05/10] octeontx2-pf: send correct vlan priority mask to npc_install_flow_req Date: Sun, 22 Aug 2021 17:32:22 +0530 Message-ID: <1629633747-22061-6-git-send-email-sgoutham@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1629633747-22061-1-git-send-email-sgoutham@marvell.com> References: <1629633747-22061-1-git-send-email-sgoutham@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: zn6vbldWQcrRLCCOqQWsly3JBCUT6i1w X-Proofpoint-ORIG-GUID: zn6vbldWQcrRLCCOqQWsly3JBCUT6i1w X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1, Aquarius:18.0.790, Hydra:6.0.391, FMLib:17.0.607.475 definitions=2021-08-21_11,2021-08-20_03,2020-04-07_01 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Naveen Mamindlapalli This patch corrects the erroneous vlan priority mask field that was send to npc_install_flow_req. Fixes: 1d4d9e42c240 ("octeontx2-pf: Add tc flower hardware offload on ingress traffic") Signed-off-by: Naveen Mamindlapalli Signed-off-by: Sunil Goutham --- drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c index 972b202..32d5c62 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_tc.c @@ -485,8 +485,8 @@ static int otx2_tc_prepare_flow(struct otx2_nic *nic, struct otx2_tc_flow *node, match.key->vlan_priority << 13; vlan_tci_mask = match.mask->vlan_id | - match.key->vlan_dei << 12 | - match.key->vlan_priority << 13; + match.mask->vlan_dei << 12 | + match.mask->vlan_priority << 13; flow_spec->vlan_tci = htons(vlan_tci); flow_mask->vlan_tci = htons(vlan_tci_mask); From patchwork Sun Aug 22 12:02:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kovvuri Goutham X-Patchwork-Id: 501490 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF196C4338F for ; Sun, 22 Aug 2021 12:03:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A6E686126A for ; Sun, 22 Aug 2021 12:03:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232252AbhHVMDl (ORCPT ); Sun, 22 Aug 2021 08:03:41 -0400 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:54350 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231723AbhHVMDj (ORCPT ); Sun, 22 Aug 2021 08:03:39 -0400 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.0.43) with SMTP id 17M9nI66017269; Sun, 22 Aug 2021 05:02:56 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=19spTkTXVDBbcPDiL8WwgwKj8BXckoV0mI61YmI9nVw=; b=I0xM0VvXocXukozzXObViaIo2Hoyh4w/0iYauNdbX405AgX+scumOEpsv8PmJk1gNjZr iVJbJ+f4fgeUp2Iaon0POBB9GVDxSAQ+6PMbG8ebmtNVU7Y8lmche1+630R6YmmG+XU0 K0cbYMzTPXDCLUPYeOditYMwc1YI97SAAKlI5Wx6ej0P/XilWmZ8Sn0KWEi78b1Lf3lt xorwfxr3qe/Dk6RArtHHRny0CHZnDg72ej110yglQXZqeTUzNYMpTTa+hahUhhSBESzA KyWuIKNihb8wApMfedAJQycZv2L3P0udhlQBRCrlJZxBNfc9v5oplGFLe7v1h6dKpNLy 9g== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3ak10mtr6c-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 22 Aug 2021 05:02:56 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Sun, 22 Aug 2021 05:02:52 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.23 via Frontend Transport; Sun, 22 Aug 2021 05:02:52 -0700 Received: from machine421.marvell.com (unknown [10.29.37.2]) by maili.marvell.com (Postfix) with ESMTP id AE98D3F7061; Sun, 22 Aug 2021 05:02:50 -0700 (PDT) From: Sunil Goutham To: , , CC: Geetha sowjanya , Sunil Goutham Subject: [net PATCH 06/10] octeontx2-af: Use DMA_ATTR_FORCE_CONTIGUOUS attribute in DMA alloc Date: Sun, 22 Aug 2021 17:32:23 +0530 Message-ID: <1629633747-22061-7-git-send-email-sgoutham@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1629633747-22061-1-git-send-email-sgoutham@marvell.com> References: <1629633747-22061-1-git-send-email-sgoutham@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: _BOYMvJR4pWe-_wrbIqUZLq4okb_qiMU X-Proofpoint-ORIG-GUID: _BOYMvJR4pWe-_wrbIqUZLq4okb_qiMU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1, Aquarius:18.0.790, Hydra:6.0.391, FMLib:17.0.607.475 definitions=2021-08-21_11,2021-08-20_03,2020-04-07_01 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Geetha sowjanya CN10K platform requires physically contiguous memory for LMTST operations which goes beyond a single page. Not having physically contiguous memory will result in HW fetching transmit descriptors from a wrong memory location. Hence use DMA_ATTR_FORCE_CONTIGUOUS attribute while allocating LMTST regions. Signed-off-by: Geetha sowjanya Signed-off-by: Sunil Goutham --- drivers/net/ethernet/marvell/octeontx2/af/common.h | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/common.h b/drivers/net/ethernet/marvell/octeontx2/af/common.h index e0b43aa..459fa95 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/common.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/common.h @@ -64,8 +64,8 @@ static inline int qmem_alloc(struct device *dev, struct qmem **q, qmem->entry_sz = entry_sz; qmem->alloc_sz = (qsize * entry_sz) + OTX2_ALIGN; - qmem->base = dma_alloc_coherent(dev, qmem->alloc_sz, - &qmem->iova, GFP_KERNEL); + qmem->base = dma_alloc_attrs(dev, qmem->alloc_sz, &qmem->iova, + GFP_KERNEL, DMA_ATTR_FORCE_CONTIGUOUS); if (!qmem->base) return -ENOMEM; @@ -84,9 +84,10 @@ static inline void qmem_free(struct device *dev, struct qmem *qmem) return; if (qmem->base) - dma_free_coherent(dev, qmem->alloc_sz, - qmem->base - qmem->align, - qmem->iova - qmem->align); + dma_free_attrs(dev, qmem->alloc_sz, + qmem->base - qmem->align, + qmem->iova - qmem->align, + DMA_ATTR_FORCE_CONTIGUOUS); devm_kfree(dev, qmem); } From patchwork Sun Aug 22 12:02:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kovvuri Goutham X-Patchwork-Id: 501770 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0F23C432BE for ; Sun, 22 Aug 2021 12:03:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D89616128A for ; Sun, 22 Aug 2021 12:03:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232362AbhHVMDm (ORCPT ); Sun, 22 Aug 2021 08:03:42 -0400 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:43032 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232204AbhHVMDj (ORCPT ); Sun, 22 Aug 2021 08:03:39 -0400 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.0.43) with SMTP id 17MB0KTd005798; Sun, 22 Aug 2021 05:02:56 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=I5P3vu8YnZDt+COy+/Nunc+oa5752Znatvl6jFbBJoo=; b=DhuE4wEXDl3Zyn8LoTfEUv7T0L2pkAEBFshBLddLtuHQd1va2qakKkTcxPHxfjQwB8a+ 9jX0xR8/X5GFIfQKXwhQJWO3VK3yTsH1CN2XuPbqGBQOsYGzgIh7UM24k9WGpwHOEnF7 ZJHd5fPLMLjuQ7MjXADcTEbcOWx6NmDOEaRAiswhyaCqBn137xEM0SYwsm7q1RHFSnKb R0DLAwHYD8+BgjIfRDYSIlRoXARqiZ0tTSyg+P+2sZM8lYNsu7ySjZLhBBms9sMYSIIM s2x1phz/ydbvmdmkFe0Vtvp3iCrQCsJhmISONgQUKwZlaeKKYB5/YsFmkMA65yAE3DZ2 eA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 3ak10mtr6f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 22 Aug 2021 05:02:56 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Sun, 22 Aug 2021 05:02:54 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.23 via Frontend Transport; Sun, 22 Aug 2021 05:02:54 -0700 Received: from machine421.marvell.com (unknown [10.29.37.2]) by maili.marvell.com (Postfix) with ESMTP id D15A33F7060; Sun, 22 Aug 2021 05:02:52 -0700 (PDT) From: Sunil Goutham To: , , CC: Geetha sowjanya , Sunil Goutham Subject: [net PATCH 07/10] octeontx2-af: Check capability flag while freeing ipolicer memory Date: Sun, 22 Aug 2021 17:32:24 +0530 Message-ID: <1629633747-22061-8-git-send-email-sgoutham@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1629633747-22061-1-git-send-email-sgoutham@marvell.com> References: <1629633747-22061-1-git-send-email-sgoutham@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: -KkQGXWTXiQylYsvZm-2M05XRG1l9yQl X-Proofpoint-ORIG-GUID: -KkQGXWTXiQylYsvZm-2M05XRG1l9yQl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1, Aquarius:18.0.790, Hydra:6.0.391, FMLib:17.0.607.475 definitions=2021-08-21_11,2021-08-20_03,2020-04-07_01 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Geetha sowjanya Bandwidth profiles (ipolicer structure)is implemented only on CN10K platform. But current code try to free the ipolicer memory without checking the capibility flag leading to driver crash on OCTEONTX2 platform. This patch fixes the issue by add capability flag check. Fixes: e8e095b3b3700 ("octeontx2-af: cn10k: Bandwidth profiles config support") Signed-off-by: Geetha sowjanya Signed-off-by: Sunil Goutham --- drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c index 4bfbbdf..c321950 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c @@ -25,7 +25,7 @@ static int nix_update_mce_rule(struct rvu *rvu, u16 pcifunc, int type, bool add); static int nix_setup_ipolicers(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr); -static void nix_ipolicer_freemem(struct nix_hw *nix_hw); +static void nix_ipolicer_freemem(struct rvu *rvu, struct nix_hw *nix_hw); static int nix_verify_bandprof(struct nix_cn10k_aq_enq_req *req, struct nix_hw *nix_hw, u16 pcifunc); static int nix_free_all_bandprof(struct rvu *rvu, u16 pcifunc); @@ -3849,7 +3849,7 @@ static void rvu_nix_block_freemem(struct rvu *rvu, int blkaddr, kfree(txsch->schq.bmap); } - nix_ipolicer_freemem(nix_hw); + nix_ipolicer_freemem(rvu, nix_hw); vlan = &nix_hw->txvlan; kfree(vlan->rsrc.bmap); @@ -4225,11 +4225,14 @@ static int nix_setup_ipolicers(struct rvu *rvu, return 0; } -static void nix_ipolicer_freemem(struct nix_hw *nix_hw) +static void nix_ipolicer_freemem(struct rvu *rvu, struct nix_hw *nix_hw) { struct nix_ipolicer *ipolicer; int layer; + if (!rvu->hw->cap.ipolicer) + return; + for (layer = 0; layer < BAND_PROF_NUM_LAYERS; layer++) { ipolicer = &nix_hw->ipolicer[layer]; From patchwork Sun Aug 22 12:02:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kovvuri Goutham X-Patchwork-Id: 501489 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27FC3C4338F for ; Sun, 22 Aug 2021 12:03:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 12B386126A for ; Sun, 22 Aug 2021 12:03:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233344AbhHVMDo (ORCPT ); Sun, 22 Aug 2021 08:03:44 -0400 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:53564 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232682AbhHVMDl (ORCPT ); Sun, 22 Aug 2021 08:03:41 -0400 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.0.43) with SMTP id 17MBIv6K004018; Sun, 22 Aug 2021 05:02:58 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=O3EjgIMK+nJWlDrxPzmFoOLe0I8nDe2ZPnpJmETsu/8=; b=IMvWP+lTMJ9qAyH0VOy6eFPP1B76/Xov7wEpvDTBRJgC74kmuXxb+OnZvqGq2OF/fA/b Sq8L5ehDeR9uo/b2641rfbj6Yrq3j73IfO6oPkQd90oCpP0nixdcUSLRkGdl7HjATX4T /0Ff+SBIz54sr3bWMzkj2ZEx5ZV0Ycii/T/dBOSR3YGteLWOXczMYjwRz1xMtDhm3iBr AC+Gm0MqBMNy1NPvqoon7nMtrnlVAIzV+sdlMfKYBDu3RrB0iQW2q0bs10dmBzP3gCfu ET2hvrOLQlGEz/mnVzPbWHSp9IDJ6b0EdGz/uXml1/xaFCHTZglSbgTsiLPEW6ihrGxt aQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3ak10mtr6n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 22 Aug 2021 05:02:58 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Sun, 22 Aug 2021 05:02:56 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.23 via Frontend Transport; Sun, 22 Aug 2021 05:02:56 -0700 Received: from machine421.marvell.com (unknown [10.29.37.2]) by maili.marvell.com (Postfix) with ESMTP id F38683F7076; Sun, 22 Aug 2021 05:02:54 -0700 (PDT) From: Sunil Goutham To: , , CC: Sunil Goutham Subject: [net PATCH 08/10] octeontx2-pf: Don't install VLAN offload rule if netdev is down Date: Sun, 22 Aug 2021 17:32:25 +0530 Message-ID: <1629633747-22061-9-git-send-email-sgoutham@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1629633747-22061-1-git-send-email-sgoutham@marvell.com> References: <1629633747-22061-1-git-send-email-sgoutham@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: mycazINstExISz-AnxFfMK8oBSYsIF7P X-Proofpoint-ORIG-GUID: mycazINstExISz-AnxFfMK8oBSYsIF7P X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1, Aquarius:18.0.790, Hydra:6.0.391, FMLib:17.0.607.475 definitions=2021-08-21_11,2021-08-20_03,2020-04-07_01 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Whenever user changes interface MAC address both default DMAC based MCAM rule and VLAN offload (for strip) rules are updated with new MAC address. To update or install VLAN offload rule PF driver needs interface's receive channel info, which is retrieved from admin function at the time of NIXLF initialization. If user changes MAC address before interface is UP, VLAN offload rule installation will fail and throw error as receive channel is not valid. To avoid this, skip VLAN offload rule installation if netdev is not UP. This rule will anyway be reinslatted as part of open() call. Fixes: fd9d7859db6c ("octeontx2-pf: Implement ingress/egress VLAN offload") Signed-off-by: Sunil Goutham --- drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c index 2112008..4e125d6 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c @@ -208,7 +208,8 @@ int otx2_set_mac_address(struct net_device *netdev, void *p) if (!otx2_hw_set_mac_addr(pfvf, addr->sa_data)) { memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); /* update dmac field in vlan offload rule */ - if (pfvf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) + if (netif_running(netdev) && + pfvf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) otx2_install_rxvlan_offload_flow(pfvf); /* update dmac address in ntuple and DMAC filter list */ if (pfvf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) From patchwork Sun Aug 22 12:02:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kovvuri Goutham X-Patchwork-Id: 501769 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7332CC4338F for ; Sun, 22 Aug 2021 12:03:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5D07C6126A for ; Sun, 22 Aug 2021 12:03:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233259AbhHVMDs (ORCPT ); Sun, 22 Aug 2021 08:03:48 -0400 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:15686 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232477AbhHVMDn (ORCPT ); Sun, 22 Aug 2021 08:03:43 -0400 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.0.43) with SMTP id 17MBO8Q5012225; Sun, 22 Aug 2021 05:03:00 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=X7G7VWFRDKWmXwY/xR1rdvZx4+rKtby3dOL8a1gQC28=; b=Rvv0E2fmhSI+ISmVJMWFESr5X96hSr07RBZgFyP9Ri67Eg8/b65XwT88jD0mYMdakKKp uLwFTUHKgzPUPYgM1qEh03EC6F7Ar3yDzM2vxWn83QzJ38oS+hQ7anb6lTrLpNbfWshL mrQO3GVWhJO+lmnSQaNe+S2fI53H4JNf2cLBjRKGRW+CLWw0Hiyof8Aza6jEnKqXS9pr 8UoJaeyPkjJWwPNhDjLMkPeK/LcAbilPA65tQvD0h+0COcdJVUCIPt0YxQdHCVanhBvo hJq287mSBP0fILoCvqJsOldv0EqETTOC/cpep/M7NUu5R23I8EtC/xTgB8lNx84XG3cT PA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 3ak10mtr6v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 22 Aug 2021 05:03:00 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Sun, 22 Aug 2021 05:02:58 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.23 via Frontend Transport; Sun, 22 Aug 2021 05:02:58 -0700 Received: from machine421.marvell.com (unknown [10.29.37.2]) by maili.marvell.com (Postfix) with ESMTP id DBFFB3F7060; Sun, 22 Aug 2021 05:02:56 -0700 (PDT) From: Sunil Goutham To: , , CC: Sunil Goutham Subject: [net PATCH 09/10] octeontx2-pf: Fix algorithm index in MCAM rules with RSS action Date: Sun, 22 Aug 2021 17:32:26 +0530 Message-ID: <1629633747-22061-10-git-send-email-sgoutham@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1629633747-22061-1-git-send-email-sgoutham@marvell.com> References: <1629633747-22061-1-git-send-email-sgoutham@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: u20qSgEZratJVkV_HiLn85535wY9hBCL X-Proofpoint-ORIG-GUID: u20qSgEZratJVkV_HiLn85535wY9hBCL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1, Aquarius:18.0.790, Hydra:6.0.391, FMLib:17.0.607.475 definitions=2021-08-21_11,2021-08-20_03,2020-04-07_01 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Otherthan setting action as RSS in NPC MCAM entry, RSS flowkey algorithm index also needs to be set. Otherwise whatever algorithm is defined at flowkey index '0' will be considered by HW and pkt flows will be distributed as such. Fix this by saving the flowkey index sent by admin function while initializing RSS and then use it when framing MCAM rules. Fixes: 81a4362016e7 ("octeontx2-pf: Add RSS multi group support") Signed-off-by: Sunil Goutham --- drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c | 11 +++++++++++ drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h | 3 +++ drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c | 1 + 3 files changed, 15 insertions(+) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c index 4e125d6..679c3f8 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c @@ -269,6 +269,7 @@ int otx2_config_pause_frm(struct otx2_nic *pfvf) int otx2_set_flowkey_cfg(struct otx2_nic *pfvf) { struct otx2_rss_info *rss = &pfvf->hw.rss_info; + struct nix_rss_flowkey_cfg_rsp *rsp; struct nix_rss_flowkey_cfg *req; int err; @@ -283,6 +284,16 @@ int otx2_set_flowkey_cfg(struct otx2_nic *pfvf) req->group = DEFAULT_RSS_CONTEXT_GROUP; err = otx2_sync_mbox_msg(&pfvf->mbox); + if (err) + goto fail; + + rsp = (struct nix_rss_flowkey_cfg_rsp *) + otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); + if (IS_ERR(rsp)) + goto fail; + + pfvf->hw.flowkey_alg_idx = rsp->alg_idx; +fail: mutex_unlock(&pfvf->mbox.lock); return err; } diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h index 8fd58cd..8c602d2 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h @@ -196,6 +196,9 @@ struct otx2_hw { u8 lso_udpv4_idx; u8 lso_udpv6_idx; + /* RSS */ + u8 flowkey_alg_idx; + /* MSI-X */ u8 cint_cnt; /* CQ interrupt count */ u16 npa_msixoff; /* Offset of NPA vectors */ diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c index 4d9de52..fdd27c4 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c @@ -858,6 +858,7 @@ static int otx2_add_flow_msg(struct otx2_nic *pfvf, struct otx2_flow *flow) if (flow->flow_spec.flow_type & FLOW_RSS) { req->op = NIX_RX_ACTIONOP_RSS; req->index = flow->rss_ctx_id; + req->flow_key_alg = pfvf->hw.flowkey_alg_idx; } else { req->op = NIX_RX_ACTIONOP_UCAST; req->index = ethtool_get_flow_spec_ring(ring_cookie); From patchwork Sun Aug 22 12:02:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil Kovvuri Goutham X-Patchwork-Id: 501488 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CC0CC4320A for ; Sun, 22 Aug 2021 12:03:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1CB03611C2 for ; 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Sun, 22 Aug 2021 05:03:02 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Sun, 22 Aug 2021 05:03:00 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.23 via Frontend Transport; Sun, 22 Aug 2021 05:03:00 -0700 Received: from machine421.marvell.com (unknown [10.29.37.2]) by maili.marvell.com (Postfix) with ESMTP id C46933F7061; Sun, 22 Aug 2021 05:02:58 -0700 (PDT) From: Sunil Goutham To: , , CC: Geetha sowjanya , Sunil Goutham Subject: [net PATCH 10/10] octeontx2-af: cn10k: Use FLIT0 register instead of FLIT1 Date: Sun, 22 Aug 2021 17:32:27 +0530 Message-ID: <1629633747-22061-11-git-send-email-sgoutham@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1629633747-22061-1-git-send-email-sgoutham@marvell.com> References: <1629633747-22061-1-git-send-email-sgoutham@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: HmIqPs-_YTpU0QnxfDH8zM1S0CWCT_yM X-Proofpoint-ORIG-GUID: HmIqPs-_YTpU0QnxfDH8zM1S0CWCT_yM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1, Aquarius:18.0.790, Hydra:6.0.391, FMLib:17.0.607.475 definitions=2021-08-21_11,2021-08-20_03,2020-04-07_01 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org From: Geetha sowjanya RVU SMMU widget stores the final translated PA at RVU_AF_SMMU_TLN_FLIT0<57:18> instead of FLIT1 register. This patch fixes the address translation logic to use the correct register. Fixes: 893ae97214c3 ("octeontx2-af: cn10k: Support configurable LMTST regions") Signed-off-by: Geetha sowjanya Signed-off-by: Sunil Goutham --- drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c | 4 ++-- drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c index 28dcce7..dbe9149 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c @@ -82,10 +82,10 @@ static int rvu_get_lmtaddr(struct rvu *rvu, u16 pcifunc, dev_err(rvu->dev, "%s LMTLINE iova transulation failed err:%llx\n", __func__, val); return -EIO; } - /* PA[51:12] = RVU_AF_SMMU_TLN_FLIT1[60:21] + /* PA[51:12] = RVU_AF_SMMU_TLN_FLIT0[57:18] * PA[11:0] = IOVA[11:0] */ - pa = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_TLN_FLIT1) >> 21; + pa = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_TLN_FLIT0) >> 18; pa &= GENMASK_ULL(39, 0); *lmt_addr = (pa << 12) | (iova & 0xFFF); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h index 8b01ef6..4215841 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h @@ -53,7 +53,7 @@ #define RVU_AF_SMMU_TXN_REQ (0x6008) #define RVU_AF_SMMU_ADDR_RSP_STS (0x6010) #define RVU_AF_SMMU_ADDR_TLN (0x6018) -#define RVU_AF_SMMU_TLN_FLIT1 (0x6030) +#define RVU_AF_SMMU_TLN_FLIT0 (0x6020) /* Admin function's privileged PF/VF registers */ #define RVU_PRIV_CONST (0x8000000)