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[209.51.188.17]) by mx.google.com with ESMTPS id y13si484337vsi.24.2021.08.18.13.21.02 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 18 Aug 2021 13:21:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yUjnjwCD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38520 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mGS3Z-00082E-HS for patch@linaro.org; Wed, 18 Aug 2021 16:21:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40194) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mGS2J-0007zU-KL for qemu-devel@nongnu.org; Wed, 18 Aug 2021 16:19:43 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:39691) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mGS2D-00066z-BO for qemu-devel@nongnu.org; Wed, 18 Aug 2021 16:19:43 -0400 Received: by mail-pf1-x429.google.com with SMTP id t13so3334495pfl.6 for ; Wed, 18 Aug 2021 13:19:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=TW2jPB+qt2tYLCLMQFTHUpeWPukL7tgvM1aowRW86hI=; b=yUjnjwCDD8adKLXQfGGIzgqtrpnGtmTC0IgFivRXjOTldM20Uao3JEj9UnjOaamXwH xd/Cd/dI4fbQaIUTMQ8VSlqZAsbJ4/A7H+69gQ+4a/isYWYziRNyhQ/KZKPFTebM4rHv Nv36JX8Xd68tBX+0Njm7Z0NMvqAMZyvQN2/MCutbXNJXtlug19WLTzf/AtAL86tTpy7g UkG/s49QpMlvMc4znWxdENrc6y9C8EKjZNgKMHmcZZpgs3XFXsvpe1fIt4lPtgl3QJTw tOaTjQIeM5mjmxb6+TI75ujyCo9Sj7K2U0fmzPzFZmXAQyHMFDWzupGBEUOHAEotu7ar lLLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TW2jPB+qt2tYLCLMQFTHUpeWPukL7tgvM1aowRW86hI=; b=MFVUEIDU9eKbjMVtN1Qt5Zebtlw2vJ2NvGIVscIQnSNz/5rL70ffcSzU7FlLg1DGAn 3Vl0lc18s1ZLEdW/kehavVRC2DcRsOKbt1Xc3R0bfHxpHUYjPX9RwPzUIalKxGeX0z5V nbFcohKmZB3vTs47CKkMmn6xeoGFiEfO8WFJDczLByuEWot7gcJ8yIYepdom3YVuRLst pL+j/dERBhd9oQ3qxVI6dFmergLsJDCHXZ3xRTd1eKHG8QOymoMYMpd1ySimd/YxYU9L Katgr6EWQwxif6+F96QHD2Tvuf/Ozxp9y4ITw5wquLGDfIK5AnbNZobtvRqYBnI5GiGO U7gw== X-Gm-Message-State: AOAM533hZG+HzNmg3XaZem+ETBQh69euu/KPknh8pXHi6hyOL9wfwzOI VWy+lzul6WMQIPcD70Olhy2m/vPnL4T5xA== X-Received: by 2002:a63:790b:: with SMTP id u11mr10394040pgc.71.1629317975388; Wed, 18 Aug 2021 13:19:35 -0700 (PDT) Received: from localhost.localdomain ([173.197.107.15]) by smtp.gmail.com with ESMTPSA id x13sm619621pjh.30.2021.08.18.13.19.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Aug 2021 13:19:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 01/16] tcg/mips: Support unaligned access for user-only Date: Wed, 18 Aug 2021 10:19:16 -1000 Message-Id: <20210818201931.393394-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818201931.393394-1-richard.henderson@linaro.org> References: <20210818201931.393394-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is kinda sorta the opposite of the other tcg hosts, where we get (normal) alignment checks for free with host SIGBUS and need to add code to support unaligned accesses. Fortunately, the ISA contains pairs of instructions that are used to implement unaligned memory accesses. Use them. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 2 - tcg/mips/tcg-target.c.inc | 324 +++++++++++++++++++++++++++++++++++++- 2 files changed, 318 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 3a62055f04..3afbb31918 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -209,8 +209,6 @@ extern bool use_mips32r2_instructions; void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); -#ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS -#endif #endif diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 02dc4b63ae..7ed0de9dae 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -24,6 +24,8 @@ * THE SOFTWARE. */ +#include "../tcg-ldst.c.inc" + #ifdef HOST_WORDS_BIGENDIAN # define MIPS_BE 1 #else @@ -230,16 +232,26 @@ typedef enum { OPC_ORI = 015 << 26, OPC_XORI = 016 << 26, OPC_LUI = 017 << 26, + OPC_BNEL = 025 << 26, + OPC_BNEZALC_R6 = 030 << 26, OPC_DADDIU = 031 << 26, + OPC_LDL = 032 << 26, + OPC_LDR = 033 << 26, OPC_LB = 040 << 26, OPC_LH = 041 << 26, + OPC_LWL = 042 << 26, OPC_LW = 043 << 26, OPC_LBU = 044 << 26, OPC_LHU = 045 << 26, + OPC_LWR = 046 << 26, OPC_LWU = 047 << 26, OPC_SB = 050 << 26, OPC_SH = 051 << 26, + OPC_SWL = 052 << 26, OPC_SW = 053 << 26, + OPC_SDL = 054 << 26, + OPC_SDR = 055 << 26, + OPC_SWR = 056 << 26, OPC_LD = 067 << 26, OPC_SD = 077 << 26, @@ -1035,8 +1047,6 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) } #if defined(CONFIG_SOFTMMU) -#include "../tcg-ldst.c.inc" - static void * const qemu_ld_helpers[(MO_SSIZE | MO_BSWAP) + 1] = { [MO_UB] = helper_ret_ldub_mmu, [MO_SB] = helper_ret_ldsb_mmu, @@ -1344,7 +1354,82 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); return true; } -#endif + +#else + +static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrlo, + TCGReg addrhi, unsigned a_bits) +{ + unsigned a_mask = (1 << a_bits) - 1; + TCGLabelQemuLdst *l = new_ldst_label(s); + + l->is_ld = is_ld; + l->addrlo_reg = addrlo; + l->addrhi_reg = addrhi; + + /* We are expecting a_bits to max out at 7, much lower than ANDI. */ + tcg_debug_assert(a_bits < 16); + tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask); + + l->label_ptr[0] = s->code_ptr; + if (use_mips32r6_instructions) { + tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); + } else { + tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); + tcg_out_nop(s); + } + + l->raddr = tcg_splitwx_to_rx(s->code_ptr); +} + +static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) +{ + void *target; + + if (!reloc_pc16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { + return false; + } + + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + /* A0 is env, A1 is skipped, A2:A3 is the uint64_t address. */ + TCGReg a2 = MIPS_BE ? l->addrhi_reg : l->addrlo_reg; + TCGReg a3 = MIPS_BE ? l->addrlo_reg : l->addrhi_reg; + + if (a3 != TCG_REG_A2) { + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, a2); + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, a3); + } else if (a2 != TCG_REG_A3) { + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, a3); + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, a2); + } else { + tcg_out_mov(s, TCG_TYPE_I32, TCG_TMP0, TCG_REG_A2); + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, TCG_REG_A3); + tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, TCG_TMP0); + } + } else { + tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_A1, l->addrlo_reg); + } + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); + + /* + * Tail call to the helper, with the return address back inline. + * We have arrived here via BNEL, so $31 is already set. + */ + target = (l->is_ld ? helper_unaligned_ld : helper_unaligned_st); + tcg_out_call_int(s, target, true); + return true; +} + +static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} + +static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + return tcg_out_fail_alignment(s, l); +} +#endif /* SOFTMMU */ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, TCGReg base, MemOp opc, bool is_64) @@ -1450,6 +1535,117 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, } } +static void __attribute__((unused)) +tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, + TCGReg base, MemOp opc, bool is_64) +{ + const MIPSInsn lw1 = MIPS_BE ? OPC_LWL : OPC_LWR; + const MIPSInsn lw2 = MIPS_BE ? OPC_LWR : OPC_LWL; + const MIPSInsn ld1 = MIPS_BE ? OPC_LDL : OPC_LDR; + const MIPSInsn ld2 = MIPS_BE ? OPC_LDR : OPC_LDL; + + bool sgn = (opc & MO_SIGN); + + switch (opc & (MO_SSIZE | MO_BSWAP)) { + case MO_SW | MO_BE: + case MO_UW | MO_BE: + tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); + tcg_out_opc_imm(s, OPC_LBU, TCG_TMP1, base, 1); + tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); + tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); + break; + + case MO_SW | MO_LE: + case MO_UW | MO_LE: + tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0); + tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1); + tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8); + tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); + break; + + case MO_SL: + case MO_UL: + tcg_out_opc_imm(s, lw1, lo, base, 0); + tcg_out_opc_imm(s, lw2, lo, base, 3); + if (TCG_TARGET_REG_BITS == 64 && is_64 && !sgn) { + tcg_out_ext32u(s, lo, lo); + } + break; + + case MO_UL | MO_BSWAP: + case MO_SL | MO_BSWAP: + if (use_mips32r2_instructions) { + tcg_out_opc_imm(s, lw1, lo, base, 0); + tcg_out_opc_imm(s, lw2, lo, base, 3); + tcg_out_bswap32(s, lo, lo, + TCG_TARGET_REG_BITS == 64 && is_64 + ? (sgn ? TCG_BSWAP_OS : TCG_BSWAP_OZ) : 0); + } else { + const tcg_insn_unit *subr = + (TCG_TARGET_REG_BITS == 64 && is_64 && !sgn + ? bswap32u_addr : bswap32_addr); + + tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0); + tcg_out_bswap_subr(s, subr); + /* delay slot */ + tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 3); + tcg_out_mov(s, is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32, lo, TCG_TMP3); + } + break; + + case MO_Q: + if (TCG_TARGET_REG_BITS == 64) { + tcg_out_opc_imm(s, ld1, lo, base, 0); + tcg_out_opc_imm(s, ld2, lo, base, 7); + } else { + tcg_out_opc_imm(s, lw1, MIPS_BE ? hi : lo, base, 0 + 0); + tcg_out_opc_imm(s, lw2, MIPS_BE ? hi : lo, base, 0 + 3); + tcg_out_opc_imm(s, lw1, MIPS_BE ? lo : hi, base, 4 + 0); + tcg_out_opc_imm(s, lw2, MIPS_BE ? lo : hi, base, 4 + 3); + } + break; + + case MO_Q | MO_BSWAP: + if (TCG_TARGET_REG_BITS == 64) { + if (use_mips32r2_instructions) { + tcg_out_opc_imm(s, ld1, lo, base, 0); + tcg_out_opc_imm(s, ld2, lo, base, 7); + tcg_out_bswap64(s, lo, lo); + } else { + tcg_out_opc_imm(s, ld1, TCG_TMP0, base, 0); + tcg_out_bswap_subr(s, bswap64_addr); + /* delay slot */ + tcg_out_opc_imm(s, ld2, TCG_TMP0, base, 7); + tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); + } + } else if (use_mips32r2_instructions) { + tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0 + 0); + tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 0 + 3); + tcg_out_opc_imm(s, lw1, TCG_TMP1, base, 4 + 0); + tcg_out_opc_imm(s, lw2, TCG_TMP1, base, 4 + 3); + tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0); + tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1); + tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16); + tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16); + } else { + tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0 + 0); + tcg_out_bswap_subr(s, bswap32_addr); + /* delay slot */ + tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 0 + 3); + tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 4 + 0); + tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3); + tcg_out_bswap_subr(s, bswap32_addr); + /* delay slot */ + tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 4 + 3); + tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3); + } + break; + + default: + tcg_abort(); + } +} + static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) { TCGReg addr_regl, addr_regh __attribute__((unused)); @@ -1458,6 +1654,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) MemOp opc; #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[2]; +#else + unsigned a_bits, s_bits; #endif TCGReg base = TCG_REG_A0; @@ -1487,7 +1685,27 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) } else { tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); } - tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); + a_bits = get_alignment_bits(opc); + s_bits = opc & MO_SIZE; + /* + * R6 removes the left/right instructions but requires the + * system to support misaligned memory accesses. + */ + if (use_mips32r6_instructions) { + if (a_bits) { + tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); + } + tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); + } else { + if (a_bits && a_bits != s_bits) { + tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); + } + if (a_bits >= s_bits) { + tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); + } else { + tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, is_64); + } + } #endif } @@ -1552,6 +1770,79 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, } } +static void __attribute__((unused)) +tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, + TCGReg base, MemOp opc) +{ + const MIPSInsn sw1 = MIPS_BE ? OPC_SWL : OPC_SWR; + const MIPSInsn sw2 = MIPS_BE ? OPC_SWR : OPC_SWL; + const MIPSInsn sd1 = MIPS_BE ? OPC_SDL : OPC_SDR; + const MIPSInsn sd2 = MIPS_BE ? OPC_SDR : OPC_SDL; + + /* Don't clutter the code below with checks to avoid bswapping ZERO. */ + if ((lo | hi) == 0) { + opc &= ~MO_BSWAP; + } + + switch (opc & (MO_SIZE | MO_BSWAP)) { + case MO_16 | MO_BE: + tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); + tcg_out_opc_imm(s, OPC_SB, TCG_TMP0, base, 0); + tcg_out_opc_imm(s, OPC_SB, lo, base, 1); + break; + + case MO_16 | MO_LE: + tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); + tcg_out_opc_imm(s, OPC_SB, lo, base, 0); + tcg_out_opc_imm(s, OPC_SB, TCG_TMP0, base, 1); + break; + + case MO_32 | MO_BSWAP: + tcg_out_bswap32(s, TCG_TMP3, lo, 0); + lo = TCG_TMP3; + /* fall through */ + case MO_32: + tcg_out_opc_imm(s, sw1, lo, base, 0); + tcg_out_opc_imm(s, sw2, lo, base, 3); + break; + + case MO_64 | MO_BSWAP: + if (TCG_TARGET_REG_BITS == 64) { + tcg_out_bswap64(s, TCG_TMP3, lo); + lo = TCG_TMP3; + } else if (use_mips32r2_instructions) { + tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? hi : lo); + tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? lo : hi); + tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16); + tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16); + hi = MIPS_BE ? TCG_TMP0 : TCG_TMP1; + lo = MIPS_BE ? TCG_TMP1 : TCG_TMP0; + } else { + tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0); + tcg_out_opc_imm(s, sw1, TCG_TMP3, base, 0); + tcg_out_opc_imm(s, sw2, TCG_TMP3, base, 3); + tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0); + tcg_out_opc_imm(s, sw1, TCG_TMP3, base, 4); + tcg_out_opc_imm(s, sw2, TCG_TMP3, base, 7); + break; + } + /* fall through */ + case MO_64: + if (TCG_TARGET_REG_BITS == 64) { + tcg_out_opc_imm(s, sd1, lo, base, 0); + tcg_out_opc_imm(s, sd2, lo, base, 7); + } else { + tcg_out_opc_imm(s, sw1, MIPS_BE ? hi : lo, base, 0); + tcg_out_opc_imm(s, sw2, MIPS_BE ? hi : lo, base, 3); + tcg_out_opc_imm(s, sw1, MIPS_BE ? lo : hi, base, 4); + tcg_out_opc_imm(s, sw2, MIPS_BE ? lo : hi, base, 7); + } + break; + + default: + tcg_abort(); + } +} static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) { TCGReg addr_regl, addr_regh __attribute__((unused)); @@ -1560,6 +1851,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) MemOp opc; #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[2]; +#else + unsigned a_bits, s_bits; #endif TCGReg base = TCG_REG_A0; @@ -1578,7 +1871,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else - base = TCG_REG_A0; if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { tcg_out_ext32u(s, base, addr_regl); addr_regl = base; @@ -1590,7 +1882,27 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) } else { tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); } - tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); + a_bits = get_alignment_bits(opc); + s_bits = opc & MO_SIZE; + /* + * R6 removes the left/right instructions but requires the + * system to support misaligned memory accesses. + */ + if (use_mips32r6_instructions) { + if (a_bits) { + tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); + } + tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); + } else { + if (a_bits && a_bits != s_bits) { + tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); + } + if (a_bits >= s_bits) { + tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); + } else { + tcg_out_qemu_st_unalign(s, data_regl, data_regh, base, opc); + } + } #endif } From patchwork Wed Aug 18 20:19:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 498991 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp1013151jab; Wed, 18 Aug 2021 13:30:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx76muxcPzBl1jxs5Lb4//CgiA5faRG/eEexxU2RJQixaMl+lZOD5LggXcVD+nsrvSjpGjX X-Received: by 2002:a67:cb0d:: with SMTP id b13mr9923472vsl.5.1629318656238; Wed, 18 Aug 2021 13:30:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629318656; cv=none; d=google.com; s=arc-20160816; b=brK9kWBMkikpt5oefonGSftMVzlFsfMb0Ke339B79ZOQ6Td82veRcvJwzq+yCagPNt VPbCaDH0CBy4Kz+xS1LNcfW6COogCWYuQU4KJ29achpJUA7JmAig9NdVsqufIr4+JO3f IvD45NPEYdQEWgGilbldUv2uSnxGkaEjAHGI2indVtpLvHpy1XLxAb9SNtCums+BYNs4 p03IeGsygSA5Htzh3aL0dv4GkTpSNBIsWtBkW6qzyPakJQkUBcSysbuqNCnHwlaq6X7u BnaUQoK+6MO2w+lfsG+kMwUv2qj6iHp5+4+oiTKCINUa2WGXA0yxgRBzk05aq+aOcWIS GzPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=r6oX0sSPyEwxmWKFqa3wE6vu1liF30zaILMwFsdFRog=; b=AWSC/jbplk+YJ/BF7ZFjbTmwmYw7IFx8V7Ow5O5s6ddlBkMjDHXz2YTX7hDm0EZ4OZ RTgfm78zy5AHR9lmpp3D8mOJ9aeBvcAm88dKxJdIQcm1hP7H1AI25if+CEM9n/8Z7fUU UPU8+6dGJTv7aOx0+NXcBv2ED3XvoQOcsZAMJK7tfei/W2KwKyZtR6I4l4j2LNwuB43O vn+KrEX8x6jzV8ZWwQn4W0JnUJ594qsocbFdmTSmlWlxcrn0n7QdiaWeADX3rkQv2BCn Hjrg7AM665zp47D2efjGCBYt4y0DPcDTaokXNCZbv/Ocgc6GD70VSIFRhasSE++7f5sP c9cA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ygtet+A4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u22si542989vsj.292.2021.08.18.13.30.56 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 18 Aug 2021 13:30:56 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ygtet+A4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43116 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mGSD9-0004oY-Iq for patch@linaro.org; Wed, 18 Aug 2021 16:30:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40186) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mGS2J-0007yQ-A3 for qemu-devel@nongnu.org; Wed, 18 Aug 2021 16:19:43 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:36413) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mGS2H-00067C-6i for qemu-devel@nongnu.org; Wed, 18 Aug 2021 16:19:43 -0400 Received: by mail-pl1-x629.google.com with SMTP id f3so2563815plg.3 for ; Wed, 18 Aug 2021 13:19:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=r6oX0sSPyEwxmWKFqa3wE6vu1liF30zaILMwFsdFRog=; b=ygtet+A4A3yMhF+PdfcCHJxPE2XsgtrHUDsb5nX7JQpwdJYZ5VNP5fzsBUW/9XTlId 7XO64KJyjRdJgwZmXsHlYfaMBNvhY8D3eydvQ1duD6cErvb3Bdw2/LqSDdVLVfOPeSgp +RyS9LUNB9k+tMrdKql+jb5o4gTR5ptdJDwRguYP+RFt5Y8Ezv9SckVBZjKvTvhUZiHd aHV/9ffH1eBUyR9WOL+51Z8JvdtsbYTHgoaPP+K7hXzMVwr12Xiag7RJEaJokJHCohBt XxlcaFtDT1HV2wKBmOAzzW8Ei1P5N14qtMG6aYIIL9r8kiZihopO7wGqiIDR/k1qcRyg MBBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=r6oX0sSPyEwxmWKFqa3wE6vu1liF30zaILMwFsdFRog=; b=mh+2j4afjmNKrjxL2Tq+jkqiMJ9BOEfBuAJ8ZqGtiNu3MUdNstssUPp/GDsMdphvWV Ecb9B1QfWB4vLVor3lGdBclG8bLxiEM0tgMcZHVXQ+vjdYO8NSI0rWIYQwbC6jgKDRmu hZb2NgPOJES+im/9Gfby9AUSyTmvoRQ7GwrxkQ+YG0mhzkLQHBcF7To6f4mNGqHZetX4 jDA5TujoDvHOYoeE4AB7qZY7OeM+KPAwvLTqxOHdmD/wJkbP9FN3U1e6lDjnyInwVBVe NlulGtUx1LX8XClhUXqq4vxtSlZWoPyQg0lkgJNjqKAN3UNQSCJnJwtuZBsZfIVkqokA cYWw== X-Gm-Message-State: AOAM533IZ6AvFiwOwlS+7LU+A2ZiZRvZEc6YKcw0Qr7JsB+61pf5PAza ATDIStI3qZ4Whz6sGYa6z3A1YCNQEmfabA== X-Received: by 2002:a17:90a:9411:: with SMTP id r17mr11070536pjo.49.1629317976310; Wed, 18 Aug 2021 13:19:36 -0700 (PDT) Received: from localhost.localdomain ([173.197.107.15]) by smtp.gmail.com with ESMTPSA id x13sm619621pjh.30.2021.08.18.13.19.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Aug 2021 13:19:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 02/16] tcg/mips: Support unaligned access for softmmu Date: Wed, 18 Aug 2021 10:19:17 -1000 Message-Id: <20210818201931.393394-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818201931.393394-1-richard.henderson@linaro.org> References: <20210818201931.393394-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We can use the routines just added for user-only to emit unaligned accesses in softmmu mode too. Signed-off-by: Richard Henderson Reviewed-by: Jiaxun Yang --- tcg/mips/tcg-target.c.inc | 91 ++++++++++++++++++++++----------------- 1 file changed, 51 insertions(+), 40 deletions(-) -- 2.25.1 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 7ed0de9dae..3d6a0ba39e 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1154,8 +1154,10 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, tcg_insn_unit *label_ptr[2], bool is_load) { MemOp opc = get_memop(oi); - unsigned s_bits = opc & MO_SIZE; unsigned a_bits = get_alignment_bits(opc); + unsigned s_bits = opc & MO_SIZE; + unsigned a_mask = (1 << a_bits) - 1; + unsigned s_mask = (1 << s_bits) - 1; int mem_index = get_mmuidx(oi); int fast_off = TLB_MASK_TABLE_OFS(mem_index); int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); @@ -1163,7 +1165,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, int add_off = offsetof(CPUTLBEntry, addend); int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); - target_ulong mask; + target_ulong tlb_mask; /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); @@ -1177,27 +1179,13 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */ tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); - /* We don't currently support unaligned accesses. - We could do so with mips32r6. */ - if (a_bits < s_bits) { - a_bits = s_bits; - } - - /* Mask the page bits, keeping the alignment bits to compare against. */ - mask = (target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1); - /* Load the (low-half) tlb comparator. */ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { - tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); - tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, mask); + tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); } else { tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW), TCG_TMP0, TCG_TMP3, cmp_off); - tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, mask); - /* No second compare is required here; - load the tlb addend for the fast path. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); } /* Zero extend a 32-bit guest address for a 64-bit host. */ @@ -1205,7 +1193,25 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, tcg_out_ext32u(s, base, addrl); addrl = base; } - tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); + + /* + * Mask the page bits, keeping the alignment bits to compare against. + * For unaligned accesses, compare against the end of the access to + * verify that it does not cross a page boundary. + */ + tlb_mask = (target_ulong)TARGET_PAGE_MASK | a_mask; + tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, tlb_mask); + if (a_mask >= s_mask) { + tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); + } else { + tcg_out_opc_imm(s, ALIAS_PADDI, TCG_TMP2, addrl, s_mask - a_mask); + tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); + } + + if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) { + /* Load the tlb addend for the fast path. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); + } label_ptr[0] = s->code_ptr; tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); @@ -1213,7 +1219,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, /* Load and test the high half tlb comparator. */ if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { /* delay slot */ - tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); + tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); /* Load the tlb addend for the fast path. */ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); @@ -1535,8 +1541,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, } } -static void __attribute__((unused)) -tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, +static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, TCGReg base, MemOp opc, bool is_64) { const MIPSInsn lw1 = MIPS_BE ? OPC_LWL : OPC_LWR; @@ -1655,8 +1660,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[2]; #else - unsigned a_bits, s_bits; #endif + unsigned a_bits, s_bits; TCGReg base = TCG_REG_A0; data_regl = *args++; @@ -1665,10 +1670,20 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); oi = *args++; opc = get_memop(oi); + a_bits = get_alignment_bits(opc); + s_bits = opc & MO_SIZE; + /* + * R6 removes the left/right instructions but requires the + * system to support misaligned memory accesses. + */ #if defined(CONFIG_SOFTMMU) tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1); - tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); + if (use_mips32r6_instructions || a_bits >= s_bits) { + tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); + } else { + tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, is_64); + } add_qemu_ldst_label(s, 1, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), data_regl, data_regh, addr_regl, addr_regh, @@ -1685,12 +1700,6 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) } else { tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); } - a_bits = get_alignment_bits(opc); - s_bits = opc & MO_SIZE; - /* - * R6 removes the left/right instructions but requires the - * system to support misaligned memory accesses. - */ if (use_mips32r6_instructions) { if (a_bits) { tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); @@ -1770,8 +1779,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, } } -static void __attribute__((unused)) -tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, +static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, TCGReg base, MemOp opc) { const MIPSInsn sw1 = MIPS_BE ? OPC_SWL : OPC_SWR; @@ -1851,9 +1859,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) MemOp opc; #if defined(CONFIG_SOFTMMU) tcg_insn_unit *label_ptr[2]; -#else - unsigned a_bits, s_bits; #endif + unsigned a_bits, s_bits; TCGReg base = TCG_REG_A0; data_regl = *args++; @@ -1862,10 +1869,20 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); oi = *args++; opc = get_memop(oi); + a_bits = get_alignment_bits(opc); + s_bits = opc & MO_SIZE; + /* + * R6 removes the left/right instructions but requires the + * system to support misaligned memory accesses. + */ #if defined(CONFIG_SOFTMMU) tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0); - tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); + if (use_mips32r6_instructions || a_bits >= s_bits) { + tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); + } else { + tcg_out_qemu_st_unalign(s, data_regl, data_regh, base, opc); + } add_qemu_ldst_label(s, 0, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), data_regl, data_regh, addr_regl, addr_regh, @@ -1882,12 +1899,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) } else { tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); } - a_bits = get_alignment_bits(opc); - s_bits = opc & MO_SIZE; - /* - * R6 removes the left/right instructions but requires the - * system to support misaligned memory accesses. - */ if (use_mips32r6_instructions) { if (a_bits) { tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); From patchwork Wed Aug 18 20:19:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 498985 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp1008368jab; Wed, 18 Aug 2021 13:23:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw9Bmom5ANeOZK1+TyLO1wBT/yTW9YsfegNu2mgWe6AtjAMZGoCW9NNW0fyGgaJvOKML/Lg X-Received: by 2002:a92:cccd:: with SMTP id u13mr7506273ilq.13.1629318234604; Wed, 18 Aug 2021 13:23:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629318234; cv=none; d=google.com; s=arc-20160816; b=Rppn93/ZEhcnR/sjiPmiVQpx2Zk6hRCKw0XVQFZZ2TJEekht2gn1rGcUAwuR/YkuPv 5tTBoQ7WW9wyzU5OOpS0c+BRbO6qW3q7CrENu2mA6YruoQvlZ7hby76lGkfry66+YPY6 tD7E1AfnwaOCGn/mrlPl0OBFg0PVsmTfJLTdaxkNnm0+om1P/ZII+tRSKs82zsbqtCsS y8Ku61gHPdcMN/CxXn2ufCsJS34J67bPd8r9QK83KYOKD20zCNWSs7jVhwZlnO56vr1z rSly+AdkG2mUsDrLKuRFUqqHWrXPUahoXlc5tPke2mKquiMx3+eBKpFyq3d9wq4+wUKP EA2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=wtevaJ7IG8tKFN4eF5alBUKWgZUImY9MLHAChMV4wyA=; b=YDZUI97fvO9CovIPWl/ietJDc6VPhe3snDKakOKcbClgenLVABh9ycTQRU0eo52NvC mKS8v/3flR7tMHJuH2zyq9r00doJiQnQXbsFpd4AmwbgNOFvFEg5Zu7TfQtwRo8C99vg 5E9Y1ph0j1amU+CeD/koq729JL/IAXxVO+E35StMU+Ma7AYbFpdhAO5Vt4nx+ENmLCcL KCiQOd/NAQ0iNmCIj4rljO5pfQaJwna9Or0Is7kBs3wdDW4bhlZdSYIWhchFXFGmlsVu Hc5SJ0GqoO8iSXWkF+7nISR9BWg1Gup1+JH+jz0T6t/In3ZZmGE3lgeVMZV7TBIcP/sI b6pw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hc3AtgXE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Remove tcg_out_ext8s and tcg_out_ext16s as unused. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 76 ++++++++++++++------------------------- 1 file changed, 27 insertions(+), 49 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 3d6a0ba39e..94f1bebdba 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -189,7 +189,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, #endif -static inline bool is_p2m1(tcg_target_long val) +static bool is_p2m1(tcg_target_long val) { return val && ((val + 1) & val) == 0; } @@ -373,8 +373,8 @@ typedef enum { /* * Type reg */ -static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, - TCGReg rd, TCGReg rs, TCGReg rt) +static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, + TCGReg rd, TCGReg rs, TCGReg rt) { int32_t inst; @@ -388,8 +388,8 @@ static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, /* * Type immediate */ -static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, - TCGReg rt, TCGReg rs, TCGArg imm) +static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, + TCGReg rt, TCGReg rs, TCGArg imm) { int32_t inst; @@ -403,8 +403,8 @@ static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, /* * Type bitfield */ -static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, - TCGReg rs, int msb, int lsb) +static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, + TCGReg rs, int msb, int lsb) { int32_t inst; @@ -416,8 +416,8 @@ static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, tcg_out32(s, inst); } -static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, - MIPSInsn oph, TCGReg rt, TCGReg rs, +static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, + MIPSInsn oph, TCGReg rt, TCGReg rs, int msb, int lsb) { if (lsb >= 32) { @@ -434,8 +434,7 @@ static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, /* * Type branch */ -static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, - TCGReg rt, TCGReg rs) +static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs) { tcg_out_opc_imm(s, opc, rt, rs, 0); } @@ -443,8 +442,8 @@ static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, /* * Type sa */ -static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, - TCGReg rd, TCGReg rt, TCGArg sa) +static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, + TCGReg rd, TCGReg rt, TCGArg sa) { int32_t inst; @@ -491,28 +490,27 @@ static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) return true; } -static inline void tcg_out_nop(TCGContext *s) +static void tcg_out_nop(TCGContext *s) { tcg_out32(s, 0); } -static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) +static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) { tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); } -static inline void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) +static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) { tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); } -static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) +static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) { tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); } -static inline bool tcg_out_mov(TCGContext *s, TCGType type, - TCGReg ret, TCGReg arg) +static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { /* Simple reg-reg move, optimising out the 'do nothing' case */ if (ret != arg) { @@ -624,27 +622,7 @@ static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) } } -static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) -{ - if (use_mips32r2_instructions) { - tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg); - } else { - tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); - tcg_out_opc_sa(s, OPC_SRA, ret, ret, 24); - } -} - -static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) -{ - if (use_mips32r2_instructions) { - tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg); - } else { - tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16); - tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); - } -} - -static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) +static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) { if (use_mips32r2_instructions) { tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); @@ -668,8 +646,8 @@ static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, tcg_out_opc_imm(s, opc, data, addr, lo); } -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) { MIPSInsn opc = OPC_LD; if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { @@ -678,8 +656,8 @@ static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, tcg_out_ldst(s, opc, arg, arg1, arg2); } -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, - TCGReg arg1, intptr_t arg2) +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) { MIPSInsn opc = OPC_SD; if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { @@ -688,8 +666,8 @@ static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, tcg_out_ldst(s, opc, arg, arg1, arg2); } -static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, - TCGReg base, intptr_t ofs) +static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, + TCGReg base, intptr_t ofs) { if (val == 0) { tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); @@ -1960,9 +1938,9 @@ static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, } } -static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, - const TCGArg args[TCG_MAX_OP_ARGS], - const int const_args[TCG_MAX_OP_ARGS]) +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg args[TCG_MAX_OP_ARGS], + const int const_args[TCG_MAX_OP_ARGS]) { MIPSInsn i1, i2; TCGArg a0, a1, a2; From patchwork Wed Aug 18 20:19:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 498984 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp1008350jab; Wed, 18 Aug 2021 13:23:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyYPbcaBpM9M1dw5WTFuMffENOPBTcWLjEeu3I9N7UY5MXsm4M1f5rRkvvUKRsruLVOBjnj X-Received: by 2002:a6b:6319:: with SMTP id p25mr8660331iog.100.1629318233517; Wed, 18 Aug 2021 13:23:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629318233; 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[209.51.188.17]) by mx.google.com with ESMTPS id v66si901326iof.105.2021.08.18.13.23.53 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 18 Aug 2021 13:23:53 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Zp2bL720; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47452 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mGS6K-0005fJ-Qv for patch@linaro.org; Wed, 18 Aug 2021 16:23:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40216) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mGS2K-00081W-L4 for qemu-devel@nongnu.org; Wed, 18 Aug 2021 16:19:44 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:39696) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mGS2H-00068t-7p for qemu-devel@nongnu.org; Wed, 18 Aug 2021 16:19:44 -0400 Received: by mail-pf1-x42e.google.com with SMTP id t13so3334639pfl.6 for ; Wed, 18 Aug 2021 13:19:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=+CMPBOKVQeWTwZGrxMiWTzbA3RbAllHepTMsTUswk6M=; b=Zp2bL720Hll6EKYci/jXuMy8QpKRNEFGZinSwnDBhJVvnqNxnGwUwKDgcZ5DwwsVBp ICxX1CPTvpa3YJ64341/iQIHJ1Tm4gIWTFjj7h8mERmuAZrJqj4h6BX35lkixCIH7RDF qDVSH1o1kO3M/M/2rjDX8jQrwP79UHCOWP4GZs9Km8VT7o/0K0c1hW3RXLmuh4DkPd+f bmrU20OZtys6MQwCTV2Hp8CNCIlgobD0A5CvcbSKuyXXFQU3hLEQLZ5rKyP7RvzJMVvr Kh9Xv8709i3US18NzOCZmwKMfZTkvDVg4wen5uw0BqtcXMgUNjYWwIDkOqBOWIbUwyAg uBfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+CMPBOKVQeWTwZGrxMiWTzbA3RbAllHepTMsTUswk6M=; b=pumQw4Am+HEAMQkBGNQwoFIMViQyi/+ZLi0SsHLvvwwm1NuqcEMuUr+ANuF+QKY1IC tup7NwU5CbcVnLHG7VlW4M9Xtxm3oSe35kdV5IS1TqcJfLb8W4ScLIFebHecNbENc/kE WwWFaZVh9T2JhuB+f8XWbf1LjCeTxiKjb8v8uFBm73UZaKduIR/mcpRCHfBatfYPjPKb mGnyVVtan7ub7z/L7eY6J1LTYpf0NktRu3B7ZsCz8TQ9A53BR+X4eMcFNFwLsnUsL1JS M0hXdFu+8TS7LXX3wWVkXqjG/Ogr+BTKj1tRf9QBiAm+hu2OjvIvBO+0uVCqnEh7nnV4 KTYg== X-Gm-Message-State: AOAM530Wm9Our3MvM++LQ1zim5Sphiw7vTkDk59RlpfdDi68uskkG/o3 EEuds6dG3KYdP0PxlwnJTXEuZpcKiF28wQ== X-Received: by 2002:a05:6a00:a0b:b0:3e1:e511:1224 with SMTP id p11-20020a056a000a0b00b003e1e5111224mr10795873pfh.67.1629317978188; Wed, 18 Aug 2021 13:19:38 -0700 (PDT) Received: from localhost.localdomain ([173.197.107.15]) by smtp.gmail.com with ESMTPSA id x13sm619621pjh.30.2021.08.18.13.19.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Aug 2021 13:19:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 04/16] tcg/mips: Move TCG_AREG0 to S8 Date: Wed, 18 Aug 2021 10:19:19 -1000 Message-Id: <20210818201931.393394-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818201931.393394-1-richard.henderson@linaro.org> References: <20210818201931.393394-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" No functional change; just moving the saved reserved regs to the end. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- tcg/mips/tcg-target.h | 2 +- tcg/mips/tcg-target.c.inc | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 3afbb31918..c34cccebd3 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -80,7 +80,7 @@ typedef enum { TCG_REG_RA, TCG_REG_CALL_STACK = TCG_REG_SP, - TCG_AREG0 = TCG_REG_S0, + TCG_AREG0 = TCG_REG_S8, } TCGReg; /* used for function call generation */ diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 94f1bebdba..92bde50704 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2542,7 +2542,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) } static const int tcg_target_callee_save_regs[] = { - TCG_REG_S0, /* used for the global env (TCG_AREG0) */ + TCG_REG_S0, TCG_REG_S1, TCG_REG_S2, TCG_REG_S3, @@ -2550,7 +2550,7 @@ static const int tcg_target_callee_save_regs[] = { TCG_REG_S5, TCG_REG_S6, TCG_REG_S7, - TCG_REG_S8, + TCG_REG_S8, /* used for the global env (TCG_AREG0) */ TCG_REG_RA, /* should be last for ABI compliance */ }; From patchwork Wed Aug 18 20:19:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 498983 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp1006333jab; Wed, 18 Aug 2021 13:21:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxms5BibULiipGthk33lBpueFo44xVT89QgWJR6RRgvNsZKruI5Q5UTyCzBHT0kd6bgoHFN X-Received: by 2002:a67:ed5a:: with SMTP id m26mr9646614vsp.59.1629318065283; Wed, 18 Aug 2021 13:21:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629318065; cv=none; d=google.com; s=arc-20160816; b=sOOmXEgc6PtuIcbc8NTXCh0hfYNQ6WmhvkRjM2d3Thk0TkAAvx+YQOSd62m2ne+lrR IHAsfdE+XE23PD31ShVXcNtWGOFP5rNxcD/3wkk5mMKMijhgsLvnJkiylCemTaSM5DrW FHwTJBZ7CrWKFm+mMjm9BSEDKn3+wthdpeY94MM2sI1SdDyPk+DWOpDIbgsiESMqgByG QDRq4/C2oHrBImXvvGHT+RXVjBjG0kq7C/RKj4TgYvKYKD4iTR5jOd+DTPMdw64NrBng JU2NI0TeEMO8DFfyfaxgf+6Q+pbA6c4Rg0dhSx3/uatYJKoUWtPNNFS6xjAPROOmLQjM iDkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3D/M6PiJA/KHiyIzYScTLEu+qTs2bRAx1trHXsXn6VU=; b=iEYJ43ZEWH3crPki7TbVF1steWECTyxA+Gr6CSAuqSVl9OhI9+iCzHTkAmaKmCNTdy 4iChWfgOUtEBtNkRq3Lw8num1pKYYdVs1HrKw52I62b6DQPiRif3K1idLva+q1jslmsp 9BugLNvj4SOdmXM5E2SW3REbiBYCKmxPlpYLbXSvHrpeGH5LucW6i/RYGfKrk7ps1Err uPjmi8qX2vPJX5AhKwJroLe1sWhAD2H9XNFyT+8DGU/oqrAIzTEjMNWulkjDCogPbSv0 frPjpdRY3awSQN5gaP9ZRPbqdOucyvLIQ3TMS5B23r+qbnEH7+adQJqkmXa87OJtY/hW oteA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SwtvxVvk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s26si549686vsj.321.2021.08.18.13.21.05 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 18 Aug 2021 13:21:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SwtvxVvk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:38866 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mGS3c-0008GJ-KG for patch@linaro.org; Wed, 18 Aug 2021 16:21:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40262) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mGS2M-00084D-46 for qemu-devel@nongnu.org; Wed, 18 Aug 2021 16:19:46 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]:40597) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mGS2H-00069G-8Z for qemu-devel@nongnu.org; Wed, 18 Aug 2021 16:19:45 -0400 Received: by mail-pg1-x52b.google.com with SMTP id y23so3480910pgi.7 for ; Wed, 18 Aug 2021 13:19:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=3D/M6PiJA/KHiyIzYScTLEu+qTs2bRAx1trHXsXn6VU=; b=SwtvxVvktXqEGyjD8CyMzVorAjhJRXwznN3H6xIOGkHXaRRxp1eg2xZ9TF9C8tYOtP qt6oiSWr/q+YvTDGsDrmHDAkuDldY2Ic7+ItPGEbcS9gxeVkIhZl074D23UE05VewMQ9 2xcZGlH10cISVqUp96ottPIeeX3ikLiPORqU1QQrS4Qpr4tnHL9Qr/eqQhYWEk3C3bKm vf1OjB1WQO/mFcewjeBxSkh8R7cCr3jApZOviorisRjpvLkFB7noW5irPsDWvSYpNq9d jFm2WvJJjoH42kXDgKA59Nszh/3xh8yFeZld085QWbzDCBRPZ5L6lY90vCvyfSKh8C4O 53Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3D/M6PiJA/KHiyIzYScTLEu+qTs2bRAx1trHXsXn6VU=; b=dHMVfDydsJcAaWc/ZkCNsqu6hBM0OTt7P10/RstgsehW5/NYmDQ5ZH7VCU2QCY2GbW P8KRZsRUQP0LZ0gJJ1e0Ds3zzWXq7ykU+wLdRcn2Q4J66GEpH/XniJv3oZsh4zfozfbX bu0P3nj0H5zD3tA+bgcLlFd8TQyaSLjDl1hlshYByLOp3CXclylPSCeBIdQ2j0tHH+59 AbF/Yhyoj/GhCO9jpwOUzNqZazMa4y0rin5Jbcvq/g6CO4k+g4QvnJUOo6lWte/50C4B pJXVGeah41YsiJ2M2IV6qdpJHpvp3SlBLgchLmMPOhkJqU+5K5UmRaAacIP3GGaxWfUe Knlw== X-Gm-Message-State: AOAM533rsVTx5BCuB5+JD2odTVwkwi584t6PcxQhwR/UEGf5SjZkPkbZ EjM7xrV+UJVSFDRZKJ3pic5EHBzg62DRPg== X-Received: by 2002:a65:428b:: with SMTP id j11mr10774429pgp.301.1629317979135; Wed, 18 Aug 2021 13:19:39 -0700 (PDT) Received: from localhost.localdomain ([173.197.107.15]) by smtp.gmail.com with ESMTPSA id x13sm619621pjh.30.2021.08.18.13.19.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Aug 2021 13:19:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 05/16] tcg/mips: Move TCG_GUEST_BASE_REG to S7 Date: Wed, 18 Aug 2021 10:19:20 -1000 Message-Id: <20210818201931.393394-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818201931.393394-1-richard.henderson@linaro.org> References: <20210818201931.393394-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" No functional change; just moving the saved reserved regs to the end. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 92bde50704..b3a2cc88ab 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -86,7 +86,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { #define TCG_TMP3 TCG_REG_T7 #ifndef CONFIG_SOFTMMU -#define TCG_GUEST_BASE_REG TCG_REG_S1 +#define TCG_GUEST_BASE_REG TCG_REG_S7 #endif /* check if we really need so many registers :P */ From patchwork Wed Aug 18 20:19:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 498993 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp1014232jab; Wed, 18 Aug 2021 13:32:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwK+4Wc1oAEOn2f/HE1Dh7hhx6vsXT+p0IYd+29hw5EHUjOImZwR/KFfyLxvfi32mskZFw7 X-Received: by 2002:ab0:3303:: with SMTP id r3mr8714711uao.17.1629318736300; Wed, 18 Aug 2021 13:32:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629318736; cv=none; d=google.com; s=arc-20160816; b=kb2uwCOGwo6+I18UzkyEXDAfIFFiw5TI00+JcjZPgqYs/X1U4x98RMda2UgGYI31w/ Y5fwzz9LtkirVSIkP0B/8ztcAnv+XiasjX1bYLawmCuldDJRwQbUAvh3H4fJqv4l1Rb4 m1nbMFRPcBfj8poTLZ8hLcIg8rK5tKz4L1PJ2uOtYRqSlG8b6dp5T/iWSaoqbO2j83Vf By5UcmDfyT0UjG32JSH8oWg8ltK7LHVHQwMktL00M3UpQgy2vKB6G74lHDWViq0e8O1Y R3uioVjEUstpiYLqyZUFDTEgZw/ILtAWDfzWLIk64rLpf8nA6sAGKLfVba/lxgAjY7oH xgrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jNjyfYROdoiW+oB5URi9KU06Tz8MB4l7ljtYIqD7XFQ=; b=HxSrbPJrk+G9mazYmLPzOAigRmEXZAcA4bIaeKGStB4M5XfTiswJWcY04MHr6G64XK d1cHEjPhup9l61Fru+aycS/Vowoo+ev8lfIQkT4VGSKTqrTJlNt5DageSg2/eq4AaVWa jrn1NiUJqwXhFf6UYsobC8OSKGTekfGhA0306UboX0WsEyPOQMngnFvY8WFHyBB3JR20 gTL29fQgdylKBFF69RKeKTVczn572A24y6ulnBpC2El9Cno4CInjuNwQpsTjMUcsLuFh hqchOZA1GPXvHqR91Gp4l0ncnchzhyQLv+BjrEWexo/fF04NEcgUArVaK3PAVmV8PZMC RVag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z9SIfqyD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b11si521194vsj.51.2021.08.18.13.32.16 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 18 Aug 2021 13:32:16 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z9SIfqyD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46186 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mGSER-0006xl-KD for patch@linaro.org; Wed, 18 Aug 2021 16:32:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40220) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mGS2K-00081z-Pp for qemu-devel@nongnu.org; Wed, 18 Aug 2021 16:19:44 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:40602) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mGS2H-0006AR-FP for qemu-devel@nongnu.org; Wed, 18 Aug 2021 16:19:44 -0400 Received: by mail-pg1-x530.google.com with SMTP id y23so3480985pgi.7 for ; Wed, 18 Aug 2021 13:19:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=jNjyfYROdoiW+oB5URi9KU06Tz8MB4l7ljtYIqD7XFQ=; b=Z9SIfqyDsZYO2wu4hTqa5jTIW9YlfFmN9k5KGHHj48mrfTZD4XW5plU3ubAgwytkdG W05D4/qe+4j6F+PzwBEcbevbEHapr5YiG381r2rKpn5MuOaGG0MBLAp8V2iB9x0ErXUY fy5yxyH0pf+zFqeR0ctbqDmbrPmQ+xggiPiiVpaVfBfSglxxNDO92HoaqpT9qTk+ojn6 KHsixE6qVvDzlQm0JXllPH0RWOr5sL7GC2hHElhWPOU2XCcJ1cjmxUCRJlZKBYl2UzBP xP9X7EUFHuGcGs/6SaI7LLbRDgUEKOx3pQR01oULXPo38IWwgqzVna1ox3hNEU18/d++ 1sfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jNjyfYROdoiW+oB5URi9KU06Tz8MB4l7ljtYIqD7XFQ=; b=ImI2M8wHs/BtMN6C6PKTwLADv8Lot6UnL4iP3nuVwuROg3LjpuirMzoN6qdkoT5DTU 6S+gzxwV0+S0q9PWAkEjl/KzErL36oNDExDnTN9+m5h9DpQrVPmnrgY94J4yUl1iZj5A kFNwzK5JKxchBdCtPdF3D0buo8Q+kWJ/MRUKwWtzSS263RxJ41ttEHmlfyN1hQ4xAaE9 iY/t8YenKv0uiKMcpbz3Hnya2zrkDkP8UULAyNBfLYORN127c5bRmoyH/Ys3EFmQM0tB w00ieuTO0l7yAl9VL6N2bbTzMQidS7Bg7QbI7X4oT4PHnK5z8AoKVaT/XsMa2lIjw/LX zF1g== X-Gm-Message-State: AOAM533R/4n+Si1jln8vGOZHGbVgj60QR/2BiqKdAue7L1d+PtRzMnzG zaygSUWHhp+LcGIDxQ+a+wUF5Qj92bIzdA== X-Received: by 2002:a63:fe41:: with SMTP id x1mr10402085pgj.272.1629317980205; Wed, 18 Aug 2021 13:19:40 -0700 (PDT) Received: from localhost.localdomain ([173.197.107.15]) by smtp.gmail.com with ESMTPSA id x13sm619621pjh.30.2021.08.18.13.19.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Aug 2021 13:19:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 06/16] tcg/mips: Unify TCG_GUEST_BASE_REG tests Date: Wed, 18 Aug 2021 10:19:21 -1000 Message-Id: <20210818201931.393394-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818201931.393394-1-richard.henderson@linaro.org> References: <20210818201931.393394-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In tcg_out_qemu_ld/st, we already check for guest_base matching int16_t. Mirror that when setting up TCG_GUEST_BASE_REG in the prologue. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index b3a2cc88ab..4019c22f3c 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2671,7 +2671,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) } #ifndef CONFIG_SOFTMMU - if (guest_base) { + if (guest_base != (int16_t)guest_base) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } From patchwork Wed Aug 18 20:19:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 498986 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp1010274jab; Wed, 18 Aug 2021 13:26:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJznFWmPG5n7DOkvkLywhZSUtEkd/Gzdespu98hm+j0YE1UGPObqX9yclIa/DiC/3thcqPad X-Received: by 2002:a05:6638:38a:: with SMTP id y10mr9748467jap.110.1629318406583; Wed, 18 Aug 2021 13:26:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629318406; cv=none; d=google.com; s=arc-20160816; b=lXof8/oUAwdVZ6vWRHlLbDC5RgfBtRZXg0nqwNotjpR2WguSFzuviS3bva+/NqfxFA r0JWEgPaT1CEkKlHBRD1ka1cfZMvG+5tOOxPqtThga3LYO0wzJ3A5JxiH+x81XcZyxHf DrGdbGrzUk4vS2ro5atwb1FushR+uZS4jFHymMc2B0t1FWGnX6hA8zTdH2+mRdjKZ6Vs Rpv1BtA5WT7hAo8aR38ccSHPnBycXoQOsExnT4M7Xa7+bo/ZZ4OQt6u+iTMaSUdN7Nho 3CF3OC+TsDebteHkY1xVeqsONuNOqmu3qh6dTBX162dVTV9iiCGbeqRDmH57Y/HoO9gx LGrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ZAJvKrninoDXi86yNb6pa5/NGflGIWCBcmCsKqBF7oE=; b=QyO2PqLpmLXlZxu+ZD0pki0upHSE95ZbPFd0H8bm9ZmjvdEf3XyohNjF3UyBlCBIKe 8eczF9H5l0pTP06KAtrRWPbjM2GU6mPAbetOfGC1uBLIQcG/klb690G+Lj1VUY7GuyiD Ebz7Dtjf81m2nyqw7wa/pyLV35Vw8S9Q3eW+bvSRsTndUCjoNxH+FUgtO2EPczLqBQv7 hUf6wzDaMVJw2WBWbL/KLvLr3IdRNfhcp/fp2qIMxsMrrYx+2QvhlAveuLIHBuy3x/Vx 7gyqLFPp1lVLRSTEdfxaP+PzMHj9LLS4D0YaiCvzU18PUPYMp+CQ0zpxVey8qt/Qn6G2 mqMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Xym+ooOP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p8si1030495ilh.18.2021.08.18.13.26.46 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 18 Aug 2021 13:26:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Xym+ooOP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55948 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mGS97-0002to-Ut for patch@linaro.org; Wed, 18 Aug 2021 16:26:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40258) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mGS2M-00083y-0u for qemu-devel@nongnu.org; Wed, 18 Aug 2021 16:19:46 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:36544) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mGS2I-0006BK-Hl for qemu-devel@nongnu.org; Wed, 18 Aug 2021 16:19:45 -0400 Received: by mail-pf1-x430.google.com with SMTP id m26so3335588pff.3 for ; Wed, 18 Aug 2021 13:19:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ZAJvKrninoDXi86yNb6pa5/NGflGIWCBcmCsKqBF7oE=; b=Xym+ooOPjszCLlRySpY5JoUHTx/B5Kuugcev6d//nnw6wsowaOzDz1wk9LMdotHdAE v0yEqziGlidu8gVQH8bLl5SoqLjgV1H0fDMKRPGy7sXWsHCQ6QP0eBq+9BrWh64QVTdk tSMld+MZLrAxTxForOe5gbk6tj+shbrABqt9FzK3mxOuPEJC4FqVrtP5USV9pYtT0MRe Ur9ejROnRIsqPk89WlG6oNRQqtEQk9HJ3ieQJCuHJQgA0Nw9NJmpgJlP3QlBFx6Tu2ni l1+8PWDw/cCVUXxUaOqgryBj2VffFSI03Q8i0/yvQj4snVMbfdr3Nhsa+xsZrVzLOeNP YkKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZAJvKrninoDXi86yNb6pa5/NGflGIWCBcmCsKqBF7oE=; b=XVCvh9q/ktyh1yGJjUQjNXRxNPer7kz6Un/4WXmJxZu/BipWqLH+qYepdVa5nLq639 ZPffWAVvWQW1C8fHC+MMAMKaHYGzJymOyCGDl1pEiB3+n6WWu22/uo295ybqCCprBfmY s4DZ2fjosH5AX9jsg8reSqF528nFG/txxWd7SGQahFGyhRszPos53L3yGnvgxJNVlrHr o1UTNl+60wVRbAgcIqIlY80JzSIeRLDXuHche3Rwi8cwxppKn8/Lnp6kYmUPTSeLRO7z xUbY+silL8FQA0DkljIvkJQZ0IPvqxGUnT41L4xnbZb7ZrGsb83D3Z72AgCck4IwMcKT uRVw== X-Gm-Message-State: AOAM533ascIFHkJi4qSOgXZ2DiQUCM8QbCnZ7TwtDRIw0h0LIRf0+kX1 1Kg4jF1FdzJlYPsPBx+e0HM4SAYhp2yPNQ== X-Received: by 2002:a63:88c7:: with SMTP id l190mr10485873pgd.438.1629317981121; Wed, 18 Aug 2021 13:19:41 -0700 (PDT) Received: from localhost.localdomain ([173.197.107.15]) by smtp.gmail.com with ESMTPSA id x13sm619621pjh.30.2021.08.18.13.19.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Aug 2021 13:19:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 07/16] tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr Date: Wed, 18 Aug 2021 10:19:22 -1000 Message-Id: <20210818201931.393394-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818201931.393394-1-richard.henderson@linaro.org> References: <20210818201931.393394-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Weaning off of unique alignment requirements, so allow JAL to not reach the target. TCG_TMP1 is always available for use as a scratch because it is clobbered by the subroutine being called. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 4019c22f3c..c65c4ee1f8 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -585,8 +585,10 @@ static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags) static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) { - bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub); - tcg_debug_assert(ok); + if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub); + tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); + } } static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags) From patchwork Wed Aug 18 20:19:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 498988 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp1011693jab; Wed, 18 Aug 2021 13:28:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJySaGpTO3GAvwM84adUBkhHTWpPDwVJRCTlIisnl0kIQvkXTjhuF1A9kPyK+Ds9V0kBDqZE X-Received: by 2002:a05:6e02:1546:: with SMTP id j6mr7152384ilu.154.1629318529202; Wed, 18 Aug 2021 13:28:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629318529; cv=none; d=google.com; s=arc-20160816; b=ZC6bhj9ahlqE8+1OE4slL6E5uyp9nKHat+cbszSLwb3YFC9Zu0XEo47yf1hPRWGPsz 4JzoV/Hsl1fWmOquA25GRm/93RVdP0N3KNqlpFburzyg6I1IUnrTv26djt8aaeyRw9Jq eTkNBS2ZJfZPVr5GUJ+MBZ/iek8CRiun803BSTCb7iNS/G1IEK6KVUA30HGBvc457Ro8 SoSP1R79C7dciiK/FjsJQa3Si1efLrkZqwZgnxC3COqc3fakTb2E33QjzZVAUVQCx/Xi 0WMZ9c1Z//c+ZRUxWj/UgnLCNllT6WTBRUq2hfFgJt/xM8qhr7CfHNvuvAZ40Dlj5SyT ap4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xt/P1E35n4DoR7F0qpGvXqATfrrFWhQKn4h1puAkVi4=; b=FoEuN43tS/rql5gjO0UcIOBdnqWK1TZCpmZVx39Ff1ykJeYAGMJ3fyM6fKbUXBdInO MhfBN6lg+yazO+erJc2RnWf/GKk91WNk1GI4gbyssak13HMOGT9ctY7sKoxOAQSrOAWR oWlmJPWrdnxP+GA2lFjkz1VeyAIFqyXGoVF5aThrKeg57O+fJn1NQfTAslLUeQhnq7bE KsXp2ueq2Q3HOjshCyMhtoYEwM9X6XwrYmWWJJl6sJvOtzhoo5sqMiS1HYpImxbLOba/ QIHz+k6Js2K8/BSDYJFXh1O6JOC+8Rcm285Auj1sM8eu5h7dBRq4hfD9WgAUr5WalmQq wOVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TSZ6T+I6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e17si799127iot.103.2021.08.18.13.28.49 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 18 Aug 2021 13:28:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TSZ6T+I6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36422 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mGSB6-0000M5-K1 for patch@linaro.org; Wed, 18 Aug 2021 16:28:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40266) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mGS2M-00084o-94 for qemu-devel@nongnu.org; Wed, 18 Aug 2021 16:19:46 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:42951) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mGS2J-0006CP-BD for qemu-devel@nongnu.org; Wed, 18 Aug 2021 16:19:46 -0400 Received: by mail-pf1-x434.google.com with SMTP id 18so3336699pfh.9 for ; Wed, 18 Aug 2021 13:19:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=xt/P1E35n4DoR7F0qpGvXqATfrrFWhQKn4h1puAkVi4=; b=TSZ6T+I6Fl9kPGjkAKvDxNK0uP7j5dR81C22y7LXAt0RPAm/iRkK38hJT9nN6apw3l ocrirZtthdWmRwDHLJYrEC9XTWuN0D7a9/Y3Sof1LpM+whOZL32X3vMU0hxtvoi4oB6G zNZKxGmMry2+HEpQDHZZSAyYH2Bx9DxrMDcWCb4ZbP0BXA7z1q2XAtlQI+MFYdOGwIld ZVsrq5j7WDZUWN2IxHaw1ON4ET+gXHH/RipY4Idkn+YRI4TSdnf57Jzx5qyNanAPMDWS 2Gpw+GO0TxQVUDEzzStoSrC2siDVskNe2PnPJiS0EWtkbOtMU3vdw7/BMyShQF1YsT/G 4KFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xt/P1E35n4DoR7F0qpGvXqATfrrFWhQKn4h1puAkVi4=; b=WRgajeqAHpcDOjcbd/aCHGuiQVwf+zjIMMSE+V2K5N8v68/1NJzoCBwkytkrocHveV kLSVS6xVAYmnOaH7byGXgLDOSFNuyPGrmN+/fWEeAg4bkyRyE/6qreKO2FQyTfbjeeFW snCicgmG2rpiw2hXbWmEBibqlRxlPXqCKYWDVN8fGY1GUN1utyHk2xFTxn077VqE+feD EMTi5xVW/JDj6OeRUEzlTtu+646OL7eCQIcfwDBKu/Qjlt0Dd2mpCfE20UTlILFlHS9o z7VFxeH9CYawWdEyolB7MsLCvASSpPf8aOsWiKc4eoD4l3oxH+LWO2vb+cePLruzLa9Q qQrw== X-Gm-Message-State: AOAM533c6e9qnu4No50Yz1NeALel1TwOBnEzH5RaxonUdRX+iHdSkim6 vOisb4zGPVD+XrzjDpOzfGLAzmnCFPgmpA== X-Received: by 2002:a65:51c7:: with SMTP id i7mr10395763pgq.300.1629317982062; Wed, 18 Aug 2021 13:19:42 -0700 (PDT) Received: from localhost.localdomain ([173.197.107.15]) by smtp.gmail.com with ESMTPSA id x13sm619621pjh.30.2021.08.18.13.19.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Aug 2021 13:19:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 08/16] tcg/mips: Unset TCG_TARGET_HAS_direct_jump Date: Wed, 18 Aug 2021 10:19:23 -1000 Message-Id: <20210818201931.393394-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818201931.393394-1-richard.henderson@linaro.org> References: <20210818201931.393394-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Only use indirect jumps. Finish weaning away from the unique alignment requirements for code_gen_buffer. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 12 +++++------- tcg/mips/tcg-target.c.inc | 23 +++++------------------ 2 files changed, 10 insertions(+), 25 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index c34cccebd3..28c42e23e1 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -39,11 +39,7 @@ #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 #define TCG_TARGET_NB_REGS 32 -/* - * We have a 256MB branch region, but leave room to make sure the - * main executable is also within that region. - */ -#define MAX_CODE_GEN_BUFFER_SIZE (128 * MiB) +#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) typedef enum { TCG_REG_ZERO = 0, @@ -136,7 +132,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_muluh_i32 1 #define TCG_TARGET_HAS_mulsh_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1 -#define TCG_TARGET_HAS_direct_jump 1 +#define TCG_TARGET_HAS_direct_jump 0 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_add2_i32 0 @@ -207,7 +203,9 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); +/* not defined -- call should be eliminated at compile time */ +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t) + QEMU_ERROR("code path is reachable"); #define TCG_TARGET_NEED_LDST_LABELS diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index c65c4ee1f8..1c5c0854c7 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1977,17 +1977,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; case INDEX_op_goto_tb: - if (s->tb_jmp_insn_offset) { - /* direct jump method */ - s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); - /* Avoid clobbering the address during retranslation. */ - tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff)); - } else { - /* indirect jump method */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, - (uintptr_t)(s->tb_jmp_target_addr + a0)); - tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); - } + /* indirect jump method */ + tcg_debug_assert(s->tb_jmp_insn_offset == 0); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, + (uintptr_t)(s->tb_jmp_target_addr + a0)); + tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); tcg_out_nop(s); set_jmp_reset_offset(s, a0); break; @@ -2861,13 +2855,6 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ } -void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, - uintptr_t jmp_rw, uintptr_t addr) -{ - qatomic_set((uint32_t *)jmp_rw, deposit32(OPC_J, 0, 26, addr >> 2)); - flush_idcache_range(jmp_rx, jmp_rw, 4); -} - typedef struct { DebugFrameHeader h; uint8_t fde_def_cfa[4]; From patchwork Wed Aug 18 20:19:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 498997 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp1017585jab; Wed, 18 Aug 2021 13:37:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwJNOCsq3csZTmVPbV5pD/Bhlspfb8NT+H2LyxfYFzJzhtfV4S89u1reUHwHCJQ+J8Z0Lqi X-Received: by 2002:a5d:928c:: with SMTP id s12mr8454081iom.151.1629319033971; Wed, 18 Aug 2021 13:37:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629319033; cv=none; d=google.com; s=arc-20160816; b=ObDZOZXyvPXf48pqTrDh8pVWZy6reEhZLYpW/JQIx0HzMI6+iUdcjqXkhQVyk2uy7q 1CmxLP50aXVdzTb/Krf2u+QFk8y4eNMUQ3ypG3zBaLj6Vcr3crEgkUongbIZ5cRpxXYE 5BMuBj+tOSa+r8WzhFSTYqEsXxn1M2s73M8fDhXl6Rkize0lwV/azyO+DH1xPUCDAWMz f99tWhclQi4/2WAK9tntcow/qa5kVf86fjGkPA8ECr562P6aGemY86BsqWhAfjBc17Ik WnS/AYPhiFi8N/etzzFyUTZrx2klWF2oCxXlQ1kpWKabmI8BzTVnYKFuMvzJnn3Nor/V 7X+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dLKp0mDnjjRjPauDQA0yKsYIxkun+14IJ8e0NroxfP0=; b=MkRGtbkPHNGUMhTrZR2E8scUf2ueBmaaw9SjExe16M88Z2qmj6kP4G36ifLGrElAC/ GbP/j0GVC3r8+/YIrHAHgjFAqZhQ4fxCF9F9Zca4xNVQiGqA0rB5yVMJs3QNhk/TKEdJ ukwIibL6GPksC4KM5ZE+f5jZYopFQyfUivOf0biwSO1xhE3f6bdTbq8ry4KleuLj/igm hZtnxR8OXkr8pfoxHHwGZ9PfuFCQq8bFIUcKQfD/JWteIeSz4JhvNQvgM0KdCxvr5Dn/ Nz+i7H5v62QsyaLMka3gO76o5mz7PmohMUShuBwgqKkC0VmF0PsCMoZpaj0XFhYTHYLU WS8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="GjB/NbVw"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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DEFAULT_CODE_GEN_BUFFER_SIZE_1 : MAX_CODE_GEN_BUFFER_SIZE) -#ifdef __mips__ -/* - * In order to use J and JAL within the code_gen_buffer, we require - * that the buffer not cross a 256MB boundary. - */ -static inline bool cross_256mb(void *addr, size_t size) -{ - return ((uintptr_t)addr ^ ((uintptr_t)addr + size)) & ~0x0ffffffful; -} - -/* - * We weren't able to allocate a buffer without crossing that boundary, - * so make do with the larger portion of the buffer that doesn't cross. - * Returns the new base and size of the buffer in *obuf and *osize. - */ -static inline void split_cross_256mb(void **obuf, size_t *osize, - void *buf1, size_t size1) -{ - void *buf2 = (void *)(((uintptr_t)buf1 + size1) & ~0x0ffffffful); - size_t size2 = buf1 + size1 - buf2; - - size1 = buf2 - buf1; - if (size1 < size2) { - size1 = size2; - buf1 = buf2; - } - - *obuf = buf1; - *osize = size1; -} -#endif - #ifdef USE_STATIC_CODE_GEN_BUFFER static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] __attribute__((aligned(CODE_GEN_ALIGN))); @@ -526,12 +494,6 @@ static int alloc_code_gen_buffer(size_t tb_size, int splitwx, Error **errp) size = QEMU_ALIGN_DOWN(tb_size, qemu_real_host_page_size); } -#ifdef __mips__ - if (cross_256mb(buf, size)) { - split_cross_256mb(&buf, &size, buf, size); - } -#endif - region.start_aligned = buf; region.total_size = size; @@ -573,39 +535,6 @@ static int alloc_code_gen_buffer_anon(size_t size, int prot, return -1; } -#ifdef __mips__ - if (cross_256mb(buf, size)) { - /* - * Try again, with the original still mapped, to avoid re-acquiring - * the same 256mb crossing. - */ - size_t size2; - void *buf2 = mmap(NULL, size, prot, flags, -1, 0); - switch ((int)(buf2 != MAP_FAILED)) { - case 1: - if (!cross_256mb(buf2, size)) { - /* Success! Use the new buffer. */ - munmap(buf, size); - break; - } - /* Failure. Work with what we had. */ - munmap(buf2, size); - /* fallthru */ - default: - /* Split the original buffer. Free the smaller half. */ - split_cross_256mb(&buf2, &size2, buf, size); - if (buf == buf2) { - munmap(buf + size2, size - size2); - } else { - munmap(buf, size - size2); - } - size = size2; - break; - } - buf = buf2; - } -#endif - region.start_aligned = buf; region.total_size = size; return prot; @@ -620,35 +549,15 @@ static bool alloc_code_gen_buffer_splitwx_memfd(size_t size, Error **errp) void *buf_rw = NULL, *buf_rx = MAP_FAILED; int fd = -1; -#ifdef __mips__ - /* Find space for the RX mapping, vs the 256MiB regions. */ - if (alloc_code_gen_buffer_anon(size, PROT_NONE, - MAP_PRIVATE | MAP_ANONYMOUS | - MAP_NORESERVE, errp) < 0) { - return false; - } - /* The size of the mapping may have been adjusted. */ - buf_rx = region.start_aligned; - size = region.total_size; -#endif - buf_rw = qemu_memfd_alloc("tcg-jit", size, 0, &fd, errp); if (buf_rw == NULL) { goto fail; } -#ifdef __mips__ - void *tmp = mmap(buf_rx, size, PROT_READ | PROT_EXEC, - MAP_SHARED | MAP_FIXED, fd, 0); - if (tmp != buf_rx) { - goto fail_rx; - } -#else buf_rx = mmap(NULL, size, PROT_READ | PROT_EXEC, MAP_SHARED, fd, 0); if (buf_rx == MAP_FAILED) { goto fail_rx; } -#endif close(fd); region.start_aligned = buf_rw; From patchwork Wed Aug 18 20:19:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 498994 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp1015819jab; Wed, 18 Aug 2021 13:34:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz/OYbkcsDGQGO6CcTYOXHXXPlXDX5IYQyoZ7V0w4mbBC3gg6W0yLSL9Ax3gsv7D2Z+2N+v X-Received: by 2002:a05:620a:6cd:: with SMTP id 13mr168767qky.10.1629318870365; Wed, 18 Aug 2021 13:34:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629318870; cv=none; d=google.com; s=arc-20160816; b=Lely+xBQUubWT5QFSU1Uzv6jCwyUGDTDnkaCoRINCzKYxB6XVGvCjpPVm5Iks6RSvZ zKBRaVmQ/QmLTftlblHOCjqay2Cc2V7RhzrrTgR836tQ+wsOiota4jQQEWlNSMmW2AQC JsvWUcQ9mo1h11nqMyQj0yR0TXNLgPviRVIGNFguzNmtE9YNJ9UGb9wppRbcf1sSgDk3 Z1znfTxFI+DeIrQZ6HSNlwSdZXLgnPYmAxJt0C8ZmA1bODyXFkJs5H/q7bRTwRGMyDBz gPBYNiBUE0JJkZItIJ6aqxbcegw0ngdA1OHcyUbVKkmZ147sPKB3yAgEradjGmT9Mplj OxKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vy83n381f/P0a9RBv7Zua8KHFnM0TgwxLmEkGAu93xY=; b=EHxvLStJ1JqSETEU7vQjxAuNjKzjwwUfoOJOtalP4M91f/3avkKYs9c6/lwO+6SqNk NSZvB3Pvx7fxL22/LunuUV7lBn+xnKH4m5ZHL/bbS9wAUh+4znuDc9PUa+Bi9mOGlQ3G UbSXdsRP+cyatzcuhW5ElHcoK5acwUbhc4YusXekwnUI/i6eioRaPRnqiYVWcvnNhs/+ Hi8I2skAi/SZHkX3OagK7l808pHlGFOlyiVPcVDEH5Uqjp/V2zaHgx/nz2yG+7G/I9xQ qYVX/5LG86FLPKdJcdUhZQk5OTKvPGH5nQZTFcn2gs2jCx+E21x2t9okpC1TVXGzHL6y oGWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="qYYB/tgu"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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The code for exit_tb, for instance, where we load a (tagged) pointer to the current TB, goes from 0x400aa9725c: li v0,64 0x400aa97260: dsll v0,v0,0x10 0x400aa97264: ori v0,v0,0xaa9 0x400aa97268: dsll v0,v0,0x10 0x400aa9726c: j 0x400aa9703c 0x400aa97270: ori v0,v0,0x7083 to 0x400aa97240: j 0x400aa97040 0x400aa97244: daddiu v0,s6,-189 Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 73 ++++++++++++++++++++++++++++++++------- 1 file changed, 61 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 1c5c0854c7..333b9572d0 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -88,6 +88,11 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { #ifndef CONFIG_SOFTMMU #define TCG_GUEST_BASE_REG TCG_REG_S7 #endif +#if TCG_TARGET_REG_BITS == 64 +#define TCG_REG_TB TCG_REG_S6 +#else +#define TCG_REG_TB (qemu_build_not_reached(), TCG_REG_ZERO) +#endif /* check if we really need so many registers :P */ static const int tcg_target_reg_alloc_order[] = { @@ -1961,34 +1966,72 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, switch (opc) { case INDEX_op_exit_tb: { - TCGReg b0 = TCG_REG_ZERO; + TCGReg base = TCG_REG_ZERO; + int16_t lo = 0; - a0 = (intptr_t)a0; - if (a0 & ~0xffff) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff); - b0 = TCG_REG_V0; + if (a0) { + intptr_t ofs; + if (TCG_TARGET_REG_BITS == 64) { + ofs = tcg_tbrel_diff(s, (void *)a0); + lo = ofs; + if (ofs == lo) { + base = TCG_REG_TB; + } else { + base = TCG_REG_V0; + tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); + tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB); + } + } else { + ofs = a0; + lo = ofs; + base = TCG_REG_V0; + tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); + } } if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr); tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); } - tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff); + tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_V0, base, lo); } break; case INDEX_op_goto_tb: /* indirect jump method */ tcg_debug_assert(s->tb_jmp_insn_offset == 0); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, - (uintptr_t)(s->tb_jmp_target_addr + a0)); - tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); - tcg_out_nop(s); - set_jmp_reset_offset(s, a0); + { + TCGReg base, dest; + intptr_t ofs; + + if (TCG_TARGET_REG_BITS == 64) { + dest = base = TCG_REG_TB; + ofs = tcg_tbrel_diff(s, s->tb_jmp_target_addr + a0); + } else { + dest = TCG_TMP0; + base = TCG_REG_ZERO; + ofs = (intptr_t)(s->tb_jmp_target_addr + a0); + } + tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs); + tcg_out_opc_reg(s, OPC_JR, 0, dest, 0); + /* delay slot */ + tcg_out_nop(s); + + set_jmp_reset_offset(s, args[0]); + if (TCG_TARGET_REG_BITS == 64) { + /* For the unlinked case, need to reset TCG_REG_TB. */ + tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB, + -tcg_current_code_size(s)); + } + } break; case INDEX_op_goto_ptr: /* jmp to the given host address (could be epilogue) */ tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); - tcg_out_nop(s); + if (TCG_TARGET_REG_BITS == 64) { + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); + } else { + tcg_out_nop(s); + } break; case INDEX_op_br: tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, @@ -2672,6 +2715,9 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } #endif + if (TCG_TARGET_REG_BITS == 64) { + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); + } /* Call generated code */ tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); @@ -2853,6 +2899,9 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ + if (TCG_TARGET_REG_BITS == 64) { + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */ + } } typedef struct { From patchwork Wed Aug 18 20:19:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 498995 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp1016214jab; Wed, 18 Aug 2021 13:35:09 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxC5gd8sVBVCTuiOhVxwWU4guFEZNfMiP/OqQWJnujwRmEx3/XjQ6rNOw0CAVXThJis/DH3 X-Received: by 2002:a67:ed09:: with SMTP id l9mr9315738vsp.53.1629318909043; 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Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 333b9572d0..b32edd5a7a 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -524,20 +524,34 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) return true; } +static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) +{ + if (arg == (int16_t)arg) { + tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); + return true; + } + if (arg == (uint16_t)arg) { + tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); + return true; + } + if (arg == (int32_t)arg && (arg & 0xffff) == 0) { + tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); + return true; + } + return false; +} + static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg) { if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { arg = (int32_t)arg; } - if (arg == (int16_t)arg) { - tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); - return; - } - if (arg == (uint16_t)arg) { - tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); + + if (tcg_out_movi_one(s, ret, arg)) { return; } + if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); } else { From patchwork Wed Aug 18 20:19:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 498987 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp1010313jab; Wed, 18 Aug 2021 13:26:49 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxjsn32h4Al7x87Z0rHhlIH494G3PJyonX1MnA+LIheTTBCYSUjI1bHfXGOVrBO4V3LErRl X-Received: by 2002:a6b:8d08:: with SMTP id p8mr8479265iod.150.1629318409445; Wed, 18 Aug 2021 13:26:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629318409; cv=none; d=google.com; s=arc-20160816; b=Q4bmb42ovbGdi3qpZrHBVB0BnQxgdCksGx41PhfOmExmgBN0aHAFBXy6vv5vVi/gq3 BBa+5C7Rwk30me0QXpASBCmOaC1LzEXZlkGDG/GDmvPrHK2mh+DTIr0SvUop+jBpQxhQ OCTyO/viQ+STPItXOEBw53p0QJkEUdVLWSIABJaLkqYxeZSvkdeEpWW3BGUHrAg0h/lI j7WSm18X4tPLSL6jH3ts6rlM2yN1t+/mMTY++1qrfG0iJ/kjg56eeIsl3LpC9hnGmQcM rm9xIIWNcMrrsiADYmuUK0iEqe7OjE06C/r49DAopWOjy4FowdkfaqxGL9TRNoRENd5k hlyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WMobBd21hxhBtnfxmCHTdmsDMrlUXdir7Qqr9MLBdJc=; b=wc24ZluxKR8I6QuyyHRcyRfuVn6z7h2k4DRt3VgGrHjxuhpoiCOzZe5UETjjbQaDd2 b54W0FAMpUIFki86RRUqyDPntOkPXKYqhqWsYPLrwDQGwP/FEFm3JvBhp0+QHjSG+HeF XJ2OplfH6PIhX2tC0d7RNHNf8C1sgkmnm/EnqtAOG/9gfLXrydSxCjKRYFsC6dLDuSQq Gm8H3vcDQEiASFg8Om996F+p2n05r70wl0njfqGBvJD3ifE9r8ApD21kNWOBwRIE92sy G45v8KTily2R+tRn6jjJCjWsVpx8cPtKK6/002/pDtdAFVT7qcQps6Z+yA24ucgU3uDY ZURQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FzLfKJcX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 35 ++++++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 11 deletions(-) -- 2.25.1 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index b32edd5a7a..d351d53a7b 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -541,6 +541,22 @@ static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) return false; } +static bool tcg_out_movi_two(TCGContext *s, TCGReg ret, tcg_target_long arg) +{ + /* + * All signed 32-bit constants are loadable with two immediates, + * and everything else requires more work. + */ + if (arg == (int32_t)arg) { + if (!tcg_out_movi_one(s, ret, arg)) { + tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); + tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); + } + return true; + } + return false; +} + static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg) { @@ -548,21 +564,18 @@ static void tcg_out_movi(TCGContext *s, TCGType type, arg = (int32_t)arg; } - if (tcg_out_movi_one(s, ret, arg)) { + /* Load all 32-bit constants. */ + if (tcg_out_movi_two(s, ret, arg)) { return; } - if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { - tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); + tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1); + if (arg & 0xffff0000ull) { + tcg_out_dsll(s, ret, ret, 16); + tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16); + tcg_out_dsll(s, ret, ret, 16); } else { - tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1); - if (arg & 0xffff0000ull) { - tcg_out_dsll(s, ret, ret, 16); - tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16); - tcg_out_dsll(s, ret, ret, 16); - } else { - tcg_out_dsll(s, ret, ret, 32); - } + tcg_out_dsll(s, ret, ret, 32); } if (arg & 0xffff) { tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); From patchwork Wed Aug 18 20:19:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 498996 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp1016953jab; Wed, 18 Aug 2021 13:36:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwPZlloKMFTg8QSMzp425PB4uGbdBTogMTDDzioLIClME1at+jPAA6Ge9UpRC3rCAOSDevY X-Received: by 2002:a1f:1fcb:: with SMTP id f194mr9256355vkf.18.1629318971468; Wed, 18 Aug 2021 13:36:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629318971; cv=none; d=google.com; s=arc-20160816; b=muMn4P2hnVTdPuxwj7PB9s+g4BlzqtdarkT7cgISpxeS83LgW3NWvOFEaUuvILsj0E VDXeE6XOCxXAkpyHqFj4HbuSazwSJ1RvOi5BNbHU2iJ5eIxBlKphijgJ8bgW8vqjAuf1 Mz7kODZ6vTjLNngV/DN03NkCDntioE95o2Q03j9Y7e9ZGn6WyLQmBidewqv1zHi3AKeR jIkI6FphjVcDBRKFWQm3fsWhJoAmP1eWQaWcFUAYhbmdB1gFhvG49mSQq7hNvldbhInG 0fZtq2krfL2H9bmwJ6vFhpfnW8hpl89UrST0K0dSbCLLc6XFQd9ikpCAoM1hYJUvZx/1 /vnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dmNHD8oMVOw6IiwNX8BcqXva18N9be8xhmnHYKvCR/4=; b=ULPdd4Bb2doIKtHXrCqDWy/GXiLNhgNwpwyQ9HRXmu5gcr/0RKcKADxdR56vn1s/uT 6oO9WeSG3VYebcGCjGwn7l1FVKZP8ESxh8TYxxO7hwzahNFkKwpQYEKkUzXy+4xR3jOD 2Pj+u5GVX91wb8XkVomQVJ+OHempXtpeQ4BPUSDJNTzGbZ2/qN+i4QnJhWqcnKHJuA9f lXgEMXDKVMs93bQRoSxbWTD7kVKG7biU/nOxpC/HO/kLmdx8U0Or3rpDZTzELYU5XOCL CyS42HVDMC1v2c+J/yMKH7R3XMJoFmVKj5lrY7k4f+jDRGGd19Qtg8tGgeurz5xDCqjX +b3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=v7UUHDIL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x9si454004vsc.301.2021.08.18.13.36.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 18 Aug 2021 13:36:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=v7UUHDIL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56458 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mGSIE-0005wA-Pr for patch@linaro.org; Wed, 18 Aug 2021 16:36:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40364) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mGS2P-0008Fe-RK for qemu-devel@nongnu.org; Wed, 18 Aug 2021 16:19:49 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:46802) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mGS2O-0006K4-6N for qemu-devel@nongnu.org; Wed, 18 Aug 2021 16:19:49 -0400 Received: by mail-pf1-x42e.google.com with SMTP id y11so3334806pfl.13 for ; Wed, 18 Aug 2021 13:19:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=dmNHD8oMVOw6IiwNX8BcqXva18N9be8xhmnHYKvCR/4=; b=v7UUHDILwNguMjgH5Y6T4vKpTdcoX3i47kNCxlhhpWSeOpDelrxdW2+lz+tYfgt7ys DkEW9IZ48AY0Xwpgs9WVa4RjiTskw+AqmQd5axVAk/G7zZFW/MKxIvgcU2OBjUPPpPji mutlI8zBrNuIV5t34QONuY21d8obm0olGOSqxUwZnbX70kDuTRtdk6yikl/a0zAcAVUn tJ0oFsM6qVuNemUuH2I00EtsDJfU+mppOmZ7pV9cpP0+Z+jLaLIcSUlnM+oi5rOdpeRw qgQr7Y0dGrXFOhrpBHmdHeWDrUyPI5OpTZZfNF2rGxUhxPlQGKjR7UvHt4cXIsczw4vI EdZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dmNHD8oMVOw6IiwNX8BcqXva18N9be8xhmnHYKvCR/4=; b=HSy1/8fYuIYJoSBhkoRqKVG0woDVXHqpiQPD3C3WmhOR1wkUJ145aSwYsjAuQSrGtA yW3zyEiqin3tOd1/uskrpsipfgZU/4qVB8x2t+8NB5/7RDm+aYbcL+4Naqgnk2t/I/OA w9ZD/qE/XHq+44i1vmCnmRTaY9k1ikcGjbL1+OFK7H1VeUYeecDP2ave1FNv6xf7nnpa ZwFpQiG9xerPM4sq+xEcSrKKLNrBKARglqWXjXCI3nPbb1B27POiWQcF/eHi7SBOg4SP zUSla+/+2pZ5Y3vQT+9XVWoaRtye3Saoorv4VTkCgXT3h/JfhHcylUCcLoQZ2yhQilaD +YvA== X-Gm-Message-State: AOAM5312Dmwk8N+FQM2WYK+a/d8vxBVcl4pMGU/4chrVBtaPEDAHFckZ TV8loJEp1NUDlettsLTT9HHtLP7rT2sbZA== X-Received: by 2002:a62:dd83:0:b029:30f:d69:895f with SMTP id w125-20020a62dd830000b029030f0d69895fmr11175081pff.17.1629317986868; Wed, 18 Aug 2021 13:19:46 -0700 (PDT) Received: from localhost.localdomain ([173.197.107.15]) by smtp.gmail.com with ESMTPSA id x13sm619621pjh.30.2021.08.18.13.19.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Aug 2021 13:19:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 13/16] tcg/mips: Use the constant pool for 64-bit constants Date: Wed, 18 Aug 2021 10:19:28 -1000 Message-Id: <20210818201931.393394-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818201931.393394-1-richard.henderson@linaro.org> References: <20210818201931.393394-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" During normal processing, the constant pool is accessible via TCG_REG_TB. During the prologue, it is accessible via TCG_REG_T9. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 1 + tcg/mips/tcg-target.c.inc | 65 +++++++++++++++++++++++++++++---------- 2 files changed, 49 insertions(+), 17 deletions(-) -- 2.25.1 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 28c42e23e1..839364b493 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -208,5 +208,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t) QEMU_ERROR("code path is reachable"); #define TCG_TARGET_NEED_LDST_LABELS +#define TCG_TARGET_NEED_POOL_LABELS #endif diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index d351d53a7b..2ab37ac7c0 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -25,6 +25,7 @@ */ #include "../tcg-ldst.c.inc" +#include "../tcg-pool.c.inc" #ifdef HOST_WORDS_BIGENDIAN # define MIPS_BE 1 @@ -166,9 +167,18 @@ static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) static bool patch_reloc(tcg_insn_unit *code_ptr, int type, intptr_t value, intptr_t addend) { - tcg_debug_assert(type == R_MIPS_PC16); - tcg_debug_assert(addend == 0); - return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); + value += addend; + switch (type) { + case R_MIPS_PC16: + return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); + case R_MIPS_16: + if (value != (int16_t)value) { + return false; + } + *code_ptr = deposit32(*code_ptr, 0, 16, value); + return true; + } + g_assert_not_reached(); } #define TCG_CT_CONST_ZERO 0x100 @@ -500,6 +510,11 @@ static void tcg_out_nop(TCGContext *s) tcg_out32(s, 0); } +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + memset(p, 0, count * sizeof(tcg_insn_unit)); +} + static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) { tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); @@ -557,8 +572,15 @@ static bool tcg_out_movi_two(TCGContext *s, TCGReg ret, tcg_target_long arg) return false; } -static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long arg) +static void tcg_out_movi_pool(TCGContext *s, TCGReg ret, + tcg_target_long arg, TCGReg tbreg) +{ + new_pool_label(s, arg, R_MIPS_16, s->code_ptr, tcg_tbrel_diff(s, NULL)); + tcg_out_opc_imm(s, OPC_LD, ret, tbreg, 0); +} + +static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, + tcg_target_long arg, TCGReg tbreg) { if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { arg = (int32_t)arg; @@ -568,18 +590,17 @@ static void tcg_out_movi(TCGContext *s, TCGType type, if (tcg_out_movi_two(s, ret, arg)) { return; } + assert(TCG_TARGET_REG_BITS == 64); - tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1); - if (arg & 0xffff0000ull) { - tcg_out_dsll(s, ret, ret, 16); - tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16); - tcg_out_dsll(s, ret, ret, 16); - } else { - tcg_out_dsll(s, ret, ret, 32); - } - if (arg & 0xffff) { - tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); - } + /* Otherwise, put 64-bit constants into the constant pool. */ + tcg_out_movi_pool(s, ret, arg, tbreg); +} + +static void tcg_out_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long arg) +{ + TCGReg tbreg = TCG_TARGET_REG_BITS == 64 ? TCG_REG_TB : 0; + tcg_out_movi_int(s, type, ret, arg, tbreg); } static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags) @@ -2738,10 +2759,20 @@ static void tcg_target_qemu_prologue(TCGContext *s) #ifndef CONFIG_SOFTMMU if (guest_base != (int16_t)guest_base) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); + /* + * The function call abi for n32 and n64 will have loaded $25 (t9) + * with the address of the prologue, so we can use that instead + * of TCG_REG_TB. + */ +#if TCG_TARGET_REG_BITS == 64 && !defined(__mips_abicalls) +# error "Unknown mips abi" +#endif + tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, + TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } #endif + if (TCG_TARGET_REG_BITS == 64) { tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); } From patchwork Wed Aug 18 20:19:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 498998 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp1018491jab; Wed, 18 Aug 2021 13:38:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyvVk4tKKjCPnW9qSp5RBwRULulLmbtnDT4lMT3IcY7bGloanUkxB6/0YPCiGqU8No1quMB X-Received: by 2002:a05:6638:1905:: with SMTP id p5mr9677320jal.25.1629319113355; Wed, 18 Aug 2021 13:38:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629319113; cv=none; d=google.com; s=arc-20160816; b=oa5RanROG674ATTajt82Pprzk4HOAzlJYFJo+knc5khC67tCykmesR+LQFO5JCVkgQ 2nSZd2zZKMFk6aaCltjZjb8vgELMbybgkfh+90nO8SfPC/EPzU+SqlABvAOfQO3Fe0Oq FcNo18sQBCCrucDskK3X9O3sUsTbj1bc+boDv2Hy3xLRntmvORp0W8xnGTsky0/Qobpv zSiTxqWOfRrW/JVhhKvbp5fBkySqpJyRvSYhcUseAOAuNZ1NpFD23J2v7zKT2/3V2qLP HrT0c/zNsqDTZZhU9fafbjtPGW9jBJgEGQAAHsBZRSm4bCeXgR2PTedrWE+UqcM9jjtk UNeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=aRM/aV1nNd+z0X6JLDx3kBkYbHw3rVDD5maGh4N4GXM=; b=IbZpPwmembJPSYSLVFIZa51VY9T5lwrQzq5QKZdTS20bZvMk96SJsVCGLBRD1Fru5E OTzWCP5KT9UCDStZy9fzI9KxYfOg6IL/NObRD5GVWzgTYFFSxtTS094Sldtuc8pq4qgW 96bR/Bb6AN8CIilTx5AtaIDLKRHu7nn06BpqpDww44VOh82qauV2xXxWKUbzmWjZ0e7v aWPI7R3exEIh+8bNEnMn/h7M3jquYNq3tHlu2Zb3o0Yn5GiWxmqQnNdJ0hzs01J9z/eB JvblFbaPMyv1EbwtTMV8Vj7DRvYKqA4LHJLJg3UEW+kKMFlSbhvV82gIT6HUPqeEComB h6SQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AheVb+eF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o3si665519jah.81.2021.08.18.13.38.33 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 18 Aug 2021 13:38:33 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AheVb+eF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33548 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mGSKW-00016O-RA for patch@linaro.org; Wed, 18 Aug 2021 16:38:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40372) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mGS2Q-0008GL-FO for qemu-devel@nongnu.org; Wed, 18 Aug 2021 16:19:53 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:41834) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mGS2P-0006LF-31 for qemu-devel@nongnu.org; Wed, 18 Aug 2021 16:19:50 -0400 Received: by mail-pg1-x52c.google.com with SMTP id k24so3485409pgh.8 for ; Wed, 18 Aug 2021 13:19:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=aRM/aV1nNd+z0X6JLDx3kBkYbHw3rVDD5maGh4N4GXM=; b=AheVb+eFo+YD6nig9aY/StyGg0faymC1Y43Tm1T2UlqrTz5E5O066z7qQIHUuWkZ6a I1A2FgFeXVsnpT3kEuD6CcwHAosJChJu2VwlcDuJxhUqDb8oGpsd17imv6yQmzNO8aan 2JQk/B/3pZQ4aWqMC0CDv4pvkX3abQN5QxM+1driwdhaem26HgMEHjLy8xpCN58aATBQ QBAU3t1Xk0rU39tIVEg6uAABTdnBeutKrwjH4OwIXVVPHZTfGUh669soXfYgCyggWqSg yxKKjmaq2Rh2b1lidsdZMdf6h5zhzuIl1K3tQeAvMkA4Yh/7+iRbhUmAeMGW0KXdEe3X /zBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aRM/aV1nNd+z0X6JLDx3kBkYbHw3rVDD5maGh4N4GXM=; b=VCzN+PBMZ11kK5DERROBtFcOP8nM7tNpWClP6zFxR4qSduTLkc7tNlWWHVCilhW4s5 C8xNOMcXTgxUemzRGBeu1cHnqkfembUR9c8Y8ntmF9K+4EbSSE7r4jQWTQtraEC7QTMG PGmntiB2KcnmmoJadjXFSexTAXnSylsGj38J3Q1wuVzJ3nW2PyeBBQmvvL+hKb8ygVs5 RQinsLfqyZ7eULHekyDbYLaLVAmAwsEy6jsRJ1IvoKfCd2yNsRn+bY7j8hqSnVZIBNNl CmoHLJENLOFBvPbCPGFKQPKq6/w0Kuhb/HBKxNCPGTyYzffs664VI/HzxShDd0oud4IO 9q6g== X-Gm-Message-State: AOAM5311jTpniqTgEGz/Q7RRO7XFMfoyZl2ngnnwgQkvg9sawYB9Cn88 9EfjwtRNsZAY8wZ08nXoCghoDydwoO/mMw== X-Received: by 2002:a05:6a00:1ace:b0:3e2:2a73:e0a4 with SMTP id f14-20020a056a001ace00b003e22a73e0a4mr11357832pfv.73.1629317987782; Wed, 18 Aug 2021 13:19:47 -0700 (PDT) Received: from localhost.localdomain ([173.197.107.15]) by smtp.gmail.com with ESMTPSA id x13sm619621pjh.30.2021.08.18.13.19.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Aug 2021 13:19:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 14/16] tcg/mips: Aggressively use the constant pool for n64 calls Date: Wed, 18 Aug 2021 10:19:29 -1000 Message-Id: <20210818201931.393394-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818201931.393394-1-richard.henderson@linaro.org> References: <20210818201931.393394-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Repeated calls to a single helper are common -- especially the ones for softmmu memory access. Prefer the constant pool to longer sequences to increase sharing. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 2ab37ac7c0..f641d86561 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1057,9 +1057,19 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) { - /* Note that the ABI requires the called function's address to be - loaded into T9, even if a direct branch is in range. */ - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); + /* + * Note that __mips_abicalls requires the called function's address + * to be loaded into $25 (t9), even if a direct branch is in range. + * + * For n64, always drop the pointer into the constant pool. + * We can re-use helper addresses often and do not want any + * of the longer sequences tcg_out_movi may try. + */ + if (sizeof(uintptr_t) == 8) { + tcg_out_movi_pool(s, TCG_REG_T9, (uintptr_t)arg, TCG_REG_TB); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); + } /* But do try a direct branch, allowing the cpu better insn prefetch. */ if (tail) { From patchwork Wed Aug 18 20:19:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 498989 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp1011716jab; Wed, 18 Aug 2021 13:28:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw2b9yhwfoF1EvPMKRyC1GZkLTNW3/Ys5yX+3LSascbqY49QJZ7Oq3/xJnDGx1Q8UOXmXMP X-Received: by 2002:a5d:9617:: with SMTP id w23mr8277983iol.115.1629318532069; Wed, 18 Aug 2021 13:28:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629318532; cv=none; d=google.com; s=arc-20160816; b=o8NU0jMQN+wEfTvyNuqyZVCDpXJ23Df1ANdobnD2E8uvSdhdw0uDtYlMLbozJyv27g e1fZ8QF52lqlDwsk0hqH4QKPqg25yr38RiW6Mv4Agzh20RK4ijZXRUjwZnePf/GzKKWY IUBiF8NUZ94JUVKTJi29d9z7QQMLDJKYSw8Rl5IjyEkcH5QtRGvsR/25sGKirLNx+vq4 xLQq02ntgY61rWkJUDpInG5nzgw1YdMMOvB2xRVuD1lUM19jm2joPChGScJ82W4WkFl2 B7DajY6RMcmY49TA2J+vFLMfoY8QiqumcB5baZxQNZraBXMM7H6elmS7hpQiFcU5aNj/ 3MYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HpQSpkjMY/HVPNmupFN14WCJnZd0Eg9bjbOHuKK4v+k=; b=KZF+yAMF+/RcnVJDx+4uh05s5moYfP6EhrTEC8MuNd/99tqiF8w2vPsxeF+hkgIUAH SBObx2iJs/BUafFWZ0yUlw12ruaQMj6/2rdPVepgycLfdTlsQ9kRkRN08HEJWdamNp4D DFHr+3uJZHhdF1zxvZGAIPGcZMqXVaBfHxHUFdJnw1UmdO/3vegVYwNoqyFu4WI3n9kD ly1FRr1mn3xMqCEVznmgHKIdQLa6/KG3aa1/jontNEYmLEl28x0CnYjQCWruEr7ddonF J9Tc1O9h5XWNzP8pYqQ7jt67324GSZrJS2lKVnX9st2Q4jwia0dkEnqZ4m9RQ1Ixkqft I9zA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jtVxb4cf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q16si826191ioj.19.2021.08.18.13.28.52 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 18 Aug 2021 13:28:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jtVxb4cf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36634 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mGSB9-0000Ue-Gd for patch@linaro.org; Wed, 18 Aug 2021 16:28:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40396) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mGS2U-0008HI-0z for qemu-devel@nongnu.org; Wed, 18 Aug 2021 16:19:54 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:40608) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mGS2Q-0006Lu-3O for qemu-devel@nongnu.org; Wed, 18 Aug 2021 16:19:51 -0400 Received: by mail-pg1-x536.google.com with SMTP id y23so3481434pgi.7 for ; Wed, 18 Aug 2021 13:19:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=HpQSpkjMY/HVPNmupFN14WCJnZd0Eg9bjbOHuKK4v+k=; b=jtVxb4cfisbRGFNexDMxEdL9ceTblFTBKFJkL7HxT6/5rdDnZPJ0WO4r4jrPCaWhKn qdNdwPL0oOB221mKImSJHwxnCVEtlZiY6jOUp7nwSN8YDrn/zWHNhSQFmHSYfw0mFn5R d99AVgoLVVEmsp+EvObCmyUmkOGTqqAHLcPBFoFS29qJo0YuP6Irpxo5FPGn4XhbgNvp d4kZWQFmG0chD8WhYsp/VCvMaVDKXBLzKb4h/oukOWpv3XaE9ahLdUKOQyDw1FGqJLN/ GPaBZoZHrqHWqJi3drj4b+sLyln1qMBce6yrskGIP0vOAw4qplp+ho8o3n4GeIBRLf4z 1aLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HpQSpkjMY/HVPNmupFN14WCJnZd0Eg9bjbOHuKK4v+k=; b=MTqsQtlcLM7hG3CQSfuPgIW2sZh3cGWlRlFLa8xfmDO/Os1AY/YRe7cG4C2IorkDfx rbw1Nq+yfo9FWZ/3sjF62GNFk7qYwosCa1YE+ufG8aJK2oZHaWgetdPPazktuL/EQxFZ 0VoW92pd3DsR3bj/NwAi9NCdDYEfE6yk5MwKU9wWOHWM4RUvOeFBto/kzR2SjS49D9B4 0auDjTq3BUVZcDhsGapPi/2g+IoDYh/G+meKC4wo2llf0tZB13G21LWL3tkqgHaLluOn vyIN6tW1+MsIDAc8EM8xV/HiRqTghitIdyf4RB3LFXzNu/EP6hqVduCIxXG2rNG4tVxd ygJQ== X-Gm-Message-State: AOAM53126osvbKK6sdCOti1DZzbNjic98RwtS+2E8UChSmM7+KSQsaNe JC6FEIIZjJmSZq1pCvzHm/jG9P6RsJKj6g== X-Received: by 2002:a65:494e:: with SMTP id q14mr10504923pgs.314.1629317988807; Wed, 18 Aug 2021 13:19:48 -0700 (PDT) Received: from localhost.localdomain ([173.197.107.15]) by smtp.gmail.com with ESMTPSA id x13sm619621pjh.30.2021.08.18.13.19.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Aug 2021 13:19:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 15/16] tcg/mips: Try tb-relative addresses in tcg_out_movi Date: Wed, 18 Aug 2021 10:19:30 -1000 Message-Id: <20210818201931.393394-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210818201931.393394-1-richard.henderson@linaro.org> References: <20210818201931.393394-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These addresses are often loaded by the qemu_ld/st slow path, for loading the retaddr value. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.25.1 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index f641d86561..27a23662c8 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -582,6 +582,8 @@ static void tcg_out_movi_pool(TCGContext *s, TCGReg ret, static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg, TCGReg tbreg) { + tcg_target_long tmp; + if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { arg = (int32_t)arg; } @@ -592,6 +594,17 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, } assert(TCG_TARGET_REG_BITS == 64); + /* Load addresses within 2GB of TB with 1 or 3 insns. */ + tmp = tcg_tbrel_diff(s, (void *)arg); + if (tmp == (int16_t)tmp) { + tcg_out_opc_imm(s, OPC_DADDIU, ret, tbreg, tmp); + return; + } + if (tcg_out_movi_two(s, ret, tmp)) { + tcg_out_opc_reg(s, OPC_DADDU, ret, ret, tbreg); + return; + } + /* Otherwise, put 64-bit constants into the constant pool. */ tcg_out_movi_pool(s, ret, arg, tbreg); } From patchwork Wed Aug 18 20:19:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 498992 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp1014076jab; Wed, 18 Aug 2021 13:32:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwskLyVOfFAPbKwcmC1qJxxU1JUzehQtjSqCDoqUQqe1j2XvMRoeca6Uqp4PbqPdGvKly+9 X-Received: by 2002:ab0:d82:: with SMTP id i2mr8422574uak.124.1629318724627; Wed, 18 Aug 2021 13:32:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629318724; cv=none; d=google.com; s=arc-20160816; b=FkFO0ynnGlDeUrHTIhmz9lrynyK2ZXu4jt7fyGEuBw3HQ4+0HGn8lMx6DVziY5IxJs Sg2xisBZH5FW4xYPvenHBrSKRxZS+S4Lok4RjaLZWWRnaUFqHoDGu8IbKO6YFm2HGarX ZYyJav56r6DqwqtOWvaPYiM159R+/JCPNmqwWxBNM4JHY/FPEo/bM4QoWGI/sZzU36Rb BqOaMDhRD0pF1AHsWzeZeA2WWhaE6JtkzBxvT0rZ6VKoswk0G9hV+t6WjtBnrDqhheuP XwULHK+OYyacRrqs/VDH/8Q13bXrIWGCIl7MLw1DifrCMKAMUtzetqXOaGoETN0m8z6N LRvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lfVt0eT0nNOIPktjRSBpSBNPqCJhivS9a0zJZSVFgMw=; b=N62EZY7ZoYbN+dsd50KJt8J5+qGPx56m+WX24dZZQZgSNHQpQqV2Ml+J8s4wX5CwU4 Q95pdT6Jv1hB5hG5v5wjXxOeQma/cExcxhIkvfPlQPslXDPhc2JbIG7LYKEiASDfqIyF B2I0aVg81VmqtjlpYkFlI2yRSYamKxFs1dTY7LGHaRgIZUmwT9TexdOW7Hpfj99oitNm 1f+xO7Gp+Y1LoGtKay5Vxs3uj8UHrnwLsSI2Jo/1zOOs607I/2+v54PrxeTSuPhNB4N9 SpHWcrLAowPFgvGANznKTj3VM1XQYvW8IG7BXK5PjB4EVtKzAKs79SxOo1PXvJvvI72L Wg2w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Y5xGaA4u; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Maxing out at three insns results in the same space as a load plus the constant pool entry. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 44 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) -- 2.25.1 diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 27a23662c8..92f324de68 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -583,6 +583,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg, TCGReg tbreg) { tcg_target_long tmp; + int sh, lo; if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { arg = (int32_t)arg; @@ -605,6 +606,49 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, return; } + /* + * Load bitmasks with a right-shift. This is good for things + * like 0x0fff_ffff_ffff_fff0: ADDUI r,0xff00 + DSRL r,r,4. + * or similarly using LUI. For this to work, bit 31 must be set. + */ + if (arg > 0 && (int32_t)arg < 0) { + sh = clz64(arg); + if (tcg_out_movi_one(s, ret, arg << sh)) { + tcg_out_dsrl(s, ret, ret, sh); + return; + } + } + + /* + * Load slightly larger constants using left-shift. + * Limit this sequence to 3 insns to avoid too much expansion. + */ + sh = ctz64(arg); + if (sh && tcg_out_movi_two(s, ret, arg >> sh)) { + tcg_out_dsll(s, ret, ret, sh); + return; + } + + /* + * Load slightly larger constants using left-shift and add/or. + * Prefer addi with a negative immediate when that would produce + * a larger shift. For this to work, bits 15 and 16 must be set. + */ + lo = arg & 0xffff; + if (lo) { + if ((arg & 0x18000) == 0x18000) { + lo = (int16_t)arg; + } + tmp = arg - lo; + sh = ctz64(tmp); + tmp >>= sh; + if (tcg_out_movi_one(s, ret, tmp)) { + tcg_out_dsll(s, ret, ret, sh); + tcg_out_opc_imm(s, lo < 0 ? OPC_DADDIU : OPC_ORI, ret, ret, lo); + return; + } + } + /* Otherwise, put 64-bit constants into the constant pool. */ tcg_out_movi_pool(s, ret, arg, tbreg); }