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Move handling of bus clocks to qnoc_probe. This both simplifies the code and allows using qnoc_probe as device's probe funcion. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/icc-rpm.c | 22 ++++++++++++++-------- drivers/interconnect/qcom/icc-rpm.h | 5 ++--- drivers/interconnect/qcom/msm8916.c | 13 +------------ drivers/interconnect/qcom/msm8939.c | 13 +------------ drivers/interconnect/qcom/qcs404.c | 13 +------------ 5 files changed, 19 insertions(+), 47 deletions(-) -- 2.32.0 diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index 54de49ca7808..394f515cc88d 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -86,8 +86,11 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) return 0; } -int qnoc_probe(struct platform_device *pdev, size_t cd_size, int cd_num, - const struct clk_bulk_data *cd) +static const char * const bus_clocks[] = { + "bus", "bus_a", +}; + +int qnoc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; const struct qcom_icc_desc *desc; @@ -97,6 +100,8 @@ int qnoc_probe(struct platform_device *pdev, size_t cd_size, int cd_num, struct qcom_icc_provider *qp; struct icc_node *node; size_t num_nodes, i; + const char * const * cds; + int cd_num; int ret; /* wait for the RPM proxy */ @@ -110,7 +115,10 @@ int qnoc_probe(struct platform_device *pdev, size_t cd_size, int cd_num, qnodes = desc->nodes; num_nodes = desc->num_nodes; - qp = devm_kzalloc(dev, sizeof(*qp), GFP_KERNEL); + cds = bus_clocks; + cd_num = ARRAY_SIZE(bus_clocks); + + qp = devm_kzalloc(dev, struct_size(qp, bus_clks, cd_num), GFP_KERNEL); if (!qp) return -ENOMEM; @@ -119,12 +127,10 @@ int qnoc_probe(struct platform_device *pdev, size_t cd_size, int cd_num, if (!data) return -ENOMEM; - qp->bus_clks = devm_kmemdup(dev, cd, cd_size, - GFP_KERNEL); - if (!qp->bus_clks) - return -ENOMEM; - + for (i = 0; i < cd_num; i++) + qp->bus_clks[i].id = cds[i]; qp->num_clks = cd_num; + ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks); if (ret) return ret; diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h index 79a6f68249c1..f4b05c20c097 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -22,8 +22,8 @@ */ struct qcom_icc_provider { struct icc_provider provider; - struct clk_bulk_data *bus_clks; int num_clks; + struct clk_bulk_data bus_clks[]; }; /** @@ -66,8 +66,7 @@ struct qcom_icc_desc { } -int qnoc_probe(struct platform_device *pdev, size_t cd_size, int cd_num, - const struct clk_bulk_data *cd); +int qnoc_probe(struct platform_device *pdev); int qnoc_remove(struct platform_device *pdev); #endif diff --git a/drivers/interconnect/qcom/msm8916.c b/drivers/interconnect/qcom/msm8916.c index fc3689c8947a..fc0d48d2997a 100644 --- a/drivers/interconnect/qcom/msm8916.c +++ b/drivers/interconnect/qcom/msm8916.c @@ -105,11 +105,6 @@ enum { MSM8916_SNOC_PNOC_SLV, }; -static const struct clk_bulk_data msm8916_bus_clocks[] = { - { .id = "bus" }, - { .id = "bus_a" }, -}; - DEFINE_QNODE(bimc_snoc_mas, MSM8916_BIMC_SNOC_MAS, 8, -1, -1, MSM8916_BIMC_SNOC_SLV); DEFINE_QNODE(bimc_snoc_slv, MSM8916_BIMC_SNOC_SLV, 8, -1, -1, MSM8916_SNOC_INT_0, MSM8916_SNOC_INT_1); DEFINE_QNODE(mas_apss, MSM8916_MASTER_AMPSS_M0, 8, -1, -1, MSM8916_SLAVE_EBI_CH0, MSM8916_BIMC_SNOC_MAS, MSM8916_SLAVE_AMPSS_L2); @@ -305,12 +300,6 @@ static struct qcom_icc_desc msm8916_pcnoc = { .num_nodes = ARRAY_SIZE(msm8916_pcnoc_nodes), }; -static int msm8916_qnoc_probe(struct platform_device *pdev) -{ - return qnoc_probe(pdev, sizeof(msm8916_bus_clocks), - ARRAY_SIZE(msm8916_bus_clocks), msm8916_bus_clocks); -} - static const struct of_device_id msm8916_noc_of_match[] = { { .compatible = "qcom,msm8916-bimc", .data = &msm8916_bimc }, { .compatible = "qcom,msm8916-pcnoc", .data = &msm8916_pcnoc }, @@ -320,7 +309,7 @@ static const struct of_device_id msm8916_noc_of_match[] = { MODULE_DEVICE_TABLE(of, msm8916_noc_of_match); static struct platform_driver msm8916_noc_driver = { - .probe = msm8916_qnoc_probe, + .probe = qnoc_probe, .remove = qnoc_remove, .driver = { .name = "qnoc-msm8916", diff --git a/drivers/interconnect/qcom/msm8939.c b/drivers/interconnect/qcom/msm8939.c index 20f31a1b4192..4a5a2ec64960 100644 --- a/drivers/interconnect/qcom/msm8939.c +++ b/drivers/interconnect/qcom/msm8939.c @@ -110,11 +110,6 @@ enum { MSM8939_SNOC_PNOC_SLV, }; -static const struct clk_bulk_data msm8939_bus_clocks[] = { - { .id = "bus" }, - { .id = "bus_a" }, -}; - DEFINE_QNODE(bimc_snoc_mas, MSM8939_BIMC_SNOC_MAS, 8, -1, -1, MSM8939_BIMC_SNOC_SLV); DEFINE_QNODE(bimc_snoc_slv, MSM8939_BIMC_SNOC_SLV, 16, -1, 2, MSM8939_SNOC_INT_0, MSM8939_SNOC_INT_1); DEFINE_QNODE(mas_apss, MSM8939_MASTER_AMPSS_M0, 16, -1, -1, MSM8939_SLAVE_EBI_CH0, MSM8939_BIMC_SNOC_MAS, MSM8939_SLAVE_AMPSS_L2); @@ -326,12 +321,6 @@ static struct qcom_icc_desc msm8939_pcnoc = { .num_nodes = ARRAY_SIZE(msm8939_pcnoc_nodes), }; -static int msm8939_qnoc_probe(struct platform_device *pdev) -{ - return qnoc_probe(pdev, sizeof(msm8939_bus_clocks), - ARRAY_SIZE(msm8939_bus_clocks), msm8939_bus_clocks); -} - static const struct of_device_id msm8939_noc_of_match[] = { { .compatible = "qcom,msm8939-bimc", .data = &msm8939_bimc }, { .compatible = "qcom,msm8939-pcnoc", .data = &msm8939_pcnoc }, @@ -342,7 +331,7 @@ static const struct of_device_id msm8939_noc_of_match[] = { MODULE_DEVICE_TABLE(of, msm8939_noc_of_match); static struct platform_driver msm8939_noc_driver = { - .probe = msm8939_qnoc_probe, + .probe = qnoc_probe, .remove = qnoc_remove, .driver = { .name = "qnoc-msm8939", diff --git a/drivers/interconnect/qcom/qcs404.c b/drivers/interconnect/qcom/qcs404.c index 36a7e30a00be..0f2fff230b13 100644 --- a/drivers/interconnect/qcom/qcs404.c +++ b/drivers/interconnect/qcom/qcs404.c @@ -92,11 +92,6 @@ enum { QCS404_SLAVE_LPASS, }; -static const struct clk_bulk_data qcs404_bus_clocks[] = { - { .id = "bus" }, - { .id = "bus_a" }, -}; - DEFINE_QNODE(mas_apps_proc, QCS404_MASTER_AMPSS_M0, 8, 0, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV); DEFINE_QNODE(mas_oxili, QCS404_MASTER_GRAPHICS_3D, 8, -1, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV); DEFINE_QNODE(mas_mdp, QCS404_MASTER_MDP_PORT0, 8, -1, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV); @@ -269,12 +264,6 @@ static struct qcom_icc_desc qcs404_snoc = { }; -static int qcs404_qnoc_probe(struct platform_device *pdev) -{ - return qnoc_probe(pdev, sizeof(qcs404_bus_clocks), - ARRAY_SIZE(qcs404_bus_clocks), qcs404_bus_clocks); -} - static const struct of_device_id qcs404_noc_of_match[] = { { .compatible = "qcom,qcs404-bimc", .data = &qcs404_bimc }, { .compatible = "qcom,qcs404-pcnoc", .data = &qcs404_pcnoc }, @@ -284,7 +273,7 @@ static const struct of_device_id qcs404_noc_of_match[] = { MODULE_DEVICE_TABLE(of, qcs404_noc_of_match); static struct platform_driver qcs404_noc_driver = { - .probe = qcs404_qnoc_probe, + .probe = qnoc_probe, .remove = qnoc_remove, .driver = { .name = "qnoc-qcs404", From patchwork Wed Aug 18 01:57:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 498877 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp190979jab; Tue, 17 Aug 2021 18:57:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxKigsuJNkVYB20oEapol8efa8YMhKmU7rxdHMiTSjCmoPCSbmhu9SxyKT4RfrGLik6CSyq X-Received: by 2002:aa7:d916:: with SMTP id a22mr7325172edr.158.1629251863436; Tue, 17 Aug 2021 18:57:43 -0700 (PDT) ARC-Seal: i=1; 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Move AP-owned nodes support from SDM660 driver to common icc-rpm.c. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/icc-rpm.c | 248 ++++++++++- drivers/interconnect/qcom/icc-rpm.h | 55 ++- drivers/interconnect/qcom/sdm660.c | 662 +++++----------------------- 3 files changed, 380 insertions(+), 585 deletions(-) -- 2.32.0 Reported-by: kernel test robot diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index 394f515cc88d..05130e74364a 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -11,60 +11,231 @@ #include #include #include +#include #include #include "smd-rpm.h" #include "icc-rpm.h" -static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) +/* BIMC QoS */ +#define M_BKE_REG_BASE(n) (0x300 + (0x4000 * n)) +#define M_BKE_EN_ADDR(n) (M_BKE_REG_BASE(n)) +#define M_BKE_HEALTH_CFG_ADDR(i, n) (M_BKE_REG_BASE(n) + 0x40 + (0x4 * i)) + +#define M_BKE_HEALTH_CFG_LIMITCMDS_MASK 0x80000000 +#define M_BKE_HEALTH_CFG_AREQPRIO_MASK 0x300 +#define M_BKE_HEALTH_CFG_PRIOLVL_MASK 0x3 +#define M_BKE_HEALTH_CFG_AREQPRIO_SHIFT 0x8 +#define M_BKE_HEALTH_CFG_LIMITCMDS_SHIFT 0x1f + +#define M_BKE_EN_EN_BMASK 0x1 + +/* NoC QoS */ +#define NOC_QOS_PRIORITYn_ADDR(n) (0x8 + (n * 0x1000)) +#define NOC_QOS_PRIORITY_MASK 0xf +#define NOC_QOS_PRIORITY_P1_SHIFT 0x2 +#define NOC_QOS_PRIORITY_P0_SHIFT 0x3 + +#define NOC_QOS_MODEn_ADDR(n) (0xc + (n * 0x1000)) +#define NOC_QOS_MODEn_MASK 0x3 + +static int qcom_icc_bimc_set_qos_health(struct regmap *rmap, + struct qcom_icc_qos *qos, + int regnum) +{ + u32 val; + u32 mask; + + val = qos->prio_level; + mask = M_BKE_HEALTH_CFG_PRIOLVL_MASK; + + val |= qos->areq_prio << M_BKE_HEALTH_CFG_AREQPRIO_SHIFT; + mask |= M_BKE_HEALTH_CFG_AREQPRIO_MASK; + + /* LIMITCMDS is not present on M_BKE_HEALTH_3 */ + if (regnum != 3) { + val |= qos->limit_commands << M_BKE_HEALTH_CFG_LIMITCMDS_SHIFT; + mask |= M_BKE_HEALTH_CFG_LIMITCMDS_MASK; + } + + return regmap_update_bits(rmap, + M_BKE_HEALTH_CFG_ADDR(regnum, qos->qos_port), + mask, val); +} + +static int qcom_icc_set_bimc_qos(struct icc_node *src, u64 max_bw, + bool bypass_mode) { struct qcom_icc_provider *qp; struct qcom_icc_node *qn; struct icc_provider *provider; - struct icc_node *n; - u64 sum_bw; - u64 max_peak_bw; - u64 rate; - u32 agg_avg = 0; - u32 agg_peak = 0; - int ret, i; + u32 mode = NOC_QOS_MODE_BYPASS; + u32 val = 0; + int i, rc = 0; qn = src->data; provider = src->provider; qp = to_qcom_provider(provider); - list_for_each_entry(n, &provider->nodes, node_list) - provider->aggregate(n, 0, n->avg_bw, n->peak_bw, - &agg_avg, &agg_peak); + if (qn->qos.qos_mode != -1) + mode = qn->qos.qos_mode; + + /* QoS Priority: The QoS Health parameters are getting considered + * only if we are NOT in Bypass Mode. + */ + if (mode != NOC_QOS_MODE_BYPASS) { + for (i = 3; i >= 0; i--) { + rc = qcom_icc_bimc_set_qos_health(qp->regmap, + &qn->qos, i); + if (rc) + return rc; + } - sum_bw = icc_units_to_bps(agg_avg); - max_peak_bw = icc_units_to_bps(agg_peak); + /* Set BKE_EN to 1 when Fixed, Regulator or Limiter Mode */ + val = 1; + } + + return regmap_update_bits(qp->regmap, M_BKE_EN_ADDR(qn->qos.qos_port), + M_BKE_EN_EN_BMASK, val); +} + +static int qcom_icc_noc_set_qos_priority(struct regmap *rmap, + struct qcom_icc_qos *qos) +{ + u32 val; + int rc; + + /* Must be updated one at a time, P1 first, P0 last */ + val = qos->areq_prio << NOC_QOS_PRIORITY_P1_SHIFT; + rc = regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port), + NOC_QOS_PRIORITY_MASK, val); + if (rc) + return rc; + + val = qos->prio_level << NOC_QOS_PRIORITY_P0_SHIFT; + return regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port), + NOC_QOS_PRIORITY_MASK, val); +} + +static int qcom_icc_set_noc_qos(struct icc_node *src, u64 max_bw) +{ + struct qcom_icc_provider *qp; + struct qcom_icc_node *qn; + struct icc_provider *provider; + u32 mode = NOC_QOS_MODE_BYPASS; + int rc = 0; + + qn = src->data; + provider = src->provider; + qp = to_qcom_provider(provider); + + if (qn->qos.qos_port < 0) { + dev_dbg(src->provider->dev, + "NoC QoS: Skipping %s: vote aggregated on parent.\n", + qn->name); + return 0; + } + + if (qn->qos.qos_mode != -1) + mode = qn->qos.qos_mode; + + if (mode == NOC_QOS_MODE_FIXED) { + dev_dbg(src->provider->dev, "NoC QoS: %s: Set Fixed mode\n", + qn->name); + rc = qcom_icc_noc_set_qos_priority(qp->regmap, &qn->qos); + if (rc) + return rc; + } else if (mode == NOC_QOS_MODE_BYPASS) { + dev_dbg(src->provider->dev, "NoC QoS: %s: Set Bypass mode\n", + qn->name); + } + + return regmap_update_bits(qp->regmap, + NOC_QOS_MODEn_ADDR(qn->qos.qos_port), + NOC_QOS_MODEn_MASK, mode); +} + +static int qcom_icc_qos_set(struct icc_node *node, u64 sum_bw) +{ + struct qcom_icc_provider *qp = to_qcom_provider(node->provider); + struct qcom_icc_node *qn = node->data; + + dev_dbg(node->provider->dev, "Setting QoS for %s\n", qn->name); + + if (qp->is_bimc_node) + return qcom_icc_set_bimc_qos(node, sum_bw, + (qn->qos.qos_mode == NOC_QOS_MODE_BYPASS)); + + return qcom_icc_set_noc_qos(node, sum_bw); +} + +static int qcom_icc_rpm_set(int mas_rpm_id, int slv_rpm_id, u64 sum_bw) +{ + int ret = 0; - /* send bandwidth request message to the RPM processor */ - if (qn->mas_rpm_id != -1) { + if (mas_rpm_id != -1) { ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE, RPM_BUS_MASTER_REQ, - qn->mas_rpm_id, + mas_rpm_id, sum_bw); if (ret) { pr_err("qcom_icc_rpm_smd_send mas %d error %d\n", - qn->mas_rpm_id, ret); + mas_rpm_id, ret); return ret; } } - if (qn->slv_rpm_id != -1) { + if (slv_rpm_id != -1) { ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE, RPM_BUS_SLAVE_REQ, - qn->slv_rpm_id, + slv_rpm_id, sum_bw); if (ret) { pr_err("qcom_icc_rpm_smd_send slv %d error %d\n", - qn->slv_rpm_id, ret); + slv_rpm_id, ret); return ret; } } + return ret; +} + +static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct qcom_icc_provider *qp; + struct qcom_icc_node *qn; + struct icc_provider *provider; + struct icc_node *n; + u64 sum_bw; + u64 max_peak_bw; + u64 rate; + u32 agg_avg = 0; + u32 agg_peak = 0; + int ret, i; + + qn = src->data; + provider = src->provider; + qp = to_qcom_provider(provider); + + list_for_each_entry(n, &provider->nodes, node_list) + provider->aggregate(n, 0, n->avg_bw, n->peak_bw, + &agg_avg, &agg_peak); + + sum_bw = icc_units_to_bps(agg_avg); + max_peak_bw = icc_units_to_bps(agg_peak); + + if (!qn->qos.ap_owned) { + /* send bandwidth request message to the RPM processor */ + ret = qcom_icc_rpm_set(qn->mas_rpm_id, qn->slv_rpm_id, sum_bw); + if (ret) + return ret; + } else if (qn->qos.qos_mode != -1) { + /* set bandwidth directly from the AP */ + ret = qcom_icc_qos_set(src, sum_bw); + if (ret) + return ret; + } + rate = max(sum_bw, max_peak_bw); do_div(rate, qn->buswidth); @@ -90,6 +261,10 @@ static const char * const bus_clocks[] = { "bus", "bus_a", }; +static const char * const bus_mm_clocks[] = { + "bus", "bus_a", "iface", +}; + int qnoc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -115,8 +290,13 @@ int qnoc_probe(struct platform_device *pdev) qnodes = desc->nodes; num_nodes = desc->num_nodes; - cds = bus_clocks; - cd_num = ARRAY_SIZE(bus_clocks); + if (desc->has_iface_clk) { + cds = bus_mm_clocks; + cd_num = ARRAY_SIZE(bus_mm_clocks); + } else { + cds = bus_clocks; + cd_num = ARRAY_SIZE(bus_clocks); + } qp = devm_kzalloc(dev, struct_size(qp, bus_clks, cd_num), GFP_KERNEL); if (!qp) @@ -131,6 +311,30 @@ int qnoc_probe(struct platform_device *pdev) qp->bus_clks[i].id = cds[i]; qp->num_clks = cd_num; + qp->is_bimc_node = desc->is_bimc_node; + + if (desc->regmap_cfg) { + struct resource *res; + void __iomem *mmio; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + mmio = devm_ioremap_resource(dev, res); + + if (IS_ERR(mmio)) { + dev_err(dev, "Cannot ioremap interconnect bus resource\n"); + return PTR_ERR(mmio); + } + + qp->regmap = devm_regmap_init_mmio(dev, mmio, desc->regmap_cfg); + if (IS_ERR(qp->regmap)) { + dev_err(dev, "Cannot regmap interconnect bus resource\n"); + return PTR_ERR(qp->regmap); + } + } + ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks); if (ret) return ret; diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h index f4b05c20c097..3cb57d8a20e6 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -9,7 +9,7 @@ #define RPM_BUS_MASTER_REQ 0x73616d62 #define RPM_BUS_SLAVE_REQ 0x766c7362 -#define QCOM_MAX_LINKS 12 +#define QCOM_MAX_LINKS 34 #define to_qcom_provider(_provider) \ container_of(_provider, struct qcom_icc_provider, provider) @@ -19,13 +19,35 @@ * @provider: generic interconnect provider * @bus_clks: the clk_bulk_data table of bus clocks * @num_clks: the total number of clk_bulk_data entries + * @is_bimc_node: indicates whether to use bimc specific setting + * @regmap: regmap for QoS registers read/write access */ struct qcom_icc_provider { struct icc_provider provider; int num_clks; + bool is_bimc_node; + struct regmap *regmap; struct clk_bulk_data bus_clks[]; }; +/** + * struct qcom_icc_qos - Qualcomm specific interconnect QoS parameters + * @areq_prio: node requests priority + * @prio_level: priority level for bus communication + * @limit_commands: activate/deactivate limiter mode during runtime + * @ap_owned: indicates if the node is owned by the AP or by the RPM + * @qos_mode: default qos mode for this node + * @qos_port: qos port number for finding qos registers of this node + */ +struct qcom_icc_qos { + u32 areq_prio; + u32 prio_level; + bool limit_commands; + bool ap_owned; + int qos_mode; + int qos_port; +}; + /** * struct qcom_icc_node - Qualcomm specific interconnect nodes * @name: the node name used in debugfs @@ -35,6 +57,7 @@ struct qcom_icc_provider { * @buswidth: width of the interconnect between a node and the bus (bytes) * @mas_rpm_id: RPM id for devices that are bus masters * @slv_rpm_id: RPM id for devices that are bus slaves + * @qos: NoC QoS setting parameters * @rate: current bus clock rate in Hz */ struct qcom_icc_node { @@ -45,12 +68,16 @@ struct qcom_icc_node { u16 buswidth; int mas_rpm_id; int slv_rpm_id; + struct qcom_icc_qos qos; u64 rate; }; struct qcom_icc_desc { struct qcom_icc_node **nodes; size_t num_nodes; + bool is_bimc_node; + bool has_iface_clk; + const struct regmap_config *regmap_cfg; }; #define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \ @@ -61,10 +88,36 @@ struct qcom_icc_desc { .buswidth = _buswidth, \ .mas_rpm_id = _mas_rpm_id, \ .slv_rpm_id = _slv_rpm_id, \ + .qos.ap_owned = false, \ + .qos.qos_mode = -1, \ + .qos.areq_prio = 0, \ + .qos.prio_level = 01, \ + .qos.qos_port = -1, \ + .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \ + .links = { __VA_ARGS__ }, \ + } + +#define DEFINE_QNODE_AP(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \ + _qos_mode, _qos_prio, _qos_port, ...) \ + static struct qcom_icc_node _name = { \ + .name = #_name, \ + .id = _id, \ + .buswidth = _buswidth, \ + .mas_rpm_id = _mas_rpm_id, \ + .slv_rpm_id = _slv_rpm_id, \ + .qos.ap_owned = true, \ + .qos.qos_mode = _qos_mode, \ + .qos.areq_prio = _qos_prio, \ + .qos.prio_level = _qos_prio, \ + .qos.qos_port = _qos_port, \ .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \ .links = { __VA_ARGS__ }, \ } +/* Valid for both NoC and BIMC */ +#define NOC_QOS_MODE_FIXED 0x0 +#define NOC_QOS_MODE_LIMITER 0x1 +#define NOC_QOS_MODE_BYPASS 0x2 int qnoc_probe(struct platform_device *pdev); int qnoc_remove(struct platform_device *pdev); diff --git a/drivers/interconnect/qcom/sdm660.c b/drivers/interconnect/qcom/sdm660.c index 632dbdd21915..5686865aabbb 100644 --- a/drivers/interconnect/qcom/sdm660.c +++ b/drivers/interconnect/qcom/sdm660.c @@ -17,39 +17,7 @@ #include #include "smd-rpm.h" - -#define RPM_BUS_MASTER_REQ 0x73616d62 -#define RPM_BUS_SLAVE_REQ 0x766c7362 - -/* BIMC QoS */ -#define M_BKE_REG_BASE(n) (0x300 + (0x4000 * n)) -#define M_BKE_EN_ADDR(n) (M_BKE_REG_BASE(n)) -#define M_BKE_HEALTH_CFG_ADDR(i, n) (M_BKE_REG_BASE(n) + 0x40 + (0x4 * i)) - -#define M_BKE_HEALTH_CFG_LIMITCMDS_MASK 0x80000000 -#define M_BKE_HEALTH_CFG_AREQPRIO_MASK 0x300 -#define M_BKE_HEALTH_CFG_PRIOLVL_MASK 0x3 -#define M_BKE_HEALTH_CFG_AREQPRIO_SHIFT 0x8 -#define M_BKE_HEALTH_CFG_LIMITCMDS_SHIFT 0x1f - -#define M_BKE_EN_EN_BMASK 0x1 - -/* Valid for both NoC and BIMC */ -#define NOC_QOS_MODE_FIXED 0x0 -#define NOC_QOS_MODE_LIMITER 0x1 -#define NOC_QOS_MODE_BYPASS 0x2 - -/* NoC QoS */ -#define NOC_PERM_MODE_FIXED 1 -#define NOC_PERM_MODE_BYPASS (1 << NOC_QOS_MODE_BYPASS) - -#define NOC_QOS_PRIORITYn_ADDR(n) (0x8 + (n * 0x1000)) -#define NOC_QOS_PRIORITY_MASK 0xf -#define NOC_QOS_PRIORITY_P1_SHIFT 0x2 -#define NOC_QOS_PRIORITY_P0_SHIFT 0x3 - -#define NOC_QOS_MODEn_ADDR(n) (0xc + (n * 0x1000)) -#define NOC_QOS_MODEn_MASK 0x3 +#include "icc-rpm.h" enum { SDM660_MASTER_IPA = 1, @@ -159,9 +127,6 @@ enum { SDM660_SNOC, }; -#define to_qcom_provider(_provider) \ - container_of(_provider, struct qcom_icc_provider, provider) - static const struct clk_bulk_data bus_clocks[] = { { .id = "bus" }, { .id = "bus_a" }, @@ -173,188 +138,103 @@ static const struct clk_bulk_data bus_mm_clocks[] = { { .id = "iface" }, }; -/** - * struct qcom_icc_provider - Qualcomm specific interconnect provider - * @provider: generic interconnect provider - * @bus_clks: the clk_bulk_data table of bus clocks - * @num_clks: the total number of clk_bulk_data entries - * @is_bimc_node: indicates whether to use bimc specific setting - * @regmap: regmap for QoS registers read/write access - * @mmio: NoC base iospace - */ -struct qcom_icc_provider { - struct icc_provider provider; - struct clk_bulk_data *bus_clks; - int num_clks; - bool is_bimc_node; - struct regmap *regmap; - void __iomem *mmio; -}; - -#define SDM660_MAX_LINKS 34 - -/** - * struct qcom_icc_qos - Qualcomm specific interconnect QoS parameters - * @areq_prio: node requests priority - * @prio_level: priority level for bus communication - * @limit_commands: activate/deactivate limiter mode during runtime - * @ap_owned: indicates if the node is owned by the AP or by the RPM - * @qos_mode: default qos mode for this node - * @qos_port: qos port number for finding qos registers of this node - */ -struct qcom_icc_qos { - u32 areq_prio; - u32 prio_level; - bool limit_commands; - bool ap_owned; - int qos_mode; - int qos_port; -}; - -/** - * struct qcom_icc_node - Qualcomm specific interconnect nodes - * @name: the node name used in debugfs - * @id: a unique node identifier - * @links: an array of nodes where we can go next while traversing - * @num_links: the total number of @links - * @buswidth: width of the interconnect between a node and the bus (bytes) - * @mas_rpm_id: RPM id for devices that are bus masters - * @slv_rpm_id: RPM id for devices that are bus slaves - * @qos: NoC QoS setting parameters - * @rate: current bus clock rate in Hz - */ -struct qcom_icc_node { - unsigned char *name; - u16 id; - u16 links[SDM660_MAX_LINKS]; - u16 num_links; - u16 buswidth; - int mas_rpm_id; - int slv_rpm_id; - struct qcom_icc_qos qos; - u64 rate; -}; - -struct qcom_icc_desc { - struct qcom_icc_node **nodes; - size_t num_nodes; - const struct regmap_config *regmap_cfg; -}; - -#define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \ - _ap_owned, _qos_mode, _qos_prio, _qos_port, ...) \ - static struct qcom_icc_node _name = { \ - .name = #_name, \ - .id = _id, \ - .buswidth = _buswidth, \ - .mas_rpm_id = _mas_rpm_id, \ - .slv_rpm_id = _slv_rpm_id, \ - .qos.ap_owned = _ap_owned, \ - .qos.qos_mode = _qos_mode, \ - .qos.areq_prio = _qos_prio, \ - .qos.prio_level = _qos_prio, \ - .qos.qos_port = _qos_port, \ - .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \ - .links = { __VA_ARGS__ }, \ - } - -DEFINE_QNODE(mas_ipa, SDM660_MASTER_IPA, 8, 59, -1, true, NOC_QOS_MODE_FIXED, 1, 3, SDM660_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(mas_cnoc_a2noc, SDM660_MASTER_CNOC_A2NOC, 8, 146, -1, true, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(mas_sdcc_1, SDM660_MASTER_SDCC_1, 8, 33, -1, false, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(mas_sdcc_2, SDM660_MASTER_SDCC_2, 8, 35, -1, false, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(mas_blsp_1, SDM660_MASTER_BLSP_1, 4, 41, -1, false, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(mas_blsp_2, SDM660_MASTER_BLSP_2, 4, 39, -1, false, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(mas_ufs, SDM660_MASTER_UFS, 8, 68, -1, true, NOC_QOS_MODE_FIXED, 1, 4, SDM660_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(mas_usb_hs, SDM660_MASTER_USB_HS, 8, 42, -1, true, NOC_QOS_MODE_FIXED, 1, 1, SDM660_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(mas_usb3, SDM660_MASTER_USB3, 8, 32, -1, true, NOC_QOS_MODE_FIXED, 1, 2, SDM660_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(mas_crypto, SDM660_MASTER_CRYPTO_C0, 8, 23, -1, true, NOC_QOS_MODE_FIXED, 1, 11, SDM660_SLAVE_A2NOC_SNOC); -DEFINE_QNODE(mas_gnoc_bimc, SDM660_MASTER_GNOC_BIMC, 4, 144, -1, true, NOC_QOS_MODE_FIXED, 0, 0, SDM660_SLAVE_EBI); -DEFINE_QNODE(mas_oxili, SDM660_MASTER_OXILI, 4, 6, -1, true, NOC_QOS_MODE_BYPASS, 0, 1, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI, SDM660_SLAVE_BIMC_SNOC); -DEFINE_QNODE(mas_mnoc_bimc, SDM660_MASTER_MNOC_BIMC, 4, 2, -1, true, NOC_QOS_MODE_BYPASS, 0, 2, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI, SDM660_SLAVE_BIMC_SNOC); -DEFINE_QNODE(mas_snoc_bimc, SDM660_MASTER_SNOC_BIMC, 4, 3, -1, false, -1, 0, -1, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI); -DEFINE_QNODE(mas_pimem, SDM660_MASTER_PIMEM, 4, 113, -1, true, NOC_QOS_MODE_FIXED, 1, 4, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI); -DEFINE_QNODE(mas_snoc_cnoc, SDM660_MASTER_SNOC_CNOC, 8, 52, -1, true, -1, 0, -1, SDM660_SLAVE_CLK_CTL, SDM660_SLAVE_QDSS_CFG, SDM660_SLAVE_QM_CFG, SDM660_SLAVE_SRVC_CNOC, SDM660_SLAVE_UFS_CFG, SDM660_SLAVE_TCSR, SDM660_SLAVE_A2NOC_SMMU_CFG, SDM660_SLAVE_SNOC_CFG, SDM660_SLAVE_TLMM_SOUTH, SDM660_SLAVE_MPM, SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, SDM660_SLAVE_SDCC_2, SDM660_SLAVE_SDCC_1, SDM660_SLAVE_SPDM, SDM660_SLAVE_PMIC_ARB, SDM660_SLAVE_PRNG, SDM660_SLAVE_MSS_CFG, SDM660_SLAVE_GPUSS_CFG, SDM660_SLAVE_IMEM_CFG, SDM660_SLAVE_USB3_0, SDM660_SLAVE_A2NOC_CFG, SDM660_SLAVE_TLMM_NORTH, SDM660_SLAVE_USB_HS, SDM660_SLAVE_PDM, SDM660_SLAVE_TLMM_CENTER, SDM660_SLAVE_AHB2PHY, SDM660_SLAVE_BLSP_2, SDM660_SLAVE_BLSP_1, SDM660_SLAVE_PIMEM_CFG, SDM660_SLAVE_GLM, SDM660_SLAVE_MESSAGE_RAM, SDM660_SLAVE_BIMC_CFG, SDM660_SLAVE_CNOC_MNOC_CFG); -DEFINE_QNODE(mas_qdss_dap, SDM660_MASTER_QDSS_DAP, 8, 49, -1, true, -1, 0, -1, SDM660_SLAVE_CLK_CTL, SDM660_SLAVE_QDSS_CFG, SDM660_SLAVE_QM_CFG, SDM660_SLAVE_SRVC_CNOC, SDM660_SLAVE_UFS_CFG, SDM660_SLAVE_TCSR, SDM660_SLAVE_A2NOC_SMMU_CFG, SDM660_SLAVE_SNOC_CFG, SDM660_SLAVE_TLMM_SOUTH, SDM660_SLAVE_MPM, SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, SDM660_SLAVE_SDCC_2, SDM660_SLAVE_SDCC_1, SDM660_SLAVE_SPDM, SDM660_SLAVE_PMIC_ARB, SDM660_SLAVE_PRNG, SDM660_SLAVE_MSS_CFG, SDM660_SLAVE_GPUSS_CFG, SDM660_SLAVE_IMEM_CFG, SDM660_SLAVE_USB3_0, SDM660_SLAVE_A2NOC_CFG, SDM660_SLAVE_TLMM_NORTH, SDM660_SLAVE_USB_HS, SDM660_SLAVE_PDM, SDM660_SLAVE_TLMM_CENTER, SDM660_SLAVE_AHB2PHY, SDM660_SLAVE_BLSP_2, SDM660_SLAVE_BLSP_1, SDM660_SLAVE_PIMEM_CFG, SDM660_SLAVE_GLM, SDM660_SLAVE_MESSAGE_RAM, SDM660_SLAVE_CNOC_A2NOC, SDM660_SLAVE_BIMC_CFG, SDM660_SLAVE_CNOC_MNOC_CFG); -DEFINE_QNODE(mas_apss_proc, SDM660_MASTER_APPS_PROC, 16, 0, -1, true, -1, 0, -1, SDM660_SLAVE_GNOC_SNOC, SDM660_SLAVE_GNOC_BIMC); -DEFINE_QNODE(mas_cnoc_mnoc_mmss_cfg, SDM660_MASTER_CNOC_MNOC_MMSS_CFG, 8, 4, -1, true, -1, 0, -1, SDM660_SLAVE_VENUS_THROTTLE_CFG, SDM660_SLAVE_VENUS_CFG, SDM660_SLAVE_CAMERA_THROTTLE_CFG, SDM660_SLAVE_SMMU_CFG, SDM660_SLAVE_CAMERA_CFG, SDM660_SLAVE_CSI_PHY_CFG, SDM660_SLAVE_DISPLAY_THROTTLE_CFG, SDM660_SLAVE_DISPLAY_CFG, SDM660_SLAVE_MMSS_CLK_CFG, SDM660_SLAVE_MNOC_MPU_CFG, SDM660_SLAVE_MISC_CFG, SDM660_SLAVE_MMSS_CLK_XPU_CFG); -DEFINE_QNODE(mas_cnoc_mnoc_cfg, SDM660_MASTER_CNOC_MNOC_CFG, 4, 5, -1, true, -1, 0, -1, SDM660_SLAVE_SRVC_MNOC); -DEFINE_QNODE(mas_cpp, SDM660_MASTER_CPP, 16, 115, -1, true, NOC_QOS_MODE_BYPASS, 0, 4, SDM660_SLAVE_MNOC_BIMC); -DEFINE_QNODE(mas_jpeg, SDM660_MASTER_JPEG, 16, 7, -1, true, NOC_QOS_MODE_BYPASS, 0, 6, SDM660_SLAVE_MNOC_BIMC); -DEFINE_QNODE(mas_mdp_p0, SDM660_MASTER_MDP_P0, 16, 8, -1, true, NOC_QOS_MODE_BYPASS, 0, 0, SDM660_SLAVE_MNOC_BIMC); /* vrail-comp???? */ -DEFINE_QNODE(mas_mdp_p1, SDM660_MASTER_MDP_P1, 16, 61, -1, true, NOC_QOS_MODE_BYPASS, 0, 1, SDM660_SLAVE_MNOC_BIMC); /* vrail-comp??? */ -DEFINE_QNODE(mas_venus, SDM660_MASTER_VENUS, 16, 9, -1, true, NOC_QOS_MODE_BYPASS, 0, 1, SDM660_SLAVE_MNOC_BIMC); -DEFINE_QNODE(mas_vfe, SDM660_MASTER_VFE, 16, 11, -1, true, NOC_QOS_MODE_BYPASS, 0, 5, SDM660_SLAVE_MNOC_BIMC); -DEFINE_QNODE(mas_qdss_etr, SDM660_MASTER_QDSS_ETR, 8, 31, -1, true, NOC_QOS_MODE_FIXED, 1, 1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IMEM, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_SNOC_BIMC); -DEFINE_QNODE(mas_qdss_bam, SDM660_MASTER_QDSS_BAM, 4, 19, -1, true, NOC_QOS_MODE_FIXED, 1, 0, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IMEM, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_SNOC_BIMC); -DEFINE_QNODE(mas_snoc_cfg, SDM660_MASTER_SNOC_CFG, 4, 20, -1, false, -1, 0, -1, SDM660_SLAVE_SRVC_SNOC); -DEFINE_QNODE(mas_bimc_snoc, SDM660_MASTER_BIMC_SNOC, 8, 21, -1, false, -1, 0, -1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IPA, SDM660_SLAVE_QDSS_STM, SDM660_SLAVE_LPASS, SDM660_SLAVE_HMSS, SDM660_SLAVE_CDSP, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_WLAN, SDM660_SLAVE_IMEM); -DEFINE_QNODE(mas_gnoc_snoc, SDM660_MASTER_GNOC_SNOC, 8, 150, -1, false, -1, 0, -1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IPA, SDM660_SLAVE_QDSS_STM, SDM660_SLAVE_LPASS, SDM660_SLAVE_HMSS, SDM660_SLAVE_CDSP, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_WLAN, SDM660_SLAVE_IMEM); -DEFINE_QNODE(mas_a2noc_snoc, SDM660_MASTER_A2NOC_SNOC, 16, 112, -1, false, -1, 0, -1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IPA, SDM660_SLAVE_QDSS_STM, SDM660_SLAVE_LPASS, SDM660_SLAVE_HMSS, SDM660_SLAVE_SNOC_BIMC, SDM660_SLAVE_CDSP, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_WLAN, SDM660_SLAVE_IMEM); -DEFINE_QNODE(slv_a2noc_snoc, SDM660_SLAVE_A2NOC_SNOC, 16, -1, 143, false, -1, 0, -1, SDM660_MASTER_A2NOC_SNOC); -DEFINE_QNODE(slv_ebi, SDM660_SLAVE_EBI, 4, -1, 0, false, -1, 0, -1, 0); -DEFINE_QNODE(slv_hmss_l3, SDM660_SLAVE_HMSS_L3, 4, -1, 160, false, -1, 0, -1, 0); -DEFINE_QNODE(slv_bimc_snoc, SDM660_SLAVE_BIMC_SNOC, 4, -1, 2, false, -1, 0, -1, SDM660_MASTER_BIMC_SNOC); -DEFINE_QNODE(slv_cnoc_a2noc, SDM660_SLAVE_CNOC_A2NOC, 8, -1, 208, true, -1, 0, -1, SDM660_MASTER_CNOC_A2NOC); -DEFINE_QNODE(slv_mpm, SDM660_SLAVE_MPM, 4, -1, 62, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_pmic_arb, SDM660_SLAVE_PMIC_ARB, 4, -1, 59, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_tlmm_north, SDM660_SLAVE_TLMM_NORTH, 8, -1, 214, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_tcsr, SDM660_SLAVE_TCSR, 4, -1, 50, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_pimem_cfg, SDM660_SLAVE_PIMEM_CFG, 4, -1, 167, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_imem_cfg, SDM660_SLAVE_IMEM_CFG, 4, -1, 54, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_message_ram, SDM660_SLAVE_MESSAGE_RAM, 4, -1, 55, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_glm, SDM660_SLAVE_GLM, 4, -1, 209, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_bimc_cfg, SDM660_SLAVE_BIMC_CFG, 4, -1, 56, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_prng, SDM660_SLAVE_PRNG, 4, -1, 44, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_spdm, SDM660_SLAVE_SPDM, 4, -1, 60, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_qdss_cfg, SDM660_SLAVE_QDSS_CFG, 4, -1, 63, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_cnoc_mnoc_cfg, SDM660_SLAVE_BLSP_1, 4, -1, 66, true, -1, 0, -1, SDM660_MASTER_CNOC_MNOC_CFG); -DEFINE_QNODE(slv_snoc_cfg, SDM660_SLAVE_SNOC_CFG, 4, -1, 70, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_qm_cfg, SDM660_SLAVE_QM_CFG, 4, -1, 212, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_clk_ctl, SDM660_SLAVE_CLK_CTL, 4, -1, 47, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_mss_cfg, SDM660_SLAVE_MSS_CFG, 4, -1, 48, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_tlmm_south, SDM660_SLAVE_TLMM_SOUTH, 4, -1, 217, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_ufs_cfg, SDM660_SLAVE_UFS_CFG, 4, -1, 92, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_a2noc_cfg, SDM660_SLAVE_A2NOC_CFG, 4, -1, 150, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_a2noc_smmu_cfg, SDM660_SLAVE_A2NOC_SMMU_CFG, 8, -1, 152, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_gpuss_cfg, SDM660_SLAVE_GPUSS_CFG, 8, -1, 11, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_ahb2phy, SDM660_SLAVE_AHB2PHY, 4, -1, 163, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_blsp_1, SDM660_SLAVE_BLSP_1, 4, -1, 39, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_sdcc_1, SDM660_SLAVE_SDCC_1, 4, -1, 31, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_sdcc_2, SDM660_SLAVE_SDCC_2, 4, -1, 33, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_tlmm_center, SDM660_SLAVE_TLMM_CENTER, 4, -1, 218, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_blsp_2, SDM660_SLAVE_BLSP_2, 4, -1, 37, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_pdm, SDM660_SLAVE_PDM, 4, -1, 41, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_cnoc_mnoc_mmss_cfg, SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, 8, -1, 58, true, -1, 0, -1, SDM660_MASTER_CNOC_MNOC_MMSS_CFG); -DEFINE_QNODE(slv_usb_hs, SDM660_SLAVE_USB_HS, 4, -1, 40, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_usb3_0, SDM660_SLAVE_USB3_0, 4, -1, 22, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_srvc_cnoc, SDM660_SLAVE_SRVC_CNOC, 4, -1, 76, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_gnoc_bimc, SDM660_SLAVE_GNOC_BIMC, 16, -1, 210, true, -1, 0, -1, SDM660_MASTER_GNOC_BIMC); -DEFINE_QNODE(slv_gnoc_snoc, SDM660_SLAVE_GNOC_SNOC, 8, -1, 211, true, -1, 0, -1, SDM660_MASTER_GNOC_SNOC); -DEFINE_QNODE(slv_camera_cfg, SDM660_SLAVE_CAMERA_CFG, 4, -1, 3, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_camera_throttle_cfg, SDM660_SLAVE_CAMERA_THROTTLE_CFG, 4, -1, 154, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_misc_cfg, SDM660_SLAVE_MISC_CFG, 4, -1, 8, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_venus_throttle_cfg, SDM660_SLAVE_VENUS_THROTTLE_CFG, 4, -1, 178, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_venus_cfg, SDM660_SLAVE_VENUS_CFG, 4, -1, 10, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_mmss_clk_xpu_cfg, SDM660_SLAVE_MMSS_CLK_XPU_CFG, 4, -1, 13, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_mmss_clk_cfg, SDM660_SLAVE_MMSS_CLK_CFG, 4, -1, 12, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_mnoc_mpu_cfg, SDM660_SLAVE_MNOC_MPU_CFG, 4, -1, 14, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_display_cfg, SDM660_SLAVE_DISPLAY_CFG, 4, -1, 4, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_csi_phy_cfg, SDM660_SLAVE_CSI_PHY_CFG, 4, -1, 224, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_display_throttle_cfg, SDM660_SLAVE_DISPLAY_THROTTLE_CFG, 4, -1, 156, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_smmu_cfg, SDM660_SLAVE_SMMU_CFG, 8, -1, 205, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_mnoc_bimc, SDM660_SLAVE_MNOC_BIMC, 16, -1, 16, true, -1, 0, -1, SDM660_MASTER_MNOC_BIMC); -DEFINE_QNODE(slv_srvc_mnoc, SDM660_SLAVE_SRVC_MNOC, 8, -1, 17, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_hmss, SDM660_SLAVE_HMSS, 8, -1, 20, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_lpass, SDM660_SLAVE_LPASS, 4, -1, 21, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_wlan, SDM660_SLAVE_WLAN, 4, -1, 206, false, -1, 0, -1, 0); -DEFINE_QNODE(slv_cdsp, SDM660_SLAVE_CDSP, 4, -1, 221, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_ipa, SDM660_SLAVE_IPA, 4, -1, 183, true, -1, 0, -1, 0); -DEFINE_QNODE(slv_snoc_bimc, SDM660_SLAVE_SNOC_BIMC, 16, -1, 24, false, -1, 0, -1, SDM660_MASTER_SNOC_BIMC); -DEFINE_QNODE(slv_snoc_cnoc, SDM660_SLAVE_SNOC_CNOC, 8, -1, 25, false, -1, 0, -1, SDM660_MASTER_SNOC_CNOC); -DEFINE_QNODE(slv_imem, SDM660_SLAVE_IMEM, 8, -1, 26, false, -1, 0, -1, 0); -DEFINE_QNODE(slv_pimem, SDM660_SLAVE_PIMEM, 8, -1, 166, false, -1, 0, -1, 0); -DEFINE_QNODE(slv_qdss_stm, SDM660_SLAVE_QDSS_STM, 4, -1, 30, false, -1, 0, -1, 0); -DEFINE_QNODE(slv_srvc_snoc, SDM660_SLAVE_SRVC_SNOC, 16, -1, 29, false, -1, 0, -1, 0); +DEFINE_QNODE_AP(mas_ipa, SDM660_MASTER_IPA, 8, 59, -1, NOC_QOS_MODE_FIXED, 1, 3, SDM660_SLAVE_A2NOC_SNOC); +DEFINE_QNODE_AP(mas_cnoc_a2noc, SDM660_MASTER_CNOC_A2NOC, 8, 146, -1, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(mas_sdcc_1, SDM660_MASTER_SDCC_1, 8, 33, -1, SDM660_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(mas_sdcc_2, SDM660_MASTER_SDCC_2, 8, 35, -1, SDM660_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(mas_blsp_1, SDM660_MASTER_BLSP_1, 4, 41, -1, SDM660_SLAVE_A2NOC_SNOC); +DEFINE_QNODE(mas_blsp_2, SDM660_MASTER_BLSP_2, 4, 39, -1, SDM660_SLAVE_A2NOC_SNOC); +DEFINE_QNODE_AP(mas_ufs, SDM660_MASTER_UFS, 8, 68, -1, NOC_QOS_MODE_FIXED, 1, 4, SDM660_SLAVE_A2NOC_SNOC); +DEFINE_QNODE_AP(mas_usb_hs, SDM660_MASTER_USB_HS, 8, 42, -1, NOC_QOS_MODE_FIXED, 1, 1, SDM660_SLAVE_A2NOC_SNOC); +DEFINE_QNODE_AP(mas_usb3, SDM660_MASTER_USB3, 8, 32, -1, NOC_QOS_MODE_FIXED, 1, 2, SDM660_SLAVE_A2NOC_SNOC); +DEFINE_QNODE_AP(mas_crypto, SDM660_MASTER_CRYPTO_C0, 8, 23, -1, NOC_QOS_MODE_FIXED, 1, 11, SDM660_SLAVE_A2NOC_SNOC); +DEFINE_QNODE_AP(mas_gnoc_bimc, SDM660_MASTER_GNOC_BIMC, 4, 144, -1, NOC_QOS_MODE_FIXED, 0, 0, SDM660_SLAVE_EBI); +DEFINE_QNODE_AP(mas_oxili, SDM660_MASTER_OXILI, 4, 6, -1, NOC_QOS_MODE_BYPASS, 0, 1, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI, SDM660_SLAVE_BIMC_SNOC); +DEFINE_QNODE_AP(mas_mnoc_bimc, SDM660_MASTER_MNOC_BIMC, 4, 2, -1, NOC_QOS_MODE_BYPASS, 0, 2, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI, SDM660_SLAVE_BIMC_SNOC); +DEFINE_QNODE(mas_snoc_bimc, SDM660_MASTER_SNOC_BIMC, 4, 3, -1, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI); +DEFINE_QNODE_AP(mas_pimem, SDM660_MASTER_PIMEM, 4, 113, -1, NOC_QOS_MODE_FIXED, 1, 4, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI); +DEFINE_QNODE_AP(mas_snoc_cnoc, SDM660_MASTER_SNOC_CNOC, 8, 52, -1, -1, 0, -1, SDM660_SLAVE_CLK_CTL, SDM660_SLAVE_QDSS_CFG, SDM660_SLAVE_QM_CFG, SDM660_SLAVE_SRVC_CNOC, SDM660_SLAVE_UFS_CFG, SDM660_SLAVE_TCSR, SDM660_SLAVE_A2NOC_SMMU_CFG, SDM660_SLAVE_SNOC_CFG, SDM660_SLAVE_TLMM_SOUTH, SDM660_SLAVE_MPM, SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, SDM660_SLAVE_SDCC_2, SDM660_SLAVE_SDCC_1, SDM660_SLAVE_SPDM, SDM660_SLAVE_PMIC_ARB, SDM660_SLAVE_PRNG, SDM660_SLAVE_MSS_CFG, SDM660_SLAVE_GPUSS_CFG, SDM660_SLAVE_IMEM_CFG, SDM660_SLAVE_USB3_0, SDM660_SLAVE_A2NOC_CFG, SDM660_SLAVE_TLMM_NORTH, SDM660_SLAVE_USB_HS, SDM660_SLAVE_PDM, SDM660_SLAVE_TLMM_CENTER, SDM660_SLAVE_AHB2PHY, SDM660_SLAVE_BLSP_2, SDM660_SLAVE_BLSP_1, SDM660_SLAVE_PIMEM_CFG, SDM660_SLAVE_GLM, SDM660_SLAVE_MESSAGE_RAM, SDM660_SLAVE_BIMC_CFG, SDM660_SLAVE_CNOC_MNOC_CFG); +DEFINE_QNODE_AP(mas_qdss_dap, SDM660_MASTER_QDSS_DAP, 8, 49, -1, -1, 0, -1, SDM660_SLAVE_CLK_CTL, SDM660_SLAVE_QDSS_CFG, SDM660_SLAVE_QM_CFG, SDM660_SLAVE_SRVC_CNOC, SDM660_SLAVE_UFS_CFG, SDM660_SLAVE_TCSR, SDM660_SLAVE_A2NOC_SMMU_CFG, SDM660_SLAVE_SNOC_CFG, SDM660_SLAVE_TLMM_SOUTH, SDM660_SLAVE_MPM, SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, SDM660_SLAVE_SDCC_2, SDM660_SLAVE_SDCC_1, SDM660_SLAVE_SPDM, SDM660_SLAVE_PMIC_ARB, SDM660_SLAVE_PRNG, SDM660_SLAVE_MSS_CFG, SDM660_SLAVE_GPUSS_CFG, SDM660_SLAVE_IMEM_CFG, SDM660_SLAVE_USB3_0, SDM660_SLAVE_A2NOC_CFG, SDM660_SLAVE_TLMM_NORTH, SDM660_SLAVE_USB_HS, SDM660_SLAVE_PDM, SDM660_SLAVE_TLMM_CENTER, SDM660_SLAVE_AHB2PHY, SDM660_SLAVE_BLSP_2, SDM660_SLAVE_BLSP_1, SDM660_SLAVE_PIMEM_CFG, SDM660_SLAVE_GLM, SDM660_SLAVE_MESSAGE_RAM, SDM660_SLAVE_CNOC_A2NOC, SDM660_SLAVE_BIMC_CFG, SDM660_SLAVE_CNOC_MNOC_CFG); +DEFINE_QNODE_AP(mas_apss_proc, SDM660_MASTER_APPS_PROC, 16, 0, -1, -1, 0, -1, SDM660_SLAVE_GNOC_SNOC, SDM660_SLAVE_GNOC_BIMC); +DEFINE_QNODE_AP(mas_cnoc_mnoc_mmss_cfg, SDM660_MASTER_CNOC_MNOC_MMSS_CFG, 8, 4, -1, -1, 0, -1, SDM660_SLAVE_VENUS_THROTTLE_CFG, SDM660_SLAVE_VENUS_CFG, SDM660_SLAVE_CAMERA_THROTTLE_CFG, SDM660_SLAVE_SMMU_CFG, SDM660_SLAVE_CAMERA_CFG, SDM660_SLAVE_CSI_PHY_CFG, SDM660_SLAVE_DISPLAY_THROTTLE_CFG, SDM660_SLAVE_DISPLAY_CFG, SDM660_SLAVE_MMSS_CLK_CFG, SDM660_SLAVE_MNOC_MPU_CFG, SDM660_SLAVE_MISC_CFG, SDM660_SLAVE_MMSS_CLK_XPU_CFG); +DEFINE_QNODE_AP(mas_cnoc_mnoc_cfg, SDM660_MASTER_CNOC_MNOC_CFG, 4, 5, -1, -1, 0, -1, SDM660_SLAVE_SRVC_MNOC); +DEFINE_QNODE_AP(mas_cpp, SDM660_MASTER_CPP, 16, 115, -1, NOC_QOS_MODE_BYPASS, 0, 4, SDM660_SLAVE_MNOC_BIMC); +DEFINE_QNODE_AP(mas_jpeg, SDM660_MASTER_JPEG, 16, 7, -1, NOC_QOS_MODE_BYPASS, 0, 6, SDM660_SLAVE_MNOC_BIMC); +DEFINE_QNODE_AP(mas_mdp_p0, SDM660_MASTER_MDP_P0, 16, 8, -1, NOC_QOS_MODE_BYPASS, 0, 0, SDM660_SLAVE_MNOC_BIMC); /* vrail-comp???? */ +DEFINE_QNODE_AP(mas_mdp_p1, SDM660_MASTER_MDP_P1, 16, 61, -1, NOC_QOS_MODE_BYPASS, 0, 1, SDM660_SLAVE_MNOC_BIMC); /* vrail-comp??? */ +DEFINE_QNODE_AP(mas_venus, SDM660_MASTER_VENUS, 16, 9, -1, NOC_QOS_MODE_BYPASS, 0, 1, SDM660_SLAVE_MNOC_BIMC); +DEFINE_QNODE_AP(mas_vfe, SDM660_MASTER_VFE, 16, 11, -1, NOC_QOS_MODE_BYPASS, 0, 5, SDM660_SLAVE_MNOC_BIMC); +DEFINE_QNODE_AP(mas_qdss_etr, SDM660_MASTER_QDSS_ETR, 8, 31, -1, NOC_QOS_MODE_FIXED, 1, 1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IMEM, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_SNOC_BIMC); +DEFINE_QNODE_AP(mas_qdss_bam, SDM660_MASTER_QDSS_BAM, 4, 19, -1, NOC_QOS_MODE_FIXED, 1, 0, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IMEM, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_SNOC_BIMC); +DEFINE_QNODE(mas_snoc_cfg, SDM660_MASTER_SNOC_CFG, 4, 20, -1, SDM660_SLAVE_SRVC_SNOC); +DEFINE_QNODE(mas_bimc_snoc, SDM660_MASTER_BIMC_SNOC, 8, 21, -1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IPA, SDM660_SLAVE_QDSS_STM, SDM660_SLAVE_LPASS, SDM660_SLAVE_HMSS, SDM660_SLAVE_CDSP, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_WLAN, SDM660_SLAVE_IMEM); +DEFINE_QNODE(mas_gnoc_snoc, SDM660_MASTER_GNOC_SNOC, 8, 150, -1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IPA, SDM660_SLAVE_QDSS_STM, SDM660_SLAVE_LPASS, SDM660_SLAVE_HMSS, SDM660_SLAVE_CDSP, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_WLAN, SDM660_SLAVE_IMEM); +DEFINE_QNODE(mas_a2noc_snoc, SDM660_MASTER_A2NOC_SNOC, 16, 112, -1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IPA, SDM660_SLAVE_QDSS_STM, SDM660_SLAVE_LPASS, SDM660_SLAVE_HMSS, SDM660_SLAVE_SNOC_BIMC, SDM660_SLAVE_CDSP, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_WLAN, SDM660_SLAVE_IMEM); +DEFINE_QNODE(slv_a2noc_snoc, SDM660_SLAVE_A2NOC_SNOC, 16, -1, 143, SDM660_MASTER_A2NOC_SNOC); +DEFINE_QNODE(slv_ebi, SDM660_SLAVE_EBI, 4, -1, 0, 0); +DEFINE_QNODE(slv_hmss_l3, SDM660_SLAVE_HMSS_L3, 4, -1, 160, 0); +DEFINE_QNODE(slv_bimc_snoc, SDM660_SLAVE_BIMC_SNOC, 4, -1, 2, SDM660_MASTER_BIMC_SNOC); +DEFINE_QNODE_AP(slv_cnoc_a2noc, SDM660_SLAVE_CNOC_A2NOC, 8, -1, 208, -1, 0, -1, SDM660_MASTER_CNOC_A2NOC); +DEFINE_QNODE_AP(slv_mpm, SDM660_SLAVE_MPM, 4, -1, 62, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_pmic_arb, SDM660_SLAVE_PMIC_ARB, 4, -1, 59, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_tlmm_north, SDM660_SLAVE_TLMM_NORTH, 8, -1, 214, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_tcsr, SDM660_SLAVE_TCSR, 4, -1, 50, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_pimem_cfg, SDM660_SLAVE_PIMEM_CFG, 4, -1, 167, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_imem_cfg, SDM660_SLAVE_IMEM_CFG, 4, -1, 54, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_message_ram, SDM660_SLAVE_MESSAGE_RAM, 4, -1, 55, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_glm, SDM660_SLAVE_GLM, 4, -1, 209, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_bimc_cfg, SDM660_SLAVE_BIMC_CFG, 4, -1, 56, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_prng, SDM660_SLAVE_PRNG, 4, -1, 44, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_spdm, SDM660_SLAVE_SPDM, 4, -1, 60, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_qdss_cfg, SDM660_SLAVE_QDSS_CFG, 4, -1, 63, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_cnoc_mnoc_cfg, SDM660_SLAVE_BLSP_1, 4, -1, 66, -1, 0, -1, SDM660_MASTER_CNOC_MNOC_CFG); +DEFINE_QNODE_AP(slv_snoc_cfg, SDM660_SLAVE_SNOC_CFG, 4, -1, 70, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_qm_cfg, SDM660_SLAVE_QM_CFG, 4, -1, 212, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_clk_ctl, SDM660_SLAVE_CLK_CTL, 4, -1, 47, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_mss_cfg, SDM660_SLAVE_MSS_CFG, 4, -1, 48, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_tlmm_south, SDM660_SLAVE_TLMM_SOUTH, 4, -1, 217, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_ufs_cfg, SDM660_SLAVE_UFS_CFG, 4, -1, 92, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_a2noc_cfg, SDM660_SLAVE_A2NOC_CFG, 4, -1, 150, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_a2noc_smmu_cfg, SDM660_SLAVE_A2NOC_SMMU_CFG, 8, -1, 152, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_gpuss_cfg, SDM660_SLAVE_GPUSS_CFG, 8, -1, 11, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_ahb2phy, SDM660_SLAVE_AHB2PHY, 4, -1, 163, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_blsp_1, SDM660_SLAVE_BLSP_1, 4, -1, 39, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_sdcc_1, SDM660_SLAVE_SDCC_1, 4, -1, 31, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_sdcc_2, SDM660_SLAVE_SDCC_2, 4, -1, 33, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_tlmm_center, SDM660_SLAVE_TLMM_CENTER, 4, -1, 218, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_blsp_2, SDM660_SLAVE_BLSP_2, 4, -1, 37, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_pdm, SDM660_SLAVE_PDM, 4, -1, 41, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_cnoc_mnoc_mmss_cfg, SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, 8, -1, 58, -1, 0, -1, SDM660_MASTER_CNOC_MNOC_MMSS_CFG); +DEFINE_QNODE_AP(slv_usb_hs, SDM660_SLAVE_USB_HS, 4, -1, 40, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_usb3_0, SDM660_SLAVE_USB3_0, 4, -1, 22, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_srvc_cnoc, SDM660_SLAVE_SRVC_CNOC, 4, -1, 76, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_gnoc_bimc, SDM660_SLAVE_GNOC_BIMC, 16, -1, 210, -1, 0, -1, SDM660_MASTER_GNOC_BIMC); +DEFINE_QNODE_AP(slv_gnoc_snoc, SDM660_SLAVE_GNOC_SNOC, 8, -1, 211, -1, 0, -1, SDM660_MASTER_GNOC_SNOC); +DEFINE_QNODE_AP(slv_camera_cfg, SDM660_SLAVE_CAMERA_CFG, 4, -1, 3, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_camera_throttle_cfg, SDM660_SLAVE_CAMERA_THROTTLE_CFG, 4, -1, 154, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_misc_cfg, SDM660_SLAVE_MISC_CFG, 4, -1, 8, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_venus_throttle_cfg, SDM660_SLAVE_VENUS_THROTTLE_CFG, 4, -1, 178, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_venus_cfg, SDM660_SLAVE_VENUS_CFG, 4, -1, 10, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_mmss_clk_xpu_cfg, SDM660_SLAVE_MMSS_CLK_XPU_CFG, 4, -1, 13, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_mmss_clk_cfg, SDM660_SLAVE_MMSS_CLK_CFG, 4, -1, 12, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_mnoc_mpu_cfg, SDM660_SLAVE_MNOC_MPU_CFG, 4, -1, 14, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_display_cfg, SDM660_SLAVE_DISPLAY_CFG, 4, -1, 4, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_csi_phy_cfg, SDM660_SLAVE_CSI_PHY_CFG, 4, -1, 224, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_display_throttle_cfg, SDM660_SLAVE_DISPLAY_THROTTLE_CFG, 4, -1, 156, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_smmu_cfg, SDM660_SLAVE_SMMU_CFG, 8, -1, 205, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_mnoc_bimc, SDM660_SLAVE_MNOC_BIMC, 16, -1, 16, -1, 0, -1, SDM660_MASTER_MNOC_BIMC); +DEFINE_QNODE_AP(slv_srvc_mnoc, SDM660_SLAVE_SRVC_MNOC, 8, -1, 17, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_hmss, SDM660_SLAVE_HMSS, 8, -1, 20, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_lpass, SDM660_SLAVE_LPASS, 4, -1, 21, -1, 0, -1, 0); +DEFINE_QNODE(slv_wlan, SDM660_SLAVE_WLAN, 4, -1, 206, 0); +DEFINE_QNODE_AP(slv_cdsp, SDM660_SLAVE_CDSP, 4, -1, 221, -1, 0, -1, 0); +DEFINE_QNODE_AP(slv_ipa, SDM660_SLAVE_IPA, 4, -1, 183, -1, 0, -1, 0); +DEFINE_QNODE(slv_snoc_bimc, SDM660_SLAVE_SNOC_BIMC, 16, -1, 24, SDM660_MASTER_SNOC_BIMC); +DEFINE_QNODE(slv_snoc_cnoc, SDM660_SLAVE_SNOC_CNOC, 8, -1, 25, SDM660_MASTER_SNOC_CNOC); +DEFINE_QNODE(slv_imem, SDM660_SLAVE_IMEM, 8, -1, 26, 0); +DEFINE_QNODE(slv_pimem, SDM660_SLAVE_PIMEM, 8, -1, 166, 0); +DEFINE_QNODE(slv_qdss_stm, SDM660_SLAVE_QDSS_STM, 4, -1, 30, 0); +DEFINE_QNODE(slv_srvc_snoc, SDM660_SLAVE_SRVC_SNOC, 16, -1, 29, 0); static struct qcom_icc_node *sdm660_a2noc_nodes[] = { [MASTER_IPA] = &mas_ipa, @@ -406,6 +286,7 @@ static const struct regmap_config sdm660_bimc_regmap_config = { static struct qcom_icc_desc sdm660_bimc = { .nodes = sdm660_bimc_nodes, .num_nodes = ARRAY_SIZE(sdm660_bimc_nodes), + .is_bimc_node = true, .regmap_cfg = &sdm660_bimc_regmap_config, }; @@ -518,6 +399,7 @@ static const struct regmap_config sdm660_mnoc_regmap_config = { static struct qcom_icc_desc sdm660_mnoc = { .nodes = sdm660_mnoc_nodes, .num_nodes = ARRAY_SIZE(sdm660_mnoc_nodes), + .has_iface_clk = true, .regmap_cfg = &sdm660_mnoc_regmap_config, }; @@ -555,350 +437,6 @@ static struct qcom_icc_desc sdm660_snoc = { .regmap_cfg = &sdm660_snoc_regmap_config, }; -static int qcom_icc_bimc_set_qos_health(struct regmap *rmap, - struct qcom_icc_qos *qos, - int regnum) -{ - u32 val; - u32 mask; - - val = qos->prio_level; - mask = M_BKE_HEALTH_CFG_PRIOLVL_MASK; - - val |= qos->areq_prio << M_BKE_HEALTH_CFG_AREQPRIO_SHIFT; - mask |= M_BKE_HEALTH_CFG_AREQPRIO_MASK; - - /* LIMITCMDS is not present on M_BKE_HEALTH_3 */ - if (regnum != 3) { - val |= qos->limit_commands << M_BKE_HEALTH_CFG_LIMITCMDS_SHIFT; - mask |= M_BKE_HEALTH_CFG_LIMITCMDS_MASK; - } - - return regmap_update_bits(rmap, - M_BKE_HEALTH_CFG_ADDR(regnum, qos->qos_port), - mask, val); -} - -static int qcom_icc_set_bimc_qos(struct icc_node *src, u64 max_bw, - bool bypass_mode) -{ - struct qcom_icc_provider *qp; - struct qcom_icc_node *qn; - struct icc_provider *provider; - u32 mode = NOC_QOS_MODE_BYPASS; - u32 val = 0; - int i, rc = 0; - - qn = src->data; - provider = src->provider; - qp = to_qcom_provider(provider); - - if (qn->qos.qos_mode != -1) - mode = qn->qos.qos_mode; - - /* QoS Priority: The QoS Health parameters are getting considered - * only if we are NOT in Bypass Mode. - */ - if (mode != NOC_QOS_MODE_BYPASS) { - for (i = 3; i >= 0; i--) { - rc = qcom_icc_bimc_set_qos_health(qp->regmap, - &qn->qos, i); - if (rc) - return rc; - } - - /* Set BKE_EN to 1 when Fixed, Regulator or Limiter Mode */ - val = 1; - } - - return regmap_update_bits(qp->regmap, M_BKE_EN_ADDR(qn->qos.qos_port), - M_BKE_EN_EN_BMASK, val); -} - -static int qcom_icc_noc_set_qos_priority(struct regmap *rmap, - struct qcom_icc_qos *qos) -{ - u32 val; - int rc; - - /* Must be updated one at a time, P1 first, P0 last */ - val = qos->areq_prio << NOC_QOS_PRIORITY_P1_SHIFT; - rc = regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port), - NOC_QOS_PRIORITY_MASK, val); - if (rc) - return rc; - - val = qos->prio_level << NOC_QOS_PRIORITY_P0_SHIFT; - return regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port), - NOC_QOS_PRIORITY_MASK, val); -} - -static int qcom_icc_set_noc_qos(struct icc_node *src, u64 max_bw) -{ - struct qcom_icc_provider *qp; - struct qcom_icc_node *qn; - struct icc_provider *provider; - u32 mode = NOC_QOS_MODE_BYPASS; - int rc = 0; - - qn = src->data; - provider = src->provider; - qp = to_qcom_provider(provider); - - if (qn->qos.qos_port < 0) { - dev_dbg(src->provider->dev, - "NoC QoS: Skipping %s: vote aggregated on parent.\n", - qn->name); - return 0; - } - - if (qn->qos.qos_mode != -1) - mode = qn->qos.qos_mode; - - if (mode == NOC_QOS_MODE_FIXED) { - dev_dbg(src->provider->dev, "NoC QoS: %s: Set Fixed mode\n", - qn->name); - rc = qcom_icc_noc_set_qos_priority(qp->regmap, &qn->qos); - if (rc) - return rc; - } else if (mode == NOC_QOS_MODE_BYPASS) { - dev_dbg(src->provider->dev, "NoC QoS: %s: Set Bypass mode\n", - qn->name); - } - - return regmap_update_bits(qp->regmap, - NOC_QOS_MODEn_ADDR(qn->qos.qos_port), - NOC_QOS_MODEn_MASK, mode); -} - -static int qcom_icc_qos_set(struct icc_node *node, u64 sum_bw) -{ - struct qcom_icc_provider *qp = to_qcom_provider(node->provider); - struct qcom_icc_node *qn = node->data; - - dev_dbg(node->provider->dev, "Setting QoS for %s\n", qn->name); - - if (qp->is_bimc_node) - return qcom_icc_set_bimc_qos(node, sum_bw, - (qn->qos.qos_mode == NOC_QOS_MODE_BYPASS)); - - return qcom_icc_set_noc_qos(node, sum_bw); -} - -static int qcom_icc_rpm_set(int mas_rpm_id, int slv_rpm_id, u64 sum_bw) -{ - int ret = 0; - - if (mas_rpm_id != -1) { - ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE, - RPM_BUS_MASTER_REQ, - mas_rpm_id, - sum_bw); - if (ret) { - pr_err("qcom_icc_rpm_smd_send mas %d error %d\n", - mas_rpm_id, ret); - return ret; - } - } - - if (slv_rpm_id != -1) { - ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE, - RPM_BUS_SLAVE_REQ, - slv_rpm_id, - sum_bw); - if (ret) { - pr_err("qcom_icc_rpm_smd_send slv %d error %d\n", - slv_rpm_id, ret); - return ret; - } - } - - return ret; -} - -static int qcom_icc_set(struct icc_node *src, struct icc_node *dst) -{ - struct qcom_icc_provider *qp; - struct qcom_icc_node *qn; - struct icc_provider *provider; - struct icc_node *n; - u64 sum_bw; - u64 max_peak_bw; - u64 rate; - u32 agg_avg = 0; - u32 agg_peak = 0; - int ret, i; - - qn = src->data; - provider = src->provider; - qp = to_qcom_provider(provider); - - list_for_each_entry(n, &provider->nodes, node_list) - provider->aggregate(n, 0, n->avg_bw, n->peak_bw, - &agg_avg, &agg_peak); - - sum_bw = icc_units_to_bps(agg_avg); - max_peak_bw = icc_units_to_bps(agg_peak); - - if (!qn->qos.ap_owned) { - /* send bandwidth request message to the RPM processor */ - ret = qcom_icc_rpm_set(qn->mas_rpm_id, qn->slv_rpm_id, sum_bw); - if (ret) - return ret; - } else if (qn->qos.qos_mode != -1) { - /* set bandwidth directly from the AP */ - ret = qcom_icc_qos_set(src, sum_bw); - if (ret) - return ret; - } - - rate = max(sum_bw, max_peak_bw); - - do_div(rate, qn->buswidth); - - if (qn->rate == rate) - return 0; - - for (i = 0; i < qp->num_clks; i++) { - ret = clk_set_rate(qp->bus_clks[i].clk, rate); - if (ret) { - pr_err("%s clk_set_rate error: %d\n", - qp->bus_clks[i].id, ret); - return ret; - } - } - - qn->rate = rate; - - return 0; -} - -static int qnoc_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - const struct qcom_icc_desc *desc; - struct icc_onecell_data *data; - struct icc_provider *provider; - struct qcom_icc_node **qnodes; - struct qcom_icc_provider *qp; - struct icc_node *node; - struct resource *res; - size_t num_nodes, i; - int ret; - - /* wait for the RPM proxy */ - if (!qcom_icc_rpm_smd_available()) - return -EPROBE_DEFER; - - desc = of_device_get_match_data(dev); - if (!desc) - return -EINVAL; - - qnodes = desc->nodes; - num_nodes = desc->num_nodes; - - qp = devm_kzalloc(dev, sizeof(*qp), GFP_KERNEL); - if (!qp) - return -ENOMEM; - - data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes), - GFP_KERNEL); - if (!data) - return -ENOMEM; - - if (of_device_is_compatible(dev->of_node, "qcom,sdm660-mnoc")) { - qp->bus_clks = devm_kmemdup(dev, bus_mm_clocks, - sizeof(bus_mm_clocks), GFP_KERNEL); - qp->num_clks = ARRAY_SIZE(bus_mm_clocks); - } else { - if (of_device_is_compatible(dev->of_node, "qcom,sdm660-bimc")) - qp->is_bimc_node = true; - - qp->bus_clks = devm_kmemdup(dev, bus_clocks, sizeof(bus_clocks), - GFP_KERNEL); - qp->num_clks = ARRAY_SIZE(bus_clocks); - } - if (!qp->bus_clks) - return -ENOMEM; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -ENODEV; - - qp->mmio = devm_ioremap_resource(dev, res); - if (IS_ERR(qp->mmio)) { - dev_err(dev, "Cannot ioremap interconnect bus resource\n"); - return PTR_ERR(qp->mmio); - } - - qp->regmap = devm_regmap_init_mmio(dev, qp->mmio, desc->regmap_cfg); - if (IS_ERR(qp->regmap)) { - dev_err(dev, "Cannot regmap interconnect bus resource\n"); - return PTR_ERR(qp->regmap); - } - - ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks); - if (ret) - return ret; - - ret = clk_bulk_prepare_enable(qp->num_clks, qp->bus_clks); - if (ret) - return ret; - - provider = &qp->provider; - INIT_LIST_HEAD(&provider->nodes); - provider->dev = dev; - provider->set = qcom_icc_set; - provider->aggregate = icc_std_aggregate; - provider->xlate = of_icc_xlate_onecell; - provider->data = data; - - ret = icc_provider_add(provider); - if (ret) { - dev_err(dev, "error adding interconnect provider: %d\n", ret); - clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks); - return ret; - } - - for (i = 0; i < num_nodes; i++) { - size_t j; - - node = icc_node_create(qnodes[i]->id); - if (IS_ERR(node)) { - ret = PTR_ERR(node); - goto err; - } - - node->name = qnodes[i]->name; - node->data = qnodes[i]; - icc_node_add(node, provider); - - for (j = 0; j < qnodes[i]->num_links; j++) - icc_link_create(node, qnodes[i]->links[j]); - - data->nodes[i] = node; - } - data->num_nodes = num_nodes; - platform_set_drvdata(pdev, qp); - - return 0; -err: - icc_nodes_remove(provider); - clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks); - icc_provider_del(provider); - - return ret; -} - -static int qnoc_remove(struct platform_device *pdev) -{ - struct qcom_icc_provider *qp = platform_get_drvdata(pdev); - - icc_nodes_remove(&qp->provider); - clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks); - return icc_provider_del(&qp->provider); -} - static const struct of_device_id sdm660_noc_of_match[] = { { .compatible = "qcom,sdm660-a2noc", .data = &sdm660_a2noc }, { .compatible = "qcom,sdm660-bimc", .data = &sdm660_bimc }, From patchwork Wed Aug 18 01:57:30 2021 Content-Type: text/plain; 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Tue, 17 Aug 2021 18:57:36 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH 3/5] interconnect: icc-rpm: add support for QoS reg offset Date: Wed, 18 Aug 2021 04:57:30 +0300 Message-Id: <20210818015732.1717810-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210818015732.1717810-1-dmitry.baryshkov@linaro.org> References: <20210818015732.1717810-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SDM660 driver expects to have QoS registers at the beginning of NoC address space (sdm660 platform shifts NoC base address). Add support for using QoS register offset, so that other platforms do not have to change existing device trees. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/icc-rpm.c | 24 ++++++++++++++---------- drivers/interconnect/qcom/icc-rpm.h | 3 +++ 2 files changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/interconnect/qcom/icc-rpm.c b/drivers/interconnect/qcom/icc-rpm.c index 05130e74364a..ea41783456b0 100644 --- a/drivers/interconnect/qcom/icc-rpm.c +++ b/drivers/interconnect/qcom/icc-rpm.c @@ -39,7 +39,7 @@ #define NOC_QOS_MODEn_ADDR(n) (0xc + (n * 0x1000)) #define NOC_QOS_MODEn_MASK 0x3 -static int qcom_icc_bimc_set_qos_health(struct regmap *rmap, +static int qcom_icc_bimc_set_qos_health(struct qcom_icc_provider *qp, struct qcom_icc_qos *qos, int regnum) { @@ -58,8 +58,8 @@ static int qcom_icc_bimc_set_qos_health(struct regmap *rmap, mask |= M_BKE_HEALTH_CFG_LIMITCMDS_MASK; } - return regmap_update_bits(rmap, - M_BKE_HEALTH_CFG_ADDR(regnum, qos->qos_port), + return regmap_update_bits(qp->regmap, + qp->qos_offset + M_BKE_HEALTH_CFG_ADDR(regnum, qos->qos_port), mask, val); } @@ -85,7 +85,7 @@ static int qcom_icc_set_bimc_qos(struct icc_node *src, u64 max_bw, */ if (mode != NOC_QOS_MODE_BYPASS) { for (i = 3; i >= 0; i--) { - rc = qcom_icc_bimc_set_qos_health(qp->regmap, + rc = qcom_icc_bimc_set_qos_health(qp, &qn->qos, i); if (rc) return rc; @@ -95,11 +95,12 @@ static int qcom_icc_set_bimc_qos(struct icc_node *src, u64 max_bw, val = 1; } - return regmap_update_bits(qp->regmap, M_BKE_EN_ADDR(qn->qos.qos_port), + return regmap_update_bits(qp->regmap, + qp->qos_offset + M_BKE_EN_ADDR(qn->qos.qos_port), M_BKE_EN_EN_BMASK, val); } -static int qcom_icc_noc_set_qos_priority(struct regmap *rmap, +static int qcom_icc_noc_set_qos_priority(struct qcom_icc_provider *qp, struct qcom_icc_qos *qos) { u32 val; @@ -107,13 +108,15 @@ static int qcom_icc_noc_set_qos_priority(struct regmap *rmap, /* Must be updated one at a time, P1 first, P0 last */ val = qos->areq_prio << NOC_QOS_PRIORITY_P1_SHIFT; - rc = regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port), + rc = regmap_update_bits(qp->regmap, + qp->qos_offset + NOC_QOS_PRIORITYn_ADDR(qos->qos_port), NOC_QOS_PRIORITY_MASK, val); if (rc) return rc; val = qos->prio_level << NOC_QOS_PRIORITY_P0_SHIFT; - return regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port), + return regmap_update_bits(qp->regmap, + qp->qos_offset + NOC_QOS_PRIORITYn_ADDR(qos->qos_port), NOC_QOS_PRIORITY_MASK, val); } @@ -142,7 +145,7 @@ static int qcom_icc_set_noc_qos(struct icc_node *src, u64 max_bw) if (mode == NOC_QOS_MODE_FIXED) { dev_dbg(src->provider->dev, "NoC QoS: %s: Set Fixed mode\n", qn->name); - rc = qcom_icc_noc_set_qos_priority(qp->regmap, &qn->qos); + rc = qcom_icc_noc_set_qos_priority(qp, &qn->qos); if (rc) return rc; } else if (mode == NOC_QOS_MODE_BYPASS) { @@ -151,7 +154,7 @@ static int qcom_icc_set_noc_qos(struct icc_node *src, u64 max_bw) } return regmap_update_bits(qp->regmap, - NOC_QOS_MODEn_ADDR(qn->qos.qos_port), + qp->qos_offset + NOC_QOS_MODEn_ADDR(qn->qos.qos_port), NOC_QOS_MODEn_MASK, mode); } @@ -312,6 +315,7 @@ int qnoc_probe(struct platform_device *pdev) qp->num_clks = cd_num; qp->is_bimc_node = desc->is_bimc_node; + qp->qos_offset = desc->qos_offset; if (desc->regmap_cfg) { struct resource *res; diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h index 3cb57d8a20e6..47070520fb08 100644 --- a/drivers/interconnect/qcom/icc-rpm.h +++ b/drivers/interconnect/qcom/icc-rpm.h @@ -20,6 +20,7 @@ * @bus_clks: the clk_bulk_data table of bus clocks * @num_clks: the total number of clk_bulk_data entries * @is_bimc_node: indicates whether to use bimc specific setting + * @qos_offset: offset to QoS registers * @regmap: regmap for QoS registers read/write access */ struct qcom_icc_provider { @@ -27,6 +28,7 @@ struct qcom_icc_provider { int num_clks; bool is_bimc_node; struct regmap *regmap; + unsigned int qos_offset; struct clk_bulk_data bus_clks[]; }; @@ -78,6 +80,7 @@ struct qcom_icc_desc { bool is_bimc_node; bool has_iface_clk; const struct regmap_config *regmap_cfg; + unsigned int qos_offset; }; #define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \ From patchwork Wed Aug 18 01:57:31 2021 Content-Type: text/plain; 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Tue, 17 Aug 2021 18:57:37 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Georgi Djakov Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH 4/5] interconnect: msm8916: add support for AP-owned nodes Date: Wed, 18 Aug 2021 04:57:31 +0300 Message-Id: <20210818015732.1717810-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210818015732.1717810-1-dmitry.baryshkov@linaro.org> References: <20210818015732.1717810-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Port support for AP-owned nodes from the downstream device tree. Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/msm8916.c | 70 +++++++++++++++++++++-------- 1 file changed, 51 insertions(+), 19 deletions(-) diff --git a/drivers/interconnect/qcom/msm8916.c b/drivers/interconnect/qcom/msm8916.c index fc0d48d2997a..680ec3190c23 100644 --- a/drivers/interconnect/qcom/msm8916.c +++ b/drivers/interconnect/qcom/msm8916.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -105,31 +106,31 @@ enum { MSM8916_SNOC_PNOC_SLV, }; -DEFINE_QNODE(bimc_snoc_mas, MSM8916_BIMC_SNOC_MAS, 8, -1, -1, MSM8916_BIMC_SNOC_SLV); -DEFINE_QNODE(bimc_snoc_slv, MSM8916_BIMC_SNOC_SLV, 8, -1, -1, MSM8916_SNOC_INT_0, MSM8916_SNOC_INT_1); -DEFINE_QNODE(mas_apss, MSM8916_MASTER_AMPSS_M0, 8, -1, -1, MSM8916_SLAVE_EBI_CH0, MSM8916_BIMC_SNOC_MAS, MSM8916_SLAVE_AMPSS_L2); +DEFINE_QNODE_AP(bimc_snoc_mas, MSM8916_BIMC_SNOC_MAS, 8, -1, -1, -1, 0, -1, MSM8916_BIMC_SNOC_SLV); +DEFINE_QNODE_AP(bimc_snoc_slv, MSM8916_BIMC_SNOC_SLV, 8, -1, -1, -1, 0, -1, MSM8916_SNOC_INT_0, MSM8916_SNOC_INT_1); +DEFINE_QNODE_AP(mas_apss, MSM8916_MASTER_AMPSS_M0, 8, -1, -1, NOC_QOS_MODE_FIXED, 0, 0, MSM8916_SLAVE_EBI_CH0, MSM8916_BIMC_SNOC_MAS, MSM8916_SLAVE_AMPSS_L2); DEFINE_QNODE(mas_audio, MSM8916_MASTER_LPASS, 4, -1, -1, MSM8916_PNOC_MAS_0); DEFINE_QNODE(mas_blsp_1, MSM8916_MASTER_BLSP_1, 4, -1, -1, MSM8916_PNOC_MAS_1); DEFINE_QNODE(mas_dehr, MSM8916_MASTER_DEHR, 4, -1, -1, MSM8916_PNOC_MAS_0); -DEFINE_QNODE(mas_gfx, MSM8916_MASTER_GRAPHICS_3D, 8, -1, -1, MSM8916_SLAVE_EBI_CH0, MSM8916_BIMC_SNOC_MAS, MSM8916_SLAVE_AMPSS_L2); -DEFINE_QNODE(mas_jpeg, MSM8916_MASTER_JPEG, 16, -1, -1, MSM8916_SNOC_MM_INT_0, MSM8916_SNOC_MM_INT_2); -DEFINE_QNODE(mas_mdp, MSM8916_MASTER_MDP_PORT0, 16, -1, -1, MSM8916_SNOC_MM_INT_0, MSM8916_SNOC_MM_INT_2); +DEFINE_QNODE_AP(mas_gfx, MSM8916_MASTER_GRAPHICS_3D, 8, -1, -1, NOC_QOS_MODE_FIXED, 0, 2, MSM8916_SLAVE_EBI_CH0, MSM8916_BIMC_SNOC_MAS, MSM8916_SLAVE_AMPSS_L2); +DEFINE_QNODE_AP(mas_jpeg, MSM8916_MASTER_JPEG, 16, -1, -1, NOC_QOS_MODE_BYPASS, 0, 6, MSM8916_SNOC_MM_INT_0, MSM8916_SNOC_MM_INT_2); +DEFINE_QNODE_AP(mas_mdp, MSM8916_MASTER_MDP_PORT0, 16, -1, -1, NOC_QOS_MODE_BYPASS, 0, 7, MSM8916_SNOC_MM_INT_0, MSM8916_SNOC_MM_INT_2); DEFINE_QNODE(mas_pcnoc_crypto_0, MSM8916_MASTER_CRYPTO_CORE0, 8, -1, -1, MSM8916_PNOC_INT_1); DEFINE_QNODE(mas_pcnoc_sdcc_1, MSM8916_MASTER_SDCC_1, 8, -1, -1, MSM8916_PNOC_INT_1); DEFINE_QNODE(mas_pcnoc_sdcc_2, MSM8916_MASTER_SDCC_2, 8, -1, -1, MSM8916_PNOC_INT_1); -DEFINE_QNODE(mas_qdss_bam, MSM8916_MASTER_QDSS_BAM, 8, -1, -1, MSM8916_SNOC_QDSS_INT); -DEFINE_QNODE(mas_qdss_etr, MSM8916_MASTER_QDSS_ETR, 8, -1, -1, MSM8916_SNOC_QDSS_INT); +DEFINE_QNODE_AP(mas_qdss_bam, MSM8916_MASTER_QDSS_BAM, 8, -1, -1, NOC_QOS_MODE_FIXED, 1, 11, MSM8916_SNOC_QDSS_INT); +DEFINE_QNODE_AP(mas_qdss_etr, MSM8916_MASTER_QDSS_ETR, 8, -1, -1, NOC_QOS_MODE_FIXED, 1, 10, MSM8916_SNOC_QDSS_INT); DEFINE_QNODE(mas_snoc_cfg, MSM8916_MASTER_SNOC_CFG, 4, -1, -1, MSM8916_SNOC_QDSS_INT); DEFINE_QNODE(mas_spdm, MSM8916_MASTER_SPDM, 4, -1, -1, MSM8916_PNOC_MAS_0); -DEFINE_QNODE(mas_tcu0, MSM8916_MASTER_TCU0, 8, -1, -1, MSM8916_SLAVE_EBI_CH0, MSM8916_BIMC_SNOC_MAS, MSM8916_SLAVE_AMPSS_L2); -DEFINE_QNODE(mas_tcu1, MSM8916_MASTER_TCU1, 8, -1, -1, MSM8916_SLAVE_EBI_CH0, MSM8916_BIMC_SNOC_MAS, MSM8916_SLAVE_AMPSS_L2); +DEFINE_QNODE_AP(mas_tcu0, MSM8916_MASTER_TCU0, 8, -1, -1, NOC_QOS_MODE_FIXED, 2, 5, MSM8916_SLAVE_EBI_CH0, MSM8916_BIMC_SNOC_MAS, MSM8916_SLAVE_AMPSS_L2); +DEFINE_QNODE_AP(mas_tcu1, MSM8916_MASTER_TCU1, 8, -1, -1, NOC_QOS_MODE_FIXED, 2, 6, MSM8916_SLAVE_EBI_CH0, MSM8916_BIMC_SNOC_MAS, MSM8916_SLAVE_AMPSS_L2); DEFINE_QNODE(mas_usb_hs, MSM8916_MASTER_USB_HS, 4, -1, -1, MSM8916_PNOC_MAS_1); -DEFINE_QNODE(mas_vfe, MSM8916_MASTER_VFE, 16, -1, -1, MSM8916_SNOC_MM_INT_1, MSM8916_SNOC_MM_INT_2); -DEFINE_QNODE(mas_video, MSM8916_MASTER_VIDEO_P0, 16, -1, -1, MSM8916_SNOC_MM_INT_0, MSM8916_SNOC_MM_INT_2); -DEFINE_QNODE(mm_int_0, MSM8916_SNOC_MM_INT_0, 16, -1, -1, MSM8916_SNOC_MM_INT_BIMC); -DEFINE_QNODE(mm_int_1, MSM8916_SNOC_MM_INT_1, 16, -1, -1, MSM8916_SNOC_MM_INT_BIMC); -DEFINE_QNODE(mm_int_2, MSM8916_SNOC_MM_INT_2, 16, -1, -1, MSM8916_SNOC_INT_0); -DEFINE_QNODE(mm_int_bimc, MSM8916_SNOC_MM_INT_BIMC, 16, -1, -1, MSM8916_SNOC_BIMC_1_MAS); +DEFINE_QNODE_AP(mas_vfe, MSM8916_MASTER_VFE, 16, -1, -1, NOC_QOS_MODE_BYPASS, 0, 9, MSM8916_SNOC_MM_INT_1, MSM8916_SNOC_MM_INT_2); +DEFINE_QNODE_AP(mas_video, MSM8916_MASTER_VIDEO_P0, 16, -1, -1, NOC_QOS_MODE_BYPASS, 0, 8, MSM8916_SNOC_MM_INT_0, MSM8916_SNOC_MM_INT_2); +DEFINE_QNODE_AP(mm_int_0, MSM8916_SNOC_MM_INT_0, 16, -1, -1, -1, 0, -1, MSM8916_SNOC_MM_INT_BIMC); +DEFINE_QNODE_AP(mm_int_1, MSM8916_SNOC_MM_INT_1, 16, -1, -1, -1, 0, -1, MSM8916_SNOC_MM_INT_BIMC); +DEFINE_QNODE_AP(mm_int_2, MSM8916_SNOC_MM_INT_2, 16, -1, -1, -1, 0, -1, MSM8916_SNOC_INT_0); +DEFINE_QNODE_AP(mm_int_bimc, MSM8916_SNOC_MM_INT_BIMC, 16, -1, -1, -1, 0, -1, MSM8916_SNOC_BIMC_1_MAS); DEFINE_QNODE(pcnoc_int_0, MSM8916_PNOC_INT_0, 8, -1, -1, MSM8916_PNOC_SNOC_MAS, MSM8916_PNOC_SLV_0, MSM8916_PNOC_SLV_1, MSM8916_PNOC_SLV_2, MSM8916_PNOC_SLV_3, MSM8916_PNOC_SLV_4, MSM8916_PNOC_SLV_8, MSM8916_PNOC_SLV_9); DEFINE_QNODE(pcnoc_int_1, MSM8916_PNOC_INT_1, 8, -1, -1, MSM8916_PNOC_SNOC_MAS); DEFINE_QNODE(pcnoc_m_0, MSM8916_PNOC_MAS_0, 8, -1, -1, MSM8916_PNOC_INT_0); @@ -143,7 +144,7 @@ DEFINE_QNODE(pcnoc_s_8, MSM8916_PNOC_SLV_8, 4, -1, -1, MSM8916_SLAVE_USB_HS, MSM DEFINE_QNODE(pcnoc_s_9, MSM8916_PNOC_SLV_9, 4, -1, -1, MSM8916_SLAVE_SDCC_2, MSM8916_SLAVE_LPASS, MSM8916_SLAVE_GRAPHICS_3D_CFG); DEFINE_QNODE(pcnoc_snoc_mas, MSM8916_PNOC_SNOC_MAS, 8, 29, -1, MSM8916_PNOC_SNOC_SLV); DEFINE_QNODE(pcnoc_snoc_slv, MSM8916_PNOC_SNOC_SLV, 8, -1, 45, MSM8916_SNOC_INT_0, MSM8916_SNOC_INT_BIMC, MSM8916_SNOC_INT_1); -DEFINE_QNODE(qdss_int, MSM8916_SNOC_QDSS_INT, 8, -1, -1, MSM8916_SNOC_INT_0, MSM8916_SNOC_INT_BIMC); +DEFINE_QNODE_AP(qdss_int, MSM8916_SNOC_QDSS_INT, 8, -1, -1, -1, 0, -1, MSM8916_SNOC_INT_0, MSM8916_SNOC_INT_BIMC); DEFINE_QNODE(slv_apps_l2, MSM8916_SLAVE_AMPSS_L2, 8, -1, -1, 0); DEFINE_QNODE(slv_apss, MSM8916_SLAVE_APSS, 4, -1, -1, 0); DEFINE_QNODE(slv_audio, MSM8916_SLAVE_LPASS, 4, -1, -1, 0); @@ -183,8 +184,8 @@ DEFINE_QNODE(slv_usb_hs, MSM8916_SLAVE_USB_HS, 4, -1, -1, 0); DEFINE_QNODE(slv_venus_cfg, MSM8916_SLAVE_VENUS_CFG, 4, -1, -1, 0); DEFINE_QNODE(snoc_bimc_0_mas, MSM8916_SNOC_BIMC_0_MAS, 8, 3, -1, MSM8916_SNOC_BIMC_0_SLV); DEFINE_QNODE(snoc_bimc_0_slv, MSM8916_SNOC_BIMC_0_SLV, 8, -1, 24, MSM8916_SLAVE_EBI_CH0); -DEFINE_QNODE(snoc_bimc_1_mas, MSM8916_SNOC_BIMC_1_MAS, 16, -1, -1, MSM8916_SNOC_BIMC_1_SLV); -DEFINE_QNODE(snoc_bimc_1_slv, MSM8916_SNOC_BIMC_1_SLV, 8, -1, -1, MSM8916_SLAVE_EBI_CH0); +DEFINE_QNODE_AP(snoc_bimc_1_mas, MSM8916_SNOC_BIMC_1_MAS, 16, -1, -1, -1, 0, -1, MSM8916_SNOC_BIMC_1_SLV); +DEFINE_QNODE_AP(snoc_bimc_1_slv, MSM8916_SNOC_BIMC_1_SLV, 8, -1, -1, -1, 0, -1, MSM8916_SLAVE_EBI_CH0); DEFINE_QNODE(snoc_int_0, MSM8916_SNOC_INT_0, 8, 99, 130, MSM8916_SLAVE_QDSS_STM, MSM8916_SLAVE_IMEM, MSM8916_SNOC_PNOC_MAS); DEFINE_QNODE(snoc_int_1, MSM8916_SNOC_INT_1, 8, -1, -1, MSM8916_SLAVE_APSS, MSM8916_SLAVE_CATS_128, MSM8916_SLAVE_OCMEM_64); DEFINE_QNODE(snoc_int_bimc, MSM8916_SNOC_INT_BIMC, 8, 101, 132, MSM8916_SNOC_BIMC_0_MAS); @@ -220,9 +221,19 @@ static struct qcom_icc_node *msm8916_snoc_nodes[] = { [SNOC_QDSS_INT] = &qdss_int, }; +static const struct regmap_config msm8916_snoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x14000, + .fast_io = true, +}; + static struct qcom_icc_desc msm8916_snoc = { .nodes = msm8916_snoc_nodes, .num_nodes = ARRAY_SIZE(msm8916_snoc_nodes), + .regmap_cfg = &msm8916_snoc_regmap_config, + .qos_offset = 0x7000, }; static struct qcom_icc_node *msm8916_bimc_nodes[] = { @@ -237,9 +248,20 @@ static struct qcom_icc_node *msm8916_bimc_nodes[] = { [SNOC_BIMC_1_SLV] = &snoc_bimc_1_slv, }; +static const struct regmap_config msm8916_bimc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x62000, + .fast_io = true, +}; + static struct qcom_icc_desc msm8916_bimc = { .nodes = msm8916_bimc_nodes, .num_nodes = ARRAY_SIZE(msm8916_bimc_nodes), + .is_bimc_node = true, + .regmap_cfg = &msm8916_bimc_regmap_config, + .qos_offset = 0x8000, }; static struct qcom_icc_node *msm8916_pcnoc_nodes[] = { @@ -295,9 +317,19 @@ static struct qcom_icc_node *msm8916_pcnoc_nodes[] = { [SNOC_PCNOC_SLV] = &snoc_pcnoc_slv, }; +static const struct regmap_config msm8916_pcnoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x11000, + .fast_io = true, +}; + static struct qcom_icc_desc msm8916_pcnoc = { .nodes = msm8916_pcnoc_nodes, .num_nodes = ARRAY_SIZE(msm8916_pcnoc_nodes), + .regmap_cfg = &msm8916_pcnoc_regmap_config, + .qos_offset = 0x7000, }; static const struct of_device_id msm8916_noc_of_match[] = { From patchwork Wed Aug 18 01:57:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 498879 Delivered-To: patch@linaro.org Received: by 2002:a02:6f15:0:0:0:0:0 with SMTP id x21csp191015jab; Tue, 17 Aug 2021 18:57:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxPM/wnGaqakjr70qbpwGIM/4/kwucr5b1wFR/OYtYX8WkdtruPPKoA7Lzc08cgZOzinPdQ X-Received: by 2002:a17:906:6dcb:: with SMTP id j11mr7087999ejt.202.1629251866155; Tue, 17 Aug 2021 18:57:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1629251866; cv=none; d=google.com; s=arc-20160816; b=BiuNVT+VF940wuB6EcAjyBFcic+MGeuVu5IsHcn2QLzfLDjZ8us8xZ0xIfvrDbhXvj /4TJQ+kBg37out9AexjGuTUOEx0foWyl32zCDk7V51sdKnLObZXfFGQjZhYL7n099wTc N/O17CC7mr0+gRQao3Qg9TRXZC7co40urFTRwajuL4hbz+dfNWxSwl23VtBRBCK3wIqa Imx6bpLt5qLU+UyKCDprOAvWdlgsa/dqOOOUK4iTWsJor1xZLfoBHrVZ6kB5wo5nCEzD Fbj9GqQgw4PZH3NhJ49+qYYhfdIh4wrA7pbfMpzLA3yc4Bcx4Bz1zYBhhg85BNWG5Eyx 2qDA== ARC-Message-Signature: i=1; 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Signed-off-by: Dmitry Baryshkov --- drivers/interconnect/qcom/msm8939.c | 82 ++++++++++++++++++++++------- 1 file changed, 62 insertions(+), 20 deletions(-) -- 2.32.0 diff --git a/drivers/interconnect/qcom/msm8939.c b/drivers/interconnect/qcom/msm8939.c index 4a5a2ec64960..55c33a9044c5 100644 --- a/drivers/interconnect/qcom/msm8939.c +++ b/drivers/interconnect/qcom/msm8939.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -110,32 +111,32 @@ enum { MSM8939_SNOC_PNOC_SLV, }; -DEFINE_QNODE(bimc_snoc_mas, MSM8939_BIMC_SNOC_MAS, 8, -1, -1, MSM8939_BIMC_SNOC_SLV); +DEFINE_QNODE_AP(bimc_snoc_mas, MSM8939_BIMC_SNOC_MAS, 8, -1, -1, -1, 0, -1, MSM8939_BIMC_SNOC_SLV); DEFINE_QNODE(bimc_snoc_slv, MSM8939_BIMC_SNOC_SLV, 16, -1, 2, MSM8939_SNOC_INT_0, MSM8939_SNOC_INT_1); -DEFINE_QNODE(mas_apss, MSM8939_MASTER_AMPSS_M0, 16, -1, -1, MSM8939_SLAVE_EBI_CH0, MSM8939_BIMC_SNOC_MAS, MSM8939_SLAVE_AMPSS_L2); +DEFINE_QNODE_AP(mas_apss, MSM8939_MASTER_AMPSS_M0, 16, -1, -1, NOC_QOS_MODE_FIXED, 0, 0, MSM8939_SLAVE_EBI_CH0, MSM8939_BIMC_SNOC_MAS, MSM8939_SLAVE_AMPSS_L2); DEFINE_QNODE(mas_audio, MSM8939_MASTER_LPASS, 4, -1, -1, MSM8939_PNOC_MAS_0); DEFINE_QNODE(mas_blsp_1, MSM8939_MASTER_BLSP_1, 4, -1, -1, MSM8939_PNOC_MAS_1); DEFINE_QNODE(mas_dehr, MSM8939_MASTER_DEHR, 4, -1, -1, MSM8939_PNOC_MAS_0); -DEFINE_QNODE(mas_gfx, MSM8939_MASTER_GRAPHICS_3D, 16, -1, -1, MSM8939_SLAVE_EBI_CH0, MSM8939_BIMC_SNOC_MAS, MSM8939_SLAVE_AMPSS_L2); -DEFINE_QNODE(mas_jpeg, MSM8939_MASTER_JPEG, 16, -1, -1, MSM8939_SNOC_MM_INT_0, MSM8939_SNOC_MM_INT_2); -DEFINE_QNODE(mas_mdp0, MSM8939_MASTER_MDP_PORT0, 16, -1, -1, MSM8939_SNOC_MM_INT_1, MSM8939_SNOC_MM_INT_2); -DEFINE_QNODE(mas_mdp1, MSM8939_MASTER_MDP_PORT1, 16, -1, -1, MSM8939_SNOC_MM_INT_0, MSM8939_SNOC_MM_INT_2); -DEFINE_QNODE(mas_cpp, MSM8939_MASTER_CPP, 16, -1, -1, MSM8939_SNOC_MM_INT_0, MSM8939_SNOC_MM_INT_2); +DEFINE_QNODE_AP(mas_gfx, MSM8939_MASTER_GRAPHICS_3D, 16, -1, -1, NOC_QOS_MODE_FIXED, 0, 2, MSM8939_SLAVE_EBI_CH0, MSM8939_BIMC_SNOC_MAS, MSM8939_SLAVE_AMPSS_L2); +DEFINE_QNODE_AP(mas_jpeg, MSM8939_MASTER_JPEG, 16, -1, -1, NOC_QOS_MODE_BYPASS, 0, 6, MSM8939_SNOC_MM_INT_0, MSM8939_SNOC_MM_INT_2); +DEFINE_QNODE_AP(mas_mdp0, MSM8939_MASTER_MDP_PORT0, 16, -1, -1, NOC_QOS_MODE_BYPASS, 0, 7, MSM8939_SNOC_MM_INT_1, MSM8939_SNOC_MM_INT_2); +DEFINE_QNODE_AP(mas_mdp1, MSM8939_MASTER_MDP_PORT1, 16, -1, -1, NOC_QOS_MODE_BYPASS, 0, 13, MSM8939_SNOC_MM_INT_0, MSM8939_SNOC_MM_INT_2); +DEFINE_QNODE_AP(mas_cpp, MSM8939_MASTER_CPP, 16, -1, -1, NOC_QOS_MODE_BYPASS, 0, 12, MSM8939_SNOC_MM_INT_0, MSM8939_SNOC_MM_INT_2); DEFINE_QNODE(mas_pcnoc_crypto_0, MSM8939_MASTER_CRYPTO_CORE0, 8, -1, -1, MSM8939_PNOC_INT_1); DEFINE_QNODE(mas_pcnoc_sdcc_1, MSM8939_MASTER_SDCC_1, 8, -1, -1, MSM8939_PNOC_INT_1); DEFINE_QNODE(mas_pcnoc_sdcc_2, MSM8939_MASTER_SDCC_2, 8, -1, -1, MSM8939_PNOC_INT_1); -DEFINE_QNODE(mas_qdss_bam, MSM8939_MASTER_QDSS_BAM, 8, -1, -1, MSM8939_SNOC_QDSS_INT); -DEFINE_QNODE(mas_qdss_etr, MSM8939_MASTER_QDSS_ETR, 8, -1, -1, MSM8939_SNOC_QDSS_INT); +DEFINE_QNODE_AP(mas_qdss_bam, MSM8939_MASTER_QDSS_BAM, 8, -1, -1, NOC_QOS_MODE_FIXED, 1, 11, MSM8939_SNOC_QDSS_INT); +DEFINE_QNODE_AP(mas_qdss_etr, MSM8939_MASTER_QDSS_ETR, 8, -1, -1, NOC_QOS_MODE_FIXED, 1, 10, MSM8939_SNOC_QDSS_INT); DEFINE_QNODE(mas_snoc_cfg, MSM8939_MASTER_SNOC_CFG, 4, -1, -1, MSM8939_SLAVE_SRVC_SNOC); DEFINE_QNODE(mas_spdm, MSM8939_MASTER_SPDM, 4, -1, -1, MSM8939_PNOC_MAS_0); -DEFINE_QNODE(mas_tcu0, MSM8939_MASTER_TCU0, 16, -1, -1, MSM8939_SLAVE_EBI_CH0, MSM8939_BIMC_SNOC_MAS, MSM8939_SLAVE_AMPSS_L2); +DEFINE_QNODE_AP(mas_tcu0, MSM8939_MASTER_TCU0, 16, -1, -1, NOC_QOS_MODE_FIXED, 2, 6, MSM8939_SLAVE_EBI_CH0, MSM8939_BIMC_SNOC_MAS, MSM8939_SLAVE_AMPSS_L2); DEFINE_QNODE(mas_usb_hs1, MSM8939_MASTER_USB_HS1, 4, -1, -1, MSM8939_PNOC_MAS_1); DEFINE_QNODE(mas_usb_hs2, MSM8939_MASTER_USB_HS2, 4, -1, -1, MSM8939_PNOC_MAS_1); -DEFINE_QNODE(mas_vfe, MSM8939_MASTER_VFE, 16, -1, -1, MSM8939_SNOC_MM_INT_1, MSM8939_SNOC_MM_INT_2); -DEFINE_QNODE(mas_video, MSM8939_MASTER_VIDEO_P0, 16, -1, -1, MSM8939_SNOC_MM_INT_0, MSM8939_SNOC_MM_INT_2); -DEFINE_QNODE(mm_int_0, MSM8939_SNOC_MM_INT_0, 16, -1, -1, MSM8939_SNOC_BIMC_2_MAS); -DEFINE_QNODE(mm_int_1, MSM8939_SNOC_MM_INT_1, 16, -1, -1, MSM8939_SNOC_BIMC_1_MAS); -DEFINE_QNODE(mm_int_2, MSM8939_SNOC_MM_INT_2, 16, -1, -1, MSM8939_SNOC_INT_0); +DEFINE_QNODE_AP(mas_vfe, MSM8939_MASTER_VFE, 16, -1, -1, NOC_QOS_MODE_BYPASS, 0, 9, MSM8939_SNOC_MM_INT_1, MSM8939_SNOC_MM_INT_2); +DEFINE_QNODE_AP(mas_video, MSM8939_MASTER_VIDEO_P0, 16, -1, -1, NOC_QOS_MODE_BYPASS, 0, 8, MSM8939_SNOC_MM_INT_0, MSM8939_SNOC_MM_INT_2); +DEFINE_QNODE_AP(mm_int_0, MSM8939_SNOC_MM_INT_0, 16, -1, -1, -1, 0, -1, MSM8939_SNOC_BIMC_2_MAS); +DEFINE_QNODE_AP(mm_int_1, MSM8939_SNOC_MM_INT_1, 16, -1, -1, -1, 0, -1, MSM8939_SNOC_BIMC_1_MAS); +DEFINE_QNODE_AP(mm_int_2, MSM8939_SNOC_MM_INT_2, 16, -1, -1, -1, 0, -1, MSM8939_SNOC_INT_0); DEFINE_QNODE(pcnoc_int_0, MSM8939_PNOC_INT_0, 8, -1, -1, MSM8939_PNOC_SNOC_MAS, MSM8939_PNOC_SLV_0, MSM8939_PNOC_SLV_1, MSM8939_PNOC_SLV_2, MSM8939_PNOC_SLV_3, MSM8939_PNOC_SLV_4, MSM8939_PNOC_SLV_8, MSM8939_PNOC_SLV_9); DEFINE_QNODE(pcnoc_int_1, MSM8939_PNOC_INT_1, 8, -1, -1, MSM8939_PNOC_SNOC_MAS); DEFINE_QNODE(pcnoc_m_0, MSM8939_PNOC_MAS_0, 8, -1, -1, MSM8939_PNOC_INT_0); @@ -149,7 +150,7 @@ DEFINE_QNODE(pcnoc_s_8, MSM8939_PNOC_SLV_8, 4, -1, -1, MSM8939_SLAVE_USB_HS1, MS DEFINE_QNODE(pcnoc_s_9, MSM8939_PNOC_SLV_9, 4, -1, -1, MSM8939_SLAVE_SDCC_2, MSM8939_SLAVE_LPASS, MSM8939_SLAVE_USB_HS2); DEFINE_QNODE(pcnoc_snoc_mas, MSM8939_PNOC_SNOC_MAS, 8, 29, -1, MSM8939_PNOC_SNOC_SLV); DEFINE_QNODE(pcnoc_snoc_slv, MSM8939_PNOC_SNOC_SLV, 8, -1, 45, MSM8939_SNOC_INT_0, MSM8939_SNOC_INT_BIMC, MSM8939_SNOC_INT_1); -DEFINE_QNODE(qdss_int, MSM8939_SNOC_QDSS_INT, 8, -1, -1, MSM8939_SNOC_INT_0, MSM8939_SNOC_INT_BIMC); +DEFINE_QNODE_AP(qdss_int, MSM8939_SNOC_QDSS_INT, 8, -1, -1, -1, 0, -1, MSM8939_SNOC_INT_0, MSM8939_SNOC_INT_BIMC); DEFINE_QNODE(slv_apps_l2, MSM8939_SLAVE_AMPSS_L2, 16, -1, -1, 0); DEFINE_QNODE(slv_apss, MSM8939_SLAVE_APSS, 4, -1, -1, 0); DEFINE_QNODE(slv_audio, MSM8939_SLAVE_LPASS, 4, -1, -1, 0); @@ -188,12 +189,12 @@ DEFINE_QNODE(slv_tlmm, MSM8939_SLAVE_TLMM, 4, -1, -1, 0); DEFINE_QNODE(slv_usb_hs1, MSM8939_SLAVE_USB_HS1, 4, -1, -1, 0); DEFINE_QNODE(slv_usb_hs2, MSM8939_SLAVE_USB_HS2, 4, -1, -1, 0); DEFINE_QNODE(slv_venus_cfg, MSM8939_SLAVE_VENUS_CFG, 4, -1, -1, 0); -DEFINE_QNODE(snoc_bimc_0_mas, MSM8939_SNOC_BIMC_0_MAS, 16, -1, -1, MSM8939_SNOC_BIMC_0_SLV); -DEFINE_QNODE(snoc_bimc_0_slv, MSM8939_SNOC_BIMC_0_SLV, 16, -1, -1, MSM8939_SLAVE_EBI_CH0); +DEFINE_QNODE_AP(snoc_bimc_0_mas, MSM8939_SNOC_BIMC_0_MAS, 16, -1, -1, -1, 0, -1, MSM8939_SNOC_BIMC_0_SLV); +DEFINE_QNODE_AP(snoc_bimc_0_slv, MSM8939_SNOC_BIMC_0_SLV, 16, -1, -1, -1, 0, -1, MSM8939_SLAVE_EBI_CH0); DEFINE_QNODE(snoc_bimc_1_mas, MSM8939_SNOC_BIMC_1_MAS, 16, 76, -1, MSM8939_SNOC_BIMC_1_SLV); DEFINE_QNODE(snoc_bimc_1_slv, MSM8939_SNOC_BIMC_1_SLV, 16, -1, 104, MSM8939_SLAVE_EBI_CH0); -DEFINE_QNODE(snoc_bimc_2_mas, MSM8939_SNOC_BIMC_2_MAS, 16, -1, -1, MSM8939_SNOC_BIMC_2_SLV); -DEFINE_QNODE(snoc_bimc_2_slv, MSM8939_SNOC_BIMC_2_SLV, 16, -1, -1, MSM8939_SLAVE_EBI_CH0); +DEFINE_QNODE_AP(snoc_bimc_2_mas, MSM8939_SNOC_BIMC_2_MAS, 16, -1, -1, -1, 0, -1, MSM8939_SNOC_BIMC_2_SLV); +DEFINE_QNODE_AP(snoc_bimc_2_slv, MSM8939_SNOC_BIMC_2_SLV, 16, -1, -1, -1, 0, -1, MSM8939_SLAVE_EBI_CH0); DEFINE_QNODE(snoc_int_0, MSM8939_SNOC_INT_0, 8, 99, 130, MSM8939_SLAVE_QDSS_STM, MSM8939_SLAVE_IMEM, MSM8939_SNOC_PNOC_MAS); DEFINE_QNODE(snoc_int_1, MSM8939_SNOC_INT_1, 8, -1, -1, MSM8939_SLAVE_APSS, MSM8939_SLAVE_CATS_128, MSM8939_SLAVE_OCMEM_64); DEFINE_QNODE(snoc_int_bimc, MSM8939_SNOC_INT_BIMC, 8, 101, 132, MSM8939_SNOC_BIMC_1_MAS); @@ -222,9 +223,19 @@ static struct qcom_icc_node *msm8939_snoc_nodes[] = { [SNOC_QDSS_INT] = &qdss_int, }; +static const struct regmap_config msm8939_snoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x14080, + .fast_io = true, +}; + static struct qcom_icc_desc msm8939_snoc = { .nodes = msm8939_snoc_nodes, .num_nodes = ARRAY_SIZE(msm8939_snoc_nodes), + .regmap_cfg = &msm8939_snoc_regmap_config, + .qos_offset = 0x7000, }; static struct qcom_icc_node *msm8939_snoc_mm_nodes[] = { @@ -239,9 +250,19 @@ static struct qcom_icc_node *msm8939_snoc_mm_nodes[] = { [SNOC_MM_INT_2] = &mm_int_2, }; +static const struct regmap_config msm8939_snoc_mm_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x14080, + .fast_io = true, +}; + static struct qcom_icc_desc msm8939_snoc_mm = { .nodes = msm8939_snoc_mm_nodes, .num_nodes = ARRAY_SIZE(msm8939_snoc_mm_nodes), + .regmap_cfg = &msm8939_snoc_mm_regmap_config, + .qos_offset = 0x7000, }; static struct qcom_icc_node *msm8939_bimc_nodes[] = { @@ -256,9 +277,20 @@ static struct qcom_icc_node *msm8939_bimc_nodes[] = { [SNOC_BIMC_2_SLV] = &snoc_bimc_2_slv, }; +static const struct regmap_config msm8939_bimc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x62000, + .fast_io = true, +}; + static struct qcom_icc_desc msm8939_bimc = { .nodes = msm8939_bimc_nodes, .num_nodes = ARRAY_SIZE(msm8939_bimc_nodes), + .is_bimc_node = true, + .regmap_cfg = &msm8939_bimc_regmap_config, + .qos_offset = 0x8000, }; static struct qcom_icc_node *msm8939_pcnoc_nodes[] = { @@ -316,9 +348,19 @@ static struct qcom_icc_node *msm8939_pcnoc_nodes[] = { [SNOC_PCNOC_SLV] = &snoc_pcnoc_slv, }; +static const struct regmap_config msm8939_pcnoc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x11000, + .fast_io = true, +}; + static struct qcom_icc_desc msm8939_pcnoc = { .nodes = msm8939_pcnoc_nodes, .num_nodes = ARRAY_SIZE(msm8939_pcnoc_nodes), + .regmap_cfg = &msm8939_pcnoc_regmap_config, + .qos_offset = 0x7000, }; static const struct of_device_id msm8939_noc_of_match[] = {