From patchwork Mon Aug 16 16:43:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Bailon X-Patchwork-Id: 497821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B342C4320A for ; Mon, 16 Aug 2021 16:41:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5DFAC60F58 for ; Mon, 16 Aug 2021 16:41:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231497AbhHPQmW (ORCPT ); Mon, 16 Aug 2021 12:42:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231368AbhHPQmV (ORCPT ); Mon, 16 Aug 2021 12:42:21 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55DB3C0613CF for ; Mon, 16 Aug 2021 09:41:49 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id u16so7406981wrn.5 for ; Mon, 16 Aug 2021 09:41:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jxcnjHPA5B0j7qX5chL1ZJXQsXksmgMefqmaOOvck6g=; b=gh2l0B5f6EJ7VXrb+GYCYmriYpOHMNPGU+nz2lisk3yiUpFuUBbr7Tmf1rybpLntdb hdpRJ/659TUr0FD1rANpNv/MxCvfr/etPOeFIrH5iuFKbzHh3Wg5gPMP0FxtJYdyG/Sn +rvl+qFCJhXyjJeAPjdCxc0/HEbb1U+6mAgWQD/4EedobPEVDBIK4V6Cru7Cu1b+pkOx hjEAfM3awnc2wpXxrBZXNT7nNy/xb+LBP1kv/HQJmSZDm8E8B8s3TyfMoEdUlGX95Ar3 hQbuKj9KYNazwHZdUkPr1axAssNcx9D5NC9LBJ7PhLJg9ACo/PgzOY/Ay61t0PcRmaIe imDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jxcnjHPA5B0j7qX5chL1ZJXQsXksmgMefqmaOOvck6g=; b=A7MHgcLFMwMmQMHBRWdg4k+nhegmhrhUMTTY6CfnAy+zdsyEpl5gwhiAnHf4JCwYmX 9UJ+IDoEBwe8W/u9JsfTPTybGbDUUknQpXQ6q1NTQYvCJLUsfU4TJq/GHTSmWOSRqbDA UzEAZB1FoQHNNC57i4NOoFnRd8GjlxstbmphNbPF1TEu4r3VQ5WPUVJih65MXMfiuLor J9wmIPLhvE+FrplC22iFA/fv9PfQ8fYltazHAhG9vwvGnOf3Var0iOHZwZiIDCJ36qQQ e7e6geWkgxcLoTWpAnodhchwauJZ+nDDG5KgILqsBIJ+rZvYH+CRq3W1G/YnMcX1BT5i uqgg== X-Gm-Message-State: AOAM532zDEU3dqpW4otyXLVsQZ81LBUa3wvQ7+qzXoo48OaA+9USPyYf X97XvZNeaNopmb3s/fp2u4wPdA== X-Google-Smtp-Source: ABdhPJz88fBErB0TXJjcCkHN84Q0xoZWg8NEBr1BSB0Iw+EaQ1/y6x2qK2vtpblHlClHO8Q5N0gAHQ== X-Received: by 2002:adf:f292:: with SMTP id k18mr19621618wro.249.1629132107978; Mon, 16 Aug 2021 09:41:47 -0700 (PDT) Received: from localhost.localdomain ([2001:861:3a81:3690:b885:8dcf:f8c6:7841]) by smtp.gmail.com with ESMTPSA id m10sm15211730wro.63.2021.08.16.09.41.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Aug 2021 09:41:47 -0700 (PDT) From: Alexandre Bailon To: rui.zhang@intel.com, daniel.lezcano@linaro.org, robh+dt@kernel.org, matthias.bgg@gmail.com Cc: ben.tseng@mediatek.com, michael.kao@mediatek.com, ethan.chang@mediatek.com, fparent@baylibre.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Alexandre Bailon Subject: [PATCH 1/3] dt-bindings: thermal: Add binding document for mt8195 thermal controller Date: Mon, 16 Aug 2021 18:43:05 +0200 Message-Id: <20210816164307.557315-2-abailon@baylibre.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210816164307.557315-1-abailon@baylibre.com> References: <20210816164307.557315-1-abailon@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org This patch adds binding document for mt8195 thermal controller. Signed-off-by: Alexandre Bailon --- .../devicetree/bindings/thermal/mediatek-thermal-lvts.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal-lvts.yaml b/Documentation/devicetree/bindings/thermal/mediatek-thermal-lvts.yaml index 69ffe7b14c212..2e1ae00d4fd18 100644 --- a/Documentation/devicetree/bindings/thermal/mediatek-thermal-lvts.yaml +++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal-lvts.yaml @@ -12,7 +12,11 @@ maintainers: properties: compatible: - const: mediatek,mt6873-lvts + oneOf: + - items: + - enum: + - mediatek,mt6873-lvts + - mediatek,mt8195-lvts reg: maxItems: 1 From patchwork Mon Aug 16 16:43:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Bailon X-Patchwork-Id: 498442 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82960C432BE for ; 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Mon, 16 Aug 2021 09:41:49 -0700 (PDT) Received: from localhost.localdomain ([2001:861:3a81:3690:b885:8dcf:f8c6:7841]) by smtp.gmail.com with ESMTPSA id m10sm15211730wro.63.2021.08.16.09.41.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Aug 2021 09:41:48 -0700 (PDT) From: Alexandre Bailon To: rui.zhang@intel.com, daniel.lezcano@linaro.org, robh+dt@kernel.org, matthias.bgg@gmail.com Cc: ben.tseng@mediatek.com, michael.kao@mediatek.com, ethan.chang@mediatek.com, fparent@baylibre.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Alexandre Bailon Subject: [PATCH 2/3] thermal: mediatek: Add thermal zone settings for mt8195 Date: Mon, 16 Aug 2021 18:43:06 +0200 Message-Id: <20210816164307.557315-3-abailon@baylibre.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210816164307.557315-1-abailon@baylibre.com> References: <20210816164307.557315-1-abailon@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Michael Kao Add thermal zone settings for mt8195 Signed-off-by: Michael Kao Signed-off-by: Ben Tseng Signed-off-by: Alexandre Bailon --- drivers/thermal/mediatek/soc_temp_lvts.c | 206 +++++++++++++++++++++-- 1 file changed, 192 insertions(+), 14 deletions(-) diff --git a/drivers/thermal/mediatek/soc_temp_lvts.c b/drivers/thermal/mediatek/soc_temp_lvts.c index 8153edaaf8150..ddcedcedbbc16 100644 --- a/drivers/thermal/mediatek/soc_temp_lvts.c +++ b/drivers/thermal/mediatek/soc_temp_lvts.c @@ -53,6 +53,7 @@ #define CLOCK_26MHZ_CYCLE_NS (38) #define BUS_ACCESS_US (2) +#define GOLDEN_TEMP_MAX (62) #define FEATURE_DEVICE_AUTO_RCK (BIT(0)) #define FEATURE_CK26M_ACTIVE (BIT(1)) @@ -577,21 +578,10 @@ static int prepare_calibration_data(struct lvts_data *lvts_data) if (!cal_data->count_rc) return -ENOMEM; - if (ops->efuse_to_cal_data) + if (ops->efuse_to_cal_data && !cal_data->use_fake_efuse) ops->efuse_to_cal_data(lvts_data); - - cal_data->use_fake_efuse = 1; - if (cal_data->golden_temp != 0) { - cal_data->use_fake_efuse = 0; - } else { - for (i = 0; i < lvts_data->num_sensor; i++) { - if (cal_data->count_r[i] != 0 || - cal_data->count_rc[i] != 0) { - cal_data->use_fake_efuse = 0; - break; - } - } - } + if (cal_data->golden_temp == 0 || cal_data->golden_temp > GOLDEN_TEMP_MAX) + cal_data->use_fake_efuse = 1; if (cal_data->use_fake_efuse) { /* It means all efuse data are equal to 0 */ @@ -1254,6 +1244,190 @@ static struct lvts_data mt6873_lvts_data = { }, }; +/*================================================== + * LVTS MT8195 + *================================================== + */ + +#define MT8195_NUM_LVTS (ARRAY_SIZE(mt8195_tc_settings)) + +enum mt8195_lvts_domain { + MT8195_AP_DOMAIN, + MT8195_MCU_DOMAIN, + MT8195_NUM_DOMAIN +}; + +enum mt8195_lvts_sensor_enum { + MT8195_TS1_0, + MT8195_TS1_1, + MT8195_TS2_0, + MT8195_TS2_1, + MT8195_TS3_0, + MT8195_TS3_1, + MT8195_TS3_2, + MT8195_TS3_3, + MT8195_TS4_0, + MT8195_TS4_1, + MT8195_TS5_0, + MT8195_TS5_1, + MT8195_TS6_0, + MT8195_TS6_1, + MT8195_TS6_2, + MT8195_TS7_0, + MT8195_TS7_1, + MT8195_NUM_TS +}; + +static void mt8195_efuse_to_cal_data(struct lvts_data *lvts_data) +{ + struct sensor_cal_data *cal_data = &lvts_data->cal_data; + + cal_data->golden_temp = GET_CAL_DATA_BITMASK(0, 31, 24); + cal_data->count_r[MT8195_TS1_0] = GET_CAL_DATA_BITMASK(1, 23, 0); + cal_data->count_r[MT8195_TS1_1] = (GET_CAL_DATA_BITMASK(2, 15, 0) << 8) + + GET_CAL_DATA_BITMASK(1, 31, 24); + cal_data->count_r[MT8195_TS2_0] = GET_CAL_DATA_BITMASK(3, 31, 8); + cal_data->count_r[MT8195_TS2_1] = GET_CAL_DATA_BITMASK(4, 23, 0); + cal_data->count_r[MT8195_TS3_0] = (GET_CAL_DATA_BITMASK(6, 7, 0) << 16) + + GET_CAL_DATA_BITMASK(5, 31, 16); + cal_data->count_r[MT8195_TS3_1] = GET_CAL_DATA_BITMASK(6, 31, 8); + cal_data->count_r[MT8195_TS3_2] = GET_CAL_DATA_BITMASK(7, 23, 0); + cal_data->count_r[MT8195_TS3_3] = (GET_CAL_DATA_BITMASK(8, 15, 0) << 8) + + GET_CAL_DATA_BITMASK(7, 31, 24); + cal_data->count_r[MT8195_TS4_0] = GET_CAL_DATA_BITMASK(9, 31, 8); + cal_data->count_r[MT8195_TS4_1] = GET_CAL_DATA_BITMASK(10, 23, 0); + cal_data->count_r[MT8195_TS5_0] = (GET_CAL_DATA_BITMASK(12, 7, 0) << 16) + + GET_CAL_DATA_BITMASK(11, 31, 16); + cal_data->count_r[MT8195_TS5_1] = GET_CAL_DATA_BITMASK(12, 31, 8); + cal_data->count_r[MT8195_TS6_0] = (GET_CAL_DATA_BITMASK(14, 15, 0) << 8) + + GET_CAL_DATA_BITMASK(13, 31, 24); + cal_data->count_r[MT8195_TS6_1] = (GET_CAL_DATA_BITMASK(15, 7, 0) << 16) + + GET_CAL_DATA_BITMASK(14, 31, 16); + cal_data->count_r[MT8195_TS6_2] = GET_CAL_DATA_BITMASK(15, 31, 8); + cal_data->count_r[MT8195_TS7_0] = (GET_CAL_DATA_BITMASK(17, 15, 0) << 8) + + GET_CAL_DATA_BITMASK(16, 31, 24); + cal_data->count_r[MT8195_TS7_1] = (GET_CAL_DATA_BITMASK(18, 7, 0) << 16) + + GET_CAL_DATA_BITMASK(17, 31, 16); + cal_data->count_rc[MT8195_TS1_0] = (GET_CAL_DATA_BITMASK(3, 7, 0) << 16) + + GET_CAL_DATA_BITMASK(2, 31, 16); + cal_data->count_rc[MT8195_TS2_0] = (GET_CAL_DATA_BITMASK(5, 15, 0) << 8) + + GET_CAL_DATA_BITMASK(4, 31, 24); + cal_data->count_rc[MT8195_TS3_0] = (GET_CAL_DATA_BITMASK(9, 7, 0) << 16) + + GET_CAL_DATA_BITMASK(8, 31, 16); + cal_data->count_rc[MT8195_TS4_0] = (GET_CAL_DATA_BITMASK(11, 15, 0) << 8) + + GET_CAL_DATA_BITMASK(10, 31, 24); + cal_data->count_rc[MT8195_TS5_0] = GET_CAL_DATA_BITMASK(13, 23, 0); + cal_data->count_rc[MT8195_TS6_0] = GET_CAL_DATA_BITMASK(16, 23, 0); + cal_data->count_rc[MT8195_TS7_0] = GET_CAL_DATA_BITMASK(18, 31, 8); +} + +static struct tc_settings mt8195_tc_settings[] = { + [0] = { + .domain_index = MT8195_MCU_DOMAIN, + .addr_offset = 0x0, + .num_sensor = 2, + .sensor_map = {MT8195_TS1_0, MT8195_TS1_1}, + .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT1, + .hw_reboot_trip_point = 117000, + .irq_bit = BIT(3), + }, + [1] = { + .domain_index = MT8195_MCU_DOMAIN, + .addr_offset = 0x100, + .num_sensor = 2, + .sensor_map = {MT8195_TS2_0, MT8195_TS2_1}, + .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT0, + .hw_reboot_trip_point = 117000, + .irq_bit = BIT(4), + }, + [2] = { + .domain_index = MT8195_MCU_DOMAIN, + .addr_offset = 0x200, + .num_sensor = 4, + .sensor_map = {MT8195_TS3_0, MT8195_TS3_1, MT8195_TS3_2, MT8195_TS3_3}, + .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT0, + .hw_reboot_trip_point = 117000, + .irq_bit = BIT(5), + }, + [3] = { + .domain_index = MT8195_AP_DOMAIN, + .addr_offset = 0x0, + .num_sensor = 2, + .sensor_map = {MT8195_TS4_0, MT8195_TS4_1}, + .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT0, + .hw_reboot_trip_point = 117000, + .irq_bit = BIT(3), + }, + [4] = { + .domain_index = MT8195_AP_DOMAIN, + .addr_offset = 0x100, + .num_sensor = 2, + .sensor_map = {MT8195_TS5_0, MT8195_TS5_1}, + .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT1, + .hw_reboot_trip_point = 117000, + .irq_bit = BIT(4), + }, + [5] = { + .domain_index = MT8195_AP_DOMAIN, + .addr_offset = 0x200, + .num_sensor = 3, + .sensor_map = {MT8195_TS6_0, MT8195_TS6_1, MT8195_TS6_2}, + .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT1, + .hw_reboot_trip_point = 117000, + .irq_bit = BIT(5), + }, + [6] = { + .domain_index = MT8195_AP_DOMAIN, + .addr_offset = 0x300, + .num_sensor = 2, + .sensor_map = {MT8195_TS7_0, MT8195_TS7_1}, + .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT0, + .hw_reboot_trip_point = 117000, + .irq_bit = BIT(6), + } +}; + +static struct lvts_data mt8195_lvts_data = { + .num_domain = MT8195_NUM_DOMAIN, + .num_tc = MT8195_NUM_LVTS, + .tc = mt8195_tc_settings, + .num_sensor = MT8195_NUM_TS, + .ops = { + .efuse_to_cal_data = mt8195_efuse_to_cal_data, + .device_enable_and_init = device_enable_and_init_v4, + .device_enable_auto_rck = device_enable_auto_rck_v4, + .device_read_count_rc_n = device_read_count_rc_n_v4, + .set_cal_data = set_calibration_data_v4, + .init_controller = init_controller_v4, + }, + .feature_bitmap = FEATURE_DEVICE_AUTO_RCK, + .num_efuse_addr = 22, + .num_efuse_block = 2, + .cal_data = { + .default_golden_temp = 50, + .default_count_r = 35000, + .default_count_rc = 2750, + }, + .coeff = { + .a = -250460, + .b = 250460, + }, +}; + /*================================================== *================================================== * Support chips @@ -1264,6 +1438,10 @@ static const struct of_device_id lvts_of_match[] = { .compatible = "mediatek,mt6873-lvts", .data = (void *)&mt6873_lvts_data, }, + { + .compatible = "mediatek,mt8195-lvts", + .data = (void *)&mt8195_lvts_data, + }, { }, }; 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Mon, 16 Aug 2021 09:41:49 -0700 (PDT) From: Alexandre Bailon To: rui.zhang@intel.com, daniel.lezcano@linaro.org, robh+dt@kernel.org, matthias.bgg@gmail.com Cc: ben.tseng@mediatek.com, michael.kao@mediatek.com, ethan.chang@mediatek.com, fparent@baylibre.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Tinghan Shen , Alexandre Bailon Subject: [PATCH 3/3] arm64: dts: mt8195: Add thermal zone and thermal policy Date: Mon, 16 Aug 2021 18:43:07 +0200 Message-Id: <20210816164307.557315-4-abailon@baylibre.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210816164307.557315-1-abailon@baylibre.com> References: <20210816164307.557315-1-abailon@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Tinghan Shen 1. Add SoC and board thermal zones. 2. Add thermal throttle policy Signed-off-by: Tinghan Shen Signed-off-by: Ben Tseng Signed-off-by: Alexandre Bailon --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 164 +++++++++++++++++++++++ 1 file changed, 164 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index d05492ff8f190..62d0944dea4db 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { compatible = "mediatek,mt8195"; @@ -475,6 +476,21 @@ spi0: spi@1100a000 { status = "disabled"; }; + lvts: lvts@1100b000 { + compatible = "mediatek,mt8195-lvts"; + #thermal-sensor-cells = <1>; + reg = <0 0x1100b000 0 0x1000>, + <0 0x11278000 0 0x1000>; + interrupts = , + ; + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; + clock-names = "lvts_clk"; + resets = <&infracfg_rst 1>, + <&infracfg_rst 2>; + nvmem-cells = <&lvts_e_data1 &lvts_e_data2>; + nvmem-cell-names = "e_data1","e_data2"; + }; + spi1: spi@11010000 { compatible = "mediatek,mt8195-spi", "mediatek,mt6765-spi"; reg = <0 0x11010000 0 0x100>; @@ -830,4 +846,152 @@ vdosys1: syscon@1c100000 { #clock-cells = <1>; }; }; + + thermal_zones: thermal-zones { + soc_max { + polling-delay = <1000>; /* milliseconds */ + polling-delay-passive = <1000>; /* milliseconds */ + thermal-sensors = <&lvts 0>; + sustainable-power = <1500>; + + trips { + threshold: trip-point@0 { + temperature = <68000>; + hysteresis = <2000>; + type = "passive"; + }; + + target: target@1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + soc_max_crit: soc_max_crit@0 { + temperature = <115000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu1 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu2 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu3 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + contribution = <3072>; + }; + map1 { + trip = <&target>; + cooling-device = <&cpu4 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu5 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu6 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu7 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + }; + cpu_big1 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 1>; + }; + cpu_big2 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 2>; + }; + cpu_big3 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 3>; + }; + cpu_big4 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 4>; + }; + cpu_little1{ + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 5>; + }; + cpu_little2 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 6>; + }; + cpu_little3 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 7>; + }; + cpu_little4 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 8>; + }; + vpu1 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 9>; + }; + vpu2 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 10>; + }; + gpu1 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 11>; + }; + gpu2 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 12>; + }; + vdec { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 13>; + }; + img { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 14>; + }; + infra { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 15>; + }; + cam1 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 16>; + }; + cam2 { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 17>; + }; + }; };