From patchwork Wed Aug 11 21:44:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Greear X-Patchwork-Id: 495578 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E468BC4338F for ; Wed, 11 Aug 2021 21:45:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C05EC60F11 for ; Wed, 11 Aug 2021 21:45:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232269AbhHKVpV (ORCPT ); Wed, 11 Aug 2021 17:45:21 -0400 Received: from dispatch1-us1.ppe-hosted.com ([148.163.129.48]:40948 "EHLO dispatch1-us1.ppe-hosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232013AbhHKVpP (ORCPT ); Wed, 11 Aug 2021 17:45:15 -0400 X-Virus-Scanned: Proofpoint Essentials engine Received: from mx1-us1.ppe-hosted.com (unknown [10.7.67.129]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id 3ACDA1A0073 for ; Wed, 11 Aug 2021 21:44:50 +0000 (UTC) Received: from mail3.candelatech.com (mail2.candelatech.com [208.74.158.173]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 0FFBE500066 for ; Wed, 11 Aug 2021 21:44:50 +0000 (UTC) Received: from ben-dt4.candelatech.com (50-251-239-81-static.hfc.comcastbusiness.net [50.251.239.81]) by mail3.candelatech.com (Postfix) with ESMTP id A2A1A13C2B3; Wed, 11 Aug 2021 14:44:49 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 mail3.candelatech.com A2A1A13C2B3 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=candelatech.com; s=default; t=1628718289; bh=cdsBliRRKVxgzD0bwAznLRhIM/EAncugm59L8twjgg8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nRm8YRR5pDbdJJ6LMKKSWexspRNZxCq7Z7ldsl0suaimFTZ+3IXbIEpmjo4QXnSUW FEkNoA6d/2X9A0fcWbukC1FpE/q+ItzSv54DQRz4tbzLJxK72wN8tffIcOqC9+imbb /fj0jFT2firsED2SGkJHNh0TnZ//A/oTm7JUFNqI= From: greearb@candelatech.com To: linux-wireless@vger.kernel.org Cc: Ben Greear Subject: [PATCH 01/15] mt76: mt7915: add comments about rx descriptor parsing Date: Wed, 11 Aug 2021 14:44:25 -0700 Message-Id: <20210811214439.17458-2-greearb@candelatech.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210811214439.17458-1-greearb@candelatech.com> References: <20210811214439.17458-1-greearb@candelatech.com> MIME-Version: 1.0 X-MDID: 1628718290-1BiIlejMYKML Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Ben Greear This is a tricky beast to understand, so add some notes for next time someone is looking at this code and trying to compare against documents. Signed-off-by: Ben Greear --- .../net/wireless/mediatek/mt76/mt7915/mac.c | 23 +++++++++++++++---- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c index 2c5b47766949..d836c665ddaf 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c +++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c @@ -410,6 +410,7 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb) __le32 *rxd = (__le32 *)skb->data; __le32 *rxv = NULL; u32 mode = 0; + /* table "PP -> HOST / X-CPU" RX Format */ u32 rxd0 = le32_to_cpu(rxd[0]); u32 rxd1 = le32_to_cpu(rxd[1]); u32 rxd2 = le32_to_cpu(rxd[2]); @@ -489,7 +490,7 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb) rxd += 6; if (rxd1 & MT_RXD1_NORMAL_GROUP_4) { - u32 v0 = le32_to_cpu(rxd[0]); + u32 v0 = le32_to_cpu(rxd[0]); /* DW6 */ u32 v2 = le32_to_cpu(rxd[2]); fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0)); @@ -502,6 +503,7 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb) } if (rxd1 & MT_RXD1_NORMAL_GROUP_1) { + /* DW10, assuming Group-4 enabled */ u8 *data = (u8 *)rxd; if (status->flag & RX_FLAG_DECRYPTED) { @@ -533,6 +535,7 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb) } if (rxd1 & MT_RXD1_NORMAL_GROUP_2) { + /* DW14, assuming group-1,4 */ status->timestamp = le32_to_cpu(rxd[0]); status->flag |= RX_FLAG_MACTIME_START; @@ -558,18 +561,22 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb) if (rxd1 & MT_RXD1_NORMAL_GROUP_3) { u32 v0, v1, v2; - rxv = rxd; + rxv = rxd; /* DW16 assuming group 1,2,3,4 */ rxd += 2; if ((u8 *)rxd - skb->data >= skb->len) return -EINVAL; - v0 = le32_to_cpu(rxv[0]); + v0 = le32_to_cpu(rxv[0]); /* DW16, P-VEC1 31:0 */ + /* DW17, RX_RCPI copied over P-VEC 64:32 Per RX Format doc. */ v1 = le32_to_cpu(rxv[1]); - v2 = le32_to_cpu(rxv[2]); + v2 = le32_to_cpu(rxv[2]); /* first DW of group-5, C-RXV */ if (v0 & MT_PRXV_HT_AD_CODE) status->enc_flags |= RX_ENC_FLAG_LDPC; + /* TODO: When group-5 is enabled, use nss (and stbc) to + * calculate chains properly for this particular skb. + */ status->chains = mphy->antenna_mask; status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1); status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1); @@ -581,12 +588,18 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb) if (!(status->chains & BIT(i))) continue; + /* TODO: Use db sum logic instead of max. */ status->signal = max(status->signal, status->chain_signal[i]); } - /* RXD Group 5 - C-RXV */ + /* RXD Group 5 - C-RXV. + * Group 5 Not currently enabled for 7915 except in + * monitor mode. + * See MT_DMA_DCR0_RXD_G5_EN + */ if (rxd1 & MT_RXD1_NORMAL_GROUP_5) { + /* See RXV document ... */ u8 stbc = FIELD_GET(MT_CRXV_HT_STBC, v2); u8 gi = FIELD_GET(MT_CRXV_HT_SHORT_GI, v2); bool cck = false; From patchwork Wed Aug 11 21:44:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Greear X-Patchwork-Id: 495576 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29484C4338F for ; Wed, 11 Aug 2021 21:45:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0E09460724 for ; Wed, 11 Aug 2021 21:45:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232345AbhHKVpr (ORCPT ); Wed, 11 Aug 2021 17:45:47 -0400 Received: from dispatch1-us1.ppe-hosted.com ([67.231.154.183]:58416 "EHLO dispatch1-us1.ppe-hosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232201AbhHKVpR (ORCPT ); Wed, 11 Aug 2021 17:45:17 -0400 X-Virus-Scanned: Proofpoint Essentials engine Received: from mx1-us1.ppe-hosted.com (unknown [10.110.51.179]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id D1CAA2A0067 for ; Wed, 11 Aug 2021 21:44:50 +0000 (UTC) Received: from mail3.candelatech.com (mail2.candelatech.com [208.74.158.173]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id A661EAC0081 for ; Wed, 11 Aug 2021 21:44:50 +0000 (UTC) Received: from ben-dt4.candelatech.com (50-251-239-81-static.hfc.comcastbusiness.net [50.251.239.81]) by mail3.candelatech.com (Postfix) with ESMTP id 0927A13C2B5; Wed, 11 Aug 2021 14:44:50 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 mail3.candelatech.com 0927A13C2B5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=candelatech.com; s=default; t=1628718290; bh=zeyhZ7B9mfXwbjo2UzCDgiCnhZgbZWzmLgZvyfjtUz8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=T1SJmyeFCLKA10jRyAkntUYaTBB6Cv46brwHcblgGs6XNYssH4NXeP/jRaXk/XLGN 6djUNab5+Zc+5tVsViZWsME4AGbpCLSuYIKwvYYlRUW7zEotoRs7g+pIBGSH8jUgUD RASpb+RQ7j7je9vzwjiL/EN2CbqTrs4oIlpPeIqc= From: greearb@candelatech.com To: linux-wireless@vger.kernel.org Cc: Ben Greear Subject: [PATCH 03/15] mt76: mt7915: tx_stats debugfs to read from mib Date: Wed, 11 Aug 2021 14:44:27 -0700 Message-Id: <20210811214439.17458-4-greearb@candelatech.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210811214439.17458-1-greearb@candelatech.com> References: <20210811214439.17458-1-greearb@candelatech.com> MIME-Version: 1.0 X-MDID: 1628718291-kLyjWr3fNvOg Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Ben Greear Read from accumulated mib values instead of directly from registers since registers are clear-on-read. Signed-off-by: Ben Greear --- .../wireless/mediatek/mt76/mt7915/debugfs.c | 20 ++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c b/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c index f2ff0d3f52cd..b48fda497ab6 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c +++ b/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c @@ -444,7 +444,9 @@ static int mt7915_tx_stats_show(struct seq_file *file, void *data) { struct mt7915_dev *dev = file->private; - int stat[8], i, n; + int i; + long n; + struct mib_stats *mib = &dev->phy.mib; mt7915_ampdu_stat_read_phy(&dev->phy, file); mt7915_txbf_stat_read_phy(&dev->phy, file); @@ -454,16 +456,16 @@ mt7915_tx_stats_show(struct seq_file *file, void *data) /* Tx amsdu info */ seq_puts(file, "Tx MSDU statistics:\n"); - for (i = 0, n = 0; i < ARRAY_SIZE(stat); i++) { - stat[i] = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i)); - n += stat[i]; - } + for (i = 0, n = 0; i < ARRAY_SIZE(mib->amsdu_pack_stats); i++) + n += mib->amsdu_pack_stats[i]; + + for (i = 0; i < ARRAY_SIZE(mib->amsdu_pack_stats); i++) { + long si = mib->amsdu_pack_stats[i]; - for (i = 0; i < ARRAY_SIZE(stat); i++) { - seq_printf(file, "AMSDU pack count of %d MSDU in TXD: 0x%x ", - i + 1, stat[i]); + seq_printf(file, "AMSDU pack count of %d MSDU in TXD: %ld ", + i + 1, si); if (n != 0) - seq_printf(file, "(%d%%)\n", stat[i] * 100 / n); + seq_printf(file, "(%ld%%)\n", si * 100 / n); else seq_puts(file, "\n"); } From patchwork Wed Aug 11 21:44:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Greear X-Patchwork-Id: 495577 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73EDEC4338F for ; Wed, 11 Aug 2021 21:45:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 59A3460F11 for ; Wed, 11 Aug 2021 21:45:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232298AbhHKVph (ORCPT ); Wed, 11 Aug 2021 17:45:37 -0400 Received: from dispatch1-us1.ppe-hosted.com ([67.231.154.164]:58414 "EHLO dispatch1-us1.ppe-hosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232198AbhHKVpR (ORCPT ); Wed, 11 Aug 2021 17:45:17 -0400 X-Virus-Scanned: Proofpoint Essentials engine Received: from mx1-us1.ppe-hosted.com (unknown [10.110.51.174]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id E18E11A006C for ; Wed, 11 Aug 2021 21:44:50 +0000 (UTC) Received: from mail3.candelatech.com (mail2.candelatech.com [208.74.158.173]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id A6B387C0071 for ; Wed, 11 Aug 2021 21:44:50 +0000 (UTC) Received: from ben-dt4.candelatech.com (50-251-239-81-static.hfc.comcastbusiness.net [50.251.239.81]) by mail3.candelatech.com (Postfix) with ESMTP id 304D013C2B7; Wed, 11 Aug 2021 14:44:50 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 mail3.candelatech.com 304D013C2B7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=candelatech.com; s=default; t=1628718290; bh=hQoAJt8ukwmro8h0mK6xwESY2xETZQMtloctEDxd3oQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qumFKy49wP10xg9NoLaKOfzfDN44Cj/whddmUA+zEwuf4h4fkfKhLd7N6QpBOF3F+ q/4LGsaf9iugqciGtGMBn3hfxaoHHJhk+pDeAgJxHawI+N+kJNjSb8ozH31B3r+a3E zmwGv0W4BJLNOtukfe2ZG3JpPK2Sxh0/c2IUaOqk= From: greearb@candelatech.com To: linux-wireless@vger.kernel.org Cc: Ben Greear Subject: [PATCH 04/15] mt76: mt7915: support enabling rx group-5 status Date: Wed, 11 Aug 2021 14:44:28 -0700 Message-Id: <20210811214439.17458-5-greearb@candelatech.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210811214439.17458-1-greearb@candelatech.com> References: <20210811214439.17458-1-greearb@candelatech.com> MIME-Version: 1.0 X-MDID: 1628718291-cqzrf_WaolHF Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Ben Greear When enabled, this allows per-skb rx rate reporting. Enabling this may degrade RX performance, so it remains disabled by default. Signed-off-by: Ben Greear --- .../wireless/mediatek/mt76/mt7915/debugfs.c | 33 +++++++++++++++++++ .../net/wireless/mediatek/mt76/mt7915/init.c | 3 +- .../net/wireless/mediatek/mt76/mt7915/mac.c | 3 +- .../net/wireless/mediatek/mt76/mt7915/main.c | 3 +- .../wireless/mediatek/mt76/mt7915/mt7915.h | 5 +++ 5 files changed, 44 insertions(+), 3 deletions(-) diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c b/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c index b48fda497ab6..885c60ea2a71 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c +++ b/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c @@ -354,6 +354,38 @@ mt7915_txs_for_no_skb_get(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(fops_txs_for_no_skb, mt7915_txs_for_no_skb_get, mt7915_txs_for_no_skb_set, "%lld\n"); +static int +mt7915_rx_group_5_enable_set(void *data, u64 val) +{ + struct mt7915_dev *dev = data; + + mutex_lock(&dev->mt76.mutex); + + dev->rx_group_5_enable = !!val; + + /* Enabled if we requested enabled OR if monitor mode is enabled. */ + mt76_rmw_field(dev, MT_DMA_DCR0(0), MT_DMA_DCR0_RXD_G5_EN, + dev->phy.is_monitor_mode || dev->rx_group_5_enable); + mt76_testmode_reset(dev->phy.mt76, true); + + mutex_unlock(&dev->mt76.mutex); + + return 0; +} + +static int +mt7915_rx_group_5_enable_get(void *data, u64 *val) +{ + struct mt7915_dev *dev = data; + + *val = dev->rx_group_5_enable; + + return 0; +} + +DEFINE_DEBUGFS_ATTRIBUTE(fops_rx_group_5_enable, mt7915_rx_group_5_enable_get, + mt7915_rx_group_5_enable_set, "%lld\n"); + static void mt7915_ampdu_stat_read_phy(struct mt7915_phy *phy, struct seq_file *file) @@ -592,6 +624,7 @@ int mt7915_init_debugfs(struct mt7915_dev *dev) debugfs_create_file("tx_stats", 0400, dir, dev, &mt7915_tx_stats_fops); debugfs_create_file("fw_debug", 0600, dir, dev, &fops_fw_debug); debugfs_create_file("txs_for_no_skb", 0600, dir, dev, &fops_txs_for_no_skb); + debugfs_create_file("rx_group_5_enable", 0600, dir, dev, &fops_rx_group_5_enable); debugfs_create_file("implicit_txbf", 0600, dir, dev, &fops_implicit_txbf); debugfs_create_u32("dfs_hw_pattern", 0400, dir, &dev->hw_pattern); diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/init.c b/drivers/net/wireless/mediatek/mt76/mt7915/init.c index 6a00c072ee56..e741c4f73d19 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/init.c +++ b/drivers/net/wireless/mediatek/mt76/mt7915/init.c @@ -302,7 +302,8 @@ mt7915_mac_init_band(struct mt7915_dev *dev, u8 band) mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 1536); /* disable rx rate report by default due to hw issues */ - mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN); + mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN, + dev->phy.is_monitor_mode || dev->rx_group_5_enable); } static void mt7915_mac_init(struct mt7915_dev *dev) diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c index d836c665ddaf..7d5156a9e48d 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c +++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c @@ -715,7 +715,8 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb) status->flag |= RX_FLAG_8023; } - if (rxv && status->flag & RX_FLAG_RADIOTAP_HE) { + if (phy->is_monitor_mode && + rxv && status->flag & RX_FLAG_RADIOTAP_HE) { mt7915_mac_decode_he_radiotap(skb, status, rxv, mode); if (status->flag & RX_FLAG_RADIOTAP_HE_MU) mt7915_mac_decode_he_mu_radiotap(skb, status, rxv); diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/main.c b/drivers/net/wireless/mediatek/mt76/mt7915/main.c index 37c484d32d0b..b3f3b53da843 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/main.c +++ b/drivers/net/wireless/mediatek/mt76/mt7915/main.c @@ -450,13 +450,14 @@ static int mt7915_config(struct ieee80211_hw *hw, u32 changed) if (changed & IEEE80211_CONF_CHANGE_MONITOR) { bool enabled = !!(hw->conf.flags & IEEE80211_CONF_MONITOR); + phy->is_monitor_mode = enabled; if (!enabled) phy->rxfilter |= MT_WF_RFCR_DROP_OTHER_UC; else phy->rxfilter &= ~MT_WF_RFCR_DROP_OTHER_UC; mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN, - enabled); + phy->is_monitor_mode || dev->rx_group_5_enable); mt76_testmode_reset(phy->mt76, true); mt76_wr(dev, MT_WF_RFCR(band), phy->rxfilter); } diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h index d5e331064682..8086233d6e2b 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h +++ b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h @@ -184,6 +184,7 @@ struct mt7915_phy { struct thermal_cooling_device *cdev; u8 throttle_state; + u8 is_monitor_mode; /* are we in monitor mode or not ? */ u32 rxfilter; u64 omac_mask; @@ -236,6 +237,10 @@ struct mt7915_dev { * creation by firmware, so may be a performance drag. */ bool txs_for_no_skb_enabled; + /* Should we enable group-5 rx descriptor logic? This may decrease RX + * throughput, but will give per skb rx rate information.. + */ + bool rx_group_5_enable; struct work_struct init_work; struct work_struct rc_work; From patchwork Wed Aug 11 21:44:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Greear X-Patchwork-Id: 495575 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EAD7C4338F for ; Wed, 11 Aug 2021 21:45:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7167F60724 for ; Wed, 11 Aug 2021 21:45:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232366AbhHKVpv (ORCPT ); Wed, 11 Aug 2021 17:45:51 -0400 Received: from dispatch1-us1.ppe-hosted.com ([67.231.154.184]:58450 "EHLO dispatch1-us1.ppe-hosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232212AbhHKVpT (ORCPT ); Wed, 11 Aug 2021 17:45:19 -0400 X-Virus-Scanned: Proofpoint Essentials engine Received: from mx1-us1.ppe-hosted.com (unknown [10.110.48.61]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id EEB3F2005E for ; Wed, 11 Aug 2021 21:44:51 +0000 (UTC) Received: from mail3.candelatech.com (mail2.candelatech.com [208.74.158.173]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id B3217C0070 for ; Wed, 11 Aug 2021 21:44:51 +0000 (UTC) Received: from ben-dt4.candelatech.com (50-251-239-81-static.hfc.comcastbusiness.net [50.251.239.81]) by mail3.candelatech.com (Postfix) with ESMTP id 00A8013C2BC; Wed, 11 Aug 2021 14:44:50 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 mail3.candelatech.com 00A8013C2BC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=candelatech.com; s=default; t=1628718291; bh=i5oeDBHi/e687OJ0AVoEccXnXu7tCfqappsSLtfOngg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CSAnVLwp9E+1qPWi0bXlOr3QpAiFTDYgSx0zaPw3J/8WEtD3Uo1DUC/WQRam+itQE mLwKXq+3WpuuLWGTjuQO6YJpzJRCbGSybwX/k/6Vj1GgRUx/UUtyotzwpOd7mrkQGN h9I9CuzfgCfhlwO/W3RQ0gYa8s9w3bcuS+SfQwIg= From: greearb@candelatech.com To: linux-wireless@vger.kernel.org Cc: Ben Greear Subject: [PATCH 07/15] mt76: mt7915: ethtool group-5 rx stats information Date: Wed, 11 Aug 2021 14:44:31 -0700 Message-Id: <20210811214439.17458-8-greearb@candelatech.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210811214439.17458-1-greearb@candelatech.com> References: <20210811214439.17458-1-greearb@candelatech.com> MIME-Version: 1.0 X-MDID: 1628718292-m0ViCENeW0vW Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Ben Greear Add ethtool support for rx-nss, rx-bw, rx-mode stats. These are only valid when the group-5 rx stats are enabled. Signed-off-by: Ben Greear --- .../net/wireless/mediatek/mt76/mt7915/mac.c | 23 ++++++++++ .../net/wireless/mediatek/mt76/mt7915/main.c | 42 +++++++++++++++++++ .../wireless/mediatek/mt76/mt7915/mt7915.h | 10 +++++ 3 files changed, 75 insertions(+) diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c index f1cff26cbc36..697dbf62c35f 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c +++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c @@ -424,6 +424,7 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb) u8 qos_ctl = 0; __le16 fc = 0; int i, idx; + struct mt7915_sta_stats *mstats = NULL; memset(status, 0, sizeof(*status)); @@ -451,6 +452,7 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb) struct mt7915_sta *msta; msta = container_of(status->wcid, struct mt7915_sta, wcid); + mstats = &msta->stats; spin_lock_bh(&dev->sta_poll_lock); if (list_empty(&msta->poll_list)) list_add_tail(&msta->poll_list, &dev->sta_poll_list); @@ -654,8 +656,19 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb) WARN_ON_ONCE(nss > 4); } + if (mstats) { + if (nss > 3) + mstats->rx_nss[3]++; + else + mstats->rx_nss[nss - 1]++; + + mstats->rx_mode[mode]++; + } + switch (FIELD_GET(MT_CRXV_FRAME_MODE, v2)) { case IEEE80211_STA_RX_BW_20: + if (mstats) + mstats->rx_bw_20++; break; case IEEE80211_STA_RX_BW_40: if (mode & MT_PHY_TYPE_HE_EXT_SU && @@ -663,14 +676,24 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb) status->bw = RATE_INFO_BW_HE_RU; status->he_ru = NL80211_RATE_INFO_HE_RU_ALLOC_106; + if (mstats) { + mstats->rx_bw_he_ru++; + mstats->rx_ru_106++; + } } else { status->bw = RATE_INFO_BW_40; + if (mstats) + mstats->rx_bw_40++; } break; case IEEE80211_STA_RX_BW_80: status->bw = RATE_INFO_BW_80; + if (mstats) + mstats->rx_bw_80++; break; case IEEE80211_STA_RX_BW_160: + if (mstats) + mstats->rx_bw_160++; status->bw = RATE_INFO_BW_160; break; default: diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/main.c b/drivers/net/wireless/mediatek/mt76/mt7915/main.c index 427b275f123a..1ce4260557c7 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/main.c +++ b/drivers/net/wireless/mediatek/mt76/mt7915/main.c @@ -1123,6 +1123,27 @@ static const char mt7915_gstrings_stats[][ETH_GSTRING_LEN] = { "v_tx_mcs_9", "v_tx_mcs_10", "v_tx_mcs_11", + + /* per-vif rx counters */ + "v_rx_nss1", + "v_rx_nss2", + "v_rx_nss3", + "v_rx_nss4", + "v_rx_mode_cck", + "v_rx_mode_ofdm", + "v_rx_mode_ht", + "v_rx_mode_ht_gf", + "v_rx_mode_vht", + "v_rx_mode_he_su", + "v_rx_mode_he_ext_su", + "v_rx_mode_he_tb", + "v_rx_mode_he_mu", + "v_rx_bw_20", + "v_rx_bw_40", + "v_rx_bw_80", + "v_rx_bw_160", + "v_rx_bw_he_ru", + "v_rx_ru_106", }; #define MT7915_SSTATS_LEN ARRAY_SIZE(mt7915_gstrings_stats) @@ -1190,6 +1211,27 @@ static void mt7915_ethtool_worker(void *wi_data, struct ieee80211_sta *sta) for (q = 0; q < 12; q++) data[ei++] += mstats->tx_mcs[q]; + /* rx stats */ + for (q = 0; q < ARRAY_SIZE(mstats->rx_nss); q++) + data[ei++] += mstats->rx_nss[q]; + + data[ei++] += mstats->rx_mode[MT_PHY_TYPE_CCK]; + data[ei++] += mstats->rx_mode[MT_PHY_TYPE_OFDM]; + data[ei++] += mstats->rx_mode[MT_PHY_TYPE_HT]; + data[ei++] += mstats->rx_mode[MT_PHY_TYPE_HT_GF]; + data[ei++] += mstats->rx_mode[MT_PHY_TYPE_VHT]; + data[ei++] += mstats->rx_mode[MT_PHY_TYPE_HE_SU]; + data[ei++] += mstats->rx_mode[MT_PHY_TYPE_HE_EXT_SU]; + data[ei++] += mstats->rx_mode[MT_PHY_TYPE_HE_TB]; + data[ei++] += mstats->rx_mode[MT_PHY_TYPE_HE_MU]; + + data[ei++] += mstats->rx_bw_20; + data[ei++] += mstats->rx_bw_40; + data[ei++] += mstats->rx_bw_80; + data[ei++] += mstats->rx_bw_160; + data[ei++] += mstats->rx_bw_he_ru; + data[ei++] += mstats->rx_ru_106; + wi->worker_stat_count = ei - wi->initial_stat_idx; } diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h index b446a5c73aa5..1f0be4fbee35 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h +++ b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h @@ -73,6 +73,16 @@ struct mt7915_sta_stats { unsigned long tx_bw[4]; /* 20, 40, 80, 160 */ unsigned long tx_nss[4]; /* 1, 2, 3, 4 */ unsigned long tx_mcs[16]; /* mcs idx */ + + /* This section requires group-5 in rxd to be enabled. */ + u32 rx_nss[4]; /* rx-nss histogram */ + u32 rx_mode[MT_PHY_TYPE_HE_LAST]; /* rx mode histogram */ + u32 rx_bw_20; + u32 rx_bw_40; + u32 rx_bw_80; + u32 rx_bw_160; + u32 rx_bw_he_ru; + u32 rx_ru_106; }; struct mt7915_sta_key_conf { From patchwork Wed Aug 11 21:44:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Greear X-Patchwork-Id: 495574 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UPPERCASE_50_75, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BDDCC4338F for ; Wed, 11 Aug 2021 21:45:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F0AC860F11 for ; Wed, 11 Aug 2021 21:45:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232419AbhHKVqC (ORCPT ); Wed, 11 Aug 2021 17:46:02 -0400 Received: from dispatch1-us1.ppe-hosted.com ([148.163.129.49]:52232 "EHLO dispatch1-us1.ppe-hosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232233AbhHKVpY (ORCPT ); Wed, 11 Aug 2021 17:45:24 -0400 X-Virus-Scanned: Proofpoint Essentials engine Received: from mx1-us1.ppe-hosted.com (unknown [10.7.67.133]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id 6ABB41C0069 for ; Wed, 11 Aug 2021 21:44:52 +0000 (UTC) Received: from mail3.candelatech.com (mail2.candelatech.com [208.74.158.173]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 3CF07B0007D for ; Wed, 11 Aug 2021 21:44:52 +0000 (UTC) Received: from ben-dt4.candelatech.com (50-251-239-81-static.hfc.comcastbusiness.net [50.251.239.81]) by mail3.candelatech.com (Postfix) with ESMTP id EBC4813C2B4; Wed, 11 Aug 2021 14:44:51 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 mail3.candelatech.com EBC4813C2B4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=candelatech.com; s=default; t=1628718292; bh=8P8wRSjVP+ECqn0enA5H9nL7znbe/vrrfUcpJGOc+bo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=by9Gf+zh0IoEgT5zDbI/jdXFF8jEXlGPhQzKU5JbvxFN0IW+e4ppicSvOKTt9iI1M W11KON+PQ6kKcKZy1RINnv8qzOMcOWge8Lrp/1X2YSmh9MqkDCXYprpk3rO/dqqfi6 BApQaeTV8eYeCDgPWDyJbUu00CIEiOqHVUm0lJyI= From: greearb@candelatech.com To: linux-wireless@vger.kernel.org Cc: Ben Greear Subject: [PATCH 11/15] mt76: mt7915: debugfs display for pse non-empty queues Date: Wed, 11 Aug 2021 14:44:35 -0700 Message-Id: <20210811214439.17458-12-greearb@candelatech.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210811214439.17458-1-greearb@candelatech.com> References: <20210811214439.17458-1-greearb@candelatech.com> MIME-Version: 1.0 X-MDID: 1628718292-cwI4-HQ--Day Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Ben Greear This may give user some idea of how the buffer utilization is being used in the firmware/hardware. Signed-off-by: Ben Greear --- .../wireless/mediatek/mt76/mt7915/debugfs.c | 141 ++++++++++++ .../net/wireless/mediatek/mt76/mt7915/regs.h | 201 ++++++++++++++++++ 2 files changed, 342 insertions(+) diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c b/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c index 688641ea4bb5..5c6a75f45f8f 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c +++ b/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c @@ -507,6 +507,146 @@ mt7915_tx_stats_show(struct seq_file *file, void *data) DEFINE_SHOW_ATTRIBUTE(mt7915_tx_stats); +struct mt7915_empty_q_info { + const char *qname; + u32 port_id; + u32 q_id; +}; + +static struct mt7915_empty_q_info pse_queue_empty_info[] = { + {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0}, + {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1}, + {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2}, + {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3}, + {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 4~7 not defined */ + {"HIF Q0", ENUM_UMAC_HIF_PORT_0, 0}, /* Q8 */ + {"HIF Q1", ENUM_UMAC_HIF_PORT_0, 1}, + {"HIF Q2", ENUM_UMAC_HIF_PORT_0, 2}, + {"HIF Q3", ENUM_UMAC_HIF_PORT_0, 3}, + {"HIF Q4", ENUM_UMAC_HIF_PORT_0, 4}, + {"HIF Q5", ENUM_UMAC_HIF_PORT_0, 5}, + {NULL, 0, 0}, {NULL, 0, 0}, /* 14~15 not defined */ + {"LMAC Q", ENUM_UMAC_LMAC_PORT_2, 0}, + {"MDP TX Q", ENUM_UMAC_LMAC_PORT_2, 1}, + {"MDP RX Q", ENUM_UMAC_LMAC_PORT_2, 2}, + {"SEC TX Q", ENUM_UMAC_LMAC_PORT_2, 3}, + {"SEC RX Q", ENUM_UMAC_LMAC_PORT_2, 4}, + {"SFD_PARK Q", ENUM_UMAC_LMAC_PORT_2, 5}, + {"MDP_TXIOC Q", ENUM_UMAC_LMAC_PORT_2, 6}, + {"MDP_RXIOC Q", ENUM_UMAC_LMAC_PORT_2, 7}, + {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, + {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 24~30 not defined */ + {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, ENUM_UMAC_PLE_CTRL_P3_Q_0X1F} +}; + +static void +mt7915_pse_q_nonempty_stat_read_phy(struct mt7915_phy *phy, + struct seq_file *file) +{ + struct mt7915_dev *dev = file->private; + u32 pse_stat; + int i; + + pse_stat = mt76_rr(dev, WF_PSE_TOP_QUEUE_EMPTY_ADDR); + + /* Queue Empty Status */ + seq_puts(file, "PSE Queue Empty Status:\n"); + seq_printf(file, "\tQUEUE_EMPTY: 0x%08x\n", pse_stat); + seq_printf(file, "\t\tCPU Q0/1/2/3 empty=%d/%d/%d/%d\n", + ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK) + >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_SHFT), + ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK) + >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_SHFT), + ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK) + >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_SHFT), + ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK) + >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_SHFT)); + seq_printf(file, "\t\tHIF Q0/1/2/3/4/5 empty=%d/%d/%d/%d/%d/%d\n", + ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_HIF_0_EMPTY_MASK) + >> WF_PSE_TOP_QUEUE_EMPTY_HIF_0_EMPTY_SHFT), + ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_HIF_1_EMPTY_MASK) + >> WF_PSE_TOP_QUEUE_EMPTY_HIF_1_EMPTY_SHFT), + ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_HIF_2_EMPTY_MASK) + >> WF_PSE_TOP_QUEUE_EMPTY_HIF_2_EMPTY_SHFT), + ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_HIF_3_EMPTY_MASK) + >> WF_PSE_TOP_QUEUE_EMPTY_HIF_3_EMPTY_SHFT), + ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_HIF_4_EMPTY_MASK) + >> WF_PSE_TOP_QUEUE_EMPTY_HIF_4_EMPTY_SHFT), + ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_HIF_5_EMPTY_MASK) + >> WF_PSE_TOP_QUEUE_EMPTY_HIF_5_EMPTY_SHFT)); + seq_printf(file, "\t\tLMAC TX Q empty=%d\n", + ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK) + >> WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_SHFT)); + seq_printf(file, "\t\tMDP TX Q/RX Q empty=%d/%d\n", + ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK) + >> WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_SHFT), + ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK) + >> WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_SHFT)); + seq_printf(file, "\t\tSEC TX Q/RX Q empty=%d/%d\n", + ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK) + >> WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_SHFT), + ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_MASK) + >> WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT)); + seq_printf(file, "\t\tSFD PARK Q empty=%d\n", + ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK) + >> WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_SHFT)); + seq_printf(file, "\t\tMDP TXIOC Q/RXIOC Q empty=%d/%d\n", + ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK) + >> WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_SHFT), + ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK) + >> WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_SHFT)); + seq_printf(file, "\t\tRLS Q empty=%d\n", + ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_MASK) + >> WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_SHFT)); + seq_printf(file, ("Non-Empty Q info:\n")); + + for (i = 0; i < 31; i++) { + if (((pse_stat & (0x1 << i)) >> i) == 0) { + u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0}; + + if (pse_queue_empty_info[i].qname) { + seq_printf(file, "\t%s: ", pse_queue_empty_info[i].qname); + fl_que_ctrl[0] |= WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK; + fl_que_ctrl[0] |= (pse_queue_empty_info[i].port_id + << WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_PID_SHFT); + fl_que_ctrl[0] |= (pse_queue_empty_info[i].q_id + << WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT); + } else { + continue; + } + + /* Executes frame link and queue structure buffer read command */ + fl_que_ctrl[0] |= (0x1 << 31); + mt76_wr(dev, WF_PSE_TOP_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]); + + fl_que_ctrl[1] = mt76_rr(dev, WF_PSE_TOP_FL_QUE_CTRL_2_ADDR); + fl_que_ctrl[2] = mt76_rr(dev, WF_PSE_TOP_FL_QUE_CTRL_3_ADDR); + hfid = (fl_que_ctrl[1] & WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK) + >> WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT; + tfid = (fl_que_ctrl[1] & WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK) + >> WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT; + pktcnt = (fl_que_ctrl[2] & WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK) + >> WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT; + seq_printf(file, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n", + tfid, hfid, pktcnt); + } + } +} + +static int +mt7915_rx_pse_stats_show(struct seq_file *file, void *data) +{ + struct mt7915_dev *dev = file->private; + + seq_puts(file, "RX PSE Stats\n"); + + mt7915_pse_q_nonempty_stat_read_phy(&dev->phy, file); + + return 0; +} + +DEFINE_SHOW_ATTRIBUTE(mt7915_rx_pse_stats); + static int mt7915_queues_acq(struct seq_file *s, void *data) { @@ -622,6 +762,7 @@ int mt7915_init_debugfs(struct mt7915_dev *dev) debugfs_create_devm_seqfile(dev->mt76.dev, "acq", dir, mt7915_queues_acq); debugfs_create_file("tx_stats", 0400, dir, dev, &mt7915_tx_stats_fops); + debugfs_create_file("rx_pse_stats", 0400, dir, dev, &mt7915_rx_pse_stats_fops); debugfs_create_file("fw_debug", 0600, dir, dev, &fops_fw_debug); debugfs_create_file("txs_for_no_skb", 0600, dir, dev, &fops_txs_for_no_skb); debugfs_create_file("rx_group_5_enable", 0600, dir, dev, &fops_rx_group_5_enable); diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/regs.h b/drivers/net/wireless/mediatek/mt76/mt7915/regs.h index ac4d233b8cf2..1e3ce90ff3dd 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/regs.h +++ b/drivers/net/wireless/mediatek/mt76/mt7915/regs.h @@ -566,4 +566,205 @@ #define MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY BIT(18) #define MT_WF_PHY_RXTD12_IRPI_SW_CLR BIT(29) +/* PSE queue related registers and enums */ + +/* PLE info */ +enum ENUM_UMAC_PORT { + ENUM_UMAC_HIF_PORT_0 = 0, + ENUM_UMAC_CPU_PORT_1 = 1, + ENUM_UMAC_LMAC_PORT_2 = 2, + ENUM_PLE_CTRL_PSE_PORT_3 = 3, + ENUM_UMAC_PSE_PLE_PORT_TOTAL_NUM = 4 +}; + +/* N9 MCU QUEUE LIST */ +enum ENUM_UMAC_CPU_P_QUEUE { + ENUM_UMAC_CTX_Q_0 = 0, + ENUM_UMAC_CTX_Q_1 = 1, + ENUM_UMAC_CTX_Q_2 = 2, + ENUM_UMAC_CTX_Q_3 = 3, + ENUM_UMAC_CRX = 0, + ENUM_UMAC_CIF_QUEUE_TOTAL_NUM = 4 +}; + +/* LMAC PLE TX QUEUE LIST */ +enum ENUM_UMAC_LMAC_PLE_TX_P_QUEUE { + ENUM_UMAC_LMAC_PLE_TX_Q_00 = 0x00, + ENUM_UMAC_LMAC_PLE_TX_Q_01 = 0x01, + ENUM_UMAC_LMAC_PLE_TX_Q_02 = 0x02, + ENUM_UMAC_LMAC_PLE_TX_Q_03 = 0x03, + + ENUM_UMAC_LMAC_PLE_TX_Q_10 = 0x04, + ENUM_UMAC_LMAC_PLE_TX_Q_11 = 0x05, + ENUM_UMAC_LMAC_PLE_TX_Q_12 = 0x06, + ENUM_UMAC_LMAC_PLE_TX_Q_13 = 0x07, + + ENUM_UMAC_LMAC_PLE_TX_Q_20 = 0x08, + ENUM_UMAC_LMAC_PLE_TX_Q_21 = 0x09, + ENUM_UMAC_LMAC_PLE_TX_Q_22 = 0x0a, + ENUM_UMAC_LMAC_PLE_TX_Q_23 = 0x0b, + + ENUM_UMAC_LMAC_PLE_TX_Q_30 = 0x0c, + ENUM_UMAC_LMAC_PLE_TX_Q_31 = 0x0d, + ENUM_UMAC_LMAC_PLE_TX_Q_32 = 0x0e, + ENUM_UMAC_LMAC_PLE_TX_Q_33 = 0x0f, + + ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0 = 0x10, + ENUM_UMAC_LMAC_PLE_TX_Q_BMC_0 = 0x11, + ENUM_UMAC_LMAC_PLE_TX_Q_BNC_0 = 0x12, + ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0 = 0x13, + + ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1 = 0x14, + ENUM_UMAC_LMAC_PLE_TX_Q_BMC_1 = 0x15, + ENUM_UMAC_LMAC_PLE_TX_Q_BNC_1 = 0x16, + ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1 = 0x17, + ENUM_UMAC_LMAC_PLE_TX_Q_NAF = 0x18, + ENUM_UMAC_LMAC_PLE_TX_Q_NBCN = 0x19, + /* DE suggests not to use 0x1f, it's only for hw free queue */ + ENUM_UMAC_LMAC_PLE_TX_Q_RELEASE = 0x1f, + ENUM_UMAC_LMAC_QUEUE_TOTAL_NUM = 24, +}; + +/* LMAC PLE For PSE Control P3 */ +enum _ENUM_UMAC_PLE_CTRL_P3_QUEUE { + ENUM_UMAC_PLE_CTRL_P3_Q_0X1E = 0x1e, + ENUM_UMAC_PLE_CTRL_P3_Q_0X1F = 0x1f, + ENUM_UMAC_PLE_CTRL_P3_TOTAL_NUM = 2 +}; + +#define WF_PSE_TOP_BASE 0x820C8000 + +#define WF_PSE_TOP_QUEUE_EMPTY_ADDR (WF_PSE_TOP_BASE + 0xB0) /* 80B0 */ +#define WF_PSE_TOP_QUEUE_EMPTY_MASK_ADDR (WF_PSE_TOP_BASE + 0xB4) /* 80B4 */ + +#define WF_PSE_TOP_FL_QUE_CTRL_0_ADDR (WF_PSE_TOP_BASE + 0x1B0) /* 81B0 */ +#define WF_PSE_TOP_FL_QUE_CTRL_1_ADDR (WF_PSE_TOP_BASE + 0x1B4) /* 81B4 */ +#define WF_PSE_TOP_FL_QUE_CTRL_2_ADDR (WF_PSE_TOP_BASE + 0x1B8) /* 81B8 */ +#define WF_PSE_TOP_FL_QUE_CTRL_3_ADDR (WF_PSE_TOP_BASE + 0x1BC) /* 81BC */ + +#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_6_EMPTY_MASK_ADDR WF_PSE_TOP_QUEUE_EMPTY_MASK_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_6_EMPTY_MASK_MASK 0x00004000 /* HIF_6_EMPTY_MASK[14] */ +#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_6_EMPTY_MASK_SHFT 14 +#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_5_EMPTY_MASK_ADDR WF_PSE_TOP_QUEUE_EMPTY_MASK_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_5_EMPTY_MASK_MASK 0x00002000 /* HIF_5_EMPTY_MASK[13] */ +#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_5_EMPTY_MASK_SHFT 13 +#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_4_EMPTY_MASK_ADDR WF_PSE_TOP_QUEUE_EMPTY_MASK_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_4_EMPTY_MASK_MASK 0x00001000 /* HIF_4_EMPTY_MASK[12] */ +#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_4_EMPTY_MASK_SHFT 12 +#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_3_EMPTY_MASK_ADDR WF_PSE_TOP_QUEUE_EMPTY_MASK_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_3_EMPTY_MASK_MASK 0x00000800 /* HIF_3_EMPTY_MASK[11] */ +#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_3_EMPTY_MASK_SHFT 11 +#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_2_EMPTY_MASK_ADDR WF_PSE_TOP_QUEUE_EMPTY_MASK_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_2_EMPTY_MASK_MASK 0x00000400 /* HIF_2_EMPTY_MASK[10] */ +#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_2_EMPTY_MASK_SHFT 10 +#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_1_EMPTY_MASK_ADDR WF_PSE_TOP_QUEUE_EMPTY_MASK_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_1_EMPTY_MASK_MASK 0x00000200 /* HIF_1_EMPTY_MASK[9] */ +#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_1_EMPTY_MASK_SHFT 9 +#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_0_EMPTY_MASK_ADDR WF_PSE_TOP_QUEUE_EMPTY_MASK_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_0_EMPTY_MASK_MASK 0x00000100 /* HIF_0_EMPTY_MASK[8] */ +#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_0_EMPTY_MASK_SHFT 8 + +#define WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_MASK 0x80000000 /* RLS_Q_EMTPY[31] */ +#define WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_SHFT 31 +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC1_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC1_QUEUE_EMPTY_MASK 0x08000000 /* MDP_RXIOC1_QE[27] */ +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC1_QUEUE_EMPTY_SHFT 27 +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC1_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC1_QUEUE_EMPTY_MASK 0x04000000 /* MDP_TXIOC1_QE[26] */ +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC1_QUEUE_EMPTY_SHFT 26 +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX1_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX1_QUEUE_EMPTY_MASK 0x02000000 /* SEC_TX1_QE[25] */ +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX1_QUEUE_EMPTY_SHFT 25 +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX1_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX1_QUEUE_EMPTY_MASK 0x01000000 /* MDP_TX1_QE[24] */ +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX1_QUEUE_EMPTY_SHFT 24 +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK 0x00800000 /* MDP_RXIOC_QE[23] */ +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_SHFT 23 +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK 0x00400000 /* MDP_TXIOC_QE[22] */ +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_SHFT 22 +#define WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK 0x00200000 /* SFD_PARK_QE[21] */ +#define WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_SHFT 21 +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_MASK 0x00100000 /* SEC_RX_QE[20] */ +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT 20 +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK 0x00080000 /* SEC_TX_QE[19] */ +#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_SHFT 19 +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK 0x00040000 /* MDP_RX_QE[18] */ +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_SHFT 18 +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK 0x00020000 /* MDP_TX_QE[17] */ +#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_SHFT 17 +#define WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK 0x00010000 /* LMAC_TX_QE[16] */ +#define WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_SHFT 16 +#define WF_PSE_TOP_QUEUE_EMPTY_HIF_6_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_HIF_6_EMPTY_MASK 0x00004000 /* HIF_6_EMPTY[14] */ +#define WF_PSE_TOP_QUEUE_EMPTY_HIF_6_EMPTY_SHFT 14 +#define WF_PSE_TOP_QUEUE_EMPTY_HIF_5_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_HIF_5_EMPTY_MASK 0x00002000 /* HIF_5_EMPTY[13] */ +#define WF_PSE_TOP_QUEUE_EMPTY_HIF_5_EMPTY_SHFT 13 +#define WF_PSE_TOP_QUEUE_EMPTY_HIF_4_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_HIF_4_EMPTY_MASK 0x00001000 /* HIF_4_EMPTY[12] */ +#define WF_PSE_TOP_QUEUE_EMPTY_HIF_4_EMPTY_SHFT 12 +#define WF_PSE_TOP_QUEUE_EMPTY_HIF_3_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_HIF_3_EMPTY_MASK 0x00000800 /* HIF_3_EMPTY[11] */ +#define WF_PSE_TOP_QUEUE_EMPTY_HIF_3_EMPTY_SHFT 11 +#define WF_PSE_TOP_QUEUE_EMPTY_HIF_2_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_HIF_2_EMPTY_MASK 0x00000400 /* HIF_2_EMPTY[10] */ +#define WF_PSE_TOP_QUEUE_EMPTY_HIF_2_EMPTY_SHFT 10 +#define WF_PSE_TOP_QUEUE_EMPTY_HIF_1_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_HIF_1_EMPTY_MASK 0x00000200 /* HIF_1_EMPTY[9] */ +#define WF_PSE_TOP_QUEUE_EMPTY_HIF_1_EMPTY_SHFT 9 +#define WF_PSE_TOP_QUEUE_EMPTY_HIF_0_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_HIF_0_EMPTY_MASK 0x00000100 /* HIF_0_EMPTY[8] */ +#define WF_PSE_TOP_QUEUE_EMPTY_HIF_0_EMPTY_SHFT 8 +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK 0x00000008 /* CPU_Q3_EMPTY[3] */ +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_SHFT 3 +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK 0x00000004 /* CPU_Q2_EMPTY[2] */ +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_SHFT 2 +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK 0x00000002 /* CPU_Q1_EMPTY[1] */ +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_SHFT 1 +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK 0x00000001 /* CPU_Q0_EMPTY[0] */ +#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_SHFT 0 + +#define WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_ADDR WF_PSE_TOP_FL_QUE_CTRL_0_ADDR +#define WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK 0x80000000 /* EXECUTE[31] */ +#define WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_SHFT 31 +#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_ADDR WF_PSE_TOP_FL_QUE_CTRL_0_ADDR +#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_MASK 0x7F000000 /* Q_BUF_QID[30..24] */ +#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT 24 +#define WF_PSE_TOP_FL_QUE_CTRL_0_FL_BUFFER_ADDR_ADDR WF_PSE_TOP_FL_QUE_CTRL_0_ADDR +#define WF_PSE_TOP_FL_QUE_CTRL_0_FL_BUFFER_ADDR_MASK 0x00FFF000 /* FL_BUFFER_ADDR[23..12] */ +#define WF_PSE_TOP_FL_QUE_CTRL_0_FL_BUFFER_ADDR_SHFT 12 +#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_PID_ADDR WF_PSE_TOP_FL_QUE_CTRL_0_ADDR +#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_PID_MASK 0x00000C00 /* Q_BUF_PID[11..10] */ +#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_PID_SHFT 10 +#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_ADDR WF_PSE_TOP_FL_QUE_CTRL_0_ADDR +#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_MASK 0x000003FF /* Q_BUF_WLANID[9..0] */ +#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_SHFT 0 + +#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_ADDR WF_PSE_TOP_FL_QUE_CTRL_2_ADDR +#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK 0x0FFF0000 /* QUEUE_TAIL_FID[27..16] */ +#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT 16 +#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_ADDR WF_PSE_TOP_FL_QUE_CTRL_2_ADDR +#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK 0x00000FFF /* QUEUE_HEAD_FID[11..0] */ +#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT 0 + +#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PAGE_NUM_ADDR WF_PSE_TOP_FL_QUE_CTRL_3_ADDR +#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PAGE_NUM_MASK 0x00FFF000 /* QUEUE_PAGE_NUM[23..12] */ +#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PAGE_NUM_SHFT 12 +#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_ADDR WF_PSE_TOP_FL_QUE_CTRL_3_ADDR +#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK 0x00000FFF /* QUEUE_PKT_NUM[11..0] */ +#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT 0 + #endif From patchwork Wed Aug 11 21:44:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Greear X-Patchwork-Id: 495571 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UPPERCASE_50_75, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 346A1C4320E for ; Wed, 11 Aug 2021 21:45:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0E0BC60F11 for ; Wed, 11 Aug 2021 21:45:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232398AbhHKVqL (ORCPT ); Wed, 11 Aug 2021 17:46:11 -0400 Received: from dispatch1-us1.ppe-hosted.com ([67.231.154.183]:59024 "EHLO dispatch1-us1.ppe-hosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232340AbhHKVpq (ORCPT ); Wed, 11 Aug 2021 17:45:46 -0400 Received: from dispatch1-us1.ppe-hosted.com (localhost.localdomain [127.0.0.1]) by dispatch1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 03E4A24AE53 for ; Wed, 11 Aug 2021 21:45:15 +0000 (UTC) X-Virus-Scanned: Proofpoint Essentials engine Received: from mx1-us1.ppe-hosted.com (unknown [10.110.51.174]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id D5A702A0074 for ; Wed, 11 Aug 2021 21:44:52 +0000 (UTC) Received: from mail3.candelatech.com (mail2.candelatech.com [208.74.158.173]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 9474F7C0066 for ; Wed, 11 Aug 2021 21:44:52 +0000 (UTC) Received: from ben-dt4.candelatech.com (50-251-239-81-static.hfc.comcastbusiness.net [50.251.239.81]) by mail3.candelatech.com (Postfix) with ESMTP id 264F913C2B7; Wed, 11 Aug 2021 14:44:52 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 mail3.candelatech.com 264F913C2B7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=candelatech.com; s=default; t=1628718292; bh=u4FuozJ3VYZ/a0gbpy61HDSMBNrkER+K0ed0WYjSpSU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VphCmOzeCjpla+9Nex7MRjhvXwvj9VMRgYyYJF0tKYN5rv/35h5b2aikaE5YWorxa MkNxUAVJRUiLiXH3Aj7Ng3AYLrnil7vFL3nxvcFLtcgx+fSFMfngdSRegbY6lvkIer caNv7FZtRMBi6PHouV5V37I26ots47saeEzvTWY4= From: greearb@candelatech.com To: linux-wireless@vger.kernel.org Cc: Ben Greear Subject: [PATCH 12/15] mt76: mt7915: add more pse queue data to debugfs Date: Wed, 11 Aug 2021 14:44:36 -0700 Message-Id: <20210811214439.17458-13-greearb@candelatech.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210811214439.17458-1-greearb@candelatech.com> References: <20210811214439.17458-1-greearb@candelatech.com> MIME-Version: 1.0 X-MDID: 1628718293-kG6eqIdbfl9V Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Ben Greear This may provide some clues in case rx packet drops are suspected. Signed-off-by: Ben Greear --- .../wireless/mediatek/mt76/mt7915/debugfs.c | 111 ++++++++ .../net/wireless/mediatek/mt76/mt7915/regs.h | 246 +++++++++++++++++- 2 files changed, 356 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c b/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c index 5c6a75f45f8f..9786fb9d7f73 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c +++ b/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c @@ -546,9 +546,120 @@ mt7915_pse_q_nonempty_stat_read_phy(struct mt7915_phy *phy, struct mt7915_dev *dev = file->private; u32 pse_stat; int i; + u32 pg_flow_ctrl[22] = {0}; + u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail; + u32 max_q, min_q, rsv_pg, used_pg; + u32 pse_buf_ctrl, pg_sz, pg_num; + pse_stat = mt76_rr(dev, WF_PSE_TOP_QUEUE_EMPTY_ADDR); + pse_buf_ctrl = mt76_rr(dev, WF_PSE_TOP_PBUF_CTRL_ADDR); + pg_flow_ctrl[0] = mt76_rr(dev, WF_PSE_TOP_FREEPG_CNT_ADDR); + pg_flow_ctrl[1] = mt76_rr(dev, WF_PSE_TOP_FREEPG_HEAD_TAIL_ADDR); + pg_flow_ctrl[2] = mt76_rr(dev, WF_PSE_TOP_PG_HIF0_GROUP_ADDR); + pg_flow_ctrl[3] = mt76_rr(dev, WF_PSE_TOP_HIF0_PG_INFO_ADDR); + pg_flow_ctrl[4] = mt76_rr(dev, WF_PSE_TOP_PG_HIF1_GROUP_ADDR); + pg_flow_ctrl[5] = mt76_rr(dev, WF_PSE_TOP_HIF1_PG_INFO_ADDR); + pg_flow_ctrl[6] = mt76_rr(dev, WF_PSE_TOP_PG_CPU_GROUP_ADDR); + pg_flow_ctrl[7] = mt76_rr(dev, WF_PSE_TOP_CPU_PG_INFO_ADDR); + pg_flow_ctrl[8] = mt76_rr(dev, WF_PSE_TOP_PG_LMAC0_GROUP_ADDR); + pg_flow_ctrl[9] = mt76_rr(dev, WF_PSE_TOP_LMAC0_PG_INFO_ADDR); + pg_flow_ctrl[10] = mt76_rr(dev, WF_PSE_TOP_PG_LMAC1_GROUP_ADDR); + pg_flow_ctrl[11] = mt76_rr(dev, WF_PSE_TOP_LMAC1_PG_INFO_ADDR); + pg_flow_ctrl[12] = mt76_rr(dev, WF_PSE_TOP_PG_LMAC2_GROUP_ADDR); + pg_flow_ctrl[13] = mt76_rr(dev, WF_PSE_TOP_LMAC2_PG_INFO_ADDR); + pg_flow_ctrl[14] = mt76_rr(dev, WF_PSE_TOP_PG_PLE_GROUP_ADDR); + pg_flow_ctrl[15] = mt76_rr(dev, WF_PSE_TOP_PLE_PG_INFO_ADDR); + pg_flow_ctrl[16] = mt76_rr(dev, WF_PSE_TOP_PG_LMAC3_GROUP_ADDR); + pg_flow_ctrl[17] = mt76_rr(dev, WF_PSE_TOP_LMAC3_PG_INFO_ADDR); + pg_flow_ctrl[18] = mt76_rr(dev, WF_PSE_TOP_PG_MDP_GROUP_ADDR); + pg_flow_ctrl[19] = mt76_rr(dev, WF_PSE_TOP_MDP_PG_INFO_ADDR); + pg_flow_ctrl[20] = mt76_rr(dev, WF_PSE_TOP_PG_PLE1_GROUP_ADDR); + pg_flow_ctrl[21] = mt76_rr(dev, WF_PSE_TOP_PLE1_PG_INFO_ADDR); + + seq_puts(file, "PSE Configuration Info:\n"); + seq_printf(file, "\tPacket Buffer Control: 0x%08x\n", pse_buf_ctrl); + + pg_sz = (pse_buf_ctrl & WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_MASK) + >> WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_SHFT; + seq_printf(file, "\t\tPage Size: %d(%d bytes per page)\n", + pg_sz, (pg_sz == 1 ? 256 : 128)); + seq_printf(file, "\t\tPage Offset: %d(in unit of 64KB)\n", + (pse_buf_ctrl & WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_MASK) + >> WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_SHFT); + pg_num = (pse_buf_ctrl & WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_MASK) + >> WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_SHFT; + seq_printf(file, "\t\tTotal page numbers: %d pages\n", pg_num); + + /* Page Flow Control */ + seq_puts(file, "PSE Page Flow Control:\n"); + seq_printf(file, "\tFree page counter: 0x%08x\n", pg_flow_ctrl[0]); + fpg_cnt = (pg_flow_ctrl[0] & WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_MASK) + >> WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_SHFT; + seq_printf(file, "\t\tThe toal page number of free: 0x%03x\n", fpg_cnt); + ffa_cnt = (pg_flow_ctrl[0] & WF_PSE_TOP_FREEPG_CNT_FFA_CNT_MASK) + >> WF_PSE_TOP_FREEPG_CNT_FFA_CNT_SHFT; + seq_printf(file, "\t\tThe free page numbers of free for all: 0x%03x\n", + ffa_cnt); + seq_printf(file, "\tFree page head and tail: 0x%08x\n", pg_flow_ctrl[1]); + fpg_head = (pg_flow_ctrl[1] & WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK) + >> WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_SHFT; + fpg_tail = (pg_flow_ctrl[1] & WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK) + >> WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_SHFT; + seq_printf(file, "\t\tThe tail/head page of free page list: 0x%03x/0x%03x\n", + fpg_tail, fpg_head); + +#define MT7915_MMQ(idx, type, text) \ + do { \ + int i2 = (idx); \ + \ + min_q = (pg_flow_ctrl[i2] & type##_MIN_QUOTA_MASK) \ + >> type##_MIN_QUOTA_SHFT; \ + max_q = (pg_flow_ctrl[i2] & type##_MAX_QUOTA_MASK) \ + >> type##_MAX_QUOTA_SHFT; \ + seq_printf(file, "\t\t%s: %d/%d\n", \ + text, max_q, min_q); \ + } while (false) + +#define MT7915_RSQ(idx, type, text) \ + do { \ + int i3 = (idx); \ + \ + rsv_pg = (pg_flow_ctrl[i3] & type##_RSV_CNT_MASK) \ + >> type##_RSV_CNT_SHFT; \ + used_pg = (pg_flow_ctrl[i3] & type##_SRC_CNT_MASK) \ + >> type##_SRC_CNT_SHFT; \ + seq_printf(file, "\t\t%s: %d/%d\n", \ + text, used_pg, rsv_pg); \ + } while (false) + +#define MT7915_MMQ_RSQ(idx, type) \ + do { \ + int i4 = (idx); \ + \ + seq_printf(file, "\tReserved page counter of " \ + #type " group: 0x%08x\n", \ + pg_flow_ctrl[i4]); \ + seq_printf(file, "\t" #type " group page status: 0x%08x\n", \ + pg_flow_ctrl[i4 + 1]); \ + MT7915_MMQ(i4, WF_PSE_TOP_PG_##type##_GROUP_##type, \ + "The max/min quota pages of " #type " group"); \ + MT7915_RSQ(i4 + 1, WF_PSE_TOP_##type##_PG_INFO_##type, \ + "The used/reserved pages of " #type " group"); \ + } while (false) + + MT7915_MMQ_RSQ(2, HIF0); + MT7915_MMQ_RSQ(4, HIF1); + MT7915_MMQ_RSQ(6, CPU); + MT7915_MMQ_RSQ(8, LMAC0); + MT7915_MMQ_RSQ(10, LMAC1); + MT7915_MMQ_RSQ(12, LMAC2); + MT7915_MMQ_RSQ(16, LMAC3); + MT7915_MMQ_RSQ(14, PLE); + MT7915_MMQ_RSQ(20, PLE1); + MT7915_MMQ_RSQ(18, MDP); + /* Queue Empty Status */ seq_puts(file, "PSE Queue Empty Status:\n"); seq_printf(file, "\tQUEUE_EMPTY: 0x%08x\n", pse_stat); diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/regs.h b/drivers/net/wireless/mediatek/mt76/mt7915/regs.h index 1e3ce90ff3dd..0bd911075aa9 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/regs.h +++ b/drivers/net/wireless/mediatek/mt76/mt7915/regs.h @@ -634,13 +634,257 @@ enum _ENUM_UMAC_PLE_CTRL_P3_QUEUE { #define WF_PSE_TOP_BASE 0x820C8000 +#define WF_PSE_TOP_GC_ADDR (WF_PSE_TOP_BASE + 0x00) /* 8000 */ +#define WF_PSE_TOP_PBUF_CTRL_ADDR (WF_PSE_TOP_BASE + 0x14) /* 8014 */ +#define WF_PSE_TOP_INT_N9_EN_MASK_ADDR (WF_PSE_TOP_BASE + 0x20) /* 8020 */ +#define WF_PSE_TOP_INT_N9_STS_ADDR (WF_PSE_TOP_BASE + 0x24) /* 8024 */ +#define WF_PSE_TOP_INT_N9_ERR_STS_ADDR (WF_PSE_TOP_BASE + 0x28) /* 8028 */ +#define WF_PSE_TOP_INT_N9_ERR_MASK_ADDR (WF_PSE_TOP_BASE + 0x2C) /* 802C */ +#define WF_PSE_TOP_INT_N9_ERR1_STS_ADDR (WF_PSE_TOP_BASE + 0x30) /* 8030 */ +#define WF_PSE_TOP_INT_N9_ERR1_MASK_ADDR (WF_PSE_TOP_BASE + 0x34) /* 8034 */ +#define WF_PSE_TOP_C_GET_FID_0_ADDR (WF_PSE_TOP_BASE + 0x40) /* 8040 */ +#define WF_PSE_TOP_C_GET_FID_1_ADDR (WF_PSE_TOP_BASE + 0x44) /* 8044 */ +#define WF_PSE_TOP_C_EN_QUEUE_0_ADDR (WF_PSE_TOP_BASE + 0x60) /* 8060 */ +#define WF_PSE_TOP_C_EN_QUEUE_1_ADDR (WF_PSE_TOP_BASE + 0x64) /* 8064 */ +#define WF_PSE_TOP_C_EN_QUEUE_2_ADDR (WF_PSE_TOP_BASE + 0x68) /* 8068 */ +#define WF_PSE_TOP_C_DE_QUEUE_0_ADDR (WF_PSE_TOP_BASE + 0x80) /* 8080 */ +#define WF_PSE_TOP_C_DE_QUEUE_1_ADDR (WF_PSE_TOP_BASE + 0x84) /* 8084 */ +#define WF_PSE_TOP_C_DE_QUEUE_2_ADDR (WF_PSE_TOP_BASE + 0x88) /* 8088 */ +#define WF_PSE_TOP_C_DE_QUEUE_3_ADDR (WF_PSE_TOP_BASE + 0x8c) /* 808C */ +#define WF_PSE_TOP_C_DE_QUEUE_4_ADDR (WF_PSE_TOP_BASE + 0x90) /* 8090 */ +#define WF_PSE_TOP_ALLOCATE_0_ADDR (WF_PSE_TOP_BASE + 0xA0) /* 80A0 */ +#define WF_PSE_TOP_ALLOCATE_1_ADDR (WF_PSE_TOP_BASE + 0xA4) /* 80A4 */ #define WF_PSE_TOP_QUEUE_EMPTY_ADDR (WF_PSE_TOP_BASE + 0xB0) /* 80B0 */ #define WF_PSE_TOP_QUEUE_EMPTY_MASK_ADDR (WF_PSE_TOP_BASE + 0xB4) /* 80B4 */ - +#define WF_PSE_TOP_FREEPG_START_END_ADDR (WF_PSE_TOP_BASE + 0xC0) /* 80C0 */ +#define WF_PSE_TOP_PSE_MODULE_CKG_DIS_ADDR (WF_PSE_TOP_BASE + 0xc4) /* 80C4 */ +#define WF_PSE_TOP_TO_N9_INT_ADDR (WF_PSE_TOP_BASE + 0xf0) /* 80F0 */ +#define WF_PSE_TOP_FREEPG_CNT_ADDR (WF_PSE_TOP_BASE + 0x100) /* 8100 */ +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_ADDR (WF_PSE_TOP_BASE + 0x104) /* 8104 */ +#define WF_PSE_TOP_GROUP_REFILL_CTRL_ADDR (WF_PSE_TOP_BASE + 0x108) /* 8108 */ +#define WF_PSE_TOP_PG_HIF0_GROUP_ADDR (WF_PSE_TOP_BASE + 0x110) /* 8110 */ +#define WF_PSE_TOP_HIF0_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x114) /* 8114 */ +#define WF_PSE_TOP_PG_HIF1_GROUP_ADDR (WF_PSE_TOP_BASE + 0x118) /* 8118 */ +#define WF_PSE_TOP_HIF1_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x11C) /* 811C */ +#define WF_PSE_TOP_PG_CPU_GROUP_ADDR (WF_PSE_TOP_BASE + 0x150) /* 8150 */ +#define WF_PSE_TOP_CPU_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x154) /* 8154 */ +#define WF_PSE_TOP_PG_PLE_GROUP_ADDR (WF_PSE_TOP_BASE + 0x160) /* 8160 */ +#define WF_PSE_TOP_PLE_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x164) /* 8164 */ +#define WF_PSE_TOP_PG_PLE1_GROUP_ADDR (WF_PSE_TOP_BASE + 0x168) /* 8168 */ +#define WF_PSE_TOP_PLE1_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x16C) /* 816C */ +#define WF_PSE_TOP_PG_LMAC0_GROUP_ADDR (WF_PSE_TOP_BASE + 0x170) /* 8170 */ +#define WF_PSE_TOP_LMAC0_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x174) /* 8174 */ +#define WF_PSE_TOP_PG_LMAC1_GROUP_ADDR (WF_PSE_TOP_BASE + 0x178) /* 8178 */ +#define WF_PSE_TOP_LMAC1_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x17C) /* 817C */ +#define WF_PSE_TOP_PG_LMAC2_GROUP_ADDR (WF_PSE_TOP_BASE + 0x180) /* 8180 */ +#define WF_PSE_TOP_LMAC2_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x184) /* 8184 */ +#define WF_PSE_TOP_PG_LMAC3_GROUP_ADDR (WF_PSE_TOP_BASE + 0x188) /* 8188 */ +#define WF_PSE_TOP_LMAC3_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x18C) /* 818C */ +#define WF_PSE_TOP_PG_MDP_GROUP_ADDR (WF_PSE_TOP_BASE + 0x198) /* 8198 */ +#define WF_PSE_TOP_MDP_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x19C) /* 819C */ +#define WF_PSE_TOP_RL_BUF_CTRL_0_ADDR (WF_PSE_TOP_BASE + 0x1A0) /* 81A0 */ +#define WF_PSE_TOP_RL_BUF_CTRL_1_ADDR (WF_PSE_TOP_BASE + 0x1A4) /* 81A4 */ #define WF_PSE_TOP_FL_QUE_CTRL_0_ADDR (WF_PSE_TOP_BASE + 0x1B0) /* 81B0 */ #define WF_PSE_TOP_FL_QUE_CTRL_1_ADDR (WF_PSE_TOP_BASE + 0x1B4) /* 81B4 */ #define WF_PSE_TOP_FL_QUE_CTRL_2_ADDR (WF_PSE_TOP_BASE + 0x1B8) /* 81B8 */ #define WF_PSE_TOP_FL_QUE_CTRL_3_ADDR (WF_PSE_TOP_BASE + 0x1BC) /* 81BC */ +#define WF_PSE_TOP_PL_QUE_CTRL_0_ADDR (WF_PSE_TOP_BASE + 0x1C0) /* 81C0 */ +#define WF_PSE_TOP_PSE_LP_CTRL_ADDR (WF_PSE_TOP_BASE + 0x1D0) /* 81D0 */ +#define WF_PSE_TOP_PSE_WFDMA_BUF_CTRL_ADDR (WF_PSE_TOP_BASE + 0x1E0) /* 81E0 */ +#define WF_PSE_TOP_PSE_CT_PRI_CTRL_ADDR (WF_PSE_TOP_BASE + 0x1EC) /* 81EC */ +#define WF_PSE_TOP_PLE_ENQ_PKT_NUM_ADDR (WF_PSE_TOP_BASE + 0x1F0) /* 81F0 */ +#define WF_PSE_TOP_CPU_ENQ_PKT_NUM_ADDR (WF_PSE_TOP_BASE + 0x1F4) /* 81F4 */ +#define WF_PSE_TOP_LMAC_ENQ_PKT_NUM_ADDR (WF_PSE_TOP_BASE + 0x1F8) /* 81F8 */ +#define WF_PSE_TOP_HIF_ENQ_PKT_NUM_ADDR (WF_PSE_TOP_BASE + 0x1FC) /* 81FC */ +#define WF_PSE_TOP_MDP_ENQ_PKT_NUM_ADDR (WF_PSE_TOP_BASE + 0x200) /* 8200 */ +#define WF_PSE_TOP_TIMEOUT_CTRL_ADDR (WF_PSE_TOP_BASE + 0x244) /* 8244 */ +#define WF_PSE_TOP_FSM_IDLE_WD_CTRL_ADDR (WF_PSE_TOP_BASE + 0x24C) /* 824C */ +#define WF_PSE_TOP_FSM_IDLE_WD_EN_ADDR (WF_PSE_TOP_BASE + 0x250) /* 8250 */ +#define WF_PSE_TOP_PSE_INTER_ERR_FLAG_ADDR (WF_PSE_TOP_BASE + 0x280) /* 8280 */ +#define WF_PSE_TOP_PSE_SER_CTRL_ADDR (WF_PSE_TOP_BASE + 0x2a0) /* 82A0 */ +#define WF_PSE_TOP_PSE_MBIST_RP_FUSE_ADDR (WF_PSE_TOP_BASE + 0x2b0) /* 82B0 */ +#define WF_PSE_TOP_PSE_MBIST_BSEL_ADDR (WF_PSE_TOP_BASE + 0x2b4) /* 82B4 */ +#define WF_PSE_TOP_SRAM_MBIST_BACKGROUND_ADDR (WF_PSE_TOP_BASE + 0x2d0) /* 82D0 */ +#define WF_PSE_TOP_PSE_MISC_FUNC_CTRL_ADDR (WF_PSE_TOP_BASE + 0x2d4) /* 82D4 */ +#define WF_PSE_TOP_SRAM_MBIST_DONE_ADDR (WF_PSE_TOP_BASE + 0x2d8) /* 82D8 */ +#define WF_PSE_TOP_SRAM_MBIST_FAIL_ADDR (WF_PSE_TOP_BASE + 0x2dc) /* 82DC */ +#define WF_PSE_TOP_SRAM_MBIST_CTRL_ADDR (WF_PSE_TOP_BASE + 0x2e0) /* 82E0 */ +#define WF_PSE_TOP_SRAM_MBIST_DELSEL_ADDR (WF_PSE_TOP_BASE + 0x2e4) /* 82E4 */ +#define WF_PSE_TOP_SRAM_AWT_HDEN_CTRL_ADDR (WF_PSE_TOP_BASE + 0x2e8) /* 82E8 */ +#define WF_PSE_TOP_PSE_SEEK_CR_00_ADDR (WF_PSE_TOP_BASE + 0x3d0) /* 83D0 */ +#define WF_PSE_TOP_PSE_SEEK_CR_01_ADDR (WF_PSE_TOP_BASE + 0x3d4) /* 83D4 */ +#define WF_PSE_TOP_PSE_SEEK_CR_02_ADDR (WF_PSE_TOP_BASE + 0x3d8) /* 83D8 */ +#define WF_PSE_TOP_PSE_SEEK_CR_03_ADDR (WF_PSE_TOP_BASE + 0x3dc) /* 83DC */ +#define WF_PSE_TOP_PSE_SEEK_CR_04_ADDR (WF_PSE_TOP_BASE + 0x3e0) /* 83E0 */ +#define WF_PSE_TOP_PSE_SEEK_CR_05_ADDR (WF_PSE_TOP_BASE + 0x3e4) /* 83E4 */ +#define WF_PSE_TOP_PSE_SEEK_CR_06_ADDR (WF_PSE_TOP_BASE + 0x3e8) /* 83E8 */ +#define WF_PSE_TOP_PSE_SEEK_CR_07_ADDR (WF_PSE_TOP_BASE + 0x3ec) /* 83EC */ +#define WF_PSE_TOP_PSE_SEEK_CR_08_ADDR (WF_PSE_TOP_BASE + 0x3f0) /* 83F0 */ +#define WF_PSE_TOP_PSE_SEEK_CR_09_ADDR (WF_PSE_TOP_BASE + 0x3f4) /* 83F4 */ + +#define WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_ADDR WF_PSE_TOP_PBUF_CTRL_ADDR +#define WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_MASK 0x80000000 /* PAGE_SIZE_CFG[31] */ +#define WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_SHFT 31 +#define WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_ADDR WF_PSE_TOP_PBUF_CTRL_ADDR +#define WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_MASK 0x03FE0000 /* PBUF_OFFSET[25..17] */ +#define WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_SHFT 17 +#define WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_ADDR WF_PSE_TOP_PBUF_CTRL_ADDR +#define WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_MASK 0x00000FFF /* TOTAL_PAGE_NUM[11..0] */ +#define WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_SHFT 0 + +#define WF_PSE_TOP_FREEPG_CNT_FFA_CNT_ADDR WF_PSE_TOP_FREEPG_CNT_ADDR +#define WF_PSE_TOP_FREEPG_CNT_FFA_CNT_MASK 0x0FFF0000 /* FFA_CNT[27..16] */ +#define WF_PSE_TOP_FREEPG_CNT_FFA_CNT_SHFT 16 +#define WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_ADDR WF_PSE_TOP_FREEPG_CNT_ADDR +#define WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_MASK 0x00000FFF /* FREEPG_CNT[11..0] */ +#define WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_SHFT 0 + +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_ADDR WF_PSE_TOP_FREEPG_HEAD_TAIL_ADDR +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK 0x0FFF0000 /* FREEPG_TAIL[27..16] */ +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_SHFT 16 +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_ADDR WF_PSE_TOP_FREEPG_HEAD_TAIL_ADDR +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK 0x00000FFF /* FREEPG_HEAD[11..0] */ +#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_SHFT 0 + +#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_ADDR WF_PSE_TOP_PG_HIF0_GROUP_ADDR +#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK 0x0FFF0000 /* HIF0_MAX_QUOTA[27..16] */ +#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_SHFT 16 +#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_ADDR WF_PSE_TOP_PG_HIF0_GROUP_ADDR +#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK 0x00000FFF /* HIF0_MIN_QUOTA[11..0] */ +#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_SHFT 0 + +#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_ADDR WF_PSE_TOP_HIF0_PG_INFO_ADDR +#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_MASK 0x0FFF0000 /* HIF0_SRC_CNT[27..16] */ +#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_SHFT 16 +#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_ADDR WF_PSE_TOP_HIF0_PG_INFO_ADDR +#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_MASK 0x00000FFF /* HIF0_RSV_CNT[11..0] */ +#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_SHFT 0 + +#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_ADDR WF_PSE_TOP_PG_HIF1_GROUP_ADDR +#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK 0x0FFF0000 /* HIF1_MAX_QUOTA[27..16] */ +#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_SHFT 16 +#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_ADDR WF_PSE_TOP_PG_HIF1_GROUP_ADDR +#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK 0x00000FFF /* HIF1_MIN_QUOTA[11..0] */ +#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_SHFT 0 + +#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_ADDR WF_PSE_TOP_HIF1_PG_INFO_ADDR +#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_MASK 0x0FFF0000 /* HIF1_SRC_CNT[27..16] */ +#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_SHFT 16 +#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_ADDR WF_PSE_TOP_HIF1_PG_INFO_ADDR +#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_MASK 0x00000FFF /* HIF1_RSV_CNT[11..0] */ +#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_SHFT 0 + +#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_ADDR WF_PSE_TOP_PG_CPU_GROUP_ADDR +#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK 0x0FFF0000 /* CPU_MAX_QUOTA[27..16] */ +#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_SHFT 16 +#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_ADDR WF_PSE_TOP_PG_CPU_GROUP_ADDR +#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK 0x00000FFF /* CPU_MIN_QUOTA[11..0] */ +#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_SHFT 0 + +#define WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_ADDR WF_PSE_TOP_CPU_PG_INFO_ADDR +#define WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_MASK 0x0FFF0000 /* CPU_SRC_CNT[27..16] */ +#define WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_SHFT 16 +#define WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_ADDR WF_PSE_TOP_CPU_PG_INFO_ADDR +#define WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_MASK 0x00000FFF /* CPU_RSV_CNT[11..0] */ +#define WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_SHFT 0 + +#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_ADDR WF_PSE_TOP_PG_PLE_GROUP_ADDR +#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK 0x0FFF0000 /* PLE_MAX_QUOTA[27..16] */ +#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_SHFT 16 +#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_ADDR WF_PSE_TOP_PG_PLE_GROUP_ADDR +#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK 0x00000FFF /* PLE_MIN_QUOTA[11..0] */ +#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_SHFT 0 + +#define WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_ADDR WF_PSE_TOP_PLE_PG_INFO_ADDR +#define WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_MASK 0x0FFF0000 /* PLE_SRC_CNT[27..16] */ +#define WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_SHFT 16 +#define WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_ADDR WF_PSE_TOP_PLE_PG_INFO_ADDR +#define WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_MASK 0x00000FFF /* PLE_RSV_CNT[11..0] */ +#define WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_SHFT 0 + +#define WF_PSE_TOP_PG_PLE1_GROUP_PLE1_MAX_QUOTA_ADDR WF_PSE_TOP_PG_PLE1_GROUP_ADDR +#define WF_PSE_TOP_PG_PLE1_GROUP_PLE1_MAX_QUOTA_MASK 0x0FFF0000 /* PLE_MAX_QUOTA[27..16] */ +#define WF_PSE_TOP_PG_PLE1_GROUP_PLE1_MAX_QUOTA_SHFT 16 +#define WF_PSE_TOP_PG_PLE1_GROUP_PLE1_MIN_QUOTA_ADDR WF_PSE_TOP_PG_PLE1_GROUP_ADDR +#define WF_PSE_TOP_PG_PLE1_GROUP_PLE1_MIN_QUOTA_MASK 0x00000FFF /* PLE_MIN_QUOTA[11..0] */ +#define WF_PSE_TOP_PG_PLE1_GROUP_PLE1_MIN_QUOTA_SHFT 0 + +#define WF_PSE_TOP_PLE1_PG_INFO_PLE1_SRC_CNT_ADDR WF_PSE_TOP_PLE1_PG_INFO_ADDR +#define WF_PSE_TOP_PLE1_PG_INFO_PLE1_SRC_CNT_MASK 0x0FFF0000 /* PLE_SRC_CNT[27..16] */ +#define WF_PSE_TOP_PLE1_PG_INFO_PLE1_SRC_CNT_SHFT 16 +#define WF_PSE_TOP_PLE1_PG_INFO_PLE1_RSV_CNT_ADDR WF_PSE_TOP_PLE1_PG_INFO_ADDR +#define WF_PSE_TOP_PLE1_PG_INFO_PLE1_RSV_CNT_MASK 0x00000FFF /* PLE_RSV_CNT[11..0] */ +#define WF_PSE_TOP_PLE1_PG_INFO_PLE1_RSV_CNT_SHFT 0 + +#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_ADDR WF_PSE_TOP_PG_LMAC0_GROUP_ADDR +#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK 0x0FFF0000 /* LMAC0_MAX_QUOTA[27..16] */ +#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_SHFT 16 +#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_ADDR WF_PSE_TOP_PG_LMAC0_GROUP_ADDR +#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK 0x00000FFF /* LMAC0_MIN_QUOTA[11..0] */ +#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_SHFT 0 + +#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_ADDR WF_PSE_TOP_LMAC0_PG_INFO_ADDR +#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK 0x0FFF0000 /* LMAC0_SRC_CNT[27..16] */ +#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_SHFT 16 +#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_ADDR WF_PSE_TOP_LMAC0_PG_INFO_ADDR +#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK 0x00000FFF /* LMAC0_RSV_CNT[11..0] */ +#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_SHFT 0 + +#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_ADDR WF_PSE_TOP_PG_LMAC1_GROUP_ADDR +#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK 0x0FFF0000 /* LMAC1_MAX_QUOTA[27..16] */ +#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_SHFT 16 +#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_ADDR WF_PSE_TOP_PG_LMAC1_GROUP_ADDR +#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK 0x00000FFF /* LMAC1_MIN_QUOTA[11..0] */ +#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_SHFT 0 + +#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_ADDR WF_PSE_TOP_LMAC1_PG_INFO_ADDR +#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK 0x0FFF0000 /* LMAC1_SRC_CNT[27..16] */ +#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_SHFT 16 +#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_ADDR WF_PSE_TOP_LMAC1_PG_INFO_ADDR +#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK 0x00000FFF /* LMAC1_RSV_CNT[11..0] */ +#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_SHFT 0 + +#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_ADDR WF_PSE_TOP_PG_LMAC2_GROUP_ADDR +#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK 0x0FFF0000 /* LMAC2_MAX_QUOTA[27..16] */ +#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_SHFT 16 +#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_ADDR WF_PSE_TOP_PG_LMAC2_GROUP_ADDR +#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK 0x00000FFF /* LMAC2_MIN_QUOTA[11..0] */ +#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_SHFT 0 + +#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_ADDR WF_PSE_TOP_LMAC2_PG_INFO_ADDR +#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK 0x0FFF0000 /* LMAC2_SRC_CNT[27..16] */ +#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_SHFT 16 +#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_ADDR WF_PSE_TOP_LMAC2_PG_INFO_ADDR +#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK 0x00000FFF /* LMAC2_RSV_CNT[11..0] */ +#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_SHFT 0 + +#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_ADDR WF_PSE_TOP_PG_LMAC3_GROUP_ADDR +#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK 0x0FFF0000 /* LMAC3_MAX_QUOTA[27..16] */ +#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_SHFT 16 +#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_ADDR WF_PSE_TOP_PG_LMAC3_GROUP_ADDR +#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK 0x00000FFF /* LMAC3_MIN_QUOTA[11..0] */ +#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_SHFT 0 + +#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_ADDR WF_PSE_TOP_LMAC3_PG_INFO_ADDR +#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK 0x0FFF0000 /* LMAC3_SRC_CNT[27..16] */ +#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_SHFT 16 +#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_ADDR WF_PSE_TOP_LMAC3_PG_INFO_ADDR +#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK 0x00000FFF /* LMAC3_RSV_CNT[11..0] */ +#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_SHFT 0 + +#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_ADDR WF_PSE_TOP_PG_MDP_GROUP_ADDR +#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK 0x0FFF0000 /* MDP_MAX_QUOTA[27..16] */ +#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_SHFT 16 +#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_ADDR WF_PSE_TOP_PG_MDP_GROUP_ADDR +#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK 0x00000FFF /* MDP_MIN_QUOTA[11..0] */ +#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_SHFT 0 + +#define WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_ADDR WF_PSE_TOP_MDP_PG_INFO_ADDR +#define WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_MASK 0x0FFF0000 /* MDP_SRC_CNT[27..16] */ +#define WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_SHFT 16 +#define WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_ADDR WF_PSE_TOP_MDP_PG_INFO_ADDR +#define WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_MASK 0x00000FFF /* MDP_RSV_CNT[11..0] */ +#define WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_SHFT 0 #define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_6_EMPTY_MASK_ADDR WF_PSE_TOP_QUEUE_EMPTY_MASK_ADDR #define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_6_EMPTY_MASK_MASK 0x00004000 /* HIF_6_EMPTY_MASK[14] */ From patchwork Wed Aug 11 21:44:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Greear X-Patchwork-Id: 495573 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4B2DC432BE for ; Wed, 11 Aug 2021 21:45:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9841660724 for ; Wed, 11 Aug 2021 21:45:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232447AbhHKVqI (ORCPT ); Wed, 11 Aug 2021 17:46:08 -0400 Received: from dispatch1-us1.ppe-hosted.com ([148.163.129.49]:52238 "EHLO dispatch1-us1.ppe-hosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232238AbhHKVp3 (ORCPT ); Wed, 11 Aug 2021 17:45:29 -0400 X-Virus-Scanned: Proofpoint Essentials engine Received: from mx1-us1.ppe-hosted.com (unknown [10.7.67.133]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id C04281C0074 for ; Wed, 11 Aug 2021 21:44:52 +0000 (UTC) Received: from mail3.candelatech.com (mail2.candelatech.com [208.74.158.173]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 8B13AB0007E for ; Wed, 11 Aug 2021 21:44:52 +0000 (UTC) Received: from ben-dt4.candelatech.com (50-251-239-81-static.hfc.comcastbusiness.net [50.251.239.81]) by mail3.candelatech.com (Postfix) with ESMTP id 4F80213C2BF; Wed, 11 Aug 2021 14:44:52 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 mail3.candelatech.com 4F80213C2BF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=candelatech.com; s=default; t=1628718292; bh=X8Zqugu+OMJeo5C8zaa/3Ph0NpZmgNtEhSXPpdJlpUU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rRknUvJQ5sIn+DY1zrjPNt4f7sSIn15GUuReMnAj//QpySdkFtCAI7VT/K9LrOBZa 1oA2XC3bimRh0AXUI56rmwmXZ2kPeYuD8KvkfrY1J7T1i/SGCBYa8SH9j1ZqmyVu/s aqT3wLAGHa08+jfVT6+/2zoREwuSl4w1jz9Glwu4= From: greearb@candelatech.com To: linux-wireless@vger.kernel.org Cc: Ben Greear Subject: [PATCH 13/15] mt76: mt7915: add rx-ppdu-size-out-of-range ethtool counter Date: Wed, 11 Aug 2021 14:44:37 -0700 Message-Id: <20210811214439.17458-14-greearb@candelatech.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210811214439.17458-1-greearb@candelatech.com> References: <20210811214439.17458-1-greearb@candelatech.com> MIME-Version: 1.0 X-MDID: 1628718293-oLya2UaV0IVH Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Ben Greear Support this additional MIB counter, it shares register with the rx-fifo-overflow counter. Signed-off-by: Ben Greear --- drivers/net/wireless/mediatek/mt76/mt7915/mac.c | 1 + drivers/net/wireless/mediatek/mt76/mt7915/main.c | 4 +++- drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h | 1 + drivers/net/wireless/mediatek/mt76/mt7915/regs.h | 1 + 4 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c index 9883d1e55f5b..44c76f7480f5 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c +++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c @@ -2146,6 +2146,7 @@ mt7915_mac_update_stats(struct mt7915_phy *phy) cnt = mt76_rr(dev, MT_MIB_SDR4(ext_phy)); mib->rx_fifo_full_cnt += FIELD_GET(MT_MIB_SDR4_RX_FIFO_FULL_MASK, cnt); + mib->rx_oor_cnt += FIELD_GET(MT_MIB_SDR4_RX_OOR_MASK, cnt); cnt = mt76_rr(dev, MT_MIB_SDR5(ext_phy)); mib->rx_mpdu_cnt += cnt; diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/main.c b/drivers/net/wireless/mediatek/mt76/mt7915/main.c index 4f609a5d38a4..fa9e3fd9bb4b 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/main.c +++ b/drivers/net/wireless/mediatek/mt76/mt7915/main.c @@ -1084,6 +1084,7 @@ static const char mt7915_gstrings_stats[][ETH_GSTRING_LEN] = { /* rx counters */ "rx_fifo_full_cnt", + "rx_oor_cnt", /* rx ppdu length is bad */ "rx_mpdu_cnt", "channel_idle_cnt", "rx_vector_mismatch_cnt", @@ -1322,7 +1323,8 @@ void mt7915_get_et_stats(struct ieee80211_hw *hw, data[ei++] = mib->tx_amsdu_pack_stats[i]; /* rx counters */ - data[ei++] = mib->rx_fifo_full_cnt; + data[ei++] = mib->rx_fifo_full_cnt; /* group-5 might exacerbate this */ + data[ei++] = mib->rx_oor_cnt; data[ei++] = mib->rx_mpdu_cnt; data[ei++] = mib->channel_idle_cnt; data[ei++] = mib->rx_vector_mismatch_cnt; diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h index 1a0d7d62c582..4515d42e5f74 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h +++ b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h @@ -168,6 +168,7 @@ struct mib_stats { /* rx stats */ u32 rx_fifo_full_cnt; + u32 rx_oor_cnt; u32 channel_idle_cnt; u32 rx_vector_mismatch_cnt; u32 rx_delimiter_fail_cnt; diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/regs.h b/drivers/net/wireless/mediatek/mt76/mt7915/regs.h index 0bd911075aa9..6898cbe34470 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/regs.h +++ b/drivers/net/wireless/mediatek/mt76/mt7915/regs.h @@ -149,6 +149,7 @@ #define MT_MIB_SDR4(_band) MT_WF_MIB(_band, 0x018) #define MT_MIB_SDR4_RX_FIFO_FULL_MASK GENMASK(15, 0) +#define MT_MIB_SDR4_RX_OOR_MASK GENMASK(23, 16) /* rx mpdu counter, full 32 bits */ #define MT_MIB_SDR5(_band) MT_WF_MIB(_band, 0x01c) From patchwork Wed Aug 11 21:44:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Greear X-Patchwork-Id: 495572 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 413F0C4338F for ; Wed, 11 Aug 2021 21:45:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 274C060724 for ; Wed, 11 Aug 2021 21:45:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232457AbhHKVqK (ORCPT ); Wed, 11 Aug 2021 17:46:10 -0400 Received: from dispatch1-us1.ppe-hosted.com ([148.163.129.49]:41006 "EHLO dispatch1-us1.ppe-hosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232251AbhHKVpb (ORCPT ); Wed, 11 Aug 2021 17:45:31 -0400 X-Virus-Scanned: Proofpoint Essentials engine Received: from mx1-us1.ppe-hosted.com (unknown [10.7.67.133]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id 2E5DB2006C for ; Wed, 11 Aug 2021 21:44:53 +0000 (UTC) Received: from mail3.candelatech.com (mail2.candelatech.com [208.74.158.173]) by mx1-us1.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTP id 0D470B0001A for ; Wed, 11 Aug 2021 21:44:53 +0000 (UTC) Received: from ben-dt4.candelatech.com (50-251-239-81-static.hfc.comcastbusiness.net [50.251.239.81]) by mail3.candelatech.com (Postfix) with ESMTP id B71AC13C35A; Wed, 11 Aug 2021 14:44:52 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 mail3.candelatech.com B71AC13C35A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=candelatech.com; s=default; t=1628718292; bh=gUPiTybpfYVVAaa4aO4DhSlMYPp2lnOkKNBbDZU5id4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pmo1z4L1/g2sDos3kVaWIjEY4G4JQEHkhSaABvFCBnT3sxHK8+XfiFAa9r3EPoFxW MLO3fqKgbliV0hVvI8Lx0WibI2/O47jb87B305PLhj1sORRJqqC6hEH4Pi2gRVUnph TDnbFeKuxxugDMivTOieOaDPh/n4XUElrx4jWDew= From: greearb@candelatech.com To: linux-wireless@vger.kernel.org Cc: Ben Greear Subject: [PATCH 15/15] mt76: mt7915: poll mib counters every 200ms Date: Wed, 11 Aug 2021 14:44:39 -0700 Message-Id: <20210811214439.17458-16-greearb@candelatech.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210811214439.17458-1-greearb@candelatech.com> References: <20210811214439.17458-1-greearb@candelatech.com> MIME-Version: 1.0 X-MDID: 1628718293-cqEXlPYjl6Td Precedence: bulk List-ID: X-Mailing-List: linux-wireless@vger.kernel.org From: Ben Greear Instead of every 500ms, this will do better job of catching wraps of 16-bit pkt counters. Signed-off-by: Ben Greear --- drivers/net/wireless/mediatek/mt76/mt7915/mac.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c index ba1c71bee149..77d7477f8667 100644 --- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c +++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c @@ -2362,7 +2362,11 @@ void mt7915_mac_work(struct work_struct *work) mutex_lock(&mphy->dev->mutex); mt76_update_survey(mphy); - if (++mphy->mac_work_count == 5) { + + /* this method is called about every 100ms. Some pkt counters are 16-bit, + * so poll every 200ms to keep overflows at a minimum. + */ + if (++mphy->mac_work_count == 2) { mphy->mac_work_count = 0; mt7915_mac_update_stats(phy);