From patchwork Wed Aug 11 11:48:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 495557 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22A55C432BE for ; Wed, 11 Aug 2021 11:48:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 01CA060FC4 for ; Wed, 11 Aug 2021 11:48:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237414AbhHKLs5 (ORCPT ); Wed, 11 Aug 2021 07:48:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237371AbhHKLs4 (ORCPT ); Wed, 11 Aug 2021 07:48:56 -0400 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B319C061765 for ; Wed, 11 Aug 2021 04:48:32 -0700 (PDT) Received: by mail-ed1-x534.google.com with SMTP id bo19so3258149edb.9 for ; Wed, 11 Aug 2021 04:48:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XqDR8o25I9iZ0astV4MjqX8UHWoiuFZZ1Xjx/J4Frsw=; b=CjpV2FHaTieFaab7z65Ddlq+e/euf14JUs8OuIRGO0rjskWhkNfmnkaUSqUCSvjDOW E+5XwPWpnADC+Cg7yE4vRXSfwCXE1EUjP/5PvskRI3sUZo2N4FC+POGxIvJtQARNtrF4 EjlyZ4LG1sXaQlE7uS71SW0LhNOHOmXCPRdnKbRrlLLmRdVmjjiqVi6tyDer51e+M5nc Bl9T8J/TTFCbip4kI23JRoV3MTooNsesJdQ3ycHMX+8qie/XqmMMDgkR5ylzrQmaJWkL D1xmzdPntg2TDUQhmXs0Vjpl6Asng9pZ5lJ28NRkJ0SHtGWg7N0jitlWn4CY3MIKLf26 noQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XqDR8o25I9iZ0astV4MjqX8UHWoiuFZZ1Xjx/J4Frsw=; b=k1+AUR9Pi7vJG3IBMS19A4UQBxxcA6YVl9YemPL80uBmXJp8t5jscxJCZe5A0E/Y+r D3nUdd2Q5EtrkEPusKJcxL77hj3iIzNq0D5QYfsoXNLfSMxqpvNK4QpBF1mM1gXBxjMD TMoMPUne8hi7Z86ru+PWdqTKub2Io/KeOnLJ0fp6KwlckNwpnqVf4WRaJpa/Mv6hxWVx eEPSoBLk25H/JSXoIL18NoE9MmtBhlHmWzUJQo9Rhr9IMptc7tHdatwli3XFmIpZQlH/ xMdCoxrU1OE4CaH6DA0vHkDegbOfeLGZJ9ZqL/Aj+/oB9OyM2CF0NSziMG781Y2WxPI+ tj/w== X-Gm-Message-State: AOAM533VcF2r3g3z8XXncbgf5qC1pC7xB7jKh15entLiDIvMte2kEPp0 RJbiRgP/MmyOAxWy65ZIoyjw8Q== X-Google-Smtp-Source: ABdhPJxPBr/lOttW3KXHEiYkxvP2K+24XoIasoO/NkyDAIWnHAl0QvjC9nJL3wA9vLAPNR8U2zYf+g== X-Received: by 2002:a50:d4cf:: with SMTP id e15mr10933562edj.2.1628682510972; Wed, 11 Aug 2021 04:48:30 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id m25sm5446793edv.81.2021.08.11.04.48.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Aug 2021 04:48:30 -0700 (PDT) From: Sam Protsenko To: Krzysztof Kozlowski , Sylwester Nawrocki , =?utf-8?q?Pawe=C5=82_Chmiel?= , Chanwoo Choi Cc: Linus Walleij , Tomasz Figa , Marc Zyngier , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v3 1/7] dt-bindings: pinctrl: samsung: Add Exynos850 doc Date: Wed, 11 Aug 2021 14:48:21 +0300 Message-Id: <20210811114827.27322-2-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210811114827.27322-1-semen.protsenko@linaro.org> References: <20210811114827.27322-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Document compatible string for Exynos850 SoC. Nothing else is changed, as Exynos850 SoC uses already existing samsung pinctrl driver. Signed-off-by: Sam Protsenko --- Changes in v3: - None Changes in v2: - This patch was made the first in the series Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index 38a1416fd2cd..e7a1b1880375 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt @@ -22,6 +22,7 @@ Required Properties: - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. - "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller. - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller. + - "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller. - reg: Base address of the pin controller hardware module and length of the address space it occupies. From patchwork Wed Aug 11 11:48:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 496403 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 493E1C432BE for ; Wed, 11 Aug 2021 11:48:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2E55661058 for ; Wed, 11 Aug 2021 11:48:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237460AbhHKLtC (ORCPT ); Wed, 11 Aug 2021 07:49:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46616 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237430AbhHKLs5 (ORCPT ); Wed, 11 Aug 2021 07:48:57 -0400 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB303C061798 for ; Wed, 11 Aug 2021 04:48:33 -0700 (PDT) Received: by mail-ed1-x536.google.com with SMTP id n12so3260088edx.8 for ; Wed, 11 Aug 2021 04:48:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IBqAGt7NCaMVSrzsG3nRnZYNyJd2DAvWfClv9tIAhNY=; b=mVxpl+IuYEZemEO9SMcLGIFeFZTygH0nPhRboBs3i9UrFGpAX585rQgd7S1Wwffk2D oN5Hw6LivDQpleLR8j0iwDtZ6Vuo7oTI3lVyJfi7K/ZJBMuEl9dLbY3zq+e6yhwODeik ZcBfJ9W6xGlzVay+icH2gXZL3wHPuj3cWTZDhTpI5+WrxPk9oinNr47AHM3aHchrh3ep elj28Ei6F1lCQsKH1iGGq8JMNouG8SqIVaRqcHL+l3XdcyceX6pFmcF4f2rgBbt6ZtfG +gUP11opeSelMEkgoh1xo8xjgp7LXQ2GWkD00dujfE1WtUc+8JEKJLjknPwv6f2LjtB9 efRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IBqAGt7NCaMVSrzsG3nRnZYNyJd2DAvWfClv9tIAhNY=; b=Rpt38p4Zbc+vtVZt//F6U+zV1ZkxkN8lsFhLHUbCBjsNL2SoIKnkeseNMUCCjeuY4w yPxshKbgqkBYqDC46y3CMYMMPEjag6aMq9WGSkxPr+fKcSTuyKhc11o1llAjQLYQjNH8 /eUeobMlFC4UGkWydK4TY96GGD/6KArvoVnItJHOPFf9onWKaORB2+xgdOQl+4qtfMDz 2xVpur8mskVPnljVcDBR3ajai5UGYeHoRtjmnkXOE4VxwjfE+pQMwRWJJqMtx9swGmIs oI8/DVQdYcbDOGCqXcEqSqVuceAIEBplWGtqBCrzotlkrnB12sge4iHrnKRaKA8HZ8/w VCmg== X-Gm-Message-State: AOAM530K2AXMKDUy4gaEHY68QQr+AmjTllK0veO07EIaK1Pwl/7VMkNJ FEox+bV2R6hmJN+TNhFvySXX7A== X-Google-Smtp-Source: ABdhPJzdhoyd6+igmt9wOLqhLsCfDszAbj6btC4lHbKMB8VJIEE/5787g0YAJPV0GFh9Wd2COZLnVA== X-Received: by 2002:a05:6402:5:: with SMTP id d5mr10658061edu.359.1628682512525; Wed, 11 Aug 2021 04:48:32 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id n10sm8159766ejk.86.2021.08.11.04.48.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Aug 2021 04:48:32 -0700 (PDT) From: Sam Protsenko To: Krzysztof Kozlowski , Sylwester Nawrocki , =?utf-8?q?Pawe=C5=82_Chmiel?= , Chanwoo Choi Cc: Linus Walleij , Tomasz Figa , Marc Zyngier , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v3 2/7] pinctrl: samsung: Add Exynos850 SoC specific data Date: Wed, 11 Aug 2021 14:48:22 +0300 Message-Id: <20210811114827.27322-3-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210811114827.27322-1-semen.protsenko@linaro.org> References: <20210811114827.27322-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add Samsung Exynos850 SoC specific data to enable pinctrl support for all platforms based on Exynos850. Signed-off-by: Sam Protsenko --- Changes in v3: - Added const qualifier to exynos850_bank_type_* structs - Added const and __initconst qualifiers to exynos850_pin_banks*[] arrays - Renamed EXYNOS9_* mactos to EXYNOS850_* Changes in v2: - Removed .suspend/.resume callbacks, as retention registers are not implemented yet for Exynos850 - Removed .eint_gpio_init for AUD domain, as there are no external interrupts available for that domain .../pinctrl/samsung/pinctrl-exynos-arm64.c | 116 ++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-exynos.h | 29 +++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 4 files changed, 148 insertions(+) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index b6e56422a700..616c7840927f 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -40,6 +40,24 @@ static const struct samsung_pin_bank_type exynos5433_bank_type_alive = { .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, }; +/* + * Bank type for non-alive type. Bit fields: + * CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4 + */ +static const struct samsung_pin_bank_type exynos850_bank_type_off = { + .fld_width = { 4, 1, 4, 4, 2, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, +}; + +/* + * Bank type for alive type. Bit fields: + * CON: 4, DAT: 1, PUD: 4, DRV: 4 + */ +static const struct samsung_pin_bank_type exynos850_bank_type_alive = { + .fld_width = { 4, 1, 4, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, +}; + /* Pad retention control code for accessing PMU regmap */ static atomic_t exynos_shared_retention_refcnt; @@ -422,3 +440,101 @@ const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = { .ctrl = exynos7_pin_ctrl, .num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl), }; + +/* pin banks of exynos850 pin-controller 0 (ALIVE) */ +static const struct samsung_pin_bank_data exynos850_pin_banks0[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), + EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), + EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), + EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), + EXYNOS850_PIN_BANK_EINTW(4, 0x080, "gpa4", 0x10), + EXYNOS850_PIN_BANK_EINTN(3, 0x0A0, "gpq0"), +}; + +/* pin banks of exynos850 pin-controller 1 (CMGP) */ +static const struct samsung_pin_bank_data exynos850_pin_banks1[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), + EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), + EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), + EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C), + EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), + EXYNOS850_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14), + EXYNOS850_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18), + EXYNOS850_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C), +}; + +/* pin banks of exynos850 pin-controller 2 (AUD) */ +static const struct samsung_pin_bank_data exynos850_pin_banks2[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), + EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gpb1", 0x04), +}; + +/* pin banks of exynos850 pin-controller 3 (HSI) */ +static const struct samsung_pin_bank_data exynos850_pin_banks3[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf2", 0x00), +}; + +/* pin banks of exynos850 pin-controller 4 (CORE) */ +static const struct samsung_pin_bank_data exynos850_pin_banks4[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), + EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04), +}; + +/* pin banks of exynos850 pin-controller 5 (PERI) */ +static const struct samsung_pin_bank_data exynos850_pin_banks5[] __initconst = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpg0", 0x00), + EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpp0", 0x04), + EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08), + EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0C), + EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg1", 0x10), + EXYNOS850_PIN_BANK_EINTG(8, 0x0A0, "gpg2", 0x14), + EXYNOS850_PIN_BANK_EINTG(1, 0x0C0, "gpg3", 0x18), + EXYNOS850_PIN_BANK_EINTG(3, 0x0E0, "gpc0", 0x1C), + EXYNOS850_PIN_BANK_EINTG(6, 0x100, "gpc1", 0x20), +}; + +static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks = exynos850_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + }, { + /* pin-controller instance 1 CMGP data */ + .pin_banks = exynos850_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + }, { + /* pin-controller instance 2 AUD data */ + .pin_banks = exynos850_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks2), + }, { + /* pin-controller instance 3 HSI data */ + .pin_banks = exynos850_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 4 CORE data */ + .pin_banks = exynos850_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 5 PERI data */ + .pin_banks = exynos850_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = { + .ctrl = exynos850_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos850_pin_ctrl), +}; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h index da1ec13697e7..bfad1ced8017 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -108,6 +108,35 @@ .pctl_res_idx = pctl_idx, \ } \ +#define EXYNOS850_PIN_BANK_EINTN(pins, reg, id) \ + { \ + .type = &exynos850_bank_type_alive, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define EXYNOS850_PIN_BANK_EINTG(pins, reg, id, offs) \ + { \ + .type = &exynos850_bank_type_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_offset = offs, \ + .name = id \ + } + +#define EXYNOS850_PIN_BANK_EINTW(pins, reg, id, offs) \ + { \ + .type = &exynos850_bank_type_alive, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_offset = offs, \ + .name = id \ + } + /** * struct exynos_weint_data: irq specific data for all the wakeup interrupts * generated by the external wakeup interrupt controller. diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 2975b4369f32..2a0fc63516f1 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1264,6 +1264,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &exynos5433_of_data }, { .compatible = "samsung,exynos7-pinctrl", .data = &exynos7_of_data }, + { .compatible = "samsung,exynos850-pinctrl", + .data = &exynos850_of_data }, #endif #ifdef CONFIG_PINCTRL_S3C64XX { .compatible = "samsung,s3c64xx-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index de44f8ec330b..4c2149e9c544 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -339,6 +339,7 @@ extern const struct samsung_pinctrl_of_match_data exynos5410_of_data; extern const struct samsung_pinctrl_of_match_data exynos5420_of_data; extern const struct samsung_pinctrl_of_match_data exynos5433_of_data; extern const struct samsung_pinctrl_of_match_data exynos7_of_data; +extern const struct samsung_pinctrl_of_match_data exynos850_of_data; extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data; extern const struct samsung_pinctrl_of_match_data s3c2412_of_data; extern const struct samsung_pinctrl_of_match_data s3c2416_of_data; From patchwork Wed Aug 11 11:48:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 496402 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DDDDC4320A for ; Wed, 11 Aug 2021 11:48:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2880460FD9 for ; Wed, 11 Aug 2021 11:48:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232155AbhHKLtH (ORCPT ); Wed, 11 Aug 2021 07:49:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237431AbhHKLtC (ORCPT ); Wed, 11 Aug 2021 07:49:02 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56AFEC0617B1 for ; Wed, 11 Aug 2021 04:48:35 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id o23so3720046ejc.3 for ; Wed, 11 Aug 2021 04:48:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dVbMUoW3ODB/HqrQj9QMsvg4UcjoOQphLtGJOfXQLG4=; b=tLqQ1Q4ZmDF0GWwO+C3F55BzoRVX2dKIyhgtgjHKKcJn/PcEISO/vhg4T66jllGPyg TjL2SEOYBd7o3vq+4AF3hONbsZpQByl/Rk2hxzZOAGtutCcFzU52yl9J+ILf6urD6uWk 3t5Jn8isV1aAB6i+H0GzYszNThuxbsDspjFZ3A/anNv1LF1M3h/KRpVJ3Xveg4LiBPXt 7WP3eNNpcEqwwR0rFHbuaOYmivA4J05/89x6Bko10CbWApIzxD0+KQdxxTtG6Gab2uAA OCrlQrN1jcMFhV/PJcP27Mks2CN71g1Hoy/V/qTiQq+3EGsfugqpRtw2o9PGX9/IjGTl zzCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dVbMUoW3ODB/HqrQj9QMsvg4UcjoOQphLtGJOfXQLG4=; b=aBDt9+wKF4iHjiAlQi5Kkqy20cmcikl0pg9nnUIc+ad9Bao95vfUdw3ZKQ8lS6zCJk 2T3nm41VZ20upRxBWlQYyBnhgTp2LJx2fl/XEu3Oevf+Bint6MtoN3jH2QvMLhqp6Fok IOluBrY4qhuLo/MZRyf+cCC4cR26zXm0Eg4YJsLakxH4gQIb3zGDiTh/V/PEA139Z9+U vcWilKXDjypoxz/EB0GDus1ENQtNFm/onfT9drPmUhlVctmCq4937kTvyQc3W5ljFKKr yVAdw8IM/ZGY66mRl+J3OrzMVnAqwwTSM4YhqLParVOMsUfpeaHTyDn7dilVs0hNlc8N EkYw== X-Gm-Message-State: AOAM530yf08opowxe/pZPW984BhU7wQqoVO6/uyAt2+PRQeLYN3ZfyuH jgv6XUzEA2/6zcpBZEXHHhhLVA== X-Google-Smtp-Source: ABdhPJxJLRHsH9CfRsfHJsy6TvmFx2W6Ic3KvGkXHyeQaKob/XnyuXcDZvw12C575KwVBsfnb1InOA== X-Received: by 2002:a17:906:5413:: with SMTP id q19mr3265627ejo.422.1628682513955; Wed, 11 Aug 2021 04:48:33 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id i10sm11096232edf.12.2021.08.11.04.48.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Aug 2021 04:48:33 -0700 (PDT) From: Sam Protsenko To: Krzysztof Kozlowski , Sylwester Nawrocki , =?utf-8?q?Pawe=C5=82_Chmiel?= , Chanwoo Choi Cc: Linus Walleij , Tomasz Figa , Marc Zyngier , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v3 3/7] dt-bindings: serial: samsung: Add Exynos850 doc Date: Wed, 11 Aug 2021 14:48:23 +0300 Message-Id: <20210811114827.27322-4-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210811114827.27322-1-semen.protsenko@linaro.org> References: <20210811114827.27322-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add compatible string for Exynos850 SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Sam Protsenko Acked-by: Rob Herring --- Changes in v3: - None Changes in v2: - None Documentation/devicetree/bindings/serial/samsung_uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml index f064e5b76cf1..2940afb874b3 100644 --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml @@ -26,6 +26,7 @@ properties: - samsung,s3c6400-uart - samsung,s5pv210-uart - samsung,exynos4210-uart + - samsung,exynos850-uart reg: maxItems: 1 From patchwork Wed Aug 11 11:48:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 495156 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:396:0:0:0:0 with SMTP id y22csp4885685jap; Wed, 11 Aug 2021 04:48:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxLvQ70GH6dmQ+gP6d5SEFbE5zR5Y0Lf9LrfXz1bCQ4lWDqLuPtlvjA8pTaK7EomaLgFopS X-Received: by 2002:a92:7b0c:: with SMTP id w12mr1166505ilc.307.1628682525151; Wed, 11 Aug 2021 04:48:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1628682525; cv=none; d=google.com; s=arc-20160816; b=jAqcWVHaUiuDPFtUklsTAP7d6pYuv1K6QdtDINA0cDPc0wRhIxEhydTlLi2Xz1A7PG /ALiT+pa0CIHp3bmq5A4rsqSYdEXgXzLVpBWAR/8//C+VQRnYWY9BQYTSpaGfCED+h4r ri4SJYbXukGI9IOYnSQQLYNhsBrTxbLHt02c5rAk4F1wpNUcSvtLxMyFGABjSwOpnyF2 4Wl1qcOman61OlhlnTkj3Q1AzPfzg0F3deQFIo7qyvlteUYTFkONQ5Q8WU+ECorvh2GT 2edKZ3EcrS79lAKnO0czd/C2wKdiUO/LqJuODmCL4cYgaWY/gdLESfJ7IsfbuSVRh3zl hP6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=15yds4+NLfeqfOc0EF0N+t+Hv6YtwmRG2QxE75vv5f4=; b=wbFDQI263JifKGs3IQZlWsLohsfr7LTLOiBYQqbpJtorZjXn4dKAcEqhdLjmehYhWo 686Nu2CeyiYW0Vay0bXSS+ZgAu67guLdio5EFSj4KzzYT/g8E2+NKf6vpzd5jSArcoWd 5BOWBPAEtWeutCmTUFQU86RF2keptm55ZemgXFJ0hCgjG2+liEPbH+Zk/hHqOmtfhTRE 3dVouHOho+ZF+irtPmOpz5iNJ//+RduJEaHW1Jrk2+8wnZFpnc68Mins1P1w8jOF8DLZ jr/Fbl8w5CtFuiuyfFmNpUfEEH/v59XLIoM5cHiNuEExevKH0+JW0t68tOOZlZe9MXIj BoIg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jkT2rtkV; spf=pass (google.com: domain of linux-serial-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id w8si581612ill.92.2021.08.11.04.48.44; Wed, 11 Aug 2021 04:48:45 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-serial-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jkT2rtkV; spf=pass (google.com: domain of linux-serial-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237522AbhHKLtF (ORCPT + 2 others); Wed, 11 Aug 2021 07:49:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237438AbhHKLtD (ORCPT ); Wed, 11 Aug 2021 07:49:03 -0400 Received: from mail-ed1-x532.google.com (mail-ed1-x532.google.com [IPv6:2a00:1450:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C011AC0617BE for ; Wed, 11 Aug 2021 04:48:36 -0700 (PDT) Received: by mail-ed1-x532.google.com with SMTP id k9so3250871edr.10 for ; Wed, 11 Aug 2021 04:48:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=15yds4+NLfeqfOc0EF0N+t+Hv6YtwmRG2QxE75vv5f4=; b=jkT2rtkVdgasC3tyUdbd1tbCUdx1RXHtzUZCBPcFXGcEhf01ZOFnIE64UnipIiTcGX HmvG4YBN471wXSAr7KMLL6y3FRFITbu9a/4wtR6lH4TjD1gOMtKTUYBnx/6rf+EGf7dg NPmMG7y6OYLFI5EJ7akmZFxrETNN3iS5kggvrhGkRu8Or0rmkJNcePCsjBRzAmvs2UnO 9doFEhD/rhaFRN8fgZClAR0lyN3P6HjU8hv9+J85OlXxJS6iA87zat9gyDyck7tsQIFG MYHeDd6cy612qvZ9roWnjodApngSXIsxAkCdSi2LtZrRZKykdtler30kTS3X4zqUzLhX CI4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=15yds4+NLfeqfOc0EF0N+t+Hv6YtwmRG2QxE75vv5f4=; b=k8YiPeyeQyGtLumnl/Um/S4yKqVSfr0OVqwKOw1xNyZJ5QQXBPuRTcWj8w9JKEb5lT 2AB2qWHEor3OahNjsw52Tzn/qFWIdY+uImv/IMCr3Y+cL94WTloflqQX7NJP8A4POIIO QLdMD7STB61uD3150fdx44aogKY/vpKP/yOwQCLl0mIyuhY3S3wpkKMnr7xvqm/wQwOB Mj8wPzTAJPaYWbu54HM+c+iHtYav4L1KITm8cbdryoG7GOGaKTicKAt1K5YhyYzO8p1k vkYtMPguKVOwNdtjnHq+6VKf6HyG+ZG0mErSCFHdI//o9CwpL52WZKDFf+ONREPiBRXu CNhA== X-Gm-Message-State: AOAM531aW/qkRwrp44DutHneqDk9VMmbqVXLDTTvfyk8kN4T/rC0494I SLiqCbLUbCkTACRSSzFb3ppF5g== X-Received: by 2002:aa7:de14:: with SMTP id h20mr10761170edv.43.1628682515357; Wed, 11 Aug 2021 04:48:35 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id r2sm6705051edv.78.2021.08.11.04.48.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Aug 2021 04:48:34 -0700 (PDT) From: Sam Protsenko To: Krzysztof Kozlowski , Sylwester Nawrocki , =?utf-8?q?Pawe=C5=82_Chmiel?= , Chanwoo Choi Cc: Linus Walleij , Tomasz Figa , Marc Zyngier , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v3 4/7] tty: serial: samsung: Init USI to keep clocks running Date: Wed, 11 Aug 2021 14:48:24 +0300 Message-Id: <20210811114827.27322-5-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210811114827.27322-1-semen.protsenko@linaro.org> References: <20210811114827.27322-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org UART block is a part of USI (Universal Serial Interface) IP-core in Samsung SoCs since Exynos9810 (e.g. in Exynos850). USI allows one to enable one of three types of serial interface: UART, SPI or I2C. That's possible because USI shares almost all internal circuits within each protocol. USI also provides some additional registers so it's possible to configure it. One USI register called USI_OPTION has reset value of 0x0. Because of this the clock gating behavior is controlled by hardware (HWACG = Hardware Auto Clock Gating), which simply means the serial won't work after reset as is. In order to make it work, USI_OPTION[2:1] bits must be set to 0b01, so that HWACG is controlled manually (by software). Bits meaning: - CLKREQ_ON = 1: clock is continuously provided to IP - CLKSTOP_ON = 0: drive IP_CLKREQ to High (needs to be set along with CLKREQ_ON = 1) USI is not present on older chips, like s3c2410, s3c2412, s3c2440, s3c6400, s5pv210, exynos5433, exynos4210. So the new boolean field '.has_usi' was added to struct s3c24xx_uart_info. USI registers will be only actually accessed when '.has_usi' field is set to "1". This feature is needed for further serial enablement on Exynos850, but some other new Exynos chips (like Exynos9810) may benefit from this feature as well. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Sam Protsenko --- Changes in v3: - Added Reviewed-by tag by Krzysztof Changes in v2: - Non-intrusive modification of USI registers - Improved comments - Rearranged USI register definitions to conform with existing style drivers/tty/serial/samsung_tty.c | 32 +++++++++++++++++++++++++++++++- include/linux/serial_s3c.h | 9 +++++++++ 2 files changed, 40 insertions(+), 1 deletion(-) -- 2.30.2 diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index 9fbc61151c2e..b8034c1168e0 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -65,6 +65,7 @@ enum s3c24xx_port_type { struct s3c24xx_uart_info { char *name; enum s3c24xx_port_type type; + unsigned int has_usi; unsigned int port_type; unsigned int fifosize; unsigned long rx_fifomask; @@ -1352,6 +1353,28 @@ static int apple_s5l_serial_startup(struct uart_port *port) return ret; } +static void exynos_usi_init(struct uart_port *port) +{ + struct s3c24xx_uart_port *ourport = to_ourport(port); + struct s3c24xx_uart_info *info = ourport->info; + unsigned int val; + + if (!info->has_usi) + return; + + /* Clear the software reset of USI block (it's set at startup) */ + val = rd_regl(port, USI_CON); + val &= ~USI_CON_RESET_MASK; + wr_regl(port, USI_CON, val); + udelay(1); + + /* Continuously provide the clock to USI IP w/o gating (for Rx mode) */ + val = rd_regl(port, USI_OPTION); + val &= ~USI_OPTION_HWACG_MASK; + val |= USI_OPTION_HWACG_CLKREQ_ON; + wr_regl(port, USI_OPTION, val); +} + /* power power management control */ static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, @@ -1379,6 +1402,7 @@ static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, if (!IS_ERR(ourport->baudclk)) clk_prepare_enable(ourport->baudclk); + exynos_usi_init(port); break; default: dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level); @@ -2102,6 +2126,8 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport, if (ret) pr_warn("uart: failed to enable baudclk\n"); + exynos_usi_init(port); + /* Keep all interrupts masked and cleared */ switch (ourport->info->type) { case TYPE_S3C6400: @@ -2750,10 +2776,11 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { #endif #if defined(CONFIG_ARCH_EXYNOS) -#define EXYNOS_COMMON_SERIAL_DRV_DATA \ +#define EXYNOS_COMMON_SERIAL_DRV_DATA_USI(_has_usi) \ .info = &(struct s3c24xx_uart_info) { \ .name = "Samsung Exynos UART", \ .type = TYPE_S3C6400, \ + .has_usi = _has_usi, \ .port_type = PORT_S3C6400, \ .has_divslot = 1, \ .rx_fifomask = S5PV210_UFSTAT_RXMASK, \ @@ -2773,6 +2800,9 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { .has_fracval = 1, \ } \ +#define EXYNOS_COMMON_SERIAL_DRV_DATA \ + EXYNOS_COMMON_SERIAL_DRV_DATA_USI(0) + static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = { EXYNOS_COMMON_SERIAL_DRV_DATA, .fifosize = { 256, 64, 16, 16 }, diff --git a/include/linux/serial_s3c.h b/include/linux/serial_s3c.h index f6c3323fc4c5..cf0de4a86640 100644 --- a/include/linux/serial_s3c.h +++ b/include/linux/serial_s3c.h @@ -27,6 +27,15 @@ #define S3C2410_UERSTAT (0x14) #define S3C2410_UFSTAT (0x18) #define S3C2410_UMSTAT (0x1C) +#define USI_CON (0xC4) +#define USI_OPTION (0xC8) + +#define USI_CON_RESET (1<<0) +#define USI_CON_RESET_MASK (1<<0) + +#define USI_OPTION_HWACG_CLKREQ_ON (1<<1) +#define USI_OPTION_HWACG_CLKSTOP_ON (1<<2) +#define USI_OPTION_HWACG_MASK (3<<1) #define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3)) From patchwork Wed Aug 11 11:48:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 495555 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC326C43214 for ; Wed, 11 Aug 2021 11:48:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D61BF6024A for ; Wed, 11 Aug 2021 11:48:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237569AbhHKLtR (ORCPT ); Wed, 11 Aug 2021 07:49:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46680 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237446AbhHKLtE (ORCPT ); Wed, 11 Aug 2021 07:49:04 -0400 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46833C061765 for ; Wed, 11 Aug 2021 04:48:38 -0700 (PDT) Received: by mail-ed1-x52d.google.com with SMTP id d6so3277875edt.7 for ; Wed, 11 Aug 2021 04:48:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HPjQiKeY/Pm3cwK5bLlcgaOU8O6PA1oY+1ashl1tZII=; b=IBsFx07oFf+vCulkJ+TaU4TZ8+TJY7oRmjHzjramGo3IIB07cb0AjF6zdiGjwHYAW1 Tqpupcr9JZsUIoJFv1IAonhPLja4SYBbpCNk3GPYB/qAtLnsD0IiIE6ENOhM2pqkGIaI DlOftRgyt6Bms1W57ULog+ewElYtugxn1FuQZRM33zfR4PP0cjXG1gn/cJpD6Sa2FwZc irT8vkNxP1o74fHgkJXCSPt8ggwKVdCqyPX+/i+Ezu0Tdba8YHfaDLvUnZzFWtmzCevp SS4oLTSxNCSMx15LdVhMiCi6HdkCWUNefTItnCF1Y8977X4crqedED2lFf/7d3JVpwmu 8Kgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HPjQiKeY/Pm3cwK5bLlcgaOU8O6PA1oY+1ashl1tZII=; b=X6Wf+RQWzCPyH7cvQ6l9rpnkhqB0iK3QC/Qvx2ZpUsHAH/r1KiKOhz0mcHkgkqWDQy Cjpm2745X/5E0Xndkt8TNJINZ/ZOsN6Ykm+IXBXvhP3SVjgLvIE5Opv07/1yQDprYGLq 6tAjeabCgTzi+/Vp4M0Dr3dcBFHs4QXJ7wxoA6hajgpcwDWvCVItNXKo1eE6mPWJAzfK yUnNHBKSCZgNCUyW6Tjr8LSkzDLhuEcp2Z68oYYhykE6L63d0okFFEGImaZJ0rZhmykw /gj224DdYFSNUlGkGYN9nXI+U/5YVzXJyKpcVl2Iuwaj4IyTUwR+h+2rfexKV0FXFagR Nn6A== X-Gm-Message-State: AOAM531SDIEKHyDenVcTqxWJCcbMlBw+4OZrW9Fg3/hUCp1yhNoMS4as tazyCVg2t+vesRxbxktSvYC7lA== X-Google-Smtp-Source: ABdhPJwwQlTLXrsIYXHANtNL1PihNzfAw6ogeS76lZDqO+9edFnOzfqvWzpuGkVw7nv8oKZ34mb/SA== X-Received: by 2002:a50:ed05:: with SMTP id j5mr11111037eds.256.1628682516768; Wed, 11 Aug 2021 04:48:36 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id lw15sm8073337ejb.50.2021.08.11.04.48.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Aug 2021 04:48:36 -0700 (PDT) From: Sam Protsenko To: Krzysztof Kozlowski , Sylwester Nawrocki , =?utf-8?q?Pawe=C5=82_Chmiel?= , Chanwoo Choi Cc: Linus Walleij , Tomasz Figa , Marc Zyngier , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v3 5/7] tty: serial: samsung: Fix driver data macros style Date: Wed, 11 Aug 2021 14:48:25 +0300 Message-Id: <20210811114827.27322-6-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210811114827.27322-1-semen.protsenko@linaro.org> References: <20210811114827.27322-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Make checkpatch happy by fixing this error: ERROR: Macros with complex values should be enclosed in parentheses Although this change is made to keep macros consistent with consequent patches (adding driver data for new SoC), it's intentionally added as a separate patch to ease possible porting efforts in future. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Sam Protsenko --- Changes in v3: - None Changes in v2: - Added Reviewed-by tag by Krzysztof Kozlowski drivers/tty/serial/samsung_tty.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index b8034c1168e0..130bdc978e93 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -2816,8 +2816,8 @@ static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = { #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data) #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data) #else -#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL -#define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL +#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)NULL) +#define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)NULL) #endif #ifdef CONFIG_ARCH_APPLE From patchwork Wed Aug 11 11:48:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 495554 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4547C4338F for ; Wed, 11 Aug 2021 11:49:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C7D7060C3E for ; Wed, 11 Aug 2021 11:49:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237517AbhHKLth (ORCPT ); Wed, 11 Aug 2021 07:49:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46642 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237449AbhHKLtE (ORCPT ); Wed, 11 Aug 2021 07:49:04 -0400 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C0B29C06139E for ; Wed, 11 Aug 2021 04:48:39 -0700 (PDT) Received: by mail-ed1-x52f.google.com with SMTP id z11so3244647edb.11 for ; Wed, 11 Aug 2021 04:48:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EmrLgkupVqTxc8/L9lxZYrujbcXsZpYLC0Uzd5BaWr4=; b=mEfotTU+4tEz1nqSr+lmns404cQ18u7hfJyZbjftAT2+YzIAkrV92eW1pwFYc+wWfb 6imwjRL4TRfc0RKuSV6SWqnCi41hQpOWLy8gn/RzXr33PwhXmkcpMBbBjOlz3k85TEMC r4U31IkAXDxL/i+h/XQKsy7tVZoqfbR5hBwk9zx0uZeSh9S5rHnA91KuUlbXHxDCi1+Z 2bCgkItJGUMVuZerKlmfupT4aKwaVHcZT8CKcrxraPpMOsCKwSVswF9xeoCrlJkj21Xx cLrmLzMfBo+Z8Amoro0etyM/RVS8OeYQkop58ySADJ9qPd1uXS8Jb3ZSQ8hEGMPdCrwd A0/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EmrLgkupVqTxc8/L9lxZYrujbcXsZpYLC0Uzd5BaWr4=; b=t5nTkPSvHz+ZOol5+xaHiv9ojEKAo3hE/S2R1Y/2rH+h/1W2JaNz3ho9Qja+D6J3xR eoc9rmkM2fgNTC5UK2vqkTHzDXRjJ1S8Spej5uYk/J7rOzp7SSCxh9VTtJhmpF/zgPep uvdRcD45Ch7ud03JYvBmMmr1jGmgYM6JbzaDS4X65NC3mGl86ldsTmN09fBbiOKUmpeX P/3c1o6qMD0lOe7Ho1KUIPpM6kOwWtB9T0Q0G9qo0xfrJaJbiEKR63KEty2A2czg3Erm 4BFXLuxwSzdJnZjyNlBBec/owQIgUQ7l8wJ3YK2cTc4QyiibrZ+Y+an4mV6tjAhi8cy/ 9qnw== X-Gm-Message-State: AOAM533k3P6LxmzzOKtNPtxEgxivTNT/JbI2bhrlIXJ2/q1NK3j4w+zu FLp4yMJsOOGFOWikftyK17ar4g== X-Google-Smtp-Source: ABdhPJzqXam1/Gn0LDYoJXt+4Sip2QlyRr/ZQ9sne5m8mRxq5wCggub4M+7avgPRrfTnLLNB5JUq7w== X-Received: by 2002:aa7:dcd1:: with SMTP id w17mr10745160edu.322.1628682518340; Wed, 11 Aug 2021 04:48:38 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id x13sm8113077ejv.64.2021.08.11.04.48.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Aug 2021 04:48:37 -0700 (PDT) From: Sam Protsenko To: Krzysztof Kozlowski , Sylwester Nawrocki , =?utf-8?q?Pawe=C5=82_Chmiel?= , Chanwoo Choi Cc: Linus Walleij , Tomasz Figa , Marc Zyngier , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v3 6/7] tty: serial: samsung: Add Exynos850 SoC data Date: Wed, 11 Aug 2021 14:48:26 +0300 Message-Id: <20210811114827.27322-7-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210811114827.27322-1-semen.protsenko@linaro.org> References: <20210811114827.27322-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add serial driver data for Exynos850 SoC. This driver data is basically reusing EXYNOS_COMMON_SERIAL_DRV_DATA, which is common for all Exynos chips, but also enables USI init, which was added in previous commit: "tty: serial: samsung: Init USI to keep clocks running". Reviewed-by: Krzysztof Kozlowski Signed-off-by: Sam Protsenko --- Changes in v3: - Added Reviewed-by tag by Krzysztof Changes in v2: - Fixed default fifo sizes drivers/tty/serial/samsung_tty.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index 130bdc978e93..a069e7bb858f 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -2813,11 +2813,19 @@ static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = { .fifosize = { 64, 256, 16, 256 }, }; +static struct s3c24xx_serial_drv_data exynos850_serial_drv_data = { + EXYNOS_COMMON_SERIAL_DRV_DATA_USI(1), + .fifosize = { 256, 64, 64, 64 }, +}; + #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data) #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data) +#define EXYNOS850_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos850_serial_drv_data) + #else #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)NULL) #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)NULL) +#define EXYNOS850_SERIAL_DRV_DATA ((kernel_ulong_t)NULL) #endif #ifdef CONFIG_ARCH_APPLE @@ -2873,6 +2881,9 @@ static const struct platform_device_id s3c24xx_serial_driver_ids[] = { }, { .name = "s5l-uart", .driver_data = S5L_SERIAL_DRV_DATA, + }, { + .name = "exynos850-uart", + .driver_data = EXYNOS850_SERIAL_DRV_DATA, }, { }, }; @@ -2896,6 +2907,8 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = { .data = (void *)EXYNOS5433_SERIAL_DRV_DATA }, { .compatible = "apple,s5l-uart", .data = (void *)S5L_SERIAL_DRV_DATA }, + { .compatible = "samsung,exynos850-uart", + .data = (void *)EXYNOS850_SERIAL_DRV_DATA }, {}, }; MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); From patchwork Wed Aug 11 11:48:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 495160 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:396:0:0:0:0 with SMTP id y22csp4886100jap; Wed, 11 Aug 2021 04:49:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxHcqcyHA2ZQ5XZtAJoG48vJtVdVS9lB+a9NDePFoVMZyc/UAOcv/diOxsKAucg/2aNTXI5 X-Received: by 2002:a05:6e02:1a43:: with SMTP id u3mr18218ilv.91.1628682555426; Wed, 11 Aug 2021 04:49:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1628682555; cv=none; d=google.com; s=arc-20160816; b=0Vv6YqvSFUpmKSsZSg5xUBcHwVyqNYGQv1Xnf3TLW4EC+f2UkqMZ0yNUbKgB6WZVKQ JNyZ3XcJ4zfeWl7gjNJaSHucnwCFAq0HJqzP3R2s9hHjHM9IcnisJ3ZGNRqzBtMCEi9f GGeT0BbgCpX0yDqm3sVJu+VHBSNzuTvCvgqGWELlFcL9GKJoCqEKGzKPZBX6W17qPBj1 KrQEkx0HvrKBBindWHgyZZmBv0PKl+aVJOm5EFO2ZApW9rjxAHWHpmvquedIlZy3TdaD mD/L4DmenkyEOEqp/YaB9tH6fHF/oamY76fk0uE8701oFIutKQnwGV0ZzBi6CYPxp4SM +nDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6SAjM69qzXk4fCE7vGVdFYc9vVok/dWqT6Ym9r8c7ZQ=; b=V6gVulz4176DwezdtHKZolUEdeP5EIGxsTGF60gqHuGBh7F1GhqS/hRWnu8l5r5GHz 22MkpAeWhMan+EsRAXc9vrPZU56KugIi/EzMCQa2l00onVqn9AUwdeovjgAClkerrY8R 84IAU29V6hE8IAqNMn0PqcSc9sSYUbJcEuLrRvgeV6+1FQ8v3kINVJUhobreyapK5OGE 8z96uris+hyikGD+x7q03WQLwmCdCZ57zZOx/0AIwReWae9WLJd4713BRfhzYZdYLCQ/ Ij3Jtx1PE4gnPnKlQ1gVqasRc/RErfY9QA0LJlQz2F9klXF5x1B15BbefOd0FSVnf1Tn aiuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="bC/t7TAn"; spf=pass (google.com: domain of linux-serial-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id w8si581612ill.92.2021.08.11.04.49.15; Wed, 11 Aug 2021 04:49:15 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-serial-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="bC/t7TAn"; spf=pass (google.com: domain of linux-serial-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237502AbhHKLtf (ORCPT + 2 others); Wed, 11 Aug 2021 07:49:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237525AbhHKLtF (ORCPT ); Wed, 11 Aug 2021 07:49:05 -0400 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D90FC0617A4 for ; Wed, 11 Aug 2021 04:48:41 -0700 (PDT) Received: by mail-ed1-x52a.google.com with SMTP id n12so3260546edx.8 for ; Wed, 11 Aug 2021 04:48:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6SAjM69qzXk4fCE7vGVdFYc9vVok/dWqT6Ym9r8c7ZQ=; b=bC/t7TAn+CIxPwLA1EH+V2uHuoOKrtxuFoLRNLUuer4EZDe7EXpN8w48djvHMTrzSF 5eh8zlGMaM2FgQE6+BT/MlLymqMkDmnbE6roZA4Q9kcwd34Pz3dJmjXr23VIHg7JtorH /F3zjiz/nH2xWHFZHlV7MI8mpuQkrrgSi33eT/S3ApnkHw8Sj3Re+kFXJzI2aZ3pYFhp xCV0jagws/IxmWnBYBwtGazAeRSfIhU+jvo2JAu1vxg6tmaoxymxNjXixBgQ69tgdEQa RnG5BO268jLmFK/pPDT4DRfA1k8a6UrP0LQ7igvWdaqVcY6e7PvSyNrlNkhnXWtRutTy sY3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6SAjM69qzXk4fCE7vGVdFYc9vVok/dWqT6Ym9r8c7ZQ=; b=lqUzT9lqk2/VH9keCZEbWNJLm0FI5uhPePTRQ9rvwwrkOlwOcW8Gnixv/OpVOuKNIm OPO9pn7IqWxiNu9x/IvdDhKmb8ajOvm3EzL0yDE3/H2hGNNU86wD6XiUWXMqboJft82W AcdaiOeJYB5gAOKZx9Bj1WnW/AQHd4b8AYWmkZV6AhXDUh50Ga3+bPy9G1JLVFWts/i5 k6uWCHbN0Np5Fq9G0fyCpKC8NOfN1Nk2bEEtgGoqGQp85+tBVAGuKBImEV2BrEwluwh4 LgeFV1H0CmnupitISk3b26GAq5ds0WeJws2aZ2lqSV53cII+iVTrpPmYwu3MjkK5z2m/ xjMg== X-Gm-Message-State: AOAM531MJupIIoX2wU0yJLpzuWId0ng4o3/bdqZBme8i7dvwJjJMkxTM xcTcaFIz/8Noi9GnnjxTjOWWZQ== X-Received: by 2002:a05:6402:26cd:: with SMTP id x13mr10987315edd.184.1628682519920; Wed, 11 Aug 2021 04:48:39 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id v21sm4541817ejw.85.2021.08.11.04.48.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Aug 2021 04:48:39 -0700 (PDT) From: Sam Protsenko To: Krzysztof Kozlowski , Sylwester Nawrocki , =?utf-8?q?Pawe=C5=82_Chmiel?= , Chanwoo Choi Cc: Linus Walleij , Tomasz Figa , Marc Zyngier , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH v3 7/7] arm64: dts: exynos: Add Exynos850 SoC support Date: Wed, 11 Aug 2021 14:48:27 +0300 Message-Id: <20210811114827.27322-8-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210811114827.27322-1-semen.protsenko@linaro.org> References: <20210811114827.27322-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Samsung Exynos850 is ARMv8-based mobile-oriented SoC. This patch adds minimal SoC support by including next Device Tree nodes: 1. Octa cores (Cortex-A55), supporting PSCI v1.0 2. ARM architecture timer (armv8-timer) 3. Interrupt controller (GIC-400) 4. Pinctrl nodes for GPIO 5. Serial node Signed-off-by: Sam Protsenko --- Changes in v3: - Used generic fixed clock for serial Changes in v2: * Commit message: - Documented added dts features instead of CPU features * exynos850-usi.dtsi: - Removed, moved everything to exynos850.dtsi * exynos850.dtsi: - Root node: - Added comment about engineering name (Exynos3830) - Renamed pinctrl nodes, adding domain names - Used hard coded IRQ numbers instead of named constants everywhere - Added soc node, moved next nodes there: gic, clock, pinctrls and serial - Used address-cells=1 for soc node and removed unneeded 0x0 from reg properties - Moved exynos850-pinctrl.dtsi include line to the end of exynos850.dtsi - Coding style fixes - cpus: - Used address-cells=1 for cpus node - Renamed cpu@0001 to cpu@1, and so on - Left only "arm,cortex-a55" for cpus compatible - Renamed reg = <0x0001> to <0x1> for cpus - armv8 timer: - Add comment about missing HV timer IRQ to armv8 timer node - Removed not existing properties from armv8 timer node - Fixed cpu number in CPU_MASK() - Removed obsolete clock-frequency property - GIC: - Fixed GIC type to be GIC-400 - Fixed size of GIC's 2nd region to be 0x2000 - serial node: - Hard coded clock number for serial_0 for now; will replace with named const once proper clock driver is implemented - Removed gate_uart_clk0 clock from serial_0, as that clock is not supported in serial driver anyway (yet) - clock node: - Fixed clock controller node name (@0x12.. -> @12..) * exynos850-pinctrl.dtsi: - Referenced pinctrl nodes instead of defining those again in root node - Fixed interrupt-cells (3 -> 2) - Fixed USI related comments for pin config nodes - Removed decon_f_te_* and fm_lna_en nodes (won't be used) - Reordered pin config nodes by pin numbers - Improved all comments - Used existing named constants for pin-function and pin-pud - Fixed node names (used hyphens instead of underscore) - Fixed warnings found in W=1 build .../boot/dts/exynos/exynos850-pinctrl.dtsi | 748 ++++++++++++++++++ arch/arm64/boot/dts/exynos/exynos850.dtsi | 261 ++++++ 2 files changed, 1009 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi -- 2.30.2 diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi new file mode 100644 index 000000000000..ba5d5f33e2f6 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi @@ -0,0 +1,748 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos850 SoC pin-mux and pin-config device tree source + * + * Copyright (C) 2017 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device + * tree nodes in this file. + */ + +#include +#include + +&pinctrl_alive { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa3: gpa3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa4: gpa4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + gpq0: gpq0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* I2C5 (also called CAM_PMIC_I2C in TRM) */ + i2c5_bus: i2c5-bus { + samsung,pins = "gpa3-5", "gpa3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + /* I2C6 (also called MOTOR_I2C in TRM) */ + i2c6_bus: i2c6-bus { + samsung,pins = "gpa3-7", "gpa4-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + /* USI: UART */ + uart0_bus: uart0-bus { + samsung,pins = "gpq0-0", "gpq0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&pinctrl_cmgp { + gpm0: gpm0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm1: gpm1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm2: gpm2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm3: gpm3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm4: gpm4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm5: gpm5 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + /* USI_CMGP0: HSI2C function */ + hsi2c3_bus: hsi2c3-bus { + samsung,pins = "gpm0-0", "gpm1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + /* USI_CMGP0: UART function (4 pins, Auto Flow Control) */ + uart1_bus_single: uart1-bus { + samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI_CMGP0: UART function (2 pins, Non-Auto Flow Control) */ + uart1_bus_dual: uart1-bus-dual { + samsung,pins = "gpm0-0", "gpm1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI_CMGP0: SPI function */ + spi1_bus: spi1-bus { + samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + spi1_cs: spi1-cs { + samsung,pins = "gpm3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + spi1_cs_func: spi1-cs-func { + samsung,pins = "gpm3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + /* USI_CMGP1: HSI2C function */ + hsi2c4_bus: hsi2c4-bus { + samsung,pins = "gpm4-0", "gpm5-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + /* USI_CMGP1: UART function (4 pins, Auto Flow Control) */ + uart2_bus_single: uart2-bus { + samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI_CMGP1: UART function (2 pins, Non-Auto Flow Control) */ + uart2_bus_dual: uart2-bus-dual { + samsung,pins = "gpm4-0", "gpm5-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI_CMGP1: SPI function */ + spi2_bus: spi2-bus { + samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + spi2_cs: spi2-cs { + samsung,pins = "gpm7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + spi2_cs_func: spi2-cs-func { + samsung,pins = "gpm7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_aud { + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + aud_codec_mclk: aud-codec-mclk { + samsung,pins = "gpb0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_codec_mclk_idle: aud-codec-mclk-idle { + samsung,pins = "gpb0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_i2s0_bus: aud-i2s0-bus { + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_i2s0_idle: aud-i2s0-idle { + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_i2s1_bus: aud-i2s1-bus { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_i2s1_idle: aud-i2s1-idle { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_fm_bus: aud-fm-bus { + samsung,pins = "gpb1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_fm_idle: aud-fm-idle { + samsung,pins = "gpb1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&pinctrl_hsi { + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sd2_clk_fast_slew_rate_1x: sd2-clk-fast-slew-rate-1x { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + sd2_clk_fast_slew_rate_1_5x: sd2-clk-fast-slew-rate-1-5x { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <1>; + }; + + sd2_clk_fast_slew_rate_2x: sd2-clk-fast-slew-rate-2x { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sd2_clk_fast_slew_rate_2_5x: sd2-clk-fast-slew-rate-2-5x { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; + + sd2_clk_fast_slew_rate_3x: sd2-clk-fast-slew-rate-3x { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <4>; + }; + + sd2_clk_fast_slew_rate_4x: sd2-clk-fast-slew-rate-4x { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <5>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpf2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpf2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpf2-3", "gpf2-4", "gpf2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sd2_pins_as_pdn: sd2-pins-as-pdn { + samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", + "gpf2-4", "gpf2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&pinctrl_core { + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk: sd0-clk { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; + + sd0_clk_fast_slew_rate_1x: sd0-clk-fast-slew-rate-1x { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <1>; + }; + + sd0_clk_fast_slew_rate_2x: sd0-clk-fast-slew-rate-2x { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sd0_clk_fast_slew_rate_3x: sd0-clk-fast-slew-rate-3x { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sd0_clk_fast_slew_rate_4x: sd0-clk-fast-slew-rate-4x { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpf0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; + + sd0_rdqs: sd0-rdqs { + samsung,pins = "gpf0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; + + sd0_nreset: sd0-nreset { + samsung,pins = "gpf0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpf1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <3>; + }; +}; + +&pinctrl_peri { + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp0: gpp0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp1: gpp1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp2: gpp2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg3: gpg3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* USI: HSI2C0 */ + hsi2c0_bus: hsi2c0-bus { + samsung,pins = "gpc1-0", "gpc1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + /* USI: HSI2C1 */ + hsi2c1_bus: hsi2c1-bus { + samsung,pins = "gpc1-2", "gpc1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + /* USI: HSI2C2 */ + hsi2c2_bus: hsi2c2-bus { + samsung,pins = "gpc1-4", "gpc1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + /* USI: SPI */ + spi0_bus: spi0-bus { + samsung,pins = "gpp2-0", "gpp2-2", "gpp2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + spi0_cs: spi0-cs { + samsung,pins = "gpp2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + spi0_cs_func: spi0-cs-func { + samsung,pins = "gpp2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + i2c0_bus: i2c0-bus { + samsung,pins = "gpp0-0", "gpp0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + i2c1_bus: i2c1-bus { + samsung,pins = "gpp0-2", "gpp0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + i2c2_bus: i2c2-bus { + samsung,pins = "gpp0-4", "gpp0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + i2c3_bus: i2c3-bus { + samsung,pins = "gpp1-0", "gpp1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + i2c4_bus: i2c4-bus { + samsung,pins = "gpp1-2", "gpp1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <0>; + }; + + sensor_mclk0_in: sensor-mclk0-in { + samsung,pins = "gpc0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sensor_mclk0_out: sensor-mclk0-out { + samsung,pins = "gpc0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sensor_mclk0_fn: sensor-mclk0-fn { + samsung,pins = "gpc0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sensor_mclk1_in: sensor-mclk1-in { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sensor_mclk1_out: sensor-mclk1-out { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sensor_mclk1_fn: sensor-mclk1-fn { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sensor_mclk2_in: sensor-mclk2-in { + samsung,pins = "gpc0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sensor_mclk2_out: sensor-mclk2-out { + samsung,pins = "gpc0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + sensor_mclk2_fn: sensor-mclk2-fn { + samsung,pins = "gpc0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = <2>; + }; + + xclkout: xclkout { + samsung,pins = "gpq0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi new file mode 100644 index 000000000000..2360f142159f --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -0,0 +1,261 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Exynos850 SoC device tree source + * + * Copyright (C) 2018 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Samsung Exynos850 SoC device nodes are listed in this file. + * Exynos based board files can include this file and provide + * values for board specific bindings. + */ + +#include + +/ { + /* Also known under engineering name Exynos3830 */ + compatible = "samsung,exynos850"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <1>; + + aliases { + pinctrl0 = &pinctrl_alive; + pinctrl1 = &pinctrl_cmgp; + pinctrl2 = &pinctrl_aud; + pinctrl3 = &pinctrl_hsi; + pinctrl4 = &pinctrl_core; + pinctrl5 = &pinctrl_peri; + serial0 = &serial_0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x1>; + enable-method = "psci"; + }; + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x2>; + enable-method = "psci"; + }; + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x3>; + enable-method = "psci"; + }; + cpu4: cpu@4 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + }; + cpu5: cpu@5 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x101>; + enable-method = "psci"; + }; + cpu6: cpu@6 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x102>; + enable-method = "psci"; + }; + cpu7: cpu@7 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x103>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + /* Hypervisor Virtual Timer interrupt is not wired to GIC */ + interrupts = , + , + , + ; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x20000000>; + + gic: interrupt-controller@12a01000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + reg = <0x12a01000 0x1000>, + <0x12a02000 0x2000>, + <0x12a04000 0x2000>, + <0x12a06000 0x2000>; + interrupt-controller; + interrupts = ; + }; + + /* + * Keep the stub clock for serial driver, until proper clock + * driver is implemented. + */ + uart_clock: uart-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "uart"; + }; + + pinctrl_alive: pinctrl@11850000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x11850000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + }; + }; + + pinctrl_cmgp: pinctrl@11c30000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x11c30000 0x1000>; + interrupts = , + , + , + , + , + , + , + ; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + }; + }; + + pinctrl_aud: pinctrl@14a60000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x14a60000 0x1000>; + }; + + pinctrl_hsi: pinctrl@13430000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x13430000 0x1000>; + interrupts = ; + }; + + pinctrl_core: pinctrl@12070000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x12070000 0x1000>; + interrupts = ; + }; + + pinctrl_peri: pinctrl@139b0000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x139b0000 0x1000>; + interrupts = ; + }; + + /* USI: UART */ + serial_0: uart@13820000 { + compatible = "samsung,exynos850-uart"; + reg = <0x13820000 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + clocks = <&uart_clock>; + clock-names = "uart"; + status = "disabled"; + }; + }; +}; + +#include "exynos850-pinctrl.dtsi"