From patchwork Fri Aug 6 11:29:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 493518 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3DECC4338F for ; Fri, 6 Aug 2021 11:32:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DA4E061176 for ; Fri, 6 Aug 2021 11:32:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245518AbhHFLcr (ORCPT ); Fri, 6 Aug 2021 07:32:47 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:12975 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238025AbhHFLcq (ORCPT ); Fri, 6 Aug 2021 07:32:46 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1628249551; x=1659785551; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rYqo0be+dvZrTBodvT604I50n0YL2LfsXiX7MNehf50=; b=ohGr7YarwksVEdGzm0KWMhNs0oNqIP2vjpcItHlF7l4y5hdRz9+lcWCB 4CdDCvV4DlI/0UVs8/fgSYlXl3qobmL2MucA/k3YPqi7LzF0DRmbWsfdv 1FXH+CPT6t3piH7ueiCvW8Hj/IChmobRXrAhk06ADVAg6inuG8WzpjfZv z2v2ZhUM8ypQYabUnsUDEvGPSdpfWlx1paTes1eaKqXwmTDwVNf9FzDwQ DSSAuZakDSD/DeD+CCvLNd88LWBZOeQu3lzzH99GLJf9J+wkgVYgOmUaU oWgUVMByiefvMFd+/0ehf5sfNTAvBxNMtQTgzlhZc0OU523lQQRyEwtD/ w==; IronPort-SDR: UkgAR6wJAwZNS04zBjeeVREIZJPzayLIWRAgeLz+klAeltWA5M9rKQcv/NXjPVPmQ1qFZlGTW9 NV9zeuzUCjsCwg7+uKkhI8Ti0LKpdK3w6dPLIO4trJ/a7a3TVok/nu8Bnx3rYm+f3xqcphdJXg v7TjE4K9fdx2vsvEvr7iaMK9N9bL0/vIxr+Abgjrwcnrsw5VC+gaW/as/Yx1PvehsgBTV2LD9X jT/ReX1xR0KO7gAaQTN3YBiODwF/85szQ2Ub+nWG0KFMOS+iU7fuU6EqgChd5aUIoE/5q7eOHr mUGt6r7PRGE1VFX/lpB/YDse X-IronPort-AV: E=Sophos;i="5.84,300,1620716400"; d="scan'208";a="127352552" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Aug 2021 04:32:31 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Fri, 6 Aug 2021 04:32:30 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Fri, 6 Aug 2021 04:32:26 -0700 From: Claudiu Beznea To: , , , , CC: , , , , Claudiu Beznea Subject: [PATCH 1/4] dt-bindings: mmc: pwrseq-sd8787: add binding for delay b/w reset and power Date: Fri, 6 Aug 2021 14:29:58 +0300 Message-ID: <20210806113001.821660-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210806113001.821660-1-claudiu.beznea@microchip.com> References: <20210806113001.821660-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add documentation for binding that specifies the delay that should be introduced b/w reset and power lines when powering up the device. Signed-off-by: Claudiu Beznea --- Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.yaml b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.yaml index e0169a285aa2..4b1e89750e94 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.yaml @@ -23,6 +23,10 @@ properties: description: contains a reset GPIO specifier with the default active state + reset-power-delay-ms: + description: + Delay in ms between powerdown and reset gpios + required: - compatible - powerdown-gpios From patchwork Fri Aug 6 11:29:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 493059 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46DC1C4338F for ; Fri, 6 Aug 2021 11:32:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2D09960FE7 for ; Fri, 6 Aug 2021 11:32:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235600AbhHFLdG (ORCPT ); Fri, 6 Aug 2021 07:33:06 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:1540 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238025AbhHFLdF (ORCPT ); Fri, 6 Aug 2021 07:33:05 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1628249571; x=1659785571; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EID46DOm+2UZGwugv+D7K8O0cradNPo86JFfmDOuibE=; b=GSSc4hrTK0Lshr3QGYP3eL0MO7Yw6FyvaO5PC+3ejIDv3md0jmr3rDrz 3F4Ibkzk28IXymxP2kCwbHIG3slfI7GSabhrPyuxehfBa4oh8SjjNzxNy ZWTX5BYw/A8NPiUpFDnsR9KLI6g6Vw5oSZ2pfWK85c/OqTsvX7+rQVZb3 0jfRStkMipah2a2XaIUtThwetoUTdSIZ1/6YRpvwWy6kqKC6n77awderv Vg7pDEAa1Dvh6j8o2NGFcyd/n223yNNHd45nepg6t99edhz9EhTO9bGUV LDxE6feXdzHoKSD7OnZjUMY4BBVbZVFChooDAXw5SRMHLLqBC8dFloBi9 w==; IronPort-SDR: v+2qe6BEIeCvs6RLsU8fNwCSTymjsQqoyOzMT82Xr739l/aIrhkU97HipgqxsB8I9krCW06jSP VE1AT4XAK/nEAk550I/qR38CoKYtbifpLSQoP12ujfVtbdsLF56xvYxdSO3vlMLFW1RU3NoHIb a0w9NkS5IekCyVsOaXgTnAh3kdvewFN3YDu0oZz0baybEGXcp4n2rZi8lWGpf8S0vdCoaGPvFc 7NLnh0sv/A6EV6Lplt77aszOwjdtdsYNGk7BxCpEq/60mVTzsgGthe/8ctfPEgjb7LhCRMvual Av8UUQCON2q5cqjeoVIICIyX X-IronPort-AV: E=Sophos;i="5.84,300,1620716400"; d="scan'208";a="131292912" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Aug 2021 04:32:50 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Fri, 6 Aug 2021 04:32:49 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Fri, 6 Aug 2021 04:32:31 -0700 From: Claudiu Beznea To: , , , , CC: , , , , Claudiu Beznea Subject: [PATCH 2/4] mmc: pwrseq: sd8787: add support for specifying the delay b/w power and reset Date: Fri, 6 Aug 2021 14:29:59 +0300 Message-ID: <20210806113001.821660-3-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210806113001.821660-1-claudiu.beznea@microchip.com> References: <20210806113001.821660-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add support to be able to specify the delay to be introduced b/w power and reset lines on power up sequence. With this, the driver could also be used by other WiFi chips (e.g. WILC1000/WILC3000 devices that need a delay of 5ms b/w power and reset line for a proper powering up sequence). Signed-off-by: Claudiu Beznea --- drivers/mmc/core/pwrseq_sd8787.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/core/pwrseq_sd8787.c b/drivers/mmc/core/pwrseq_sd8787.c index 68a826f1c0a1..a554eefdf1b1 100644 --- a/drivers/mmc/core/pwrseq_sd8787.c +++ b/drivers/mmc/core/pwrseq_sd8787.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -27,6 +28,7 @@ struct mmc_pwrseq_sd8787 { struct mmc_pwrseq pwrseq; struct gpio_desc *reset_gpio; struct gpio_desc *pwrdn_gpio; + u32 reset_pwrdwn_delay_ms; }; #define to_pwrseq_sd8787(p) container_of(p, struct mmc_pwrseq_sd8787, pwrseq) @@ -37,7 +39,7 @@ static void mmc_pwrseq_sd8787_pre_power_on(struct mmc_host *host) gpiod_set_value_cansleep(pwrseq->reset_gpio, 1); - msleep(300); + msleep(pwrseq->reset_pwrdwn_delay_ms); gpiod_set_value_cansleep(pwrseq->pwrdn_gpio, 1); } @@ -64,6 +66,7 @@ static int mmc_pwrseq_sd8787_probe(struct platform_device *pdev) { struct mmc_pwrseq_sd8787 *pwrseq; struct device *dev = &pdev->dev; + int ret; pwrseq = devm_kzalloc(dev, sizeof(*pwrseq), GFP_KERNEL); if (!pwrseq) @@ -77,6 +80,12 @@ static int mmc_pwrseq_sd8787_probe(struct platform_device *pdev) if (IS_ERR(pwrseq->reset_gpio)) return PTR_ERR(pwrseq->reset_gpio); + ret = device_property_read_u32(dev, "reset-power-delay-ms", + &pwrseq->reset_pwrdwn_delay_ms); + /* Keep compatibility with old devices. */ + if (ret) + pwrseq->reset_pwrdwn_delay_ms = 300; + pwrseq->pwrseq.dev = dev; pwrseq->pwrseq.ops = &mmc_pwrseq_sd8787_ops; pwrseq->pwrseq.owner = THIS_MODULE; From patchwork Fri Aug 6 11:30:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 493517 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62E26C432BE for ; Fri, 6 Aug 2021 11:33:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 423AF611ED for ; Fri, 6 Aug 2021 11:33:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245538AbhHFLdR (ORCPT ); Fri, 6 Aug 2021 07:33:17 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:1555 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245528AbhHFLdQ (ORCPT ); Fri, 6 Aug 2021 07:33:16 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1628249582; x=1659785582; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fWsatgcloSsqrB7wvaudTGqBX8SMP/WQ4Wac0C232F0=; b=e8hZ4ueFyO6teZum9nhCHDkbCtB6S67QBWybCBvrwsD16sOCsnoNPzy3 tKbBWywoev7MtYZh4r8+b1TL+/Xd4JoUx62BsOUMC1SAAK95/OAs8nUp/ u91PqBqJYu5c9j3c1HBMGlDq+LVoKt+HzUS2B/FWfJDymz7dbN67un5zC bntEb0+rYM0uPF0CgH5VUYv3+wloZSEskd65GmDAxlZJOrfwBRmxxTjX/ C7G9k9tQUlSTqmBPG9nlKBDc+vAc+EwdWYqyBF859vdTsWpwneKXiu+ud XmcgCuNHhmir7le7pF9p/vBOqdtMlI6EhlXUsPYy0/nAJRdfrwyt3LQd/ A==; IronPort-SDR: bLp8kW0I9z1F93DdPPuNjojyxZDjb+egPuLsdA5Ba4GDPvR5RSlo/NawHzsOEH+cTFGaho2RL9 bLBiIZk+UVKkBzl/wuFZHbmsGKbeANhzaRXg6x2U4ETLKnM+skKspJprOWJxEjhzHSljqtaMy3 pfGXjmS75yJTdFMFoUTFfJ9/roCnOXT9k378tu7jjhs5edI66f8Pp5OMxUXlTQN83+tYczUH2+ wpd9vGjXp19w488lItv3tgXxj095UkR67evJHKE2z5wL4rnptCSK/DaRcnINCmeMFUv63Ouc/6 ZglEM+fddHGkQ8kckxJ16HQ2 X-IronPort-AV: E=Sophos;i="5.84,300,1620716400"; d="scan'208";a="131292925" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Aug 2021 04:33:00 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Fri, 6 Aug 2021 04:32:59 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Fri, 6 Aug 2021 04:32:53 -0700 From: Claudiu Beznea To: , , , , CC: , , , , Claudiu Beznea Subject: [PATCH 3/4] mmc: pwrseq: add wilc1000_sdio dependency for pwrseq_sd8787 Date: Fri, 6 Aug 2021 14:30:00 +0300 Message-ID: <20210806113001.821660-4-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210806113001.821660-1-claudiu.beznea@microchip.com> References: <20210806113001.821660-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org pwseq_sd8787 could also be used with wilc1000_sdio driver. Add a dependency for this. Signed-off-by: Claudiu Beznea --- drivers/mmc/core/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/core/Kconfig b/drivers/mmc/core/Kconfig index ae8b69aee619..6f25c34e4fec 100644 --- a/drivers/mmc/core/Kconfig +++ b/drivers/mmc/core/Kconfig @@ -15,7 +15,7 @@ config PWRSEQ_EMMC config PWRSEQ_SD8787 tristate "HW reset support for SD8787 BT + Wifi module" - depends on OF && (MWIFIEX || BT_MRVL_SDIO || LIBERTAS_SDIO) + depends on OF && (MWIFIEX || BT_MRVL_SDIO || LIBERTAS_SDIO || WILC1000_SDIO) help This selects hardware reset support for the SD8787 BT + Wifi module. By default this option is set to n. From patchwork Fri Aug 6 11:30:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 493058 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BC08C432BE for ; Fri, 6 Aug 2021 11:33:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 45B1361050 for ; Fri, 6 Aug 2021 11:33:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245548AbhHFLdX (ORCPT ); Fri, 6 Aug 2021 07:33:23 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:1563 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245541AbhHFLdW (ORCPT ); Fri, 6 Aug 2021 07:33:22 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1628249588; x=1659785588; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uQOYpWS7Qrcgkx+VH2ts2v8g+61j0yRDKNU96qalLg4=; b=Rnm9vVU5D4m8Qf489qC5xnKgVPQshdxz7UuHBE3QzbqHh7BpcQxGsmT/ LX0kev5uJVJXtqM130zGBvBOQWqPEQvZX+4eB3Rxwk+6wh5caAlPJ1DLZ HRrn1+OVaFouaCr9z5KK2YUDBKImECLEatD9aIqxYVq6MlmOcdb2goE99 QrIyttTcnxdeF6Wf8o3fZT2m5wrKT4I7NllzEyVlrmRG2fEfltnivv6XT 94Oy7UCSnUXroBSAwfYOrsUWel4xS5zil3oSMFw+9sQbfZ2ZqwaXi2w/J 7+O3QebU6nRwJpkEJpA6VVGKGp4rWGd8UkyBBgF6BBSSrt5q12OegLgYG A==; IronPort-SDR: N9C65RxcqZ5RibRA/eC5z1L/pV/gBDNOXlTzOYwpwpNylUaCJ3ylAAuoEdKVouZqPp4Vselt0P MJ6I92rqREF/8FpbNcqfE42jxt/mf/g/8SXuASVY0le5hSmWoblXXybnPCXG+IR8FCp8e3aEta mu7+SBZssYCxwVfwV/bOnOYuecFjhWjmfMJR3rBUyKFa5EF1StPR42VxSPfA9+qmk4jyC8C2ua dfWeoKyUFvVflXXwDZTSYMvTq2r6B8MbWGbZNCUZWcmwJneYD8YaxqoE+xYCXmjfdm3i17Wr49 ATbysUABDpGKTeuoQyDN7edy X-IronPort-AV: E=Sophos;i="5.84,300,1620716400"; d="scan'208";a="131292938" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 06 Aug 2021 04:33:06 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Fri, 6 Aug 2021 04:33:04 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Fri, 6 Aug 2021 04:32:59 -0700 From: Claudiu Beznea To: , , , , CC: , , , , "Eugen Hristev" , Claudiu Beznea Subject: [PATCH 4/4] ARM: dts: at91: sama5d27_wlsom1: add wifi device Date: Fri, 6 Aug 2021 14:30:01 +0300 Message-ID: <20210806113001.821660-5-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210806113001.821660-1-claudiu.beznea@microchip.com> References: <20210806113001.821660-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Eugen Hristev SAMA5D27 WLSOM1 boards has a WILC3000 device soldered. Add proper device tree nodes for this. [eugen.hristev: original author of this code] Signed-off-by: Eugen Hristev [nicolas.ferre: original author of this code] Signed-off-by: Nicolas Ferre [claudiu.beznea: adapt for mmc-pwrseq-sd8787, commit message] Signed-off-by: Claudiu Beznea --- arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 72 +++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi index 025a78310e3a..de8bb3439aef 100644 --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi @@ -30,6 +30,16 @@ main_xtal { clock-frequency = <24000000>; }; }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-sd8787"; + reset-gpios = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>; + powerdown-gpios = <&pioA PIN_PA29 GPIO_ACTIVE_HIGH>; + reset-power-delay-ms = <5>; + pinctrl-0 = <&pinctrl_wilc_pwrseq>; + pinctrl-names = "default"; + status = "okay"; + }; }; &flx1 { @@ -310,5 +320,67 @@ pinctrl_qspi1_default: qspi1_default { ; bias-pull-up; }; + + pinctrl_sdmmc1_default: sdmmc1_default { + cmd-data { + pinmux = , + , + , + , + ; + bias-disable; + }; + + conf-ck { + pinmux = ; + bias-disable; + }; + }; + + pinctrl_wilc_default: wilc_default { + conf-irq { + pinmux = ; + bias-disable; + }; + }; + + pinctrl_wilc_pwrseq: wilc_pwrseq { + conf-ce-nrst { + pinmux = , + ; + bias-disable; + }; + + conf-rtcclk { + pinmux = ; + bias-disable; + }; + }; +}; + +&sdmmc1 { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_default>; + mmc-pwrseq = <&wifi_pwrseq>; + no-1-8-v; + non-removable; + status = "okay"; + + wilc: wilc@0 { + reg = <0>; + bus-width = <4>; + compatible = "microchip,wilc3000", "microchip,wilc1000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wilc_default>; + irq-gpios = <&pioA PIN_PB25 GPIO_ACTIVE_LOW>; + clocks = <&pmc PMC_TYPE_SYSTEM 9>; + clock-names = "rtc"; + assigned-clocks = <&pmc PMC_TYPE_SYSTEM 9>; + assigned-clock-rates = <32768>; + status = "okay"; + }; };