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Mon, 24 Sep 2018 12:01:07 +0100 (BST) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eucas1p2.samsung.com (KnoxPortal) with ESMTP id 20180924110106eucas1p2465d1fdd263f7921ae6e9c65d32155f6~XUQHvobiN0510705107eucas1p2n; Mon, 24 Sep 2018 11:01:06 +0000 (GMT) X-AuditID: cbfec7f5-34dff700000012c6-fd-5ba8c3f3f371 Received: from eusync4.samsung.com ( [203.254.199.214]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 9D.AC.04128.2F3C8AB5; Mon, 24 Sep 2018 12:01:06 +0100 (BST) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0PFK00L7C3XQOM40@eusync4.samsung.com>; Mon, 24 Sep 2018 12:01:06 +0100 (BST) From: Marek Szyprowski To: linux-clk@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Joonyoung Shim , Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz Subject: [PATCH] clk: samsung: exynos5420: Define CLK_SECKEY gate clock only or Exynos5420 Date: Mon, 24 Sep 2018 13:00:56 +0200 Message-id: <20180924110056.21033-1-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprJIsWRmVeSWpSXmKPExsWy7djP87qfD6+INrjxi8Vi44z1rBbXvzxn tXhx7yKLxfnzG9gtPvbcY7WYcX4fk8XaI3fZLdqfvmR24PDYtKqTzaNvyypGj8+b5AKYo7hs UlJzMstSi/TtErgyjp9/wFQwmadia+ct5gbGLVxdjJwcEgImEnu3fmTsYuTiEBJYwShx5PN3 KOczo8Tkp1+ZYKqW3N7PDmILCSxjlDj9ggeiqIFJomNaIzNIgk3AUKLrbRcbiC0i4CDx+dNr sEnMAr1MEv9PXwRLCAvESDz/dQxsEouAqkTHy31gcV4BW4mD/8+yQmyTl1i94QAzSLOEwFNW ic+n57FDJFwk3mz9CmULS7w6vgXKlpG4PLmbBaKhmVGifcYsdginh1Fi65wdbBBV1hKHj18E W8EswCcxadt0oBUcQHFeiY42IYgSD4lpT5eyQfwZK7GpcQHbBEaJBYwMqxjFU0uLc9NTi43z Usv1ihNzi0vz0vWS83M3MQIj7PS/4193MO77k3SIUYCDUYmHl+He8mgh1sSy4srcQ4wSHMxK Irxut4BCvCmJlVWpRfnxRaU5qcWHGKU5WJTEefm00qKFBNITS1KzU1MLUotgskwcnFINjGvP r1hwv/zr04ja6nuOk8Ju+0Z/S3WLFxOS0l50YoeMtoBgbJ9KmQBH9sHOXTcyfVb2TP7w97nh 1apXh9gue5/JfsZcYDmJReBZ76+GyYXH519YarN+Oqeu7X+flE2Z770PXznTfnm35qYw2ZxD YZPn/HWdtI+/cOKmAOHqeX8/2exqLWBREFBiKc5INNRiLipOBAAAHu8PrAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrNJMWRmVeSWpSXmKPExsVy+t/xa7qfDq+INti6jtti44z1rBbXvzxn tXhx7yKLxfnzG9gtPvbcY7WYcX4fk8XaI3fZLdqfvmR24PDYtKqTzaNvyypGj8+b5AKYo7hs UlJzMstSi/TtErgyjp9/wFQwmadia+ct5gbGLVxdjJwcEgImEktu72fvYuTiEBJYwijxdO1z FginiUmio+0FK0gVm4ChRNfbLjYQW0TAQeLzp9eMIEXMAv1MEjuPvmUGSQgLxEi8vPacCcRm EVCV6Hi5D6yBV8BW4uD/s6wQ6+QlVm84wDyBkWsBI8MqRpHU0uLc9NxiI73ixNzi0rx0veT8 3E2MwCDYduznlh2MXe+CDzEKcDAq8fCuuL08Wog1say4MvcQowQHs5IIr9stoBBvSmJlVWpR fnxRaU5q8SFGaQ4WJXHe8waVUUIC6YklqdmpqQWpRTBZJg5OqQbG6Xve/D/2r3P3lp+sdq57 5Vn+ru7dG/D++81lN4tX57tv9txqnaQxk9tQU0Pm3HWmn0zq9xXzfzVJhvGxnYj5+zGdKf/J Sr3LCecctwXq+mrYpR0UNmq/dc7MYGe9s1XEyli+6mnezx+59fDv1Y4MVNDS/3N9W5/mo+Yn UgvWGK6X2Hbv+nQGJZbijERDLeai4kQAWQbCJP4BAAA= X-CMS-MailID: 20180924110106eucas1p2465d1fdd263f7921ae6e9c65d32155f6 X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20180924110106eucas1p2465d1fdd263f7921ae6e9c65d32155f6 References: Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org From: Joonyoung Shim The bit of GATE_BUS_PERIS1 for CLK_SECKEY is just reserved on exynos5422/5800, not exynos5420. Define gate clk for exynos5420 to handle the bit only on exynos5420. Signed-off-by: Joonyoung Shim [m.szyprow: rewrote commit subject] Signed-off-by: Marek Szyprowski --- drivers/clk/samsung/clk-exynos5420.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 76e7686c6162..a2d6e7f4bcd3 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -568,6 +568,7 @@ static const struct samsung_div_clock exynos5420_div_clks[] __initconst = { }; static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = { + GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk", SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0), }; @@ -1097,8 +1098,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0), GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0), - GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0), - /* GEN Block */ GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0), GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),