From patchwork Mon Sep 24 05:50:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 147337 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp326615lji; Sun, 23 Sep 2018 22:50:52 -0700 (PDT) X-Google-Smtp-Source: ACcGV63tlMjvTKuhtrM1ru01OU6AnlRo3YmUH1aIZufLoV4EbNcrn98BvgqvEXK3WH/tZZmvexYS X-Received: by 2002:a17:902:6689:: with SMTP id e9-v6mr8993823plk.115.1537768252700; Sun, 23 Sep 2018 22:50:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537768252; cv=none; d=google.com; s=arc-20160816; b=D2AQIScezVNbDJmqawcZI3q4CpHojygIsaa+1V4SoRfu4i51bDxesS18sk8ZanimST b5dttJO9wmeZ4ZmgdainZpPngdvJCfr9t9wS1gTCdRWgtwqLRJ4P/Y7yuKWOzxBTAB4n x0SMBd7OeqxLF8Ct0nHYv4a48/tS74d6M77esAEV9P0b8v7jJAwsVeHFC9rhSZXXIX4u zCPrqHgezRFiX9r3nENKXdDLjtJ2wLyDjNKnbA8Snz9NtxWWodQKlbm4/PpP0yvujw/4 bSdv0m4zh5MzhatHfCkhVNgWXZuW+NzsDD2TIJWty10RhL6bCGsa9Ukq/XeSQnH135XU TIjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=fgMUOehphvZNmcYG2yU0po/x+iNAshQ5kx+eSduG4BU=; b=g9WK7s1N/4hts3dyXhvKihFYOyxQCX7DEwEt0TjsUPAM2kmtoWUyVdNeNExeFez5J+ LweK+g+jVjxkCq49uxSgXG+Fw94W5IOijx0YkovvJfdEKKNKE9xs5poVbu+BqX6SZKpp TP5PnWiKBFXM4uJcGv4OiQ1V6OcBnhQz9BeI1LHx4qUIf3y0NKW5LWrLPr5kG/kkMiL7 LBq4i7i1fdv2oGd37Mvwdfz/vANjB/W5/2fYP6ZbeQHkFQBvIRglFpnkv9eiN45XtukN puF2DFsNyp6IekCPwAq0M4GvTEdTptLrgVBNycY3WUwiQ8n8SzgVizXvP03/BtDd0EOs h7Uw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="f/1h4Lig"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.136.154.89]) by smtp.gmail.com with ESMTPSA id w94-v6sm43886226wrc.38.2018.09.23.22.50.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 23 Sep 2018 22:50:43 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: mingo@kernel.org, Keerthy , Tony Lindgren , linux-kernel@vger.kernel.org (open list:CLOCKSOURCE, CLOCKEVENT DRIVERS) Subject: [PATCH 1/2] clocksource/drivers/ti-32k: Add CLOCK_SOURCE_SUSPEND_NONSTOP flag for non-am43 SoCs Date: Mon, 24 Sep 2018 07:50:28 +0200 Message-Id: <1537768229-3241-1-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Keerthy The 32k clocksource is NONSTOP for non-am43 SoCs. Hence add the flag for all the other SoCs. Reported-by: Tony Lindgren Signed-off-by: Keerthy Acked-by: Tony Lindgren Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-ti-32k.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.7.4 diff --git a/drivers/clocksource/timer-ti-32k.c b/drivers/clocksource/timer-ti-32k.c index 29e2e1a..6949a91 100644 --- a/drivers/clocksource/timer-ti-32k.c +++ b/drivers/clocksource/timer-ti-32k.c @@ -97,6 +97,9 @@ static int __init ti_32k_timer_init(struct device_node *np) return -ENXIO; } + if (!of_machine_is_compatible("ti,am43")) + ti_32k_timer.cs.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; + ti_32k_timer.counter = ti_32k_timer.base; /* From patchwork Mon Sep 24 05:50:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 147338 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp326621lji; Sun, 23 Sep 2018 22:50:53 -0700 (PDT) X-Google-Smtp-Source: ACcGV62TmU6zzxalHeqXfN96AluVZdhgKjVe3KKMuDbpgOJDMItHS48uABG0sWRA02Hq1obU7SD+ X-Received: by 2002:a63:5964:: with SMTP id j36-v6mr7956117pgm.222.1537768253042; Sun, 23 Sep 2018 22:50:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537768253; cv=none; d=google.com; s=arc-20160816; b=n1Ho3gpBjRFz2W45WoRkExwpvdHxMVcD5HbI/8LUGjeUdIO/kiI46RwFLUbF7KULBV WJg/lPcpZeqYHOBcSzDMCL8UwvoxyqjHDzpIIgwBxcPIdqHsqj55Wv0UtumzhZWa9qpM LXI1yytU2NHpKrQ4MrRl/n55HSE/lssqfD8AH1p672lDzlGTTAja4VAUiwW1mhsGwPKD Oh3VK0AdlvStCGLWC2r2tA2l3LEegtXvY3KIwHcjI400M49vGjkozfWNlOat6Ia0nwzt 7JDsKv2ShPmRuIBdNXJ+ubk83vNaBwaZpaXk0iIhlivwc1SPYcv6BHu+TMwCTCwrGTA5 udCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=pldtDI51qYuZ3dKbItu0/9cAgULQDz05Gb+R9ZIrxLA=; b=d5rwdW6suU0SyI0JFeun0Qs9IelJInZxEwNIWDMl6kqons5TNKhZGMZbcZv+VQdjwb lAnj0IYN0m/VX+hq4CgPfVCE7/tXep4ph16wVQy4OHRB7HhlLr6j2NVLVPrvrsf+B/Rl yirtGtlnrVecvWe5k1BlK8ACGV3KM2LzkYXMIm194oI787ppdn1yNh6HUc64QPZXGDc8 T1jy4/Qi0+Ubm1t2ZaRPe5/gFPYw05g46EK/IS1Rd1BZOaXU+TA/GaDy8IUAb/jy3SdP 87JhvTVqPdmP37GKhMZcIjdnT20xZzS3oZL6DLW59DZiO/5s/HH55sguvxXn+bJnlFQc Tkcw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MgtPRmyS; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.136.154.89]) by smtp.gmail.com with ESMTPSA id w94-v6sm43886226wrc.38.2018.09.23.22.50.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 23 Sep 2018 22:50:45 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: mingo@kernel.org, Tao Ren , Lei YU , linux-kernel@vger.kernel.org (open list:CLOCKSOURCE, CLOCKEVENT DRIVERS) Subject: [PATCH 2/2] clocksource/drivers/fttmr010: Fix set_next_event handler Date: Mon, 24 Sep 2018 07:50:29 +0200 Message-Id: <1537768229-3241-2-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537768229-3241-1-git-send-email-daniel.lezcano@linaro.org> References: <1537768229-3241-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Tao Ren Currently, the aspeed MATCH1 register is updated to in set_next_event handler, with the assumption that COUNT register value is preserved when the timer is disabled and it continues decrementing after the timer is enabled. But the assumption is wrong: RELOAD register is loaded into COUNT register when the aspeed timer is enabled, which means the next event may be delayed because timer interrupt won't be generated until <0xFFFFFFFF - current_count + cycles>. The problem can be fixed by updating RELOAD register to , and COUNT register will be re-loaded when the timer is enabled and interrupt is generated when COUNT register overflows. The test result on Facebook Backpack-CMM BMC hardware (AST2500) shows the issue is fixed: without the patch, usleep(100) suspends the process for several milliseconds (and sometimes even over 40 milliseconds); after applying the fix, usleep(100) takes averagely 240 microseconds to return under the same workload level. Signed-off-by: Tao Ren Reviewed-by: Linus Walleij Tested-by: Lei YU Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-fttmr010.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) -- 2.7.4 diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c index c020038..cf93f64 100644 --- a/drivers/clocksource/timer-fttmr010.c +++ b/drivers/clocksource/timer-fttmr010.c @@ -130,13 +130,17 @@ static int fttmr010_timer_set_next_event(unsigned long cycles, cr &= ~fttmr010->t1_enable_val; writel(cr, fttmr010->base + TIMER_CR); - /* Setup the match register forward/backward in time */ - cr = readl(fttmr010->base + TIMER1_COUNT); - if (fttmr010->count_down) - cr -= cycles; - else - cr += cycles; - writel(cr, fttmr010->base + TIMER1_MATCH1); + if (fttmr010->count_down) { + /* + * ASPEED Timer Controller will load TIMER1_LOAD register + * into TIMER1_COUNT register when the timer is re-enabled. + */ + writel(cycles, fttmr010->base + TIMER1_LOAD); + } else { + /* Setup the match register forward in time */ + cr = readl(fttmr010->base + TIMER1_COUNT); + writel(cr + cycles, fttmr010->base + TIMER1_MATCH1); + } /* Start */ cr = readl(fttmr010->base + TIMER_CR);