From patchwork Sun Aug 1 04:05:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 490181 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC491C4338F for ; Sun, 1 Aug 2021 04:06:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 889F560249 for ; Sun, 1 Aug 2021 04:06:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229576AbhHAEGV (ORCPT ); Sun, 1 Aug 2021 00:06:21 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:48109 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229491AbhHAEGV (ORCPT ); Sun, 1 Aug 2021 00:06:21 -0400 X-UUID: c0a184bf8ca04392a4dc94520dfad349-20210801 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=c7qAG0km9s8UfLDAudvX69W67QH1Jy3xeC2kKUw1eTc=; b=p5ClV3oGYWHXiUTG4P2YkRWXzMMgdxO8A1TBu1LSHxjK/pe6L4x339t1HR0k+uywAydmoinCirsH3Snixz8iYpuqRe989b/etUwKsXaBvk8/z4Ey8+maRs9RYmbMglnRpFEvYOTN6RK7+vE6taz2wwalHE6DdZq2m/J7z7M45ow=; X-UUID: c0a184bf8ca04392a4dc94520dfad349-20210801 Received: from mtkcas32.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 458207670; Sun, 01 Aug 2021 12:06:10 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS33N2.mediatek.inc (172.27.4.76) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 1 Aug 2021 12:06:05 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (10.16.6.18) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 1 Aug 2021 12:06:04 +0800 From: Jitao Shi To: Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , Daniel Vetter , David Airlie , , CC: , , , , , , , , , Jitao Shi Subject: [PATCH v4 1/2] drm/mediatek: force hsa hbp hfp packets multiple of lanenum to avoid screen shift Date: Sun, 1 Aug 2021 12:05:43 +0800 Message-ID: <20210801040544.104135-1-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-TM-SNTS-SMTP: BC15D500DEC9D58CBE5FB134A9971573A631EA12E984F2BAB0B2E7A33414CDA12000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The bridge chip ANX7625 requires the packets on lanes aligned at the end, or ANX7625 will shift the screen. Signed-off-by: Jitao Shi --- drivers/gpu/drm/mediatek/mtk_dsi.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.25.1 diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index ae403c67cbd9..4735e0092ffe 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -194,6 +194,8 @@ struct mtk_dsi { struct clk *hs_clk; u32 data_rate; + /* force dsi line end without dsi_null data */ + bool force_dsi_end_without_null; unsigned long mode_flags; enum mipi_dsi_pixel_format format; @@ -499,6 +501,13 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) DRM_WARN("HFP + HBP less than d-phy, FPS will under 60Hz\n"); } + if (dsi->force_dsi_end_without_null) { + horizontal_sync_active_byte = roundup(horizontal_sync_active_byte, dsi->lanes) - 2; + horizontal_frontporch_byte = roundup(horizontal_frontporch_byte, dsi->lanes) - 2; + horizontal_backporch_byte = roundup(horizontal_backporch_byte, dsi->lanes) - 2; + horizontal_backporch_byte -= (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes; + } + writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC); writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC); @@ -1095,6 +1104,10 @@ static int mtk_dsi_probe(struct platform_device *pdev) dsi->bridge.of_node = dev->of_node; dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; + if (dsi->next_bridge) + dsi->force_dsi_end_without_null = of_property_read_bool(dsi->next_bridge->of_node, + "force_dsi_end_without_null"); + drm_bridge_add(&dsi->bridge); ret = component_add(&pdev->dev, &mtk_dsi_component_ops); From patchwork Sun Aug 1 04:05:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 490500 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94BCDC432BE for ; Sun, 1 Aug 2021 04:06:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7B95960249 for ; Sun, 1 Aug 2021 04:06:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229736AbhHAEGa (ORCPT ); Sun, 1 Aug 2021 00:06:30 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:6443 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229491AbhHAEGa (ORCPT ); Sun, 1 Aug 2021 00:06:30 -0400 X-UUID: a75e0143f8a2404fa033d902be4dc94c-20210801 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=tVl842wftAnMAO9fwQ64B34pCPAJw05tuHgSke2JKe4=; b=V7x4lR2wEadoplFzF4wIcrDWb1gb1tgNB79eydi28JSz8TdVoJhSW6ZQJuTsn+gnzyib6M40L/mK4FGh0WceccKdvO1S++iFvnev5AITtHMTZj0z7NpG29flygqKF+PRP+lfnllummKzuYEUhzSvkz71AGvISRq9Rq41VFBOcqk=; X-UUID: a75e0143f8a2404fa033d902be4dc94c-20210801 Received: from mtkmrs31.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 461988250; Sun, 01 Aug 2021 12:06:16 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS33N1.mediatek.inc (172.27.4.75) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 1 Aug 2021 12:06:14 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (10.16.6.18) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 1 Aug 2021 12:06:13 +0800 From: Jitao Shi To: Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , Daniel Vetter , David Airlie , , CC: , , , , , , , , , Jitao Shi Subject: [PATCH v4 2/2] dt-bindings: mediatek: add force_dsi_end_without_null Date: Sun, 1 Aug 2021 12:05:44 +0800 Message-ID: <20210801040544.104135-2-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210801040544.104135-1-jitao.shi@mediatek.com> References: <20210801040544.104135-1-jitao.shi@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 274FAD2CEAB345486A9ACF4D6C3725599FB588F1E24F37B11444DDF0626652F32000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The force_dsi_end_without_null requires the dsi host ent at the same time in line. Signed-off-by: Jitao Shi --- .../bindings/display/bridge/analogix,anx7625.yaml | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.25.1 diff --git a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml index ab48ab2f4240..8b868a6a3d60 100644 --- a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml +++ b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml @@ -43,6 +43,11 @@ properties: vdd33-supply: description: Regulator that provides the supply 3.3V power. + force_dsi_end_without_null: + description: | + Requires the dsi host send the dsi packets on all lanes aligned + at the end. + ports: $ref: /schemas/graph.yaml#/properties/ports @@ -87,6 +92,7 @@ examples: vdd10-supply = <&pp1000_mipibrdg>; vdd18-supply = <&pp1800_mipibrdg>; vdd33-supply = <&pp3300_mipibrdg>; + force_dsi_end_without_null; ports { #address-cells = <1>;