From patchwork Sat Jul 31 17:38:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 490045 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D232C19F35 for ; Sat, 31 Jul 2021 17:39:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DCFF060F94 for ; Sat, 31 Jul 2021 17:39:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231577AbhGaRjI (ORCPT ); Sat, 31 Jul 2021 13:39:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231467AbhGaRjG (ORCPT ); Sat, 31 Jul 2021 13:39:06 -0400 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EDB49C0613CF; Sat, 31 Jul 2021 10:38:59 -0700 (PDT) Received: by mail-lj1-x232.google.com with SMTP id x7so17599096ljn.10; Sat, 31 Jul 2021 10:38:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3PQPHGOW6QQhg7v1jHH53jvk1y+aGZu+fHQa7m9Qum4=; b=UDr7pC40P/YfA0jkgVCLqi0PdJSkiZfDidxhht9T9p6KDVIJLT2ux5UUNgcUOauiYd Qg00SvX57IqEE0eL89RSXMWveWXGDzOEDX7zhXeVVlPZ/mEo1zODJabOv39ik8dZynI0 rvJ3uLn2nvpD4gvNpQ92c3g7FL+wHEp9tN6vdFwQh1VOzrUu4TjkrNp03nAn6k/Sellt TuH+6vfSnlqbFq0Lb6YXNkIY20/QylZ7Aj310PZEApO8B1BO0LXBJBNZ9ZxxydEc1bRB XYxoBHDuelDkvERBIWd+oxRB4dOHmm64fsgcdqxRso74szheA4tjroTD51CLlu2qsVga Pq6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3PQPHGOW6QQhg7v1jHH53jvk1y+aGZu+fHQa7m9Qum4=; b=cd/xy1A/+hSLiZbQaB7SVNF1ZhX6M+QAgMiZUCVxfdaPcWM0Q9cgbQyxr+lsA5UyYF 1kfbeWFG9EqSLBVW0qgp3yEUuVNq8ITfHGAlZ1XCuEdAg2cUN9ADsV+6uAvNO/rqpXeL REvg3ADf2FGqxvTjCS9KTzhFmKB7t447Akyv2nsdO6ZXaWjXRVdi4HRBah726UhBjgbZ iVcVisnS47kdPddcwtnz6NtlkPddJHgff7ayjQs+0UnJnuKPPG9CVtnokK4t19ethrBQ o+JdwS9DtYwl5o3meGhJMVfBdHUrmef5Zd7R5kkOufDiSnS0fBZpRyBsjFbXdV3B+4wK +gdw== X-Gm-Message-State: AOAM532l5lVzIalk/95OigUcwR3GpVaF72o+oz8zxmL4oIpWmjj9F4/V P2U1bc5Ac5Mq8FW2LxRjpOk= X-Google-Smtp-Source: ABdhPJyhqbVkgs6HS/sDLeUPU8r1Y3+jJWMz1zEi/VmpDY1c4z6uXO+hM4QHMY1GQLmb71jBo+Hg/Q== X-Received: by 2002:a05:651c:1143:: with SMTP id h3mr5619898ljo.300.1627753138271; Sat, 31 Jul 2021 10:38:58 -0700 (PDT) Received: from localhost.localdomain (94-29-22-96.dynamic.spd-mgts.ru. [94.29.22.96]) by smtp.gmail.com with ESMTPSA id s15sm445272lfp.216.2021.07.31.10.38.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Jul 2021 10:38:57 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Sebastian Reichel , Peter Chen , Greg Kroah-Hartman , Felipe Balbi , David Heidelberg Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v6 01/12] dt-bindings: phy: tegra20-usb-phy: Convert to schema Date: Sat, 31 Jul 2021 20:38:31 +0300 Message-Id: <20210731173842.19643-2-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210731173842.19643-1-digetx@gmail.com> References: <20210731173842.19643-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Convert NVIDIA Tegra20 USB PHY binding to schema. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../bindings/phy/nvidia,tegra20-usb-phy.txt | 74 ---- .../bindings/phy/nvidia,tegra20-usb-phy.yaml | 357 ++++++++++++++++++ 2 files changed, 357 insertions(+), 74 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt create mode 100644 Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt deleted file mode 100644 index 1aa6f2674af5..000000000000 --- a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt +++ /dev/null @@ -1,74 +0,0 @@ -Tegra SOC USB PHY - -The device node for Tegra SOC USB PHY: - -Required properties : - - compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy". - For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain - "nvidia,-usb-phy" plus at least one of the above, where is - tegra114, tegra124, tegra132, or tegra210. - - reg : Defines the following set of registers, in the order listed: - - The PHY's own register set. - Always present. - - The register set of the PHY containing the UTMI pad control registers. - Present if-and-only-if phy_type == utmi. - - phy_type : Should be one of "utmi", "ulpi" or "hsic". - - clocks : Defines the clocks listed in the clock-names property. - - clock-names : The following clock names must be present: - - reg: The clock needed to access the PHY's own registers. This is the - associated EHCI controller's clock. Always present. - - pll_u: PLL_U. Always present. - - timer: The timeout clock (clk_m). Present if phy_type == utmi. - - utmi-pads: The clock needed to access the UTMI pad control registers. - Present if phy_type == utmi. - - ulpi-link: The clock Tegra provides to the ULPI PHY (usually pad DAP_MCLK2 - with pad group aka "nvidia,pins" cdev2 and pin mux option config aka - "nvidia,function" pllp_out4). - Present if phy_type == ulpi, and ULPI link mode is in use. - - resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names : Must include the following entries: - - usb: The PHY's own reset signal. - - utmi-pads: The reset of the PHY containing the chip-wide UTMI pad control - registers. Required even if phy_type == ulpi. - -Required properties for phy_type == ulpi: - - nvidia,phy-reset-gpio : The GPIO used to reset the PHY. - -Required PHY timing params for utmi phy, for all chips: - - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before - start of sync launches RxActive - - nvidia,elastic-limit : Variable FIFO Depth of elastic input store - - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait - before declare IDLE. - - nvidia,term-range-adj : Range adjusment on terminations - - Either one of the following for HS driver output control: - - nvidia,xcvr-setup : integer, uses the provided value. - - nvidia,xcvr-setup-use-fuses : boolean, indicates that the value is read - from the on-chip fuses - If both are provided, nvidia,xcvr-setup-use-fuses takes precedence. - - nvidia,xcvr-lsfslew : LS falling slew rate control. - - nvidia,xcvr-lsrslew : LS rising slew rate control. - -Required PHY timing params for utmi phy, only on Tegra30 and above: - - nvidia,xcvr-hsslew : HS slew rate control. - - nvidia,hssquelch-level : HS squelch detector level. - - nvidia,hsdiscon-level : HS disconnect detector level. - -Optional properties: - - nvidia,has-legacy-mode : boolean indicates whether this controller can - operate in legacy mode (as APX 2500 / 2600). In legacy mode some - registers are accessed through the APB_MISC base address instead of - the USB controller. - - nvidia,is-wired : boolean. Indicates whether we can do certain kind of power - optimizations for the devices that are always connected. e.g. modem. - - dr_mode : dual role mode. Indicates the working mode for the PHY. Can be - "host", "peripheral", or "otg". Defaults to "host" if not defined. - host means this is a host controller - peripheral means it is device controller - otg means it can operate as either ("on the go") - - nvidia,has-utmi-pad-registers : boolean indicates whether this controller - contains the UTMI pad control registers common to all USB controllers. - -VBUS control (required for dr_mode == otg, optional for dr_mode == host): - - vbus-supply: regulator for VBUS diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml new file mode 100644 index 000000000000..593187234e6a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml @@ -0,0 +1,357 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra USB PHY + +maintainers: + - Dmitry Osipenko + - Jon Hunter + - Thierry Reding + +properties: + compatible: + oneOf: + - items: + - enum: + - nvidia,tegra124-usb-phy + - nvidia,tegra114-usb-phy + - enum: + - nvidia,tegra30-usb-phy + - items: + - enum: + - nvidia,tegra30-usb-phy + - nvidia,tegra20-usb-phy + + reg: + minItems: 1 + maxItems: 2 + description: | + PHY0 and PHY2 share power and ground, PHY0 contains shared registers. + PHY0 and PHY2 must specify two register sets, where the first set is + PHY own registers and the second set is the PHY0 registers. + + clocks: + anyOf: + - items: + - description: Registers clock + - description: Main PHY clock + + - items: + - description: Registers clock + - description: Main PHY clock + - description: ULPI PHY clock + + - items: + - description: Registers clock + - description: Main PHY clock + - description: UTMI pads control registers clock + + - items: + - description: Registers clock + - description: Main PHY clock + - description: UTMI timeout clock + - description: UTMI pads control registers clock + + clock-names: + oneOf: + - items: + - const: reg + - const: pll_u + + - items: + - const: reg + - const: pll_u + - const: ulpi-link + + - items: + - const: reg + - const: pll_u + - const: utmi-pads + + - items: + - const: reg + - const: pll_u + - const: timer + - const: utmi-pads + + resets: + oneOf: + - maxItems: 1 + description: PHY reset + + - items: + - description: PHY reset + - description: UTMI pads reset + + reset-names: + oneOf: + - const: usb + + - items: + - const: usb + - const: utmi-pads + + "#phy-cells": + const: 0 + + phy_type: + $ref: /schemas/types.yaml#/definitions/string + enum: [utmi, ulpi, hsic] + + dr_mode: + $ref: /schemas/types.yaml#/definitions/string + enum: [host, peripheral, otg] + default: host + + vbus-supply: + description: Regulator controlling USB VBUS. + + nvidia,has-legacy-mode: + description: | + Indicates whether this controller can operate in legacy mode + (as APX 2500 / 2600). In legacy mode some registers are accessed + through the APB_MISC base address instead of the USB controller. + type: boolean + + nvidia,is-wired: + description: | + Indicates whether we can do certain kind of power optimizations for + the devices that are always connected. e.g. modem. + type: boolean + + nvidia,has-utmi-pad-registers: + description: | + Indicates whether this controller contains the UTMI pad control + registers common to all USB controllers. + type: boolean + + nvidia,hssync-start-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + description: | + Number of 480 MHz clock cycles to wait before start of sync launches + RxActive. + + nvidia,elastic-limit: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + description: Variable FIFO Depth of elastic input store. + + nvidia,idle-wait-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + description: | + Number of 480 MHz clock cycles of idle to wait before declare IDLE. + + nvidia,term-range-adj: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: Range adjustment on terminations. + + nvidia,xcvr-setup: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 127 + description: Input of XCVR cell, HS driver output control. + + nvidia,xcvr-setup-use-fuses: + description: Indicates that the value is read from the on-chip fuses. + type: boolean + + nvidia,xcvr-lsfslew: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + description: LS falling slew rate control. + + nvidia,xcvr-lsrslew: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + description: LS rising slew rate control. + + nvidia,xcvr-hsslew: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 511 + description: HS slew rate control. + + nvidia,hssquelch-level: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + description: HS squelch detector level. + + nvidia,hsdiscon-level: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + description: HS disconnect detector level. + + nvidia,phy-reset-gpio: + maxItems: 1 + description: GPIO used to reset the PHY. + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - "#phy-cells" + - phy_type + +additionalProperties: false + +allOf: + - if: + properties: + phy_type: + const: utmi + + then: + properties: + reg: + minItems: 2 + maxItems: 2 + + resets: + maxItems: 2 + + reset-names: + maxItems: 2 + + required: + - nvidia,hssync-start-delay + - nvidia,elastic-limit + - nvidia,idle-wait-delay + - nvidia,term-range-adj + - nvidia,xcvr-lsfslew + - nvidia,xcvr-lsrslew + + anyOf: + - required: ["nvidia,xcvr-setup"] + - required: ["nvidia,xcvr-setup-use-fuses"] + + if: + properties: + compatible: + contains: + const: nvidia,tegra30-usb-phy + + then: + properties: + clocks: + maxItems: 3 + + clock-names: + items: + - const: reg + - const: pll_u + - const: utmi-pads + + required: + - nvidia,xcvr-hsslew + - nvidia,hssquelch-level + - nvidia,hsdiscon-level + + else: + properties: + clocks: + maxItems: 4 + + clock-names: + items: + - const: reg + - const: pll_u + - const: timer + - const: utmi-pads + + - if: + properties: + phy_type: + const: ulpi + + then: + properties: + reg: + minItems: 1 + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + minItems: 2 + maxItems: 3 + + oneOf: + - items: + - const: reg + - const: pll_u + + - items: + - const: reg + - const: pll_u + - const: ulpi-link + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + maxItems: 2 + +examples: + - | + #include + + usb-phy@7d008000 { + compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; + reg = <0x7d008000 0x4000>, + <0x7d000000 0x4000>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USB3>, + <&tegra_car TEGRA124_CLK_PLL_U>, + <&tegra_car TEGRA124_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + resets = <&tegra_car 59>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <0>; + nvidia,xcvr-lsrslew = <3>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,xcvr-hsslew = <12>; + }; + + - | + #include + + usb-phy@c5004000 { + compatible = "nvidia,tegra20-usb-phy"; + reg = <0xc5004000 0x4000>; + phy_type = "ulpi"; + clocks = <&tegra_car TEGRA20_CLK_USB2>, + <&tegra_car TEGRA20_CLK_PLL_U>, + <&tegra_car TEGRA20_CLK_CDEV2>; + clock-names = "reg", "pll_u", "ulpi-link"; + resets = <&tegra_car 58>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; + }; From patchwork Sat Jul 31 17:38:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 490254 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0A73C432BE for ; Sat, 31 Jul 2021 17:39:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B79EC60FE7 for ; Sat, 31 Jul 2021 17:39:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231643AbhGaRjJ (ORCPT ); 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[94.29.22.96]) by smtp.gmail.com with ESMTPSA id s15sm445272lfp.216.2021.07.31.10.38.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Jul 2021 10:38:58 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Sebastian Reichel , Peter Chen , Greg Kroah-Hartman , Felipe Balbi , David Heidelberg Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v6 02/12] dt-bindings: phy: tegra20-usb-phy: Document properties needed for OTG mode Date: Sat, 31 Jul 2021 20:38:32 +0300 Message-Id: <20210731173842.19643-3-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210731173842.19643-1-digetx@gmail.com> References: <20210731173842.19643-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org In order to support OTG mode we need these new properties: - interrupt - nvidia,pmc Add the new properties to the binding. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../bindings/phy/nvidia,tegra20-usb-phy.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml index 593187234e6a..dfde0eaf66e1 100644 --- a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml @@ -77,6 +77,9 @@ properties: - const: timer - const: utmi-pads + interrupts: + maxItems: 1 + resets: oneOf: - maxItems: 1 @@ -199,6 +202,15 @@ properties: maxItems: 1 description: GPIO used to reset the PHY. + nvidia,pmc: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to Power Management controller. + - description: USB controller ID. + description: + Phandle to Power Management controller. + required: - compatible - reg @@ -320,6 +332,7 @@ examples: compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x7d008000 0x4000>, <0x7d000000 0x4000>; + interrupts = <0 97 4>; phy_type = "utmi"; clocks = <&tegra_car TEGRA124_CLK_USB3>, <&tegra_car TEGRA124_CLK_PLL_U>, @@ -338,6 +351,7 @@ examples: nvidia,hssquelch-level = <2>; nvidia,hsdiscon-level = <5>; nvidia,xcvr-hsslew = <12>; + nvidia,pmc = <&tegra_pmc 2>; }; - | @@ -346,6 +360,7 @@ examples: usb-phy@c5004000 { compatible = "nvidia,tegra20-usb-phy"; reg = <0xc5004000 0x4000>; + interrupts = <0 21 4>; phy_type = "ulpi"; clocks = <&tegra_car TEGRA20_CLK_USB2>, <&tegra_car TEGRA20_CLK_PLL_U>, @@ -354,4 +369,5 @@ examples: resets = <&tegra_car 58>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; #phy-cells = <0>; + nvidia,pmc = <&tegra_pmc 1>; }; From patchwork Sat Jul 31 17:38:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 490253 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8E4FC4338F for ; Sat, 31 Jul 2021 17:39:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C1EE260F94 for ; Sat, 31 Jul 2021 17:39:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231467AbhGaRjL (ORCPT ); Sat, 31 Jul 2021 13:39:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52110 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231578AbhGaRjI (ORCPT ); Sat, 31 Jul 2021 13:39:08 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F012C0613D3; Sat, 31 Jul 2021 10:39:01 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id h14so24913064lfv.7; Sat, 31 Jul 2021 10:39:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PXMoaxYyUFyeBQf/z4hD/RbH6NiurueNUmtWOBswMCg=; b=nxJf7RheO/stMR+RezGMKcmcK0oDekk2Vh4y7QU29nSNwI+nvNlA64ox/zit7I54Gk QksHfFWlPPlyf+qhbUE5uGYNS6yPSwMTh6Mm07+oP2K4MvIdQ6/MwHH56bbrU+BgsXi7 DdPuSDkQiasLiQKnj2Bbr/lVjfkpk+iNOGfcMZHP1853ntTy0+43wVuTplzMW+juf71Z LWIxt4TF7bGBsXzPGGsWh1jDZniW0zgA+mFk8Gg2DTZW6IUoAHOWqublbX8rj5SfmiEM tq0TKMtWVumccTVAcHCexHko6Gu38tTDIip7e5mAko495/kZFxI36rxdPW0WsAsInf5/ ukIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PXMoaxYyUFyeBQf/z4hD/RbH6NiurueNUmtWOBswMCg=; b=RGDG5CbIcGrd7VqTXY+2gMCiGmI5j/kGQ0kWrE5vcsn2NyJ0OPZS6Yh7kB081uxab6 HZx0vMAxctL6ZwIMhIi6dQUuADPVrM8LVLw3if2Jsp7eD6La5IYLUPFVcLSRxrOFZXtQ ZuMisYMxN+J4fiROBTkmpy4keA3nRg64QzBT/j/DJX9iEZCTlE4Ios9wDTFXcDOWNGDb vr/GUYkq1EAEooeyPAAnAawPdtMK7Zc29BpBT43vgb0daXKm0b9bnemsX3ks7VSEfsTo 9nCIaPFbW/Cb2xvGf1OIk971thx9Ssi3a5t1t7numlwVYjA/VI+NSeb73YSL1URF9S/M fbNw== X-Gm-Message-State: AOAM532Q3gjXckoIHG40vE3FjR3rmP+1Go662sIuUqPm0Gd/MFGyQOGC HY7hUZQLkLnXnWVJHD5LaIo= X-Google-Smtp-Source: ABdhPJwi5j5iTxuXyKI+2kUzkdXGXA1hWANqhzCes4StUiYdW3Uto9B4T+VD57J24tdskvyTwJfc2Q== X-Received: by 2002:ac2:5cd9:: with SMTP id f25mr6295419lfq.79.1627753139751; Sat, 31 Jul 2021 10:38:59 -0700 (PDT) Received: from localhost.localdomain (94-29-22-96.dynamic.spd-mgts.ru. [94.29.22.96]) by smtp.gmail.com with ESMTPSA id s15sm445272lfp.216.2021.07.31.10.38.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Jul 2021 10:38:59 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Sebastian Reichel , Peter Chen , Greg Kroah-Hartman , Felipe Balbi , David Heidelberg Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v6 03/12] soc/tegra: pmc: Expose USB regmap to all SoCs Date: Sat, 31 Jul 2021 20:38:33 +0300 Message-Id: <20210731173842.19643-4-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210731173842.19643-1-digetx@gmail.com> References: <20210731173842.19643-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org All Tegra SoCs prior to Tegra186 have USB power controls within the Power Management controller. These controls need to be configured by USB driver. Expose the regmap to these SoCs. Signed-off-by: Dmitry Osipenko --- drivers/soc/tegra/pmc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 59ae7277fdda..81d1f019fa0c 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -3214,7 +3214,7 @@ static const struct tegra_pmc_soc tegra20_pmc_soc = { .pmc_clks_data = NULL, .num_pmc_clks = 0, .has_blink_output = true, - .has_usb_sleepwalk = false, + .has_usb_sleepwalk = true, }; static const char * const tegra30_powergates[] = { @@ -3275,7 +3275,7 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = { .pmc_clks_data = tegra_pmc_clks_data, .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), .has_blink_output = true, - .has_usb_sleepwalk = false, + .has_usb_sleepwalk = true, }; static const char * const tegra114_powergates[] = { @@ -3332,7 +3332,7 @@ static const struct tegra_pmc_soc tegra114_pmc_soc = { .pmc_clks_data = tegra_pmc_clks_data, .num_pmc_clks = ARRAY_SIZE(tegra_pmc_clks_data), .has_blink_output = true, - .has_usb_sleepwalk = false, + .has_usb_sleepwalk = true, }; static const char * const tegra124_powergates[] = { From patchwork Sat Jul 31 17:38:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 490252 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10CE1C19F37 for ; Sat, 31 Jul 2021 17:39:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E5810610A8 for ; Sat, 31 Jul 2021 17:39:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232226AbhGaRjV (ORCPT ); Sat, 31 Jul 2021 13:39:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52114 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231645AbhGaRjK (ORCPT ); Sat, 31 Jul 2021 13:39:10 -0400 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 213D0C06175F; Sat, 31 Jul 2021 10:39:02 -0700 (PDT) Received: by mail-lj1-x236.google.com with SMTP id r23so17609079lji.3; Sat, 31 Jul 2021 10:39:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y3OZLq2rPlmjb4eTZVA72YHD2U1D5fyvvBeZCksHTBM=; b=pFpNtDKdTeHGRCkhR47YREr8k2nhqjgvnUuqi7SUszENmdBgYwiPEhUFV4/CaAYpDL MpaOoW59Zo37GFQLN7BbdJ+LezjODHEIycXinCh3Y/R1b4j5Vo4EQdAy8CihvZl+6GR7 v+bfD6o1BsWwT5tRxgOftyqPfJwmed3aNqaMIm1stmduChzjtX5zvQ9NU9LZ510+Nihv ynEVc2Cm93sMx+a147oWRbHRbiv3R9oEUA45jO6Yrvv3A6TwRkSTXCt01Qams9ofXscA tyqpiy/D5giBrRWdm4qZnndwghOn9qsN3DGhEEFHd7oqktJYBORMUsqG9o7TpHpnAobX jAwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y3OZLq2rPlmjb4eTZVA72YHD2U1D5fyvvBeZCksHTBM=; b=M2ib00cZf0x3hFYlsaAah9nRtWKgN/HKKHsboyigDQaXVRvSrGnusk1xnakPlm2p3l wlQA+OjghalEh+8IhYURicHluqtdGXtXe9Z0qJLrt9cfIFItU6k32Z8Y/3HBB2UcmbYR UQsDWUOohPO7cLmHia72BZwMwJM7DIqrCThG1386qRkB1dnswfY49f9evh07+vk+nh2q 3CRoyefO3PePf/OFMUq4kP+hxnipYxfNz+Gw5r2bkB5YIUJivbmpe7345adOPcCqGThd JLdoozXZloeMV3gIWJ/syxkF4rqepT5xG/IdNDsC+1BFud8iVzhDZMEsU47QGmqiXL3J a4yA== X-Gm-Message-State: AOAM533FOFf3bW5Eolmc3TSF83S9Kl4caabdHXcMP5XngjP62rXPdM1H 1KdnjgYEzcE3v0fXCjT88fc= X-Google-Smtp-Source: ABdhPJwSdbg3Rb/nxEeM1cm6STjQYcs3vBcyFeQD9iLMw1mhQ1Y43ZzMwqSkCXD6Ae9R/4KVJqXI+g== X-Received: by 2002:a05:651c:22d:: with SMTP id z13mr5811681ljn.14.1627753140479; Sat, 31 Jul 2021 10:39:00 -0700 (PDT) Received: from localhost.localdomain (94-29-22-96.dynamic.spd-mgts.ru. [94.29.22.96]) by smtp.gmail.com with ESMTPSA id s15sm445272lfp.216.2021.07.31.10.38.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Jul 2021 10:39:00 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Sebastian Reichel , Peter Chen , Greg Kroah-Hartman , Felipe Balbi , David Heidelberg Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v6 04/12] usb: phy: tegra: Support OTG mode programming Date: Sat, 31 Jul 2021 20:38:34 +0300 Message-Id: <20210731173842.19643-5-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210731173842.19643-1-digetx@gmail.com> References: <20210731173842.19643-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Support programming USB PHY into OTG mode. Signed-off-by: Dmitry Osipenko --- drivers/usb/phy/phy-tegra-usb.c | 197 +++++++++++++++++++++++++++++- include/linux/usb/tegra_usb_phy.h | 5 + 2 files changed, 197 insertions(+), 5 deletions(-) diff --git a/drivers/usb/phy/phy-tegra-usb.c b/drivers/usb/phy/phy-tegra-usb.c index c0f432d509aa..d6197a462749 100644 --- a/drivers/usb/phy/phy-tegra-usb.c +++ b/drivers/usb/phy/phy-tegra-usb.c @@ -63,6 +63,10 @@ #define A_VBUS_VLD_WAKEUP_EN BIT(30) #define USB_PHY_VBUS_WAKEUP_ID 0x408 +#define ID_INT_EN BIT(0) +#define ID_CHG_DET BIT(1) +#define VBUS_WAKEUP_INT_EN BIT(8) +#define VBUS_WAKEUP_CHG_DET BIT(9) #define VBUS_WAKEUP_STS BIT(10) #define VBUS_WAKEUP_WAKEUP_EN BIT(30) @@ -158,6 +162,10 @@ #define USB_USBMODE_HOST (3 << 0) #define USB_USBMODE_DEVICE (2 << 0) +#define PMC_USB_AO 0xf0 +#define VBUS_WAKEUP_PD_P0 BIT(2) +#define ID_PD_P0 BIT(3) + static DEFINE_SPINLOCK(utmip_pad_lock); static unsigned int utmip_pad_count; @@ -533,13 +541,14 @@ static int utmi_phy_power_on(struct tegra_usb_phy *phy) val &= ~USB_WAKE_ON_RESUME_EN; writel_relaxed(val, base + USB_SUSP_CTRL); - if (phy->mode == USB_DR_MODE_PERIPHERAL) { + if (phy->mode != USB_DR_MODE_HOST) { val = readl_relaxed(base + USB_SUSP_CTRL); val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV); writel_relaxed(val, base + USB_SUSP_CTRL); val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID); val &= ~VBUS_WAKEUP_WAKEUP_EN; + val &= ~(ID_CHG_DET | VBUS_WAKEUP_CHG_DET); writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID); val = readl_relaxed(base + USB_PHY_VBUS_SENSORS); @@ -687,9 +696,10 @@ static int utmi_phy_power_off(struct tegra_usb_phy *phy) * Ask VBUS sensor to generate wake event once cable is * connected. */ - if (phy->mode == USB_DR_MODE_PERIPHERAL) { + if (phy->mode != USB_DR_MODE_HOST) { val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID); val |= VBUS_WAKEUP_WAKEUP_EN; + val &= ~(ID_CHG_DET | VBUS_WAKEUP_CHG_DET); writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID); val = readl_relaxed(base + USB_PHY_VBUS_SENSORS); @@ -904,26 +914,146 @@ static void tegra_usb_phy_shutdown(struct usb_phy *u_phy) phy->freq = NULL; } +static irqreturn_t tegra_usb_phy_isr(int irq, void *data) +{ + u32 val, int_mask = ID_CHG_DET | VBUS_WAKEUP_CHG_DET; + struct tegra_usb_phy *phy = data; + void __iomem *base = phy->regs; + + /* + * The PHY interrupt also wakes the USB controller driver since + * interrupt is shared. We don't do anything in the PHY driver, + * so just clear the interrupt. + */ + val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID); + writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID); + + return val & int_mask ? IRQ_HANDLED : IRQ_NONE; +} + static int tegra_usb_phy_set_wakeup(struct usb_phy *u_phy, bool enable) { struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy); + void __iomem *base = phy->regs; + int ret = 0; + u32 val; + + if (phy->wakeup_enabled && phy->mode != USB_DR_MODE_HOST && + phy->irq > 0) { + disable_irq(phy->irq); + + val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID); + val &= ~(ID_INT_EN | VBUS_WAKEUP_INT_EN); + writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID); + + enable_irq(phy->irq); + + free_irq(phy->irq, phy); + + phy->wakeup_enabled = false; + } + + if (enable && phy->mode != USB_DR_MODE_HOST && phy->irq > 0) { + ret = request_irq(phy->irq, tegra_usb_phy_isr, IRQF_SHARED, + dev_name(phy->u_phy.dev), phy); + if (!ret) { + disable_irq(phy->irq); + + /* + * USB clock will be resumed once wake event will be + * generated. The ID-change event requires to have + * interrupts enabled, otherwise it won't be generated. + */ + val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID); + val |= ID_INT_EN | VBUS_WAKEUP_INT_EN; + writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID); + + enable_irq(phy->irq); + } else { + dev_err(phy->u_phy.dev, + "Failed to request interrupt: %d", ret); + enable = false; + } + } phy->wakeup_enabled = enable; - return 0; + return ret; } static int tegra_usb_phy_set_suspend(struct usb_phy *u_phy, int suspend) { struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy); + int ret; if (WARN_ON(!phy->freq)) return -EINVAL; + /* + * PHY is sharing IRQ with the CI driver, hence here we either + * disable interrupt for both PHY and CI or for CI only. The + * interrupt needs to be disabled while hardware is reprogrammed + * because interrupt touches the programmed registers, and thus, + * there could be a race condition. + */ + if (phy->irq > 0) + disable_irq(phy->irq); + if (suspend) - return tegra_usb_phy_power_off(phy); + ret = tegra_usb_phy_power_off(phy); else - return tegra_usb_phy_power_on(phy); + ret = tegra_usb_phy_power_on(phy); + + if (phy->irq > 0) + enable_irq(phy->irq); + + return ret; +} + +static int tegra_usb_phy_configure_pmc(struct tegra_usb_phy *phy) +{ + int err, val = 0; + + /* older device-trees don't have PMC regmap */ + if (!phy->pmc_regmap) + return 0; + + /* + * Tegra20 has a different layout of PMC USB register bits and AO is + * enabled by default after system reset on Tegra20, so assume nothing + * to do on Tegra20. + */ + if (!phy->soc_config->requires_pmc_ao_power_up) + return 0; + + /* enable VBUS wake-up detector */ + if (phy->mode != USB_DR_MODE_HOST) + val |= VBUS_WAKEUP_PD_P0 << phy->instance * 4; + + /* enable ID-pin ACC detector for OTG mode switching */ + if (phy->mode == USB_DR_MODE_OTG) + val |= ID_PD_P0 << phy->instance * 4; + + /* disable detectors to reset them */ + err = regmap_set_bits(phy->pmc_regmap, PMC_USB_AO, val); + if (err) { + dev_err(phy->u_phy.dev, "Failed to disable PMC AO: %d\n", err); + return err; + } + + usleep_range(10, 100); + + /* enable detectors */ + err = regmap_clear_bits(phy->pmc_regmap, PMC_USB_AO, val); + if (err) { + dev_err(phy->u_phy.dev, "Failed to enable PMC AO: %d\n", err); + return err; + } + + /* detectors starts to work after 10ms */ + usleep_range(10000, 15000); + + return 0; } static int tegra_usb_phy_init(struct usb_phy *u_phy) @@ -967,6 +1097,10 @@ static int tegra_usb_phy_init(struct usb_phy *u_phy) goto disable_vbus; } + err = tegra_usb_phy_configure_pmc(phy); + if (err) + goto close_phy; + err = tegra_usb_phy_power_on(phy); if (err) goto close_phy; @@ -1135,11 +1269,56 @@ static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy, return 0; } +static void tegra_usb_phy_put_pmc_device(void *dev) +{ + put_device(dev); +} + +static int tegra_usb_phy_parse_pmc(struct device *dev, + struct tegra_usb_phy *phy) +{ + struct platform_device *pmc_pdev; + struct of_phandle_args args; + int err; + + err = of_parse_phandle_with_fixed_args(dev->of_node, "nvidia,pmc", + 1, 0, &args); + if (err) { + if (err != -ENOENT) + return err; + + dev_warn_once(dev, "nvidia,pmc is missing, please update your device-tree\n"); + return 0; + } + + pmc_pdev = of_find_device_by_node(args.np); + of_node_put(args.np); + if (!pmc_pdev) + return -ENODEV; + + err = devm_add_action_or_reset(dev, tegra_usb_phy_put_pmc_device, + &pmc_pdev->dev); + if (err) + return err; + + if (!platform_get_drvdata(pmc_pdev)) + return -EPROBE_DEFER; + + phy->pmc_regmap = dev_get_regmap(&pmc_pdev->dev, "usb_sleepwalk"); + if (!phy->pmc_regmap) + return -EINVAL; + + phy->instance = args.args[0]; + + return 0; +} + static const struct tegra_phy_soc_config tegra20_soc_config = { .utmi_pll_config_in_car_module = false, .has_hostpc = false, .requires_usbmode_setup = false, .requires_extra_tuning_parameters = false, + .requires_pmc_ao_power_up = false, }; static const struct tegra_phy_soc_config tegra30_soc_config = { @@ -1147,6 +1326,7 @@ static const struct tegra_phy_soc_config tegra30_soc_config = { .has_hostpc = true, .requires_usbmode_setup = true, .requires_extra_tuning_parameters = true, + .requires_pmc_ao_power_up = true, }; static const struct of_device_id tegra_usb_phy_id_table[] = { @@ -1172,6 +1352,7 @@ static int tegra_usb_phy_probe(struct platform_device *pdev) return -ENOMEM; tegra_phy->soc_config = of_device_get_match_data(&pdev->dev); + tegra_phy->irq = platform_get_irq_optional(pdev, 0); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { @@ -1215,6 +1396,12 @@ static int tegra_usb_phy_probe(struct platform_device *pdev) return err; } + err = tegra_usb_phy_parse_pmc(&pdev->dev, tegra_phy); + if (err) { + dev_err_probe(&pdev->dev, err, "Failed to get PMC regmap\n"); + return err; + } + phy_type = of_usb_get_phy_mode(np); switch (phy_type) { case USBPHY_INTERFACE_MODE_UTMI: diff --git a/include/linux/usb/tegra_usb_phy.h b/include/linux/usb/tegra_usb_phy.h index fd1c9f6a4e37..d3e65eb9e16f 100644 --- a/include/linux/usb/tegra_usb_phy.h +++ b/include/linux/usb/tegra_usb_phy.h @@ -18,6 +18,7 @@ #include #include +#include #include #include @@ -30,6 +31,7 @@ * enter host mode * requires_extra_tuning_parameters: true if xcvr_hsslew, hssquelch_level * and hsdiscon_level should be set for adequate signal quality + * requires_pmc_ao_power_up: true if USB AO is powered down by default */ struct tegra_phy_soc_config { @@ -37,6 +39,7 @@ struct tegra_phy_soc_config { bool has_hostpc; bool requires_usbmode_setup; bool requires_extra_tuning_parameters; + bool requires_pmc_ao_power_up; }; struct tegra_utmip_config { @@ -62,6 +65,7 @@ enum tegra_usb_phy_port_speed { struct tegra_xtal_freq; struct tegra_usb_phy { + int irq; int instance; const struct tegra_xtal_freq *freq; void __iomem *regs; @@ -70,6 +74,7 @@ struct tegra_usb_phy { struct clk *pll_u; struct clk *pad_clk; struct regulator *vbus; + struct regmap *pmc_regmap; enum usb_dr_mode mode; void *config; const struct tegra_phy_soc_config *soc_config; From patchwork Sat Jul 31 17:38:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 490043 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E9F7C19F38 for ; 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[94.29.22.96]) by smtp.gmail.com with ESMTPSA id s15sm445272lfp.216.2021.07.31.10.39.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Jul 2021 10:39:00 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Sebastian Reichel , Peter Chen , Greg Kroah-Hartman , Felipe Balbi , David Heidelberg Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v6 05/12] dt-bindings: power: supply: smb347-charger: Document USB VBUS regulator Date: Sat, 31 Jul 2021 20:38:35 +0300 Message-Id: <20210731173842.19643-6-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210731173842.19643-1-digetx@gmail.com> References: <20210731173842.19643-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org SMB347 can supply power to USB VBUS, which is required by OTG-cable devices that want to switch USB port into the host mode. Add USB VBUS regulator properties. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko Reviewed-by: Sebastian Reichel --- .../power/supply/summit,smb347-charger.yaml | 30 +++++++++++++++++++ .../dt-bindings/power/summit,smb347-charger.h | 4 +++ 2 files changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml b/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml index 983fc215c1e5..20862cdfc116 100644 --- a/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml +++ b/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml @@ -73,6 +73,26 @@ properties: - 1 # SMB3XX_SOFT_TEMP_COMPENSATE_CURRENT Current compensation - 2 # SMB3XX_SOFT_TEMP_COMPENSATE_VOLTAGE Voltage compensation + summit,inok-polarity: + description: | + Polarity of INOK signal indicating presence of external power supply. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # SMB3XX_SYSOK_INOK_ACTIVE_LOW + - 1 # SMB3XX_SYSOK_INOK_ACTIVE_HIGH + + usb-vbus: + $ref: "../../regulator/regulator.yaml#" + type: object + + properties: + summit,needs-inok-toggle: + type: boolean + description: INOK signal is fixed and polarity needs to be toggled + in order to enable/disable output mode. + + unevaluatedProperties: false + allOf: - if: properties: @@ -134,6 +154,7 @@ examples: reg = <0x7f>; summit,enable-charge-control = ; + summit,inok-polarity = ; summit,chip-temperature-threshold-celsius = <110>; summit,mains-current-limit-microamp = <2000000>; summit,usb-current-limit-microamp = <500000>; @@ -141,6 +162,15 @@ examples: summit,enable-mains-charging; monitored-battery = <&battery>; + + usb-vbus { + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-min-microamp = <750000>; + regulator-max-microamp = <750000>; + summit,needs-inok-toggle; + }; }; }; diff --git a/include/dt-bindings/power/summit,smb347-charger.h b/include/dt-bindings/power/summit,smb347-charger.h index d918bf321a71..3205699b5e41 100644 --- a/include/dt-bindings/power/summit,smb347-charger.h +++ b/include/dt-bindings/power/summit,smb347-charger.h @@ -16,4 +16,8 @@ #define SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW 1 #define SMB3XX_CHG_ENABLE_PIN_ACTIVE_HIGH 2 +/* Polarity of INOK signal */ +#define SMB3XX_SYSOK_INOK_ACTIVE_LOW 0 +#define SMB3XX_SYSOK_INOK_ACTIVE_HIGH 1 + #endif From patchwork Sat Jul 31 17:38:36 2021 Content-Type: text/plain; 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[94.29.22.96]) by smtp.gmail.com with ESMTPSA id s15sm445272lfp.216.2021.07.31.10.39.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Jul 2021 10:39:01 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Sebastian Reichel , Peter Chen , Greg Kroah-Hartman , Felipe Balbi , David Heidelberg Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v6 06/12] power: supply: smb347-charger: Make smb347_set_writable() IRQ-safe Date: Sat, 31 Jul 2021 20:38:36 +0300 Message-Id: <20210731173842.19643-7-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210731173842.19643-1-digetx@gmail.com> References: <20210731173842.19643-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org The smb347_set_writable() is used by interrupt handler and outside of it. The interrupt should be disabled when the function is used outside of interrupt handler in order to prevent racing with the interrupt context. Add new parameter to smb347_set_writable() that allows to disable IRQ. Signed-off-by: Dmitry Osipenko Reviewed-by: Sebastian Reichel --- drivers/power/supply/smb347-charger.c | 30 +++++++++++++++++++-------- 1 file changed, 21 insertions(+), 9 deletions(-) diff --git a/drivers/power/supply/smb347-charger.c b/drivers/power/supply/smb347-charger.c index df240420f2de..db1378b41f80 100644 --- a/drivers/power/supply/smb347-charger.c +++ b/drivers/power/supply/smb347-charger.c @@ -671,10 +671,22 @@ static int smb347_set_temp_limits(struct smb347_charger *smb) * * Returns %0 on success and negative errno in case of failure. */ -static int smb347_set_writable(struct smb347_charger *smb, bool writable) +static int smb347_set_writable(struct smb347_charger *smb, bool writable, + bool irq_toggle) { - return regmap_update_bits(smb->regmap, CMD_A, CMD_A_ALLOW_WRITE, - writable ? CMD_A_ALLOW_WRITE : 0); + struct i2c_client *client = to_i2c_client(smb->dev); + int ret; + + if (writable && irq_toggle && !smb->irq_unsupported) + disable_irq(client->irq); + + ret = regmap_update_bits(smb->regmap, CMD_A, CMD_A_ALLOW_WRITE, + writable ? CMD_A_ALLOW_WRITE : 0); + + if ((!writable || ret) && irq_toggle && !smb->irq_unsupported) + enable_irq(client->irq); + + return ret; } static int smb347_hw_init(struct smb347_charger *smb) @@ -682,7 +694,7 @@ static int smb347_hw_init(struct smb347_charger *smb) unsigned int val; int ret; - ret = smb347_set_writable(smb, true); + ret = smb347_set_writable(smb, true, false); if (ret < 0) return ret; @@ -758,7 +770,7 @@ static int smb347_hw_init(struct smb347_charger *smb) ret = smb347_start_stop_charging(smb); fail: - smb347_set_writable(smb, false); + smb347_set_writable(smb, false, false); return ret; } @@ -866,7 +878,7 @@ static int smb347_irq_set(struct smb347_charger *smb, bool enable) if (smb->irq_unsupported) return 0; - ret = smb347_set_writable(smb, true); + ret = smb347_set_writable(smb, true, true); if (ret < 0) return ret; @@ -891,7 +903,7 @@ static int smb347_irq_set(struct smb347_charger *smb, bool enable) ret = regmap_update_bits(smb->regmap, CFG_PIN, CFG_PIN_EN_CHARGER_ERROR, enable ? CFG_PIN_EN_CHARGER_ERROR : 0); fail: - smb347_set_writable(smb, false); + smb347_set_writable(smb, false, true); return ret; } @@ -919,7 +931,7 @@ static int smb347_irq_init(struct smb347_charger *smb, if (!client->irq) return 0; - ret = smb347_set_writable(smb, true); + ret = smb347_set_writable(smb, true, false); if (ret < 0) return ret; @@ -931,7 +943,7 @@ static int smb347_irq_init(struct smb347_charger *smb, CFG_STAT_ACTIVE_HIGH | CFG_STAT_DISABLED, CFG_STAT_DISABLED); - smb347_set_writable(smb, false); + smb347_set_writable(smb, false, false); if (ret < 0) { dev_warn(smb->dev, "failed to initialize IRQ: %d\n", ret); From patchwork Sat Jul 31 17:38:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 490044 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22F74C19F3A for ; Sat, 31 Jul 2021 17:39:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0AA3760EE6 for ; Sat, 31 Jul 2021 17:39:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229811AbhGaRjY (ORCPT ); Sat, 31 Jul 2021 13:39:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231979AbhGaRjO (ORCPT ); Sat, 31 Jul 2021 13:39:14 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 41735C06179F; Sat, 31 Jul 2021 10:39:04 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id e5so17617727ljp.6; Sat, 31 Jul 2021 10:39:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yP6S2T4oQUXBPJzLj6JChwZNeadgwpgXfp2tQNc6v5U=; b=deUskVg3oSa4TdKJzd3l5DM8ygli4WAPYQlZamdeMEEasb94cUMPSwqi7KIyCwZPk5 oLqVZagPxxnvfKaFrg7PjAp0mlPJw+oTel3ipGcrT0KsyLoNskI+/AgeAzZU4qQ8Zp18 PWplzL8SQL1/WWW21VUH0MLMo7bMiPvAd03LEWV6etGfi+VxcNI4beAsk1eRmwXbyAEw g/T9IRVp4Nrlmwanbbe4x6Kp3dX8icaqZA2/1w95fMVVb006Kace9dHKDghAIrx4XUHs 1YZrzCMBZOTlrip1Xa/m2Dr8eMdYh1KrnW7gfyp6w5RY6SvckYjWOna/lupXt3A/4J92 M0mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yP6S2T4oQUXBPJzLj6JChwZNeadgwpgXfp2tQNc6v5U=; b=B1fw/3JHcvTQjvDyRxRfpDO3y0v4x1n17HO/FPS2GPWsX3TIghXzeabrbm04/4jkbv 3xFVTjsCPvalIsEUGkFObe/3s2g3BwDEYAlAWkaVPiTN70J3Nqy1RYB79at95HTGUMMN yvsq+JFQ2THoJdjqonHdRczpTinCFpBWVcZqFGedCuExxaO1RXWqveaZMNbyWXDYQkZk j3e1pP3BP2QiroCbLhzk21CgwGr6EL6Mb7mDlGkNr821OCriWo/dkmileEtEdh/voLMZ xgKcya984uUt3GlwltsjgqmAFndwI1oBE/mHqSeJaLjGUeCpAG0uf6s4UoN0jqvAXltN UOnQ== X-Gm-Message-State: AOAM532aGBXpUUsyxqKEkxqjbjFtBNwnygYscP0u2OiFwWFXCybSzLLS ezksjJBwdgn2/3XJc1PQvT4= X-Google-Smtp-Source: ABdhPJwJwrGb8ek+xMSWKTOXoZWv/E9mHJtnrLRuSutxKVe3f6GUHeavio7Z/94lGrZZ4xXmSYFyRw== X-Received: by 2002:a05:651c:235:: with SMTP id z21mr5710651ljn.462.1627753142657; Sat, 31 Jul 2021 10:39:02 -0700 (PDT) Received: from localhost.localdomain (94-29-22-96.dynamic.spd-mgts.ru. [94.29.22.96]) by smtp.gmail.com with ESMTPSA id s15sm445272lfp.216.2021.07.31.10.39.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Jul 2021 10:39:02 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Sebastian Reichel , Peter Chen , Greg Kroah-Hartman , Felipe Balbi , David Heidelberg Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v6 07/12] power: supply: smb347-charger: Utilize generic regmap caching Date: Sat, 31 Jul 2021 20:38:37 +0300 Message-Id: <20210731173842.19643-8-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210731173842.19643-1-digetx@gmail.com> References: <20210731173842.19643-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Utilize generic regmap caching in order to avoid unnecessary slow I2C accesses to all constant registers each time the supply status updated and remove local caching of charger state to make code cleaner. Signed-off-by: Dmitry Osipenko Reviewed-by: Sebastian Reichel --- drivers/power/supply/smb347-charger.c | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/power/supply/smb347-charger.c b/drivers/power/supply/smb347-charger.c index db1378b41f80..27254e6efdde 100644 --- a/drivers/power/supply/smb347-charger.c +++ b/drivers/power/supply/smb347-charger.c @@ -135,7 +135,6 @@ * @id: SMB charger ID * @mains_online: is AC/DC input connected * @usb_online: is USB input connected - * @charging_enabled: is charging enabled * @irq_unsupported: is interrupt unsupported by SMB hardware * @max_charge_current: maximum current (in uA) the battery can be charged * @max_charge_voltage: maximum voltage (in uV) the battery can be charged @@ -192,7 +191,6 @@ struct smb347_charger { unsigned int id; bool mains_online; bool usb_online; - bool charging_enabled; bool irq_unsupported; unsigned int max_charge_current; @@ -358,21 +356,13 @@ static int smb347_charging_status(struct smb347_charger *smb) static int smb347_charging_set(struct smb347_charger *smb, bool enable) { - int ret = 0; - if (smb->enable_control != SMB3XX_CHG_ENABLE_SW) { dev_dbg(smb->dev, "charging enable/disable in SW disabled\n"); return 0; } - if (smb->charging_enabled != enable) { - ret = regmap_update_bits(smb->regmap, CMD_A, CMD_A_CHG_ENABLED, - enable ? CMD_A_CHG_ENABLED : 0); - if (!ret) - smb->charging_enabled = enable; - } - - return ret; + return regmap_update_bits(smb->regmap, CMD_A, CMD_A_CHG_ENABLED, + enable ? CMD_A_CHG_ENABLED : 0); } static inline int smb347_charging_enable(struct smb347_charger *smb) @@ -1310,6 +1300,8 @@ static const struct regmap_config smb347_regmap = { .max_register = SMB347_MAX_REGISTER, .volatile_reg = smb347_volatile_reg, .readable_reg = smb347_readable_reg, + .cache_type = REGCACHE_FLAT, + .num_reg_defaults_raw = SMB347_MAX_REGISTER, }; static const struct power_supply_desc smb347_mains_desc = { From patchwork Sat Jul 31 17:38:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 490040 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62A6AC4320E for ; Sat, 31 Jul 2021 17:39:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4B55F60EE6 for ; Sat, 31 Jul 2021 17:39:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231951AbhGaRjv (ORCPT ); Sat, 31 Jul 2021 13:39:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232033AbhGaRjP (ORCPT ); Sat, 31 Jul 2021 13:39:15 -0400 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED12DC0617A0; Sat, 31 Jul 2021 10:39:04 -0700 (PDT) Received: by mail-lj1-x22e.google.com with SMTP id u20so17684323ljo.0; Sat, 31 Jul 2021 10:39:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Tx4QIDj2b8nSMmqdedBogqNF+XkSAZXWaRA6r8AMMQ0=; b=UGDdC313UxBt0B1prkmf7X5eJ8sDH+Qf1joGI/pLnZPxr537SsvU0eHsCzmw2acVut +PNDZjla+YWmIc1iPBuB9vLBCqJDjleXlYHcxn8Ub3UopjbZcuJANTeyrRKZTXuSMDP5 EA95OOTl0/Icb+9ItyCZIIPlEBeF3lubHrSXdlAV2vrLrS+kZ1y7Ju7/pq6alHjwpKBN bthvRG2C+Hf/5IoNpCuHxbBM15/jqNJ8WQLczjQ2xMj3i4gHv9XH7HbRaufoHrHZ/jZY 7s5Y+MjnisEp2h2HGKkqUk/4Ns08wPr0L1UV0MUcnZVoLg49qXwnk6RVFsk78xLrQEJo BI7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Tx4QIDj2b8nSMmqdedBogqNF+XkSAZXWaRA6r8AMMQ0=; b=lrw1dUEJnaswBCsTFf5fEzqxkx/U/7+S5qeVCpJfTqvYIPRBsWLll3gOsSm96RHv2E gXYZi+1uGoGo1lAydMFg/P0/zIJTMSJEPxMfzp0vcuIl/Cggli282a3qxygPY6iVjJdE JWSM+PDRpBTmW+iP/AR4lkOYT6X9gPd9dyQmAPbrp6sWWFzf41L0eyGVnrcx8TmV7u5q WRfbYaVEo1xH2LEUXj8UwotqDeWfn7wX+30ZHWNeINMSRe8mZYbnhQSgcw/px6Hyptei clzA1+J1XeMi5KrX/dpdYM71GBWp0J+39PY8w8olfFY5Fz3afIr+f1rpiSvdFcKnsl2m lrhA== X-Gm-Message-State: AOAM5339czSeIzDYgkBMI5xjEcur8XwxmcJ9BF+r5J+3sEWIy5dFjiwf XLB7Pgwa4xZ4/876qFS7zyc= X-Google-Smtp-Source: ABdhPJyIYw26kkZ3eGiyn+Uw4xed+Gtn+TnJjeTsJME6QRUueoW3oHLYA+H+45AHKtQ4CHEl7y5V9w== X-Received: by 2002:a2e:a4aa:: with SMTP id g10mr5545170ljm.348.1627753143367; Sat, 31 Jul 2021 10:39:03 -0700 (PDT) Received: from localhost.localdomain (94-29-22-96.dynamic.spd-mgts.ru. [94.29.22.96]) by smtp.gmail.com with ESMTPSA id s15sm445272lfp.216.2021.07.31.10.39.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Jul 2021 10:39:03 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Sebastian Reichel , Peter Chen , Greg Kroah-Hartman , Felipe Balbi , David Heidelberg Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v6 08/12] power: supply: smb347-charger: Add missing pin control activation Date: Sat, 31 Jul 2021 20:38:38 +0300 Message-Id: <20210731173842.19643-9-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210731173842.19643-1-digetx@gmail.com> References: <20210731173842.19643-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Pin control needs to be activated by setting the enable bit, otherwise hardware rejects all pin changes. Previously this stayed unnoticed on Nexus 7 because pin control was enabled by default after rebooting from downstream kernel, which uses driver that enables the bit and charger registers are non-volatile until power supply (battery) is disconnected. Configure the pin control enable bit. This fixes the potentially never-enabled charging on devices that use pin control. Signed-off-by: Dmitry Osipenko Reviewed-by: Sebastian Reichel --- drivers/power/supply/smb347-charger.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/power/supply/smb347-charger.c b/drivers/power/supply/smb347-charger.c index 27254e6efdde..1c9205ca0993 100644 --- a/drivers/power/supply/smb347-charger.c +++ b/drivers/power/supply/smb347-charger.c @@ -55,6 +55,7 @@ #define CFG_PIN_EN_CTRL_ACTIVE_LOW 0x60 #define CFG_PIN_EN_APSD_IRQ BIT(1) #define CFG_PIN_EN_CHARGER_ERROR BIT(2) +#define CFG_PIN_EN_CTRL BIT(4) #define CFG_THERM 0x07 #define CFG_THERM_SOFT_HOT_COMPENSATION_MASK 0x03 #define CFG_THERM_SOFT_HOT_COMPENSATION_SHIFT 0 @@ -726,6 +727,15 @@ static int smb347_hw_init(struct smb347_charger *smb) if (ret < 0) goto fail; + /* Activate pin control, making it writable. */ + switch (smb->enable_control) { + case SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW: + case SMB3XX_CHG_ENABLE_PIN_ACTIVE_HIGH: + ret = regmap_set_bits(smb->regmap, CFG_PIN, CFG_PIN_EN_CTRL); + if (ret < 0) + goto fail; + } + /* * Make the charging functionality controllable by a write to the * command register unless pin control is specified in the platform From patchwork Sat Jul 31 17:38:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 490251 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7525AC43216 for ; Sat, 31 Jul 2021 17:39:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5365A60EE6 for ; Sat, 31 Jul 2021 17:39:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232360AbhGaRjZ (ORCPT ); Sat, 31 Jul 2021 13:39:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232012AbhGaRjP (ORCPT ); Sat, 31 Jul 2021 13:39:15 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC5D4C0617A4; Sat, 31 Jul 2021 10:39:05 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id g13so24884215lfj.12; Sat, 31 Jul 2021 10:39:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RDICfGHbTY94i4toOgpe7CZZ2fpzvwQMArarHy2h/dI=; b=G2S4pdURWw41y+BR0G8yz0mw2qSD5rCKf5jjKmPH+gBWCg/Xjfx3XKIwrSNRSlWX3S 84yZwimEgT2ikAq9ypCyEyImwkjIvKviA9/9CH6++mN7qiOxr7sKt8qE1kkI1ejJtzTY nnVVz4g9tERyfkpzdGHgudfSV5ZrtzWgYsSRJGUl1VxZpsOELvjcXc1gJU581zKLpZVA 0pB2dXSM3co20qbnB9iwVsYC4vKKzkGMtZ8YHib+EO+jeM+nnUMzg7jLWst6OkDjDMzg OetJof5IzHlSaN9un801nixhhOTDjr7tGBkxcBApw/vhj8MjSixajpV+uCh+o4kzfHxp BU+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RDICfGHbTY94i4toOgpe7CZZ2fpzvwQMArarHy2h/dI=; b=hy2H8+uJWMy4zpx+9kETZj692OZdPHI+E1zhd51P81XMEPSevEU3TnTuBsvj089xt9 tAmEtiyuH69ChH6TL2T8nEck7PBpVSRYSSCBi1+NaOvmkJqaS7IyMsEPl+IdTPTFIzLq NjUlO/XZjx+8K4ZOLcWhBT/YlEoN71ZEenT2b5aA63aAsWXm8wPjubhMmHD2lolxIuDi b0Y9fIfUadXiBJ6iPPalDmWrd05WbNXan9+A0CfJ0ZBtIF/XpiPz40cjirU3HADuLlUT tJCYWYqZyqA9ecV1J20ualsaxWgaM6SSs99ZiSjLXjADI+vCDTRSx3XTuUlbzOcAunZ0 nHVw== X-Gm-Message-State: AOAM531OwyohL73o/cTizY4yHzzx27pBTKIJoNJQ7WRr2uzWhQ4yKiqb g5icgDYIWtpNUwQxpud7Ag0= X-Google-Smtp-Source: ABdhPJy6OoBaI9qqWE118NO38OcwuZ20hHSGLj6XNqDEWvyOFOMAIRTQueh6wto9cO3BxTHj83paxA== X-Received: by 2002:a19:ee1a:: with SMTP id g26mr6045515lfb.141.1627753144087; Sat, 31 Jul 2021 10:39:04 -0700 (PDT) Received: from localhost.localdomain (94-29-22-96.dynamic.spd-mgts.ru. [94.29.22.96]) by smtp.gmail.com with ESMTPSA id s15sm445272lfp.216.2021.07.31.10.39.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Jul 2021 10:39:03 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Sebastian Reichel , Peter Chen , Greg Kroah-Hartman , Felipe Balbi , David Heidelberg Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v6 09/12] power: supply: smb347-charger: Implement USB VBUS regulator Date: Sat, 31 Jul 2021 20:38:39 +0300 Message-Id: <20210731173842.19643-10-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210731173842.19643-1-digetx@gmail.com> References: <20210731173842.19643-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org SMB347 can supply power to USB VBUS, implement the USB VBUS regulator. USB VBUS needs to be powered for switching OTG-cable USB port into host mode. Signed-off-by: Dmitry Osipenko Reviewed-by: Sebastian Reichel --- drivers/power/supply/Kconfig | 1 + drivers/power/supply/smb347-charger.c | 219 ++++++++++++++++++++++++++ 2 files changed, 220 insertions(+) diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig index 8543c89a0c1a..e83e9e4d512c 100644 --- a/drivers/power/supply/Kconfig +++ b/drivers/power/supply/Kconfig @@ -694,6 +694,7 @@ config CHARGER_BQ256XX config CHARGER_SMB347 tristate "Summit Microelectronics SMB3XX Battery Charger" depends on I2C + depends on REGULATOR select REGMAP_I2C help Say Y to include support for Summit Microelectronics SMB345, diff --git a/drivers/power/supply/smb347-charger.c b/drivers/power/supply/smb347-charger.c index 1c9205ca0993..753944e774c4 100644 --- a/drivers/power/supply/smb347-charger.c +++ b/drivers/power/supply/smb347-charger.c @@ -18,6 +18,7 @@ #include #include #include +#include #include @@ -63,12 +64,15 @@ #define CFG_THERM_SOFT_COLD_COMPENSATION_SHIFT 2 #define CFG_THERM_MONITOR_DISABLED BIT(4) #define CFG_SYSOK 0x08 +#define CFG_SYSOK_INOK_ACTIVE_HIGH BIT(0) #define CFG_SYSOK_SUSPEND_HARD_LIMIT_DISABLED BIT(2) #define CFG_OTHER 0x09 #define CFG_OTHER_RID_MASK 0xc0 #define CFG_OTHER_RID_ENABLED_AUTO_OTG 0xc0 #define CFG_OTG 0x0a #define CFG_OTG_TEMP_THRESHOLD_MASK 0x30 +#define CFG_OTG_CURRENT_LIMIT_250mA BIT(2) +#define CFG_OTG_CURRENT_LIMIT_750mA BIT(3) #define CFG_OTG_TEMP_THRESHOLD_SHIFT 4 #define CFG_OTG_CC_COMPENSATION_MASK 0xc0 #define CFG_OTG_CC_COMPENSATION_SHIFT 6 @@ -92,6 +96,7 @@ #define CMD_A 0x30 #define CMD_A_CHG_ENABLED BIT(1) #define CMD_A_SUSPEND_ENABLED BIT(2) +#define CMD_A_OTG_ENABLED BIT(4) #define CMD_A_ALLOW_WRITE BIT(7) #define CMD_B 0x31 #define CMD_C 0x33 @@ -133,10 +138,12 @@ * @regmap: pointer to driver regmap * @mains: power_supply instance for AC/DC power * @usb: power_supply instance for USB power + * @usb_rdev: USB VBUS regulator device * @id: SMB charger ID * @mains_online: is AC/DC input connected * @usb_online: is USB input connected * @irq_unsupported: is interrupt unsupported by SMB hardware + * @usb_vbus_enabled: is USB VBUS powered by SMB charger * @max_charge_current: maximum current (in uA) the battery can be charged * @max_charge_voltage: maximum voltage (in uV) the battery can be charged * @pre_charge_current: current (in uA) to use in pre-charging phase @@ -167,6 +174,8 @@ * @use_usb_otg: USB OTG output can be used (not implemented yet) * @enable_control: how charging enable/disable is controlled * (driver/pin controls) + * @inok_polarity: polarity of INOK signal which denotes presence of external + * power supply * * @use_main, @use_usb, and @use_usb_otg are means to enable/disable * hardware support for these. This is useful when we want to have for @@ -189,10 +198,12 @@ struct smb347_charger { struct regmap *regmap; struct power_supply *mains; struct power_supply *usb; + struct regulator_dev *usb_rdev; unsigned int id; bool mains_online; bool usb_online; bool irq_unsupported; + bool usb_vbus_enabled; unsigned int max_charge_current; unsigned int max_charge_voltage; @@ -213,6 +224,7 @@ struct smb347_charger { bool use_usb; bool use_usb_otg; unsigned int enable_control; + unsigned int inok_polarity; }; enum smb_charger_chipid { @@ -362,6 +374,11 @@ static int smb347_charging_set(struct smb347_charger *smb, bool enable) return 0; } + if (enable && smb->usb_vbus_enabled) { + dev_dbg(smb->dev, "charging not enabled because USB is in host mode\n"); + return 0; + } + return regmap_update_bits(smb->regmap, CMD_A, CMD_A_CHG_ENABLED, enable ? CMD_A_CHG_ENABLED : 0); } @@ -1253,6 +1270,13 @@ static void smb347_dt_parse_dev_info(struct smb347_charger *smb) /* Select charging control */ device_property_read_u32(dev, "summit,enable-charge-control", &smb->enable_control); + + /* + * Polarity of INOK signal indicating presence of external power + * supply connected to the charger. + */ + device_property_read_u32(dev, "summit,inok-polarity", + &smb->inok_polarity); } static int smb347_get_battery_info(struct smb347_charger *smb) @@ -1304,6 +1328,160 @@ static int smb347_get_battery_info(struct smb347_charger *smb) return 0; } +static int smb347_usb_vbus_get_current_limit(struct regulator_dev *rdev) +{ + struct smb347_charger *smb = rdev_get_drvdata(rdev); + unsigned int val; + int ret; + + ret = regmap_read(smb->regmap, CFG_OTG, &val); + if (ret < 0) + return ret; + + /* + * It's unknown what happens if this bit is unset due to lack of + * access to the datasheet, assume it's limit-enable. + */ + if (!(val & CFG_OTG_CURRENT_LIMIT_250mA)) + return 0; + + return val & CFG_OTG_CURRENT_LIMIT_750mA ? 750000 : 250000; +} + +static int smb347_usb_vbus_set_new_current_limit(struct smb347_charger *smb, + int max_uA) +{ + const unsigned int mask = CFG_OTG_CURRENT_LIMIT_750mA | + CFG_OTG_CURRENT_LIMIT_250mA; + unsigned int val = CFG_OTG_CURRENT_LIMIT_250mA; + int ret; + + if (max_uA >= 750000) + val |= CFG_OTG_CURRENT_LIMIT_750mA; + + ret = regmap_update_bits(smb->regmap, CFG_OTG, mask, val); + if (ret < 0) + dev_err(smb->dev, "failed to change USB current limit\n"); + + return ret; +} + +static int smb347_usb_vbus_set_current_limit(struct regulator_dev *rdev, + int min_uA, int max_uA) +{ + struct smb347_charger *smb = rdev_get_drvdata(rdev); + int ret; + + ret = smb347_set_writable(smb, true, true); + if (ret < 0) + return ret; + + ret = smb347_usb_vbus_set_new_current_limit(smb, max_uA); + smb347_set_writable(smb, false, true); + + return ret; +} + +static int smb347_usb_vbus_regulator_enable(struct regulator_dev *rdev) +{ + struct smb347_charger *smb = rdev_get_drvdata(rdev); + int ret, max_uA; + + ret = smb347_set_writable(smb, true, true); + if (ret < 0) + return ret; + + smb347_charging_disable(smb); + + if (device_property_read_bool(&rdev->dev, "summit,needs-inok-toggle")) { + unsigned int sysok = 0; + + if (smb->inok_polarity == SMB3XX_SYSOK_INOK_ACTIVE_LOW) + sysok = CFG_SYSOK_INOK_ACTIVE_HIGH; + + /* + * VBUS won't be powered if INOK is active, so we need to + * manually disable INOK on some platforms. + */ + ret = regmap_update_bits(smb->regmap, CFG_SYSOK, + CFG_SYSOK_INOK_ACTIVE_HIGH, sysok); + if (ret < 0) { + dev_err(smb->dev, "failed to disable INOK\n"); + goto done; + } + } + + ret = smb347_usb_vbus_get_current_limit(rdev); + if (ret < 0) { + dev_err(smb->dev, "failed to get USB VBUS current limit\n"); + goto done; + } + + max_uA = ret; + + ret = smb347_usb_vbus_set_new_current_limit(smb, 250000); + if (ret < 0) { + dev_err(smb->dev, "failed to preset USB VBUS current limit\n"); + goto done; + } + + ret = regmap_set_bits(smb->regmap, CMD_A, CMD_A_OTG_ENABLED); + if (ret < 0) { + dev_err(smb->dev, "failed to enable USB VBUS\n"); + goto done; + } + + smb->usb_vbus_enabled = true; + + ret = smb347_usb_vbus_set_new_current_limit(smb, max_uA); + if (ret < 0) { + dev_err(smb->dev, "failed to restore USB VBUS current limit\n"); + goto done; + } +done: + smb347_set_writable(smb, false, true); + + return ret; +} + +static int smb347_usb_vbus_regulator_disable(struct regulator_dev *rdev) +{ + struct smb347_charger *smb = rdev_get_drvdata(rdev); + int ret; + + ret = smb347_set_writable(smb, true, true); + if (ret < 0) + return ret; + + ret = regmap_clear_bits(smb->regmap, CMD_A, CMD_A_OTG_ENABLED); + if (ret < 0) { + dev_err(smb->dev, "failed to disable USB VBUS\n"); + goto done; + } + + smb->usb_vbus_enabled = false; + + if (device_property_read_bool(&rdev->dev, "summit,needs-inok-toggle")) { + unsigned int sysok = 0; + + if (smb->inok_polarity == SMB3XX_SYSOK_INOK_ACTIVE_HIGH) + sysok = CFG_SYSOK_INOK_ACTIVE_HIGH; + + ret = regmap_update_bits(smb->regmap, CFG_SYSOK, + CFG_SYSOK_INOK_ACTIVE_HIGH, sysok); + if (ret < 0) { + dev_err(smb->dev, "failed to enable INOK\n"); + goto done; + } + } + + smb347_start_stop_charging(smb); +done: + smb347_set_writable(smb, false, true); + + return ret; +} + static const struct regmap_config smb347_regmap = { .reg_bits = 8, .val_bits = 8, @@ -1314,6 +1492,14 @@ static const struct regmap_config smb347_regmap = { .num_reg_defaults_raw = SMB347_MAX_REGISTER, }; +static const struct regulator_ops smb347_usb_vbus_regulator_ops = { + .is_enabled = regulator_is_enabled_regmap, + .enable = smb347_usb_vbus_regulator_enable, + .disable = smb347_usb_vbus_regulator_disable, + .get_current_limit = smb347_usb_vbus_get_current_limit, + .set_current_limit = smb347_usb_vbus_set_current_limit, +}; + static const struct power_supply_desc smb347_mains_desc = { .name = "smb347-mains", .type = POWER_SUPPLY_TYPE_MAINS, @@ -1330,10 +1516,24 @@ static const struct power_supply_desc smb347_usb_desc = { .num_properties = ARRAY_SIZE(smb347_properties), }; +static const struct regulator_desc smb347_usb_vbus_regulator_desc = { + .name = "smb347-usb-vbus", + .of_match = of_match_ptr("usb-vbus"), + .ops = &smb347_usb_vbus_regulator_ops, + .type = REGULATOR_VOLTAGE, + .owner = THIS_MODULE, + .enable_reg = CMD_A, + .enable_mask = CMD_A_OTG_ENABLED, + .enable_val = CMD_A_OTG_ENABLED, + .fixed_uV = 5000000, + .n_voltages = 1, +}; + static int smb347_probe(struct i2c_client *client, const struct i2c_device_id *id) { struct power_supply_config mains_usb_cfg = {}; + struct regulator_config usb_rdev_cfg = {}; struct device *dev = &client->dev; struct smb347_charger *smb; int ret; @@ -1381,6 +1581,18 @@ static int smb347_probe(struct i2c_client *client, if (ret) return ret; + usb_rdev_cfg.dev = dev; + usb_rdev_cfg.driver_data = smb; + usb_rdev_cfg.regmap = smb->regmap; + + smb->usb_rdev = devm_regulator_register(dev, + &smb347_usb_vbus_regulator_desc, + &usb_rdev_cfg); + if (IS_ERR(smb->usb_rdev)) { + smb347_irq_disable(smb); + return PTR_ERR(smb->usb_rdev); + } + return 0; } @@ -1388,11 +1600,17 @@ static int smb347_remove(struct i2c_client *client) { struct smb347_charger *smb = i2c_get_clientdata(client); + smb347_usb_vbus_regulator_disable(smb->usb_rdev); smb347_irq_disable(smb); return 0; } +static void smb347_shutdown(struct i2c_client *client) +{ + smb347_remove(client); +} + static const struct i2c_device_id smb347_id[] = { { "smb345", SMB345 }, { "smb347", SMB347 }, @@ -1416,6 +1634,7 @@ static struct i2c_driver smb347_driver = { }, .probe = smb347_probe, .remove = smb347_remove, + .shutdown = smb347_shutdown, .id_table = smb347_id, }; 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[94.29.22.96]) by smtp.gmail.com with ESMTPSA id s15sm445272lfp.216.2021.07.31.10.39.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Jul 2021 10:39:04 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Sebastian Reichel , Peter Chen , Greg Kroah-Hartman , Felipe Balbi , David Heidelberg Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v6 10/12] ARM: tegra: Add new properties to USB PHY device-tree nodes Date: Sat, 31 Jul 2021 20:38:40 +0300 Message-Id: <20210731173842.19643-11-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210731173842.19643-1-digetx@gmail.com> References: <20210731173842.19643-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Add new properties to USB PHYs needed for enabling USB OTG mode. Signed-off-by: Dmitry Osipenko --- arch/arm/boot/dts/tegra114.dtsi | 4 ++++ arch/arm/boot/dts/tegra124.dtsi | 6 ++++++ arch/arm/boot/dts/tegra20.dtsi | 6 ++++++ arch/arm/boot/dts/tegra30.dtsi | 6 ++++++ 4 files changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index fb99b3e971c3..b391c7940b8f 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -706,6 +706,7 @@ phy1: usb-phy@7d000000 { compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x7d000000 0x4000>, <0x7d000000 0x4000>; + interrupts = ; phy_type = "utmi"; clocks = <&tegra_car TEGRA114_CLK_USBD>, <&tegra_car TEGRA114_CLK_PLL_U>, @@ -725,6 +726,7 @@ phy1: usb-phy@7d000000 { nvidia,hsdiscon-level = <5>; nvidia,xcvr-hsslew = <12>; nvidia,has-utmi-pad-registers; + nvidia,pmc = <&tegra_pmc 0>; status = "disabled"; }; @@ -744,6 +746,7 @@ phy3: usb-phy@7d008000 { compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x7d008000 0x4000>, <0x7d000000 0x4000>; + interrupts = ; phy_type = "utmi"; clocks = <&tegra_car TEGRA114_CLK_USB3>, <&tegra_car TEGRA114_CLK_PLL_U>, @@ -762,6 +765,7 @@ phy3: usb-phy@7d008000 { nvidia,hssquelch-level = <2>; nvidia,hsdiscon-level = <5>; nvidia,xcvr-hsslew = <12>; + nvidia,pmc = <&tegra_pmc 2>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 8b38f123f554..ee28bb2b01ba 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -1094,6 +1094,7 @@ phy1: usb-phy@7d000000 { compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x0 0x7d000000 0x0 0x4000>, <0x0 0x7d000000 0x0 0x4000>; + interrupts = ; phy_type = "utmi"; clocks = <&tegra_car TEGRA124_CLK_USBD>, <&tegra_car TEGRA124_CLK_PLL_U>, @@ -1113,6 +1114,7 @@ phy1: usb-phy@7d000000 { nvidia,hsdiscon-level = <5>; nvidia,xcvr-hsslew = <12>; nvidia,has-utmi-pad-registers; + nvidia,pmc = <&tegra_pmc 0>; status = "disabled"; }; @@ -1132,6 +1134,7 @@ phy2: usb-phy@7d004000 { compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x0 0x7d004000 0x0 0x4000>, <0x0 0x7d000000 0x0 0x4000>; + interrupts = ; phy_type = "utmi"; clocks = <&tegra_car TEGRA124_CLK_USB2>, <&tegra_car TEGRA124_CLK_PLL_U>, @@ -1150,6 +1153,7 @@ phy2: usb-phy@7d004000 { nvidia,hssquelch-level = <2>; nvidia,hsdiscon-level = <5>; nvidia,xcvr-hsslew = <12>; + nvidia,pmc = <&tegra_pmc 1>; status = "disabled"; }; @@ -1169,6 +1173,7 @@ phy3: usb-phy@7d008000 { compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x0 0x7d008000 0x0 0x4000>, <0x0 0x7d000000 0x0 0x4000>; + interrupts = ; phy_type = "utmi"; clocks = <&tegra_car TEGRA124_CLK_USB3>, <&tegra_car TEGRA124_CLK_PLL_U>, @@ -1187,6 +1192,7 @@ phy3: usb-phy@7d008000 { nvidia,hssquelch-level = <2>; nvidia,hsdiscon-level = <5>; nvidia,xcvr-hsslew = <12>; + nvidia,pmc = <&tegra_pmc 2>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 2015147c2de3..ce2171739cf8 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -879,6 +879,7 @@ phy1: usb-phy@c5000000 { compatible = "nvidia,tegra20-usb-phy"; reg = <0xc5000000 0x4000>, <0xc5000000 0x4000>; + interrupts = ; phy_type = "utmi"; clocks = <&tegra_car TEGRA20_CLK_USBD>, <&tegra_car TEGRA20_CLK_PLL_U>, @@ -897,6 +898,7 @@ phy1: usb-phy@c5000000 { nvidia,xcvr-lsfslew = <1>; nvidia,xcvr-lsrslew = <1>; nvidia,has-utmi-pad-registers; + nvidia,pmc = <&tegra_pmc 0>; status = "disabled"; }; @@ -917,6 +919,7 @@ usb@c5004000 { phy2: usb-phy@c5004000 { compatible = "nvidia,tegra20-usb-phy"; reg = <0xc5004000 0x4000>; + interrupts = ; phy_type = "ulpi"; clocks = <&tegra_car TEGRA20_CLK_USB2>, <&tegra_car TEGRA20_CLK_PLL_U>, @@ -925,6 +928,7 @@ phy2: usb-phy@c5004000 { resets = <&tegra_car 58>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; #phy-cells = <0>; + nvidia,pmc = <&tegra_pmc 1>; status = "disabled"; }; @@ -946,6 +950,7 @@ phy3: usb-phy@c5008000 { compatible = "nvidia,tegra20-usb-phy"; reg = <0xc5008000 0x4000>, <0xc5000000 0x4000>; + interrupts = ; phy_type = "utmi"; clocks = <&tegra_car TEGRA20_CLK_USB3>, <&tegra_car TEGRA20_CLK_PLL_U>, @@ -962,6 +967,7 @@ phy3: usb-phy@c5008000 { nvidia,xcvr-setup = <9>; nvidia,xcvr-lsfslew = <2>; nvidia,xcvr-lsrslew = <2>; + nvidia,pmc = <&tegra_pmc 2>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 339ddda4b2a7..9c757b63a197 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -1151,6 +1151,7 @@ phy1: usb-phy@7d000000 { compatible = "nvidia,tegra30-usb-phy"; reg = <0x7d000000 0x4000>, <0x7d000000 0x4000>; + interrupts = ; phy_type = "utmi"; clocks = <&tegra_car TEGRA30_CLK_USBD>, <&tegra_car TEGRA30_CLK_PLL_U>, @@ -1171,6 +1172,7 @@ phy1: usb-phy@7d000000 { nvidia,hssquelch-level = <2>; nvidia,hsdiscon-level = <5>; nvidia,has-utmi-pad-registers; + nvidia,pmc = <&tegra_pmc 0>; status = "disabled"; }; @@ -1192,6 +1194,7 @@ phy2: usb-phy@7d004000 { compatible = "nvidia,tegra30-usb-phy"; reg = <0x7d004000 0x4000>, <0x7d000000 0x4000>; + interrupts = ; phy_type = "utmi"; clocks = <&tegra_car TEGRA30_CLK_USB2>, <&tegra_car TEGRA30_CLK_PLL_U>, @@ -1211,6 +1214,7 @@ phy2: usb-phy@7d004000 { nvidia,xcvr-hsslew = <32>; nvidia,hssquelch-level = <2>; nvidia,hsdiscon-level = <5>; + nvidia,pmc = <&tegra_pmc 1>; status = "disabled"; }; @@ -1232,6 +1236,7 @@ phy3: usb-phy@7d008000 { compatible = "nvidia,tegra30-usb-phy"; reg = <0x7d008000 0x4000>, <0x7d000000 0x4000>; + interrupts = ; phy_type = "utmi"; clocks = <&tegra_car TEGRA30_CLK_USB3>, <&tegra_car TEGRA30_CLK_PLL_U>, @@ -1251,6 +1256,7 @@ phy3: usb-phy@7d008000 { nvidia,xcvr-hsslew = <32>; nvidia,hssquelch-level = <2>; nvidia,hsdiscon-level = <5>; + nvidia,pmc = <&tegra_pmc 2>; status = "disabled"; }; From patchwork Sat Jul 31 17:38:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 490041 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDB9BC47422 for ; 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[94.29.22.96]) by smtp.gmail.com with ESMTPSA id s15sm445272lfp.216.2021.07.31.10.39.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Jul 2021 10:39:05 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Sebastian Reichel , Peter Chen , Greg Kroah-Hartman , Felipe Balbi , David Heidelberg Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v6 11/12] ARM: tegra: nexus7: Enable USB OTG mode Date: Sat, 31 Jul 2021 20:38:41 +0300 Message-Id: <20210731173842.19643-12-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210731173842.19643-1-digetx@gmail.com> References: <20210731173842.19643-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Nexus 7 has OTG-cable microUSB port, enable OTG mode. USB peripheral devices now can be connected to Nexus 7 using OTG adapter, switching USB port into host mode. Signed-off-by: Dmitry Osipenko --- .../tegra30-asus-nexus7-grouper-common.dtsi | 25 +++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index 4f116c26f6ce..798ac22a50d2 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -941,9 +941,29 @@ power_supply: charger@6a { interrupts = ; summit,enable-charge-control = ; + summit,inok-polarity = ; summit,enable-usb-charging; monitored-battery = <&battery_cell>; + + usb_vbus: usb-vbus { + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-min-microamp = <750000>; + regulator-max-microamp = <750000>; + + /* + * SMB347 INOK input pin is connected to PMIC's + * ACOK output, which is fixed to ACTIVE_LOW as + * long as battery voltage is in a good range. + * + * Active INOK disables SMB347 output, so polarity + * needs to be toggled when we want to get the + * output. + */ + summit,needs-inok-toggle; + }; }; }; @@ -1017,12 +1037,13 @@ sdmmc4: mmc@78000600 { usb@7d000000 { compatible = "nvidia,tegra30-udc"; status = "okay"; - dr_mode = "peripheral"; + dr_mode = "otg"; + vbus-supply = <&usb_vbus>; }; usb-phy@7d000000 { status = "okay"; - dr_mode = "peripheral"; + dr_mode = "otg"; nvidia,hssync-start-delay = <0>; nvidia,xcvr-lsfslew = <2>; nvidia,xcvr-lsrslew = <2>; From patchwork Sat Jul 31 17:38:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 490042 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC132C43216 for ; Sat, 31 Jul 2021 17:39:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9A0DF60EE6 for ; Sat, 31 Jul 2021 17:39:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231684AbhGaRjf (ORCPT ); Sat, 31 Jul 2021 13:39:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52114 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232091AbhGaRjT (ORCPT ); Sat, 31 Jul 2021 13:39:19 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ADC87C0617BD; Sat, 31 Jul 2021 10:39:07 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id m13so24899993lfg.13; Sat, 31 Jul 2021 10:39:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=y7SaHURNXyUBjsQfPYlKAP5ckfuIlCfIy3J3ukz+tBo=; b=MQujzLlEnO36raJBMAT9fzpDdMWfWGz1uVH0Uu5hA9Xx1PD1KBkSvTCXaTZMVdczJB lPupngVIb+yocPz38kxOOSTCE2JuW4FRTpSclkb/trtdWTNtAjdVZjK51KeNSywI91rZ B2XbRpZVcZqDPgNRmOIIha3gZLsqf/W3CT5mbGXSqXgk98fLFSpdJY+VbOQIi6ZWLwgz hainLQYoyk/fmAg2fjkY90VcNOOYaX4en/B5cB1Pv0qO1Li9IiTIKBDa73v6gSJtlDk4 XhSpd2nbbrhi4oQkM5PZVblNumQ//dq2x5BoewCUDF7XgCwaCcRoXbECCg5T+8LWFW4+ JhOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=y7SaHURNXyUBjsQfPYlKAP5ckfuIlCfIy3J3ukz+tBo=; b=X+p2iCkQ4eH2ELzeiK++M37yU8rKL9ZC7peved9rcbUNFPrgztXlmaYKteXsg3EgWP ROkqo64XyQQ+WCQRwQRh7Mw9hziKPfl0xW8JlhvoXZQVJn4EfG42LAkqoODYmtuXcm6/ bjkMyqCxvN9qJa3FpJp/LlHkjRc3pX+fz8epmQMjf5T6vAoHb5n0qxddLWL8irSG0AZy fncW6C86nyYkQ2u9rC596oYDLP6WcgG3uFF7O3+4omuR53e5eCVE313MTt9IlHgblSqV eTKQ7Jjc9WEUilbpMfhdElYBrULD1LKL1LMEJ8Sz+SAmrVnDtz/pTRY+y28P65aSbiPz vGdg== X-Gm-Message-State: AOAM531sWc7m8e8EMVGH+YhSvQYh0ks1VbwCtrG60oKcpWGy5vVmbTXA VFqhiS6T8a2XX8bGa1XSun8= X-Google-Smtp-Source: ABdhPJzUMpYaCzhlyTvF2sPmwQ/o7m7NJzBlbqGXRAIBp7NvEr3VJpCMhBpsb2K0T7fhVbLfBds4Yg== X-Received: by 2002:a05:6512:3ca6:: with SMTP id h38mr6292523lfv.94.1627753146135; Sat, 31 Jul 2021 10:39:06 -0700 (PDT) Received: from localhost.localdomain (94-29-22-96.dynamic.spd-mgts.ru. [94.29.22.96]) by smtp.gmail.com with ESMTPSA id s15sm445272lfp.216.2021.07.31.10.39.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Jul 2021 10:39:05 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Sebastian Reichel , Peter Chen , Greg Kroah-Hartman , Felipe Balbi , David Heidelberg Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v6 12/12] arm64: tegra132: Add new properties to USB PHY device-tree node Date: Sat, 31 Jul 2021 20:38:42 +0300 Message-Id: <20210731173842.19643-13-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210731173842.19643-1-digetx@gmail.com> References: <20210731173842.19643-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Add new properties to USB PHYs needed for enabling USB OTG mode. Signed-off-by: Dmitry Osipenko --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 9928a87f593a..f79a66226457 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -1123,6 +1123,7 @@ phy1: usb-phy@7d000000 { compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x0 0x7d000000 0x0 0x4000>, <0x0 0x7d000000 0x0 0x4000>; + interrupts = ; phy_type = "utmi"; clocks = <&tegra_car TEGRA124_CLK_USBD>, <&tegra_car TEGRA124_CLK_PLL_U>, @@ -1142,6 +1143,7 @@ phy1: usb-phy@7d000000 { nvidia,hsdiscon-level = <5>; nvidia,xcvr-hsslew = <12>; nvidia,has-utmi-pad-registers; + nvidia,pmc = <&tegra_pmc 0>; status = "disabled"; }; @@ -1162,6 +1164,7 @@ phy2: usb-phy@7d004000 { compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x0 0x7d004000 0x0 0x4000>, <0x0 0x7d000000 0x0 0x4000>; + interrupts = ; phy_type = "utmi"; clocks = <&tegra_car TEGRA124_CLK_USB2>, <&tegra_car TEGRA124_CLK_PLL_U>, @@ -1180,6 +1183,7 @@ phy2: usb-phy@7d004000 { nvidia,hssquelch-level = <2>; nvidia,hsdiscon-level = <5>; nvidia,xcvr-hsslew = <12>; + nvidia,pmc = <&tegra_pmc 1>; status = "disabled"; }; @@ -1200,6 +1204,7 @@ phy3: usb-phy@7d008000 { compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x0 0x7d008000 0x0 0x4000>, <0x0 0x7d000000 0x0 0x4000>; + interrupts = ; phy_type = "utmi"; clocks = <&tegra_car TEGRA124_CLK_USB3>, <&tegra_car TEGRA124_CLK_PLL_U>, @@ -1218,6 +1223,7 @@ phy3: usb-phy@7d008000 { nvidia,hssquelch-level = <2>; nvidia,hsdiscon-level = <5>; nvidia,xcvr-hsslew = <12>; + nvidia,pmc = <&tegra_pmc 2>; status = "disabled"; };