From patchwork Fri Jul 30 14:49:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 489649 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E431CC41537 for ; Fri, 30 Jul 2021 14:49:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D245360C3F for ; Fri, 30 Jul 2021 14:49:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239413AbhG3Ote (ORCPT ); Fri, 30 Jul 2021 10:49:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239351AbhG3Otc (ORCPT ); Fri, 30 Jul 2021 10:49:32 -0400 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 22E38C061798 for ; Fri, 30 Jul 2021 07:49:27 -0700 (PDT) Received: by mail-ed1-x533.google.com with SMTP id h8so13545901ede.4 for ; Fri, 30 Jul 2021 07:49:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VTDgPgWodE/cSRF6bHIc6D1D5Dn1jvPwRYXuY/lAMLo=; b=TkueiDTdOMqYTmTxIiWclFQDmAoJQIi9pKg/pDn4T1rA2VjfILkGJNRgYCunu870MP qypWhzFqenbxNDZV4QPpZvTBiL0T6ZzwAkBRHMaovinMWM8mTUwcZ1jc6pskjFipGKIM IXhUOo6SBJYFp2Yht0rWwR6rKjHOixSLarchv5uf56EVbCILFXRb+G0Y547em6aa4I8/ BqZr3+joyNVs85IjpkswpDcIjciP+mlO9g6EoGxO1/d3NIEJTlZbuskA5bb08gAkGtd4 2oFBaMMAzmc1lYRJdhu9xkPqeQH6gQLUdBaAq+YpDbbvFgnFduiJnZeySi1IBccyGB81 Sgjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VTDgPgWodE/cSRF6bHIc6D1D5Dn1jvPwRYXuY/lAMLo=; b=HZa3wBoFN7ocO84qdH3cJ7nKvaeJ60aUWTcDXJ4CpUvH53FrfPpMpoY1fZ1vo7TBFw u+YKjYtyGvw8xFHLA98YBzw4nXJuaLUtZNbMXgsAnbK7A0SSc8c0QW2RYUqqVtB/1b1T bSonDbJRVPLoDSqAQsW4HodQiRO2STLbc5LdTLtFQMmFawGlucViEZqPEha7PKo89vW2 2FfvgRVkN5rWTQ/ss8s4o6BokZyInKDwx9MJ1Yee23eNdZSl3XFAuMBVBQF6xeqZwbdQ jCCtzOHbgiqs8rYQg6S/P7lalKfqlIVjBMpDpQJWESoUOzyoJl5DXYUmHKWAjSTPRDYk 8sEQ== X-Gm-Message-State: AOAM532nbefWOv7Yiv/d9C4bIAfJGt2J/gEv7jzqbfwSBQ0XpSKmPNG/ ViNbFCDMm4lcuPvwFoE3rTD97Q== X-Google-Smtp-Source: ABdhPJwQ3Vu/iMAI2TwOY1RDcotd+8kXvX1qj2ZROjO1I6ex2OtKHUvLBmtYk8c0mf//n0KTncs5Fw== X-Received: by 2002:a05:6402:31ba:: with SMTP id dj26mr3436625edb.252.1627656565567; Fri, 30 Jul 2021 07:49:25 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id o17sm629581ejb.84.2021.07.30.07.49.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jul 2021 07:49:25 -0700 (PDT) From: Sam Protsenko To: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa Cc: Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 01/12] pinctrl: samsung: Fix pinctrl bank pin count Date: Fri, 30 Jul 2021 17:49:11 +0300 Message-Id: <20210730144922.29111-2-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210730144922.29111-1-semen.protsenko@linaro.org> References: <20210730144922.29111-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Jaehyoung Choi Commit 1abd18d1a51a ("pinctrl: samsung: Register pinctrl before GPIO") changes the order of GPIO and pinctrl registration: now pinctrl is registered before GPIO. That means gpio_chip->ngpio is not set when samsung_pinctrl_register() called, and one cannot rely on that value anymore. Use `pin_bank->nr_pins' instead of `pin_bank->gpio_chip.ngpio' to fix mentioned inconsistency. Fixes: 1abd18d1a51a ("pinctrl: samsung: Register pinctrl before GPIO") Signed-off-by: Jaehyoung Choi Signed-off-by: Sam Protsenko --- drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 376876bd6605..2975b4369f32 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -918,7 +918,7 @@ static int samsung_pinctrl_register(struct platform_device *pdev, pin_bank->grange.pin_base = drvdata->pin_base + pin_bank->pin_base; pin_bank->grange.base = pin_bank->grange.pin_base; - pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; + pin_bank->grange.npins = pin_bank->nr_pins; pin_bank->grange.gc = &pin_bank->gpio_chip; pinctrl_add_gpio_range(drvdata->pctl_dev, &pin_bank->grange); } From patchwork Fri Jul 30 14:49:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 490036 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 780F2C4320A for ; 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Fri, 30 Jul 2021 07:49:27 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id g23sm634979ejm.26.2021.07.30.07.49.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jul 2021 07:49:26 -0700 (PDT) From: Sam Protsenko To: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa Cc: Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 02/12] pinctrl: samsung: Add Exynos850 SoC specific data Date: Fri, 30 Jul 2021 17:49:12 +0300 Message-Id: <20210730144922.29111-3-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210730144922.29111-1-semen.protsenko@linaro.org> References: <20210730144922.29111-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add Samsung Exynos850 SoC specific data to enable pinctrl support for all platforms based on Exynos850. Signed-off-by: Sam Protsenko --- .../pinctrl/samsung/pinctrl-exynos-arm64.c | 129 ++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-exynos.h | 29 ++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 4 files changed, 161 insertions(+) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index b6e56422a700..9c71ff84ba7e 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -40,6 +40,24 @@ static const struct samsung_pin_bank_type exynos5433_bank_type_alive = { .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, }; +/* + * Bank type for non-alive type. Bit fields: + * CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4 + */ +static struct samsung_pin_bank_type exynos850_bank_type_off = { + .fld_width = { 4, 1, 4, 4, 2, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, +}; + +/* + * Bank type for alive type. Bit fields: + * CON: 4, DAT: 1, PUD: 4, DRV: 4 + */ +static struct samsung_pin_bank_type exynos850_bank_type_alive = { + .fld_width = { 4, 1, 4, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, +}; + /* Pad retention control code for accessing PMU regmap */ static atomic_t exynos_shared_retention_refcnt; @@ -422,3 +440,114 @@ const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = { .ctrl = exynos7_pin_ctrl, .num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl), }; + +/* pin banks of exynos850 pin-controller 0 (ALIVE) */ +static struct samsung_pin_bank_data exynos850_pin_banks0[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS9_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), + EXYNOS9_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), + EXYNOS9_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), + EXYNOS9_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), + EXYNOS9_PIN_BANK_EINTW(4, 0x080, "gpa4", 0x10), + EXYNOS9_PIN_BANK_EINTN(3, 0x0A0, "gpq0"), +}; + +/* pin banks of exynos850 pin-controller 1 (CMGP) */ +static struct samsung_pin_bank_data exynos850_pin_banks1[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS9_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00), + EXYNOS9_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04), + EXYNOS9_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08), + EXYNOS9_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0C), + EXYNOS9_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10), + EXYNOS9_PIN_BANK_EINTW(1, 0x0A0, "gpm5", 0x14), + EXYNOS9_PIN_BANK_EINTW(1, 0x0C0, "gpm6", 0x18), + EXYNOS9_PIN_BANK_EINTW(1, 0x0E0, "gpm7", 0x1C), +}; + +/* pin banks of exynos850 pin-controller 2 (AUD) */ +static struct samsung_pin_bank_data exynos850_pin_banks2[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS9_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), + EXYNOS9_PIN_BANK_EINTG(5, 0x020, "gpb1", 0x04), +}; + +/* pin banks of exynos850 pin-controller 3 (HSI) */ +static struct samsung_pin_bank_data exynos850_pin_banks3[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS9_PIN_BANK_EINTG(6, 0x000, "gpf2", 0x00), +}; + +/* pin banks of exynos850 pin-controller 4 (CORE) */ +static struct samsung_pin_bank_data exynos850_pin_banks4[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS9_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00), + EXYNOS9_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04), +}; + +/* pin banks of exynos850 pin-controller 5 (PERI) */ +static struct samsung_pin_bank_data exynos850_pin_banks5[] = { + /* Must start with EINTG banks, ordered by EINT group number. */ + EXYNOS9_PIN_BANK_EINTG(2, 0x000, "gpg0", 0x00), + EXYNOS9_PIN_BANK_EINTG(6, 0x020, "gpp0", 0x04), + EXYNOS9_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08), + EXYNOS9_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0C), + EXYNOS9_PIN_BANK_EINTG(8, 0x080, "gpg1", 0x10), + EXYNOS9_PIN_BANK_EINTG(8, 0x0A0, "gpg2", 0x14), + EXYNOS9_PIN_BANK_EINTG(1, 0x0C0, "gpg3", 0x18), + EXYNOS9_PIN_BANK_EINTG(3, 0x0E0, "gpc0", 0x1C), + EXYNOS9_PIN_BANK_EINTG(6, 0x100, "gpc1", 0x20), +}; + +static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks = exynos850_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 1 CMGP data */ + .pin_banks = exynos850_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 2 AUD data */ + .pin_banks = exynos850_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 3 HSI data */ + .pin_banks = exynos850_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 4 CORE data */ + .pin_banks = exynos850_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 5 PERI data */ + .pin_banks = exynos850_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, +}; + +const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = { + .ctrl = exynos850_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynos850_pin_ctrl), +}; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h index da1ec13697e7..595086f2d5dd 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -108,6 +108,35 @@ .pctl_res_idx = pctl_idx, \ } \ +#define EXYNOS9_PIN_BANK_EINTN(pins, reg, id) \ + { \ + .type = &exynos850_bank_type_alive, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_NONE, \ + .name = id \ + } + +#define EXYNOS9_PIN_BANK_EINTG(pins, reg, id, offs) \ + { \ + .type = &exynos850_bank_type_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_offset = offs, \ + .name = id \ + } + +#define EXYNOS9_PIN_BANK_EINTW(pins, reg, id, offs) \ + { \ + .type = &exynos850_bank_type_alive, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_offset = offs, \ + .name = id \ + } + /** * struct exynos_weint_data: irq specific data for all the wakeup interrupts * generated by the external wakeup interrupt controller. diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 2975b4369f32..2a0fc63516f1 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1264,6 +1264,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &exynos5433_of_data }, { .compatible = "samsung,exynos7-pinctrl", .data = &exynos7_of_data }, + { .compatible = "samsung,exynos850-pinctrl", + .data = &exynos850_of_data }, #endif #ifdef CONFIG_PINCTRL_S3C64XX { .compatible = "samsung,s3c64xx-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index de44f8ec330b..4c2149e9c544 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -339,6 +339,7 @@ extern const struct samsung_pinctrl_of_match_data exynos5410_of_data; extern const struct samsung_pinctrl_of_match_data exynos5420_of_data; extern const struct samsung_pinctrl_of_match_data exynos5433_of_data; extern const struct samsung_pinctrl_of_match_data exynos7_of_data; +extern const struct samsung_pinctrl_of_match_data exynos850_of_data; extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data; extern const struct samsung_pinctrl_of_match_data s3c2412_of_data; extern const struct samsung_pinctrl_of_match_data s3c2416_of_data; From patchwork Fri Jul 30 14:49:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 489323 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:1185:0:0:0:0 with SMTP id f5csp3221743jas; Fri, 30 Jul 2021 07:49:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyE5sKtOAs38Wh+DQQyuqoUX3KwLxa/lzsxL4fhKKeFeCS+FZUyjg/pn/uGogMlwjidlSgP X-Received: by 2002:a02:c95a:: with SMTP id u26mr2500019jao.49.1627656576337; Fri, 30 Jul 2021 07:49:36 -0700 (PDT) ARC-Seal: i=1; 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[23.128.96.18]) by mx.google.com with ESMTP id x1si1842506jan.58.2021.07.30.07.49.36; Fri, 30 Jul 2021 07:49:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-serial-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xBHhd9zv; spf=pass (google.com: domain of linux-serial-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239496AbhG3Otk (ORCPT + 2 others); Fri, 30 Jul 2021 10:49:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46508 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239418AbhG3Ote (ORCPT ); Fri, 30 Jul 2021 10:49:34 -0400 Received: from mail-ed1-x530.google.com (mail-ed1-x530.google.com [IPv6:2a00:1450:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E38A0C06179C for ; Fri, 30 Jul 2021 07:49:29 -0700 (PDT) Received: by mail-ed1-x530.google.com with SMTP id h8so13546089ede.4 for ; Fri, 30 Jul 2021 07:49:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U9K2fCuQkFkuejqJypW0+59cAZpu5FWH3o4en7PCa/U=; b=xBHhd9zvnsIklZ1GYG2DllDAjGkCvzS1dG3aJNp2jJBUjGCODD25G5qxsc2ero+kap RpCdICsb5OUgHCuWG7tnZnMbM3MenMlhhh6Us32/VRdY3+PzBzn8R4/DOJeoRZZE5rQ8 uzzVSVy/gCAn685CUUH8MSNnTu8iENv6JV7pC3EscmTCEj6NtZuXP58g8fwocXspBy1u MVIeizHdTl5IMp+ptpOLLfPsyg1TX0mDKnSatp61VSaOc1wiTWROa2J9DeGZvd/ygkHm X5duQR4eJDCRyu7okuNaMH+BeBYZyhWPWyAxgKidQsPo4pto1ZKIeHiRlfzVqJam76cc FA7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U9K2fCuQkFkuejqJypW0+59cAZpu5FWH3o4en7PCa/U=; b=VDfqb39XZ3DY9MiLzkRpH66vrt7r0CpFFqLcB0Uq2nVvpELe3Zm0qmIdbouUyEE9+H HinFOegwi/rtvurgihjWtaj78vnBGHhxuv8/zplmY91emuRJEZTm2wFqPjcTuEplKjnj 1W863OHf6y4T5ILwaDhxBH3qdykXLZ2XIeIBeWpgLErGUKRGHNNEAf3jfSAv4Y1YQks7 KZHu06Go1TkcRt7SvvXuu9LkZPpxjMcpkrnwC8nFRPcrvAUeMxQoBd2IuDj5yaVTqwot 6Qu+I934KqOAUWIIT0tZXxpxZz5hobVQHC9iupK67SNqhahuM4Zg5jkpZJPEgEKvzKfu 0Myw== X-Gm-Message-State: AOAM532WRYK3wh0x5cJ6nzceei36GSzqlR1EWp99x//ioCHFm/uV7qpC /PUe7sYSEV9d+H7A0ALL/qyvEg== X-Received: by 2002:a05:6402:411:: with SMTP id q17mr3370148edv.29.1627656568574; Fri, 30 Jul 2021 07:49:28 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id b15sm622945ejv.15.2021.07.30.07.49.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jul 2021 07:49:28 -0700 (PDT) From: Sam Protsenko To: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa Cc: Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 03/12] dt-bindings: pinctrl: samsung: Add Exynos850 doc Date: Fri, 30 Jul 2021 17:49:13 +0300 Message-Id: <20210730144922.29111-4-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210730144922.29111-1-semen.protsenko@linaro.org> References: <20210730144922.29111-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Document compatible string for Exynos850 SoC. Nothing else is changed, as Exynos850 SoC uses already existing samsung pinctrl driver. Signed-off-by: Sam Protsenko --- Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt | 1 + 1 file changed, 1 insertion(+) -- 2.30.2 diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index 38a1416fd2cd..e7a1b1880375 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt @@ -22,6 +22,7 @@ Required Properties: - "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller. - "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller. - "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller. + - "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller. - reg: Base address of the pin controller hardware module and length of the address space it occupies. From patchwork Fri Jul 30 14:49:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 489324 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:1185:0:0:0:0 with SMTP id f5csp3221827jas; Fri, 30 Jul 2021 07:49:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxi8LlYezv6DyUHrO4UMCDqhOoCWvQEbxIFSUz9PBq6sec2tkbDZOYAU7i4D869SLvRFlCE X-Received: by 2002:a05:6602:38d:: with SMTP id f13mr1698387iov.153.1627656581715; Fri, 30 Jul 2021 07:49:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627656581; cv=none; d=google.com; s=arc-20160816; b=GJ96VE4X0JAI0ODGhoY5RpSDKFqnYK7yQGetbUa1SHVdaob0/9wTxsVAMkBv3vLO0/ AXXOCcFwZY2pwv01LxZ+pHYMb4fdsgq/y6g+cAlRvt77TduXupqNYqU2T/dIB3HAI2my NK/+7yKkWes2hdRO3UcsRok0lGf9eQCrk1mkKswcV9a9SrNot7pBOYfZpRo/Ey2OqfX5 mo/i09d6SnENH8YpJITJ7PDcwT0FZSZ3sTlXb1OdzfsfgHPiO6YEoQ2I16TdznWPIFoX xaqiifzBJaDJs6vP/Y3bg16xymVdV1sJ0H0K12ipPE0ytKfxd91ELUKMIdmAsONjaTG2 2sZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=21ZGNuzwEHiEcUhGsOE28cnE6TpdhYH0dz9pLV6DTy8=; b=nbZ5TCvn/mF2vv1iH/h/NADoSP+iIEZwiiTwYc2WmKDjv3QZ6b2rolgofgqz79HnR7 627AAydtpKEt8oac6/c45AewgZMFjseZGY/Sny+xmCEu3pTho5GIUBj9T0rlg/l8a7Pv KNcZsB1F8oLrBV4+oLBxywmp6xm/pEuOXWNsZ/RNnZi7ptsTfg9g6nQBA4OWghDPCL9X lRU5DuYIom9OMjW6xGM00oUihSmoJsnBSkwX+T5uxi0EgpvqAhv5ShKPjSr5E+DALn3I xXoYWXP8UDhkyzz4IczubpCnpyROXfmAPejVcvxJ3l+4tNePaAu3SVX/A9kVsRV68PmO R1XA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=q+TZ4GN7; spf=pass (google.com: domain of linux-serial-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id g6si2029207ilf.57.2021.07.30.07.49.41; Fri, 30 Jul 2021 07:49:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-serial-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=q+TZ4GN7; spf=pass (google.com: domain of linux-serial-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239514AbhG3Otm (ORCPT + 2 others); Fri, 30 Jul 2021 10:49:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46530 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239459AbhG3Oti (ORCPT ); Fri, 30 Jul 2021 10:49:38 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8227FC061799 for ; Fri, 30 Jul 2021 07:49:31 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id v21so17301071ejg.1 for ; Fri, 30 Jul 2021 07:49:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=21ZGNuzwEHiEcUhGsOE28cnE6TpdhYH0dz9pLV6DTy8=; b=q+TZ4GN7NDpiauPfHRA8wuq0TXGl5nFCopympoMiK713uSG1Tqg/ML90uERBQgTqwz ZbzE0VZVrIT3MrkXC9Urw7GFfbRQwOegHhKhUd1C98HqcBIM3cPvyvw/TA8HeEZs7lF7 jpECUsIB7Bqxpt6hgbsHOF7p14eT7JzvpBlrOD28t1i7NQZJsAwiqtim466FDLR9BjGz kpXC/3OTpvmrDA1YZWUlFv0LynIJrawjdXd3uLO88RfSrmjJaYc35VyAU0bMEWpvoZ6U R29l5WKsh845qdVu5PFo0vc/riQkQlLIQn1N+MBqd7gCLs3RThwTUrrnew7puSNm+zhc HXAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=21ZGNuzwEHiEcUhGsOE28cnE6TpdhYH0dz9pLV6DTy8=; b=tS6RBWfkmBC2qyBz01vFN1RIas56+DU35seqBncpQgGAMVPUDXW1J7DuzNPe92pX/J /hoVNztS8Ny2ZskMVX38QaSplfaniLbO4WRNmUp0L+qlf6nlWc+iipyqzCMHINLp/jHS /DBCmC7C8DsQ47caLFHWIZLAHPF+uxHA2CdPHTSILl/e+6iizx30dQYy5T/6m2um4qTj Rbz6y8IZUHtU66jkqy4QQOmKHCD7Qks3xVfKvS5aEUsgSKWlBucJjDfbSVfV9ef7QgIa B92zTzoxYgvFXrTpjDewq/g1C8OgdB2XxB1/UZnzDD1bBV7Fv8DntrcnZj2EtNjXXkNu 9THw== X-Gm-Message-State: AOAM533+xps6KN3BiIS3ZfDqJu0PEEFidSi1bK69fK0ifmQ2B3BvmSpo UN9lgNvgVhkHPIQCqd6ExDheWQ== X-Received: by 2002:a17:906:4fd6:: with SMTP id i22mr2976400ejw.92.1627656570097; Fri, 30 Jul 2021 07:49:30 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id p23sm813317edw.94.2021.07.30.07.49.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jul 2021 07:49:29 -0700 (PDT) From: Sam Protsenko To: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa Cc: Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 04/12] tty: serial: samsung: Init USI to keep clocks running Date: Fri, 30 Jul 2021 17:49:14 +0300 Message-Id: <20210730144922.29111-5-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210730144922.29111-1-semen.protsenko@linaro.org> References: <20210730144922.29111-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org UART block is a part of USI (Universal Serial Interface) IP-core in Samsung SoCs since Exynos9810 (e.g. in Exynos850). USI allows one to enable one of three types of serial interface: UART, SPI or I2C. That's possible because USI shares almost all internal circuits within each protocol. USI also provides some additional registers so it's possible to configure it. One USI register called USI_OPTION has reset value of 0x0. Because of this the clock gating behavior is controlled by hardware (HWACG = Hardware Auto Clock Gating), which simply means the serial won't work after reset as is. In order to make it work, USI_OPTION[2:1] bits must be set to 0b01, so that HWACG is controlled manually (by software). Bits meaning: - CLKREQ_ON = 1: clock is continuously provided to IP - CLKSTOP_ON = 0: drive IP_CLKREQ to High (needs to be set along with CLKREQ_ON = 1) USI is not present on older chips, like s3c2410, s3c2412, s3c2440, s3c6400, s5pv210, exynos5433, exynos4210. So the new boolean field '.has_usi' was added to struct s3c24xx_uart_info. USI registers will be only actually accessed when '.has_usi' field is set to "1". This feature is needed for further serial enablement on Exynos850, but some other new Exynos chips (like Exynos9810) may benefit from this feature as well. Signed-off-by: Sam Protsenko --- drivers/tty/serial/samsung_tty.c | 33 +++++++++++++++++++++++++++++++- include/linux/serial_s3c.h | 9 +++++++++ 2 files changed, 41 insertions(+), 1 deletion(-) -- 2.30.2 diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index 9fbc61151c2e..0f3cbd0b37e3 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -65,6 +65,7 @@ enum s3c24xx_port_type { struct s3c24xx_uart_info { char *name; enum s3c24xx_port_type type; + unsigned int has_usi; unsigned int port_type; unsigned int fifosize; unsigned long rx_fifomask; @@ -1352,6 +1353,29 @@ static int apple_s5l_serial_startup(struct uart_port *port) return ret; } +static void exynos_usi_init(struct uart_port *port) +{ + struct s3c24xx_uart_port *ourport = to_ourport(port); + struct s3c24xx_uart_info *info = ourport->info; + + if (!info->has_usi) + return; + + /* + * USI_RESET is an active High signal. Reset value of USI_RESET is 0x1 + * to drive stable value to PAD. Due to this feature, the USI_RESET must + * be cleared (set as 0x0) before starting a transaction. + */ + wr_regl(port, USI_CON, USI_RESET); + udelay(1); + + /* + * Set the HWACG option bit in case of UART Rx mode. + * CLKREQ_ON = 1, CLKSTOP_ON = 0 (set USI_OPTION[2:1] = 0x1). + */ + wr_regl(port, USI_OPTION, USI_HWACG_CLKREQ_ON); +} + /* power power management control */ static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, @@ -1379,6 +1403,7 @@ static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, if (!IS_ERR(ourport->baudclk)) clk_prepare_enable(ourport->baudclk); + exynos_usi_init(port); break; default: dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level); @@ -2102,6 +2127,8 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport, if (ret) pr_warn("uart: failed to enable baudclk\n"); + exynos_usi_init(port); + /* Keep all interrupts masked and cleared */ switch (ourport->info->type) { case TYPE_S3C6400: @@ -2750,10 +2777,11 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { #endif #if defined(CONFIG_ARCH_EXYNOS) -#define EXYNOS_COMMON_SERIAL_DRV_DATA \ +#define EXYNOS_COMMON_SERIAL_DRV_DATA_USI(_has_usi) \ .info = &(struct s3c24xx_uart_info) { \ .name = "Samsung Exynos UART", \ .type = TYPE_S3C6400, \ + .has_usi = _has_usi, \ .port_type = PORT_S3C6400, \ .has_divslot = 1, \ .rx_fifomask = S5PV210_UFSTAT_RXMASK, \ @@ -2773,6 +2801,9 @@ static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { .has_fracval = 1, \ } \ +#define EXYNOS_COMMON_SERIAL_DRV_DATA \ + EXYNOS_COMMON_SERIAL_DRV_DATA_USI(0) + static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = { EXYNOS_COMMON_SERIAL_DRV_DATA, .fifosize = { 256, 64, 16, 16 }, diff --git a/include/linux/serial_s3c.h b/include/linux/serial_s3c.h index f6c3323fc4c5..013c2646863e 100644 --- a/include/linux/serial_s3c.h +++ b/include/linux/serial_s3c.h @@ -28,6 +28,15 @@ #define S3C2410_UFSTAT (0x18) #define S3C2410_UMSTAT (0x1C) +/* USI Control Register offset */ +#define USI_CON (0xC4) +/* USI Option Register offset */ +#define USI_OPTION (0xC8) +/* USI_CON[0] = 0b0: clear USI global software reset (Active High) */ +#define USI_RESET (0<<0) +/* USI_OPTION[2:1] = 0b01: continuously provide the clock to IP w/o gating */ +#define USI_HWACG_CLKREQ_ON (1<<1) + #define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3)) #define S3C2410_LCON_CS5 (0x0) From patchwork Fri Jul 30 14:49:15 2021 Content-Type: text/plain; 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Fri, 30 Jul 2021 07:49:31 -0700 (PDT) From: Sam Protsenko To: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa Cc: Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 05/12] tty: serial: samsung: Fix driver data macros style Date: Fri, 30 Jul 2021 17:49:15 +0300 Message-Id: <20210730144922.29111-6-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210730144922.29111-1-semen.protsenko@linaro.org> References: <20210730144922.29111-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Make checkpatch happy by fixing this error: ERROR: Macros with complex values should be enclosed in parentheses Although this change is made to keep macros consistent with consequent patches (adding driver data for new SoC), it's intentionally added as a separate patch to ease possible porting efforts in future. Signed-off-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski --- drivers/tty/serial/samsung_tty.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index 0f3cbd0b37e3..75ccbb08df4a 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -2817,8 +2817,8 @@ static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = { #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data) #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data) #else -#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL -#define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL +#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)NULL) +#define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)NULL) #endif #ifdef CONFIG_ARCH_APPLE From patchwork Fri Jul 30 14:49:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 490034 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44B8CC4338F for ; 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Fri, 30 Jul 2021 07:49:33 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id i10sm784560edf.12.2021.07.30.07.49.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jul 2021 07:49:32 -0700 (PDT) From: Sam Protsenko To: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa Cc: Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 06/12] tty: serial: samsung: Add Exynos850 SoC data Date: Fri, 30 Jul 2021 17:49:16 +0300 Message-Id: <20210730144922.29111-7-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210730144922.29111-1-semen.protsenko@linaro.org> References: <20210730144922.29111-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add serial driver data for Exynos850 SoC. This driver data is basically reusing EXYNOS_COMMON_SERIAL_DRV_DATA, which is common for all Exynos chips, but also enables USI init, which was added in previous commit: "tty: serial: samsung: Init USI to keep clocks running". Signed-off-by: Sam Protsenko --- drivers/tty/serial/samsung_tty.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c index 75ccbb08df4a..d059b516a0f4 100644 --- a/drivers/tty/serial/samsung_tty.c +++ b/drivers/tty/serial/samsung_tty.c @@ -2814,11 +2814,19 @@ static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = { .fifosize = { 64, 256, 16, 256 }, }; +static struct s3c24xx_serial_drv_data exynos850_serial_drv_data = { + EXYNOS_COMMON_SERIAL_DRV_DATA_USI(1), + .fifosize = { 0, }, +}; + #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data) #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data) +#define EXYNOS850_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos850_serial_drv_data) + #else #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)NULL) #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)NULL) +#define EXYNOS850_SERIAL_DRV_DATA ((kernel_ulong_t)NULL) #endif #ifdef CONFIG_ARCH_APPLE @@ -2874,6 +2882,9 @@ static const struct platform_device_id s3c24xx_serial_driver_ids[] = { }, { .name = "s5l-uart", .driver_data = S5L_SERIAL_DRV_DATA, + }, { + .name = "exynos850-uart", + .driver_data = EXYNOS850_SERIAL_DRV_DATA, }, { }, }; @@ -2897,6 +2908,8 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = { .data = (void *)EXYNOS5433_SERIAL_DRV_DATA }, { .compatible = "apple,s5l-uart", .data = (void *)S5L_SERIAL_DRV_DATA }, + { .compatible = "samsung,exynos850-uart", + .data = (void *)EXYNOS850_SERIAL_DRV_DATA }, {}, }; MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); From patchwork Fri Jul 30 14:49:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 489327 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:1185:0:0:0:0 with SMTP id f5csp3222042jas; Fri, 30 Jul 2021 07:49:56 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzUtKjQY4mytv1YomxtkiiNboEZX2AOoBWEJMVsM4rLEtXUruoV/Lion89I4Xg35RuqPwEE X-Received: by 2002:a92:d3d2:: with SMTP id c18mr530603ilh.192.1627656595977; Fri, 30 Jul 2021 07:49:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627656595; cv=none; d=google.com; s=arc-20160816; b=lCF6gLULsGvRTWXuJtE3t37l7o4EfOHxOEjCn3wfbUJYJMwtYD/TQ0OOpZAr2ff2jX uioHm3DUDpYhM4/OWYtGvYHFjYUqjAg0VL+SOYVyjjIJomVN4YB2k+WvpO1YJJd65GSC HVEr4HWBEM9JloWeagKlRsugeQJPRMUOOEuiD8FrPo0OwezLlbIj7h9UKltQqw8X0DBd rbKx00TnAa4q98LqOCgDHlKhGqLEzWnLsu8t0kGv/OAzZ+hulsG/QHU++qC/P5mXikI0 WqPSvP81IYmgIp+HWifS5B4SORD8uRayexEOs5M3jmgvVjk5+w/CSOBFtYOKs8W8YKvD ztGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=1JbUamQBQTeeK5FgvIv/xtu/RYU45rMZWaCOPLzo3D4=; b=CRdX9NnQKeJKneMSzfFELx4kfYdxdC2IkVojUWV44nwHr29G8QK6J6jDCfdb5SEig9 AHoWOukBae63Fm+C3Q6yUSu8KdiC4c/WTMO7jmYvgWYYuVTV/QhxW/j+ZzR9rzye0imG 4TBomjuJHn+ejZ8tZVleZPfb2uYA+HLsSovuw+GmHdkh8hJ2jy8GILFfjo/KtpPBKQKn OYs30mkMMYJt/tHlt0qHaalCOf5bFAj9DguZpaMkB6B4RYKLE1H19vCIMyxy6KMYv0nQ pXuOozprJRKEJg1PbqEXK64LOBYsKm7YgzxIdbN1GLUqKApu9MIUEwJo9mpipvrMbM08 DZdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=r4nEdjAh; spf=pass (google.com: domain of linux-serial-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Sam Protsenko --- Documentation/devicetree/bindings/serial/samsung_uart.yaml | 1 + 1 file changed, 1 insertion(+) -- 2.30.2 Reviewed-by: Krzysztof Kozlowski diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml index f064e5b76cf1..2940afb874b3 100644 --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml @@ -26,6 +26,7 @@ properties: - samsung,s3c6400-uart - samsung,s5pv210-uart - samsung,exynos4210-uart + - samsung,exynos850-uart reg: maxItems: 1 From patchwork Fri Jul 30 14:49:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 490033 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-23.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 348ABC4320E for ; Fri, 30 Jul 2021 14:50:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1F1C360F36 for ; Fri, 30 Jul 2021 14:50:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239602AbhG3OuH (ORCPT ); Fri, 30 Jul 2021 10:50:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239294AbhG3Ot5 (ORCPT ); Fri, 30 Jul 2021 10:49:57 -0400 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 758C8C061368 for ; Fri, 30 Jul 2021 07:49:37 -0700 (PDT) Received: by mail-ed1-x52a.google.com with SMTP id y7so11303255eda.5 for ; Fri, 30 Jul 2021 07:49:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kHxnIKoGMj+viA9SkCXyUhvwBThKkIIkNV1jgxaZB7A=; b=p2s7e7IGzpFpnksHeTsdi3WVo56e16ft+NwBT7ci/aAghxjETLx0uo5rRAq9yguHHc 6hqtVwzZpWPc1zCVCc7SYA6fBMGigy1WPXfoL0LmUGhb0jS7QZtFNNv3dDwV1P7G5NGx d+FTjh2Yna4S5hLGmA53sW4CACka+Zz5ys+FuEITUi7yBc2Nzom1IQ+rIm2xh/E31bi2 uP3qdxBMYnqItJGFfMJqFmcQyIaxeQqGqYWAKXaJtgwkQRxFGhzQN6IYEIQRby79tPSM QfWBPu+A5lOiOydjjeiDmcesTjL2P2/5NHXSk9W5fsfUzc7pVKvH9IirVIo07nKu/ZnO RRLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kHxnIKoGMj+viA9SkCXyUhvwBThKkIIkNV1jgxaZB7A=; b=bCMRK0kXNQ0gbUAySskUJdqOyErJVv59J4ND+nCgAzYie3nKUSPt6Kf8KP32FHd/ci 1UbTcPzKbYALjdFMkohA+qRueKg53elXZs3rbjAXAaKKYsQD04OZsWmzeK5TwK1dTkfx RLC2CaE+iunpTKBaIqkHlBc5xfnWPlq3Q4HIWbySWpcCx6dYzTs/zVUnHagk2Em4ju4k zZd05tk8+3QZop2NOHKjfrAz+iY3mwqI+QW4JJbIVhTGyaK/uQ+kt+M9xbVmiTFGTmHQ /jtWctCeYMTNttkxAjo8Qo0vqgltzhrPtlTGyz7NI4bW+rdqeEdQgw1zwlT5QO2MPZbc orOA== X-Gm-Message-State: AOAM530gZcaCZLFx8EFinor9E1DLogC7pziClMPf5FVX+hTqcit05Cxu CN42J/oIAb2WM97hX1ak3aKRWA== X-Google-Smtp-Source: ABdhPJxeVxIYWunZ0Q7rzXbRnDubJU2cx6qLTylTgDIb+MRFWKXgpEQNC/HuHomqN/perHrDk0gEbg== X-Received: by 2002:a05:6402:1c83:: with SMTP id cy3mr3478479edb.231.1627656576069; Fri, 30 Jul 2021 07:49:36 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id g3sm634964ejp.2.2021.07.30.07.49.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jul 2021 07:49:35 -0700 (PDT) From: Sam Protsenko To: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa Cc: Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 08/12] MAINTAINERS: Cover Samsung clock YAML bindings Date: Fri, 30 Jul 2021 17:49:18 +0300 Message-Id: <20210730144922.29111-9-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210730144922.29111-1-semen.protsenko@linaro.org> References: <20210730144922.29111-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org New device tree bindings are usually added in YAML format. Fix "SAMSUNG SOC CLOCK DRIVERS" entry to cover both txt and yaml docs for Exynos clock drivers. Signed-off-by: Sam Protsenko --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 056966c9aac9..4483ccb46883 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16404,7 +16404,7 @@ M: Chanwoo Choi L: linux-samsung-soc@vger.kernel.org S: Supported T: git git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git -F: Documentation/devicetree/bindings/clock/exynos*.txt +F: Documentation/devicetree/bindings/clock/exynos* F: Documentation/devicetree/bindings/clock/samsung,s3c* F: Documentation/devicetree/bindings/clock/samsung,s5p* F: drivers/clk/samsung/ From patchwork Fri Jul 30 14:49:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 489329 Delivered-To: patch@linaro.org Received: by 2002:a05:6638:1185:0:0:0:0 with SMTP id f5csp3222167jas; Fri, 30 Jul 2021 07:50:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwV3xdw8AWnBgnBYmw1MsynFAO3264fcRQA+r6ZoGfkj7MZF5QWOWoSCgEocn8WxaH7SSUp X-Received: by 2002:a6b:4015:: with SMTP id k21mr1872570ioa.28.1627656605118; Fri, 30 Jul 2021 07:50:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627656605; cv=none; d=google.com; s=arc-20160816; b=rvcWs8FxcH2ATiVTZs0xUhDOebEfsCW8A4zt54j4SuWkEByws2IfJX8Nx+z+sxaEEG mRExwjtDm61B899HvLg33OHucZiWtAMWuh8YWhduQw/S6Zzs8dlGTKv6QEPY9FV+xz+2 SRvUXch3ZMC5zvKVPjBrQX+YGsaJLdsiXxTdlMVoM9ErlrzkVJYAi/khkSJk+TlAlK8G 28fe8M1ikb9DwYlXNorNoNvxM4G4JZSM8uTF6YnQhRI/WRVbOF1GXj28MoNhkXcIqJRz ghrbPaWl6uOUAa4EucGaMc5qWww0L3KAh6T6NQlXbxw3Ryffw1bW6Mt0RB7C288sg7t3 /pzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZLLSVppmE/RVCbEA1xTEsZE8W6wm39t886R9xa0xNrY=; b=PXOR+7xFQ6viT1EOwOpRFhUGugnIcX8sUPiRKkd7BUqHD6c7byqUVUG+9u1TnbBKSE TNj5yTK4mUrAy7o2xVFwATviGntxtcV4xm+bBHmc2tM70pg5M+m23jtoYLtpE0PkyPXH r3iMN6jvvGR/Z2Rcd9Qygd0nwvlvs9pYr2MpjS1mSAQNmJcle2zO3Prx52QzPPS9fjsf mYYW7O33GxQZ9GO2a5KVJA2F4GYbjfYSmQrn4tJsJKOgEmwTVP/kuUXSOxF9wOQQEOiM gW2B9MQjXtoC1CdN6cI+jaoMsiSULS+IW8J7XzapFHH7y+m6na2BSgWDEMvgWabvKDvi iZFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hprBOmjD; spf=pass (google.com: domain of linux-serial-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-serial-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Constants are grouped per domain basis (CMU) for more convenient usage, but those are just unique numbers and have nothing to do with register offsets, etc. Signed-off-by: Sam Protsenko --- .../bindings/clock/exynos850-clock.yaml | 70 +++++ include/dt-bindings/clock/exynos850.h | 267 ++++++++++++++++++ 2 files changed, 337 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos850-clock.yaml create mode 100644 include/dt-bindings/clock/exynos850.h -- 2.30.2 diff --git a/Documentation/devicetree/bindings/clock/exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/exynos850-clock.yaml new file mode 100644 index 000000000000..201c2b79e629 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/exynos850-clock.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/exynos850-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock bindings for Samsung Exynos850 clock controller + +maintainers: + - Sam Protsenko + +description: | + The Exynos850 clock controller generates and supplies clock to various + controllers within the SoC. Each clock is assigned an identifier and client + nodes can use this identifier to specify the clock which they consume. + + All available clocks are defined as preprocessor macros in + dt-bindings/clock/exynos850.h header and can be used in device tree sources. + +properties: + compatible: + const: samsung,exynos850-clock + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + # Clock controller node + - | + clock: clock-controller@0x120e0000 { + compatible = "samsung,exynos850-clock"; + reg = <0x0 0x120e0000 0x8000>; + #clock-cells = <1>; + }; + + # Required external clocks (should be provided in particular board DTS) + - | + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos850-oscclk"; + clock-frequency = <26000000>; + }; + }; + + # UART controller node that consumes the clock generated by the clock + # controller + - | + #include + + serial_0: uart@13820000 { + compatible = "samsung,exynos850-uart"; + reg = <0x0 0x13820000 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + clocks = <&clock GATE_UART_QCH>, <&clock DOUT_UART>; + clock-names = "gate_uart_clk0", "uart"; + }; + +... diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h new file mode 100644 index 000000000000..b197db4427fc --- /dev/null +++ b/include/dt-bindings/clock/exynos850.h @@ -0,0 +1,267 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Device Tree binding constants for Exynos850 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_850_H +#define _DT_BINDINGS_CLOCK_EXYNOS_850_H + +#define NONE (0 + 0) +#define OSCCLK (0 + 1) + +#define CLK_APM_BASE (10) +#define UMUX_DLL_USER (CLK_APM_BASE + 0) +#define UMUX_CLK_APM_BUS (CLK_APM_BASE + 1) +#define GATE_APM_CMU_APM_QCH (CLK_APM_BASE + 2) +#define GATE_GREBEINTEGRATION_QCH_GREBE (CLK_APM_BASE + 3) +#define GATE_GREBEINTEGRATION_QCH_DBG (CLK_APM_BASE + 4) +#define GATE_I3C_APM_PMIC_QCH_S_I3C (CLK_APM_BASE + 5) +#define GATE_I3C_APM_PMIC_QCH (CLK_APM_BASE + 6) +#define GATE_INTMEM_QCH (CLK_APM_BASE + 7) +#define GATE_MAILBOX_APM_AP_QCH (CLK_APM_BASE + 8) +#define GATE_MAILBOX_APM_CHUB_QCH (CLK_APM_BASE + 9) +#define GATE_MAILBOX_APM_CP_QCH (CLK_APM_BASE + 10) +#define GATE_MAILBOX_APM_GNSS_QCH (CLK_APM_BASE + 11) +#define GATE_MAILBOX_APM_WLBT_QCH (CLK_APM_BASE + 12) +#define GATE_MAILBOX_AP_CHUB_QCH (CLK_APM_BASE + 13) +#define GATE_MAILBOX_AP_CP_QCH (CLK_APM_BASE + 14) +#define GATE_MAILBOX_AP_CP_S_QCH (CLK_APM_BASE + 15) +#define GATE_MAILBOX_AP_GNSS_QCH (CLK_APM_BASE + 16) +#define GATE_MAILBOX_AP_WLBT_QCH (CLK_APM_BASE + 17) +#define GATE_MAILBOX_CP_CHUB_QCH (CLK_APM_BASE + 18) +#define GATE_MAILBOX_CP_GNSS_QCH (CLK_APM_BASE + 19) +#define GATE_MAILBOX_CP_WLBT_QCH (CLK_APM_BASE + 20) +#define GATE_MAILBOX_GNSS_CHUB_QCH (CLK_APM_BASE + 21) +#define GATE_MAILBOX_GNSS_WLBT_QCH (CLK_APM_BASE + 22) +#define GATE_MAILBOX_WLBT_ABOX_QCH (CLK_APM_BASE + 23) +#define GATE_MAILBOX_WLBT_CHUB_QCH (CLK_APM_BASE + 24) +#define GATE_PMU_INTR_GEN_QCH (CLK_APM_BASE + 25) +#define GATE_ROM_CRC32_HOST_QCH (CLK_APM_BASE + 26) +#define GATE_SPEEDY_APM_QCH (CLK_APM_BASE + 27) +#define GATE_WDT_APM_QCH (CLK_APM_BASE + 28) + +#define CLK_AUD_BASE (50) +#define UMUX_CLK_AUD_CPU_HCH (CLK_AUD_BASE + 0) +#define GATE_ABOX_QCH_CPU (CLK_AUD_BASE + 1) +#define GATE_ABOX_QCH_ACLK (CLK_AUD_BASE + 2) +#define GATE_ABOX_QCH_BCLK0 (CLK_AUD_BASE + 3) +#define GATE_ABOX_QCH_BCLK1 (CLK_AUD_BASE + 4) +#define GATE_ABOX_QCH_FM (CLK_AUD_BASE + 5) +#define GATE_ABOX_QCH_BCLK2 (CLK_AUD_BASE + 6) +#define GATE_ABOX_QCH_CCLK_ASB (CLK_AUD_BASE + 7) +#define GATE_ABOX_QCH_BCLK3 (CLK_AUD_BASE + 8) +#define GATE_ABOX_QCH_BCLK4 (CLK_AUD_BASE + 9) +#define GATE_ABOX_QCH_BCLK5 (CLK_AUD_BASE + 10) +#define GATE_ABOX_QCH_BCLK6 (CLK_AUD_BASE + 11) +#define GATE_ABOX_QCH_BCLK_CNT (CLK_AUD_BASE + 12) +#define GATE_AUD_CMU_AUD_QCH (CLK_AUD_BASE + 13) +#define GATE_GPIO_AUD_QCH (CLK_AUD_BASE + 14) +#define GATE_SYSMMU_AUD_QCH_S1 (CLK_AUD_BASE + 15) +#define GATE_WDT_AUD_QCH (CLK_AUD_BASE + 16) +#define PLL_AUD_OUT (CLK_AUD_BASE + 17) +#define DOUT_CLK_AUD_CPU (CLK_AUD_BASE + 18) +#define DOUT_CLK_AUD_CPU_ACLK (CLK_AUD_BASE + 19) +#define DOUT_CLK_AUD_CPU_PCLKDBG (CLK_AUD_BASE + 20) +#define DOUT_CLK_AUD_BUSD (CLK_AUD_BASE + 21) +#define DOUT_CLK_AUD_UAIF0 (CLK_AUD_BASE + 23) +#define DOUT_CLK_AUD_UAIF1 (CLK_AUD_BASE + 24) +#define DOUT_CLK_AUD_FM (CLK_AUD_BASE + 25) +#define DOUT_CLK_AUD_BUSP (CLK_AUD_BASE + 26) +#define DOUT_CLK_AUD_UAIF2 (CLK_AUD_BASE + 27) +#define DOUT_CLK_AUD_CNT (CLK_AUD_BASE + 28) +#define DOUT_CLK_AUD_UAIF3 (CLK_AUD_BASE + 29) +#define DOUT_CLK_AUD_UAIF4 (CLK_AUD_BASE + 30) +#define DOUT_CLK_AUD_UAIF5 (CLK_AUD_BASE + 31) +#define DOUT_CLK_AUD_UAIF6 (CLK_AUD_BASE + 32) +#define DOUT_CLK_AUD_AUDIF (CLK_AUD_BASE + 33) +#define DOUT_CLK_AUD_MCLK (CLK_AUD_BASE + 34) +#define UMUX_CLK_AUD_FM (CLK_AUD_BASE + 35) + +#define CLK_CHUB_BASE (100) +#define GATE_BAAW_C_CHUB_QCH (CLK_CHUB_BASE + 0) +#define GATE_BAAW_D_CHUB_QCH (CLK_CHUB_BASE + 1) +#define GATE_CHUB_CMU_CHUB_QCH (CLK_CHUB_BASE + 2) +#define GATE_CM4_CHUB_QCH (CLK_CHUB_BASE + 3) +#define GATE_DMIC_AHB0_QCH (CLK_CHUB_BASE + 4) +#define GATE_DMIC_IF_QCH_PCLK (CLK_CHUB_BASE + 5) +#define GATE_DMIC_IF_QCH_DMIC_CLK (CLK_CHUB_BASE + 6) +#define GATE_HWACG_SYS_DMIC0_QCH (CLK_CHUB_BASE + 7) +#define GATE_PWM_CHUB_QCH (CLK_CHUB_BASE + 8) +#define GATE_SWEEPER_C_CHUB_QCH (CLK_CHUB_BASE + 9) +#define GATE_SWEEPER_D_CHUB_QCH (CLK_CHUB_BASE + 10) +#define GATE_TIMER_CHUB_QCH (CLK_CHUB_BASE + 11) +#define GATE_WDT_CHUB_QCH (CLK_CHUB_BASE + 12) +#define GATE_U_DMIC_CLK_SCAN_MUX_QCH (CLK_CHUB_BASE + 13) +#define DOUT_CLK_CHUB_BUS (CLK_CHUB_BASE + 14) +#define DOUT_CLK_CHUB_DMIC_IF (CLK_CHUB_BASE + 15) +#define DOUT_CLK_CHUB_DMIC_IF_DIV2 (CLK_CHUB_BASE + 16) +#define DOUT_CLK_CHUB_DMIC (CLK_CHUB_BASE + 17) + +#define CLK_CMGP_BASE (150) +#define UMUX_CLK_CMGP_USI_CMGP0 (CLK_CMGP_BASE + 0) +#define UMUX_CLK_CMGP_USI_CMGP1 (CLK_CMGP_BASE + 1) +#define GATE_ADC_CMGP_QCH_S0 (CLK_CMGP_BASE + 2) +#define GATE_ADC_CMGP_QCH_S1 (CLK_CMGP_BASE + 3) +#define GATE_ADC_CMGP_QCH_ADC (CLK_CMGP_BASE + 4) +#define GATE_CMGP_CMU_CMGP_QCH (CLK_CMGP_BASE + 5) +#define GATE_GPIO_CMGP_QCH (CLK_CMGP_BASE + 6) +#define GATE_USI_CMGP0_QCH (CLK_CMGP_BASE + 7) +#define GATE_USI_CMGP1_QCH (CLK_CMGP_BASE + 8) +#define DOUT_CLK_CMGP_ADC (CLK_CMGP_BASE + 9) +#define DOUT_CLK_CMGP_USI_CMGP0 (CLK_CMGP_BASE + 10) +#define DOUT_CLK_CMGP_USI_CMGP1 (CLK_CMGP_BASE + 11) + +#define CLK_TOP_BASE (200) +#define GATE_CMU_TOP_CMUREF_QCH (CLK_TOP_BASE + 0) +#define GATE_DFTMUX_CMU_QCH_CLK_CIS0 (CLK_TOP_BASE + 1) +#define GATE_DFTMUX_CMU_QCH_CLK_CIS1 (CLK_TOP_BASE + 2) +#define GATE_DFTMUX_CMU_QCH_CLK_CIS2 (CLK_TOP_BASE + 3) +#define GATE_OTP_QCH (CLK_TOP_BASE + 4) +#define GATE_ADM_AHB_SSS_QCH (CLK_TOP_BASE + 5) +#define GATE_BAAW_P_CHUB_QCH (CLK_TOP_BASE + 6) +#define GATE_BAAW_P_GNSS_QCH (CLK_TOP_BASE + 7) +#define GATE_BAAW_P_MODEM_QCH (CLK_TOP_BASE + 8) +#define GATE_BAAW_P_WLBT_QCH (CLK_TOP_BASE + 9) + +#define CLK_CORE_BASE (250) +#define GATE_CCI_550_QCH (CLK_CORE_BASE + 0) +#define GATE_CORE_CMU_CORE_QCH (CLK_CORE_BASE + 1) +#define GATE_GIC_QCH (CLK_CORE_BASE + 2) +#define GATE_GPIO_CORE_QCH (CLK_CORE_BASE + 3) +#define GATE_MMC_EMBD_QCH (CLK_CORE_BASE + 4) +#define GATE_PDMA_CORE_QCH (CLK_CORE_BASE + 5) +#define GATE_RTIC_QCH (CLK_CORE_BASE + 6) +#define GATE_SPDMA_CORE_QCH (CLK_CORE_BASE + 7) +#define GATE_SSS_QCH (CLK_CORE_BASE + 8) +#define GATE_TREX_D_CORE_QCH (CLK_CORE_BASE + 9) +#define GATE_TREX_P_CORE_QCH (CLK_CORE_BASE + 10) +#define GATE_CSSYS_DBG_QCH (CLK_CORE_BASE + 11) +#define GATE_SECJTAG_QCH (CLK_CORE_BASE + 12) +#define DOUT_CORE_MMC_EMBD (CLK_CORE_BASE + 13) + +#define CLK_DPU_BASE (300) +#define GATE_DPU_QCH_S_DPP (CLK_DPU_BASE + 0) +#define GATE_DPU_QCH_S_DMA (CLK_DPU_BASE + 1) +#define GATE_DPU_QCH_S_DECON (CLK_DPU_BASE + 2) +#define GATE_DPU_CMU_DPU_QCH (CLK_DPU_BASE + 3) +#define GATE_SMMU_DPU_QCH (CLK_DPU_BASE + 4) +#define DOUT_CLK_DPU_BUSP (CLK_DPU_BASE + 5) + +#define CLK_G3D_BASE (350) +#define GATE_G3D_CMU_G3D_QCH (CLK_G3D_BASE + 0) +#define GATE_GPU_QCH (CLK_G3D_BASE + 1) +#define DOUT_CLK_G3D_BUSP (CLK_G3D_BASE + 2) + +#define CLK_HIS_BASE (400) +#define GATE_GPIO_HSI_QCH (CLK_HIS_BASE + 0) +#define GATE_HSI_CMU_HSI_QCH (CLK_HIS_BASE + 1) +#define GATE_MMC_CARD_QCH (CLK_HIS_BASE + 2) +#define GATE_USB20DRD_TOP_QCH_LINK (CLK_HIS_BASE + 3) +#define GATE_USB20DRD_TOP_QCH_20CTRL (CLK_HIS_BASE + 4) +#define GATE_USB20DRD_TOP_QCH_REFCLK (CLK_HIS_BASE + 5) +#define GATE_USB20DRD_TOP_QCH_RTC (CLK_HIS_BASE + 6) +#define PLL_MMC_OUT (CLK_HIS_BASE + 7) +#define HSI_BUS (CLK_HIS_BASE + 8) +#define HSI_MMC_CARD (CLK_HIS_BASE + 9) +#define HSI_USB20DRD (CLK_HIS_BASE + 10) + +#define CLK_IS_BASE (450) +#define GATE_CSIS0_QCH (CLK_IS_BASE + 0) +#define GATE_CSIS1_QCH (CLK_IS_BASE + 1) +#define GATE_CSIS2_QCH (CLK_IS_BASE + 2) +#define GATE_IS_CMU_IS_QCH (CLK_IS_BASE + 3) +#define GATE_IS_TOP_QCH_S_00 (CLK_IS_BASE + 4) +#define GATE_IS_TOP_QCH_S_02 (CLK_IS_BASE + 5) +#define GATE_IS_TOP_QCH_S_03 (CLK_IS_BASE + 6) +#define GATE_IS_TOP_QCH_S_04 (CLK_IS_BASE + 7) +#define GATE_IS_TOP_QCH_S_05 (CLK_IS_BASE + 8) +#define GATE_IS_TOP_QCH_S_06 (CLK_IS_BASE + 9) +#define GATE_SYSMMU_IS0_QCH (CLK_IS_BASE + 10) +#define GATE_SYSMMU_IS1_QCH (CLK_IS_BASE + 11) +#define IS_BUS (CLK_IS_BASE + 12) +#define IS_VRA (CLK_IS_BASE + 13) +#define IS_ITP (CLK_IS_BASE + 14) +#define IS_GDC (CLK_IS_BASE + 15) +#define UMUX_CLK_IS_BUS (CLK_IS_BASE + 15) +#define UMUX_CLK_IS_ITP (CLK_IS_BASE + 16) +#define UMUX_CLK_IS_VRA (CLK_IS_BASE + 17) +#define UMUX_CLK_IS_GDC (CLK_IS_BASE + 18) +#define GATE_CLK_ITP (CLK_IS_BASE + 19) +#define GATE_CLK_VRA (CLK_IS_BASE + 20) +#define GATE_CLK_GDC (CLK_IS_BASE + 21) +#define CIS_CLK0 (CLK_IS_BASE + 22) +#define CIS_CLK1 (CLK_IS_BASE + 23) +#define CIS_CLK2 (CLK_IS_BASE + 24) + +#define CLK_MFCMSCL_BASE (500) +#define GATE_JPEG_QCH (CLK_MFCMSCL_BASE + 0) +#define GATE_M2M_QCH (CLK_MFCMSCL_BASE + 1) +#define GATE_MCSC_QCH (CLK_MFCMSCL_BASE + 2) +#define GATE_MFC_QCH (CLK_MFCMSCL_BASE + 3) +#define GATE_MFCMSCL_CMU_MFCMSCL_QCH (CLK_MFCMSCL_BASE + 4) +#define GATE_SYSMMU_MFCMSCL_QCH (CLK_MFCMSCL_BASE + 5) +#define GATE_CMU_MIF_CMUREF_QCH (CLK_MFCMSCL_BASE + 6) +#define GATE_DMC_QCH (CLK_MFCMSCL_BASE + 7) +#define GATE_MIF_CMU_MIF_QCH (CLK_MFCMSCL_BASE + 8) +#define GATE_CMU_MIF1_CMU_REF_QCH (CLK_MFCMSCL_BASE + 9) +#define GATE_DMC1_QCH (CLK_MFCMSCL_BASE + 10) +#define GATE_MIF1_CMU_MIF1_QCH (CLK_MFCMSCL_BASE + 11) +#define GATE_MODEM_CMU_MODEM_QCH (CLK_MFCMSCL_BASE + 12) +#define DOUT_CLK_MFCMSCL_BUSP (CLK_MFCMSCL_BASE + 13) +#define MFCMSCL_MFC (CLK_MFCMSCL_BASE + 14) +#define MFCMSCL_M2M (CLK_MFCMSCL_BASE + 15) +#define MFCMSCL_MCSC (CLK_MFCMSCL_BASE + 16) +#define MFCMSCL_JPEG (CLK_MFCMSCL_BASE + 17) +#define UMUX_CLKCMU_MFCMSCL_MFC (CLK_MFCMSCL_BASE + 18) +#define UMUX_CLKCMU_MFCMSCL_M2M (CLK_MFCMSCL_BASE + 19) +#define UMUX_CLKCMU_MFCMSCL_MCSC (CLK_MFCMSCL_BASE + 20) +#define UMUX_CLKCMU_MFCMSCL_JPEG (CLK_MFCMSCL_BASE + 21) + +#define CLK_PERI_BASE (550) +#define UMUX_CLKCMU_PERI_BUS_USER (CLK_PERI_BASE + 0) +#define UMUX_CLKCMU_PERI_UART_USER (CLK_PERI_BASE + 1) +#define UMUX_CLKCMU_PERI_HSI2C_USER (CLK_PERI_BASE + 2) +#define UMUX_CLKCMU_PERI_SPI_USER (CLK_PERI_BASE + 3) +#define GATE_BUSIF_TMU_QCH (CLK_PERI_BASE + 4) +#define GATE_GPIO_PERI_QCH (CLK_PERI_BASE + 5) +#define GATE_HSI2C_0_QCH (CLK_PERI_BASE + 6) +#define GATE_HSI2C_1_QCH (CLK_PERI_BASE + 7) +#define GATE_HSI2C_2_QCH (CLK_PERI_BASE + 8) +#define GATE_I2C_0_QCH (CLK_PERI_BASE + 9) +#define GATE_I2C_1_QCH (CLK_PERI_BASE + 10) +#define GATE_I2C_2_QCH (CLK_PERI_BASE + 11) +#define GATE_I2C_3_QCH (CLK_PERI_BASE + 12) +#define GATE_I2C_4_QCH (CLK_PERI_BASE + 13) +#define GATE_I2C_5_QCH (CLK_PERI_BASE + 14) +#define GATE_I2C_6_QCH (CLK_PERI_BASE + 15) +#define GATE_MCT_QCH (CLK_PERI_BASE + 16) +#define GATE_OTP_CON_TOP_QCH (CLK_PERI_BASE + 17) +#define GATE_PWM_MOTOR_QCH (CLK_PERI_BASE + 18) +#define GATE_SPI_0_QCH (CLK_PERI_BASE + 19) +#define GATE_UART_QCH (CLK_PERI_BASE + 20) +#define GATE_WDT_0_QCH (CLK_PERI_BASE + 21) +#define GATE_WDT_1_QCH (CLK_PERI_BASE + 22) +#define DOUT_CLK_PERI_SPI_0 (CLK_PERI_BASE + 23) +#define DOUT_CLK_PERI_HSI2C_0 (CLK_PERI_BASE + 24) +#define DOUT_CLK_PERI_HSI2C_1 (CLK_PERI_BASE + 25) +#define DOUT_CLK_PERI_HSI2C_2 (CLK_PERI_BASE + 26) +#define DOUT_I2C_0 (CLK_PERI_BASE + 27) +#define DOUT_I2C_1 (CLK_PERI_BASE + 28) +#define DOUT_I2C_2 (CLK_PERI_BASE + 29) +#define DOUT_I2C_3 (CLK_PERI_BASE + 30) +#define DOUT_I2C_4 (CLK_PERI_BASE + 31) +#define DOUT_I2C_5 (CLK_PERI_BASE + 32) +#define DOUT_I2C_6 (CLK_PERI_BASE + 33) +#define DOUT_UART (CLK_PERI_BASE + 34) + +#define CLK_CLKOUT_BASE (700) +#define OSC_NFC (CLK_CLKOUT_BASE + 0) +#define OSC_AUD (CLK_CLKOUT_BASE + 1) + +/* Must be greater than maximal clock ID */ +#define CLK_NR_CLKS (1125 + 1) + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_850_H */ From patchwork Fri Jul 30 14:49:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 490032 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55E99C19F35 for ; Fri, 30 Jul 2021 14:50:10 +0000 (UTC) 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linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 10/12] clk: samsung: Add Exynos850 clock driver stub Date: Fri, 30 Jul 2021 17:49:20 +0300 Message-Id: <20210730144922.29111-11-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210730144922.29111-1-semen.protsenko@linaro.org> References: <20210730144922.29111-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org For now it's just a stub driver to make serial driver work. Later it will be implemented properly. This driver doesn't really change clocks, only registers the UART clock as a fixed-rate clock. Without this clock driver the UART driver won't work, as it's trying to obtain "uart" clock and fails if it's not able to. From drivers/tty/serial/samsung_tty.c: 8<------------------------------------------------------------------->8 ourport->clk = clk_get(&platdev->dev, "uart"); if (IS_ERR(ourport->clk)) { pr_err("%s: Controller clock not found\n", dev_name(&platdev->dev)); ret = PTR_ERR(ourport->clk); goto err; } 8<------------------------------------------------------------------->8 In order to get functional serial console we have to implement that minimal clock driver with "uart" clock. It's not necessary to actually configure clocks, as those are already configured in bootloader, so kernel can rely on that for now. 80 column limit is broken here to make checkpatch happy, otherwise it swears about incorrect __initconst usage. Signed-off-by: Sam Protsenko --- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos850.c | 63 +++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+) create mode 100644 drivers/clk/samsung/clk-exynos850.c diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 028b2e27a37e..c46cf11e4d0b 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c new file mode 100644 index 000000000000..3192ec9bb90b --- /dev/null +++ b/drivers/clk/samsung/clk-exynos850.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Common Clock Framework support for Exynos850 SoC. + */ + +#include +#include +#include +#include +#include +#include + +#include "clk.h" + +/* Fixed rate clocks generated outside the SoC */ +static struct samsung_fixed_rate_clock exynos850_fixed_rate_ext_clks[] __initdata = { + FRATE(OSCCLK, "fin_pll", NULL, 0, 26000000), +}; + +/* + * Model the UART clock as a fixed-rate clock for now, to make serial driver + * work. This clock is already configured in the bootloader. + */ +static const struct samsung_fixed_rate_clock exynos850_peri_clks[] __initconst = { + FRATE(DOUT_UART, "DOUT_UART", NULL, 0, 200000000), +}; + +static const struct of_device_id ext_clk_match[] __initconst = { + { .compatible = "samsung,exynos850-oscclk", .data = (void *)0 }, + {}, +}; + +void __init exynos850_clk_init(struct device_node *np) +{ + void __iomem *reg_base; + struct samsung_clk_provider *ctx; + + if (!np) + panic("%s: unable to determine soc\n", __func__); + + reg_base = of_iomap(np, 0); + if (!reg_base) + panic("%s: failed to map registers\n", __func__); + + ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS); + if (!ctx) + panic("%s: unable to allocate ctx\n", __func__); + + samsung_clk_of_register_fixed_ext(ctx, + exynos850_fixed_rate_ext_clks, + ARRAY_SIZE(exynos850_fixed_rate_ext_clks), + ext_clk_match); + + samsung_clk_register_fixed_rate(ctx, exynos850_peri_clks, + ARRAY_SIZE(exynos850_peri_clks)); + + samsung_clk_of_add_provider(np, ctx); +} + +CLK_OF_DECLARE(exynos850_clk, "samsung,exynos850-clock", exynos850_clk_init); From patchwork Fri Jul 30 14:49:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 489644 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UPPERCASE_50_75, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2279CC432BE for ; Fri, 30 Jul 2021 14:50:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 04BFA60C3F for ; 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Fri, 30 Jul 2021 07:49:40 -0700 (PDT) From: Sam Protsenko To: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa Cc: Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 11/12] dt-bindings: interrupt-controller: Add IRQ constants for Exynos850 Date: Fri, 30 Jul 2021 17:49:21 +0300 Message-Id: <20210730144922.29111-12-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210730144922.29111-1-semen.protsenko@linaro.org> References: <20210730144922.29111-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add external GIC interrupt constants for SPI[479:0] for Exynos850 SoC. Interrupt names were taken from TRM without change, hence double underscore in const namings. Only level-sensitive interrupt is allowed for each SPI, so each SPI should be configured as level-sensitive in GIC. Also update MAINTAINERS file, so that Exynos interrupt binding headers are covered in "ARM/SAMSUNG S3C, S5P AND EXYNOS ARM ARCHITECTURES" section. Signed-off-by: Sam Protsenko --- MAINTAINERS | 1 + .../interrupt-controller/exynos850.h | 290 ++++++++++++++++++ 2 files changed, 291 insertions(+) create mode 100644 include/dt-bindings/interrupt-controller/exynos850.h diff --git a/MAINTAINERS b/MAINTAINERS index 4483ccb46883..ceb929e6bfa7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2488,6 +2488,7 @@ F: drivers/pwm/pwm-samsung.c F: drivers/soc/samsung/ F: drivers/tty/serial/samsung* F: include/clocksource/samsung_pwm.h +F: include/dt-bindings/interrupt-controller/exynos*.h F: include/linux/platform_data/*s3c* F: include/linux/serial_s3c.h F: include/linux/soc/samsung/ diff --git a/include/dt-bindings/interrupt-controller/exynos850.h b/include/dt-bindings/interrupt-controller/exynos850.h new file mode 100644 index 000000000000..0c24ba2e27da --- /dev/null +++ b/include/dt-bindings/interrupt-controller/exynos850.h @@ -0,0 +1,290 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2017 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Device Tree binding constants for Exynos850 interrupt controller. + */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_EXYNOS_850_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_EXYNOS_850_H + +#include + +#define INTREQ__ADC_CMGP2AP 0 +#define INTREQ__ALIVE_EINT0 1 +#define INTREQ__ALIVE_EINT1 2 +#define INTREQ__ALIVE_EINT2 3 +#define INTREQ__ALIVE_EINT3 4 +#define INTREQ__ALIVE_EINT4 5 +#define INTREQ__ALIVE_EINT5 6 +#define INTREQ__ALIVE_EINT6 7 +#define INTREQ__ALIVE_EINT7 8 +#define INTREQ__ALIVE_EINT8 9 +#define INTREQ__ALIVE_EINT9 10 +#define INTREQ__ALIVE_EINT10 11 +#define INTREQ__ALIVE_EINT11 12 +#define INTREQ__ALIVE_EINT12 13 +#define INTREQ__ALIVE_EINT13 14 +#define INTREQ__ALIVE_EINT14 15 +#define INTREQ__ALIVE_EINT15 16 +#define INTREQ__ALIVE_EINT16 17 +#define INTREQ__ALIVE_EINT17 18 +#define INTREQ__ALIVE_EINT18 19 +#define INTREQ__ALIVE_EINT19 20 +#define INTREQ__ALIVE_EINT20 21 +#define INTREQ__ALIVE_EINT21 22 +#define INTREQ__ALIVE_EINT22 23 +#define INTREQ__ALIVE_EINT23 24 +#define INTREQ__ALIVE_EINT24 25 +#define INTREQ__ALIVE_EINT25 26 +#define INTREQ__ALIVE_EINT26 27 +#define INTREQ__ALIVE_EINT27 28 +#define INTREQ__ALIVE_EINT28 29 +#define INTREQ__ALIVE_EINT29 30 +#define INTREQ__ALIVE_EINT30 31 +#define INTREQ__ALIVE_EINT31 32 +#define INTREQ__ALIVE_EINT32 33 +#define INTREQ__ALIVE_EINT33 34 +#define INTREQ__ALIVE_EINT34 35 +#define INTREQ__ALIVE_EINT35 36 +#define INTREQ__ALIVE_GNSS_ACTIVE 37 +#define INTREQ__ALIVE_WLBT_ACTIVE 38 +#define INTREQ__CMGP_EXT_INTM00 39 +#define INTREQ__CMGP_EXT_INTM01 40 +#define INTREQ__CMGP_EXT_INTM02 41 +#define INTREQ__CMGP_EXT_INTM03 42 +#define INTREQ__CMGP_EXT_INTM04 43 +#define INTREQ__CMGP_EXT_INTM05 44 +#define INTREQ__CMGP_EXT_INTM06 45 +#define INTREQ__CMGP_EXT_INTM07 46 +#define INTREQ__COMB_SFI_CE_NONSECURE_SYSREG_APM 47 +#define INTREQ__COMB_SFI_UCE_NONSECURE_SYSREG_APM 48 +#define INTREQ__MAILBOX_APM2AP 49 +#define INTREQ__MAILBOX_CHUB2AP 50 +#define INTREQ__MAILBOX_CP2AP 51 +#define INTREQ__MAILBOX_CP2AP_S 52 +#define INTREQ__MAILBOX_GNSS2AP 53 +#define INTREQ__MAILBOX_WLBT2AP 54 +#define INTREQ__NOTIFY 55 +#define INTREQ__PMIC 56 +#define INTREQ__RTC_ALARM_INT 57 +#define INTREQ__RTC_TIC_INT_0 58 +#define INTREQ__SPEEDY_APM 59 +#define INTREQ__TOP_RTC_ALARM_INT 60 +#define INTREQ__TOP_RTC_TIC_INT_0 61 +#define INTREQ__USI_CMGP0 62 +#define INTREQ__USI_CMGP1 63 +#define INTREQ__AUD_ABOX_GIC400_MCPU 64 +#define INTREQ__AUD_WDT 65 +#define INTREQ__SYSMMU_ABOX_S1_NS 66 +#define INTREQ__SYSMMU_ABOX_S1_S 67 +#define INTREQ__PWM_CHUB_0 68 +#define INTREQ__PWM_CHUB_1 69 +#define INTREQ__PWM_CHUB_2 70 +#define INTREQ__PWM_CHUB_3 71 +#define INTREQ__TIMER_CHUB 72 +#define INTREQ__WDT_CHUB 73 +#define INTREQ__CPUCL0_CLUSTERPMUIRQ 74 +#define INTREQ__CPUCL0_COMMIRQ_0 75 +#define INTREQ__CPUCL0_COMMIRQ_1 76 +#define INTREQ__CPUCL0_COMMIRQ_2 77 +#define INTREQ__CPUCL0_COMMIRQ_3 78 +#define INTREQ__CPUCL0_ERRIRQ_0 79 +#define INTREQ__CPUCL0_ERRIRQ_1 80 +#define INTREQ__CPUCL0_ERRIRQ_2 81 +#define INTREQ__CPUCL0_ERRIRQ_3 82 +#define INTREQ__CPUCL0_ERRIRQ_4 83 +#define INTREQ__CPUCL0_FAULTIRQ_0 84 +#define INTREQ__CPUCL0_FAULTIRQ_1 85 +#define INTREQ__CPUCL0_FAULTIRQ_2 86 +#define INTREQ__CPUCL0_FAULTIRQ_3 87 +#define INTREQ__CPUCL0_FAULTIRQ_4 88 +#define INTREQ__CPUCL0_PMUIRQ_0 89 +#define INTREQ__CPUCL0_PMUIRQ_1 90 +#define INTREQ__CPUCL0_PMUIRQ_2 91 +#define INTREQ__CPUCL0_PMUIRQ_3 92 +#define INTREQ__CPUCL1_CLUSTERPMUIRQ 93 +#define INTREQ__CPUCL1_COMMIRQ_0 94 +#define INTREQ__CPUCL1_COMMIRQ_1 95 +#define INTREQ__CPUCL1_COMMIRQ_2 96 +#define INTREQ__CPUCL1_COMMIRQ_3 97 +#define INTREQ__CPUCL1_ERRIRQ_0 98 +#define INTREQ__CPUCL1_ERRIRQ_1 99 +#define INTREQ__CPUCL1_ERRIRQ_2 100 +#define INTREQ__CPUCL1_ERRIRQ_3 101 +#define INTREQ__CPUCL1_ERRIRQ_4 102 +#define INTREQ__CPUCL1_FAULTIRQ_0 103 +#define INTREQ__CPUCL1_FAULTIRQ_1 104 +#define INTREQ__CPUCL1_FAULTIRQ_2 105 +#define INTREQ__CPUCL1_FAULTIRQ_3 106 +#define INTREQ__CPUCL1_FAULTIRQ_4 107 +#define INTREQ__CPUCL1_PMUIRQ_0 108 +#define INTREQ__CPUCL1_PMUIRQ_1 109 +#define INTREQ__CPUCL1_PMUIRQ_2 110 +#define INTREQ__CPUCL1_PMUIRQ_3 111 +#define INTREQ__DECON0_EXTRA 112 +#define INTREQ__DECON0_FRAME_DONE 113 +#define INTREQ__DECON0_FRAME_START 114 +#define INTREQ__DECON0_UNDER_FLOW 115 +#define INTREQ__DPP_VG0 116 +#define INTREQ__DPU_DMA_G0 117 +#define INTREQ__DPU_DMA_G1 118 +#define INTREQ__DPU_DMA_GF 119 +#define INTREQ__DPU_DMA_VG0 120 +#define INTREQ__DSIM0 121 +#define INTREQ__SMMU_DPU_NS 122 +#define INTREQ__SMMU_DPU_S 123 +#define INTREQ__G3D_IRQEVENT 124 +#define INTREQ__G3D_IRQGPU 125 +#define INTREQ__G3D_IRQJOB 126 +#define INTREQ__G3D_IRQMMU 127 +#define INTREQ__GNSS_SW_INT 128 +#define INTREQ__GNSS_WAKEUP_INT 129 +#define INTREQ__GNSS_WDOG_RESET 130 +#define INTREQ__GPIO_HSI 131 +#define INTREQ__MMC_CARD 132 +#define INTREQ__PPMU_HSI_UPPER 133 +#define INTREQ__USB2_REMOTE_CONNECT 134 +#define INTREQ__USB2_REMOTE_TIMER 135 +#define INTREQ__USB2_REMOTE_WAKEUP 136 +#define INTREQ__USB20DRD_0 137 +#define INTREQ__USB20DRD_1 138 +#define INTREQ__USB20_PHY_FSVMINUS 139 +#define INTREQ__USB20_PHY_FSVPLUS 140 +#define INTREQ__CSIS0 141 +#define INTREQ__CSIS1 142 +#define INTREQ__CSIS2 143 +#define INTREQ__CSIS_DMA_0 144 +#define INTREQ__CSIS_DMA_1 145 +#define INTREQ__GDC 146 +#define INTREQ__IPP0_0 147 +#define INTREQ__CPUCL0_CTIIRQ_0 148 +#define INTREQ__CPUCL0_CTIIRQ_1 149 +#define INTREQ__CPUCL0_CTIIRQ_2 150 +#define INTREQ__CPUCL0_CTIIRQ_3 151 +#define INTREQ__CPUCL1_CTIIRQ_0 152 +#define INTREQ__CPUCL1_CTIIRQ_1 153 +#define INTREQ__CPUCL1_CTIIRQ_2 154 +#define INTREQ__CPUCL1_CTIIRQ_3 155 +#define INTREQ__IPP0_1 156 +#define INTREQ__IPP1_0 157 +#define INTREQ__IPP1_1 158 +#define INTREQ__ITP_0 159 +#define INTREQ__ITP_1 160 +#define INTREQ__MCSC_IS 161 +#define INTREQ__PPMU_IS0_UPPER_OR_NORMAL 162 +#define INTREQ__PPMU_IS1_UPPER_OR_NORMAL 163 +#define INTREQ__SYSMMU_IS0_S1_NS 164 +#define INTREQ__SYSMMU_IS0_S1_S 165 +#define INTREQ__SYSMMU_IS1_S1_NS 166 +#define INTREQ__SYSMMU_IS1_S1_S 167 +#define INTREQ__VRA 168 +#define INTREQ__JPEG 169 +#define INTREQ__M2M 170 +#define INTREQ__MCSC_MFC 171 +#define INTREQ__MFC 172 +#define INTREQ__PPMU_MFCMSCL_interrupt_upper_or_normal 173 +#define INTREQ__SYSMMU_MFCMSCL_S1_NS 174 +#define INTREQ__SYSMMU_MFCMSCL_S1_S 175 +#define INTREQ__DERATE_INTR_MIF0 176 +#define INTREQ__DMC_INTR_MIF0 177 +#define INTREQ__DMC_PEREV_INTR_MIF0 178 +#define INTREQ__HIGHTEMP_INTR_MIF0 179 +#define INTREQ__NORMTEMP_INTR_MIF0 180 +#define INTREQ__PPMU_UPPER_OR_NORMAL_MIF0 181 +#define INTREQ__TEMPERR_INTR_MIF0 182 +#define INTREQ__DERATE_INTR_MIF1 183 +#define INTREQ__DMC_INTR_MIF1 184 +#define INTREQ__DMC_PEREV_INTR_MIF1 185 +#define INTREQ__HIGHTEMP_INTR_MIF1 186 +#define INTREQ__NORMTEMP_INTR_MIF1 187 +#define INTREQ__PPMU_UPPER_OR_NORMAL_MIF1 188 +#define INTREQ__TEMPERR_INTR_MIF1 189 +#define INTREQ__RESET_REQ 190 +#define INTREQ__SFR_BUS_RDY 191 +#define INTREQ__GPIO_PERI 192 +#define INTREQ__HSI2C_0 193 +#define INTREQ__HSI2C_1 194 +#define INTREQ__HSI2C_2 195 +#define INTREQ__I2C_0 196 +#define INTREQ__I2C_1 197 +#define INTREQ__I2C_2 198 +#define INTREQ__I2C_3 199 +#define INTREQ__I2C_4 200 +#define INTREQ__I2C_5 201 +#define INTREQ__I2C_6 202 +#define INTREQ__MCT_G0 203 +#define INTREQ__MCT_G1 204 +#define INTREQ__MCT_G2 205 +#define INTREQ__MCT_G3 206 +#define INTREQ__MCT_L0 207 +#define INTREQ__MCT_L1 208 +#define INTREQ__MCT_L2 209 +#define INTREQ__MCT_L3 210 +#define INTREQ__MCT_L4 211 +#define INTREQ__MCT_L5 212 +#define INTREQ__MCT_L6 213 +#define INTREQ__MCT_L7 214 +#define INTREQ__OTP_CON 215 +#define INTREQ__PWM0 216 +#define INTREQ__PWM1 217 +#define INTREQ__PWM2 218 +#define INTREQ__PWM3 219 +#define INTREQ__PWM4 220 +#define INTREQ__SPI_0 221 + +#define INTREQ__SECURE_LOG 224 +#define INTREQ__TBASE 223 +#define INTREQ__RPMB 225 + +#define INTREQ__TMU 226 +#define INTREQ__UART 227 +#define INTREQ__WDT_0 228 +#define INTREQ__WDT_1 229 +#define INTREQ__WB2AP_CFG_REQ 230 +#define INTREQ__WB2AP_WDOG_RESET_REQ_IRQ 231 +#define INTREQ__CCI_NEVNTCNTOVERFLOW_7 438 +#define INTREQ__CCI_NEVNTCNTOVERFLOW_6 439 +#define INTREQ__CCI_NEVNTCNTOVERFLOW_5 440 +#define INTREQ__CCI_NEVNTCNTOVERFLOW_4 441 +#define INTREQ__CCI_NEVNTCNTOVERFLOW_3 442 +#define INTREQ__CCI_NEVNTCNTOVERFLOW_2 443 +#define INTREQ__CCI_NEVNTCNTOVERFLOW_1 444 +#define INTREQ__CCI_NEVNTCNTOVERFLOW_0 445 +#define INTREQ__CCI_NERR 446 +#define INTREQ__PPMU_ACE_CPUCL1_LOW 447 +#define INTREQ__PPMU_ACE_CPUCL1_UPN 448 +#define INTREQ__PPMU_ACE_CPUCL0_LOW 449 +#define INTREQ__PPMU_ACE_CPUCL0_UPN 450 +#define INTREQ__GPIO_CORE 451 +#define INTREQ__MMC_EMBD_CORE 452 +#define INTREQ__RTIC 453 +#define INTREQ__SSS_WDT2 454 +#define INTREQ__SSS_WDT1 455 +#define INTREQ__SSS_KM 456 +#define INTREQ__SSS_MAILBOX 457 +#define INTREQ__SSS 458 +#define INTREQ__TREX_P_CORE_PPMU_M_PERI 459 +#define INTREQ__TREX_P_CORE_PPMU_M_CPU 460 +#define INTREQ__TREX_P_CORE_DEBUG_INT 461 +#define INTREQ__TREX_D_CORE_DEBUG_INT 462 +#define INTREQ__TREX_D_CORE_PPMU_S_PERI 463 +#define INTREQ__TREX_D_CORE_PPMU_NRT_MEM1 464 +#define INTREQ__TREX_D_CORE_PPMU_NRT_MEM0 465 +#define INTREQ__TREX_D_CORE_PPMU_RT_MEM1 466 +#define INTREQ__TREX_D_CORE_PPMU_RT_MEM0 467 +#define INTREQ__TREX_D_CORE_PPMU_CP_MEM1 468 +#define INTREQ__TREX_D_CORE_PPMU_CP_MEM0 469 +#define INTREQ__TREX_D_CORE_PPMU_WLBT 470 +#define INTREQ__TREX_D_CORE_PPMU_MODEM1 471 +#define INTREQ__TREX_D_CORE_PPMU_MODEM0 472 +#define INTREQ__TREX_D_CORE_PPMU_GNSS 473 +#define INTREQ__TREX_D_CORE_PPMU_G3D 474 +#define INTREQ__TREX_D_CORE_PPMU_COREX 475 +#define INTREQ__TREX_D_CORE_PPMU_CHUB 476 +#define INTREQ__TREX_D_CORE_PPMU_APM 477 +#define INTREQ__SPDMA0 478 +#define INTREQ__PDMA0 479 + +#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_EXYNOS_850_H */ From patchwork Fri Jul 30 14:49:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit 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-0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id f16sm766283edt.57.2021.07.30.07.49.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jul 2021 07:49:41 -0700 (PDT) From: Sam Protsenko To: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa Cc: Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org Subject: [PATCH 12/12] arm64: dts: exynos: Add Exynos850 SoC support Date: Fri, 30 Jul 2021 17:49:22 +0300 Message-Id: <20210730144922.29111-13-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210730144922.29111-1-semen.protsenko@linaro.org> References: <20210730144922.29111-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Samsung Exynos850 is ARMv8-based mobile-oriented SoC. Features: * CPU: Cortex-A55 Octa (8 cores), up to 2 GHz * Memory interface: LPDDR4/4x 2 channels (12.8 GB/s) * SD/MMC: SD 3.0, eMMC5.1 DDR 8-bit * Modem: 4G LTE, 3G, GSM/GPRS/EDGE * RF: Quad GNSS, WiFi 5 (802.11ac), Bluetooth 5.0 * GPU: Mali-G52 MP1 * Codec: 1080p 60fps H64, HEVC, JPEG HW Codec * Display: Full HD+ (2520x1080)@60fps LCD * Camera: 16+5MP/13+8MP ISP, MIPI CSI 4/4/2, FD, DRC * Connectivity: USB 2.0 DRD, USI (SPI/UART/I2C), HSI2C, I3C, ADC, Audio This patch adds minimal SoC support. Particular board device tree files can include exynos850.dtsi file to get SoC related nodes, and then reference those nodes further as needed. Signed-off-by: Sam Protsenko --- .../boot/dts/exynos/exynos850-pinctrl.dtsi | 782 ++++++++++++++++++ arch/arm64/boot/dts/exynos/exynos850-usi.dtsi | 30 + arch/arm64/boot/dts/exynos/exynos850.dtsi | 245 ++++++ 3 files changed, 1057 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos850-usi.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi new file mode 100644 index 000000000000..4cf0a22cc6db --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi @@ -0,0 +1,782 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos850 SoC pin-mux and pin-config device tree source + * + * Copyright (C) 2017 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device + * tree nodes in this file. + */ + +#include + +/ { + /* ALIVE */ + pinctrl@11850000 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = + , + , + , + , + , + , + , + ; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = + , + , + , + , + , + , + , + ; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = + , + , + , + , + , + , + , + ; + }; + + gpa3: gpa3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = + , + , + , + , + , + , + , + ; + }; + + gpa4: gpa4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = + , + , + , + ; + }; + + gpq0: gpq0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* USI_PERI_UART_DBG */ + uart0_bus: uart0-bus { + samsung,pins = "gpq0-0", "gpq0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + decon_f_te_on: decon_f_te_on { + samsung,pins = "gpa4-1"; + samsung,pin-function = <0xf>; + }; + + decon_f_te_off: decon_f_te_off { + samsung,pins = "gpa4-1"; + samsung,pin-function = <0x0>; + }; + + /* I2C_5 | CAM_PMIC_I2C */ + i2c5_bus: i2c5-bus { + samsung,pins = "gpa3-5", "gpa3-6"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + /* I2C_6 | MOTOR_I2C */ + i2c6_bus: i2c6-bus { + samsung,pins = "gpa3-7", "gpa4-0"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + }; + + /* CMGP */ + pinctrl@11c30000 { + gpm0: gpm0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = + ; + }; + + gpm1: gpm1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = + ; + }; + + gpm2: gpm2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = + ; + }; + + gpm3: gpm3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = + ; + }; + + gpm4: gpm4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = + ; + }; + + gpm5: gpm5 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + interrupts = + ; + }; + + /* usi_cmgp00 */ + hsi2c3_bus: hsi2c3-bus { + samsung,pins = "gpm0-0", "gpm1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + /* usi_cmgp01 */ + hsi2c4_bus: hsi2c4-bus { + samsung,pins = "gpm4-0", "gpm5-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + /* spi usi_cmgp00 */ + spi1_bus: spi1-bus { + samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi1_cs: spi1-cs { + samsung,pins = "gpm3-0"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi1_cs_func: spi1-cs-func { + samsung,pins = "gpm3-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + /* spi usi_cmgp01 */ + spi2_bus: spi2-bus { + samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi2_cs: spi2-cs { + samsung,pins = "gpm7-0"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi2_cs_func: spi2-cs-func { + samsung,pins = "gpm7-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + /* usi_cmgp00_uart */ + uart1_bus_single: uart1-bus { + samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + uart1_bus_dual: uart1-bus-dual { + samsung,pins = "gpm0-0", "gpm1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + /* usi_cmgp01_uart */ + uart2_bus_single: uart2-bus { + samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + uart2_bus_dual: uart2-bus-dual { + samsung,pins = "gpm4-0", "gpm5-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + }; + + /* AUD */ + pinctrl@14a60000 { + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + aud_codec_mclk: aud-codec-mclk { + samsung,pins = "gpb0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + }; + + aud_codec_mclk_idle: aud-codec-mclk-idle { + samsung,pins = "gpb0-0"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + }; + + aud_i2s0_bus: aud-i2s0-bus { + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + }; + + aud_i2s0_idle: aud-i2s0-idle { + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + }; + + aud_i2s1_bus: aud-i2s1-bus { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + }; + + aud_i2s1_idle: aud-i2s1-idle { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + }; + + aud_fm_bus: aud-fm-bus { + samsung,pins = "gpb1-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + }; + + aud_fm_idle: aud-fm-idle { + samsung,pins = "gpb1-4"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + }; + }; + + /* HSI */ + pinctrl@13430000 { + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpf2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpf2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <2>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpf2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <2>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpf2-3", "gpf2-4", "gpf2-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <2>; + }; + + sd2_clk_fast_slew_rate_1x: sd2-clk_fast_slew_rate_1x { + samsung,pins = "gpf2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd2_clk_fast_slew_rate_1_5x: sd2-clk_fast_slew_rate_1_5x { + samsung,pins = "gpf2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <1>; + }; + + sd2_clk_fast_slew_rate_2x: sd2-clk_fast_slew_rate_2x { + samsung,pins = "gpf2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd2_clk_fast_slew_rate_2_5x: sd2-clk_fast_slew_rate_2_5x { + samsung,pins = "gpf2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_clk_fast_slew_rate_3x: sd2-clk_fast_slew_rate_3x { + samsung,pins = "gpf2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <4>; + }; + + sd2_clk_fast_slew_rate_4x: sd2-clk_fast_slew_rate_4x { + samsung,pins = "gpf2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <5>; + }; + + sd2_pins_as_pdn: sd2-pins-as-pdn { + samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", + "gpf2-4", "gpf2-5"; + samsung,pin-function = <0>; + samsung,pin-pud = <2>; + }; + + }; + + /* CORE */ + pinctrl@12070000 { + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk: sd0-clk { + samsung,pins = "gpf0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpf0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_rdqs: sd0-rdqs { + samsung,pins = "gpf0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <3>; + }; + + sd0_nreset: sd0-nreset { + samsung,pins = "gpf0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_clk_fast_slew_rate_1x: sd0-clk_fast_slew_rate_1x { + samsung,pins = "gpf0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <1>; + }; + + sd0_clk_fast_slew_rate_2x: sd0-clk_fast_slew_rate_2x { + samsung,pins = "gpf0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd0_clk_fast_slew_rate_3x: sd0-clk_fast_slew_rate_3x { + samsung,pins = "gpf0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd0_clk_fast_slew_rate_4x: sd0-clk_fast_slew_rate_4x { + samsung,pins = "gpf0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpf1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + }; + + /* PERI */ + pinctrl@139b0000 { + gpg0: gpg0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp0: gpp0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp1: gpp1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp2: gpp2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg3: gpg3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + xclkout: xclkout { + samsung,pins = "gpq0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + /* usi_hsi2c_0 */ + hsi2c0_bus: hsi2c0-bus { + samsung,pins = "gpc1-0", "gpc1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + /* usi_hsi2c_1 */ + hsi2c1_bus: hsi2c1-bus { + samsung,pins = "gpc1-2", "gpc1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + /* usi_hsi2c_2 */ + hsi2c2_bus: hsi2c2-bus { + samsung,pins = "gpc1-4", "gpc1-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + /* usi_spi_0 */ + spi0_bus: spi0-bus { + samsung,pins = "gpp2-0", "gpp2-2", "gpp2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi0_cs: spi0-cs { + samsung,pins = "gpp2-1"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + spi0_cs_func: spi0-cs-func { + samsung,pins = "gpp2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c0_bus: i2c0-bus { + samsung,pins = "gpp0-0", "gpp0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c1_bus: i2c1-bus { + samsung,pins = "gpp0-2", "gpp0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c2_bus: i2c2-bus { + samsung,pins = "gpp0-4", "gpp0-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c3_bus: i2c3-bus { + samsung,pins = "gpp1-0", "gpp1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c4_bus: i2c4-bus { + samsung,pins = "gpp1-2", "gpp1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + fm_lna_en: fm-lna-en { + samsung,pins = "gpg2-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-val = <0>; + }; + + sensor_mclk0_in: sensor-mclk0-in { + samsung,pins = "gpc0-0"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sensor_mclk0_out: sensor-mclk0-out { + samsung,pins = "gpc0-0"; + samsung,pin-function = <1>; + samsung,pin-pud = <1>; + samsung,pin-drv = <2>; + }; + + sensor_mclk0_fn: sensor-mclk0-fn { + samsung,pins = "gpc0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sensor_mclk1_in: sensor-mclk1-in { + samsung,pins = "gpc0-1"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sensor_mclk1_out: sensor-mclk1-out { + samsung,pins = "gpc0-1"; + samsung,pin-function = <1>; + samsung,pin-pud = <1>; + samsung,pin-drv = <2>; + }; + + sensor_mclk1_fn: sensor-mclk1-fn { + samsung,pins = "gpc0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sensor_mclk2_in: sensor-mclk2-in { + samsung,pins = "gpc0-2"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sensor_mclk2_out: sensor-mclk2-out { + samsung,pins = "gpc0-2"; + samsung,pin-function = <1>; + samsung,pin-pud = <1>; + samsung,pin-drv = <2>; + }; + + sensor_mclk2_fn: sensor-mclk2-fn { + samsung,pins = "gpc0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos850-usi.dtsi b/arch/arm64/boot/dts/exynos/exynos850-usi.dtsi new file mode 100644 index 000000000000..fb243e0a6260 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos850-usi.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos850 SoC USI device tree source + * + * Copyright (C) 2019 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Samsung's Exynos850 SoC USI channels are listed in this file as device tree + * nodes. + */ + +#include + +/ { + aliases { + uart0 = &serial_0; + }; + + /* USI_UART */ + serial_0: uart@13820000 { + compatible = "samsung,exynos850-uart"; + reg = <0x0 0x13820000 0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_bus>; + clocks = <&clock GATE_UART_QCH>, <&clock DOUT_UART>; + clock-names = "gate_uart_clk0", "uart"; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi new file mode 100644 index 000000000000..ed2d1c8ae0c3 --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Exynos850 SoC device tree source + * + * Copyright (C) 2018 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Samsung Exynos850 SoC device nodes are listed in this file. + * Exynos based board files can include this file and provide + * values for board specific bindings. + */ + +#include +#include +#include "exynos850-pinctrl.dtsi" +#include "exynos850-usi.dtsi" + +/ { + compatible = "samsung,exynos850"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <1>; + + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + pinctrl3 = &pinctrl_3; + pinctrl4 = &pinctrl_4; + pinctrl5 = &pinctrl_5; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0000 { + device_type = "cpu"; + compatible = "arm,cortex-a55", "arm,armv8"; + reg = <0x0 0x0000>; + enable-method = "psci"; + }; + cpu1: cpu@0001 { + device_type = "cpu"; + compatible = "arm,cortex-a55", "arm,armv8"; + reg = <0x0 0x0001>; + enable-method = "psci"; + }; + cpu2: cpu@0002 { + device_type = "cpu"; + compatible = "arm,cortex-a55", "arm,armv8"; + reg = <0x0 0x0002>; + enable-method = "psci"; + }; + cpu3: cpu@0003 { + device_type = "cpu"; + compatible = "arm,cortex-a55", "arm,armv8"; + reg = <0x0 0x0003>; + enable-method = "psci"; + }; + cpu4: cpu@0004 { + device_type = "cpu"; + compatible = "arm,cortex-a55", "arm,armv8"; + reg = <0x0 0x0100>; + enable-method = "psci"; + }; + cpu5: cpu@0005 { + device_type = "cpu"; + compatible = "arm,cortex-a55", "arm,armv8"; + reg = <0x0 0x0101>; + enable-method = "psci"; + }; + cpu6: cpu@0006 { + device_type = "cpu"; + compatible = "arm,cortex-a55", "arm,armv8"; + reg = <0x0 0x0102>; + enable-method = "psci"; + }; + cpu7: cpu@0007 { + device_type = "cpu"; + compatible = "arm,cortex-a55", "arm,armv8"; + reg = <0x0 0x0103>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + gic: interrupt-controller@12a00000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x12a01000 0x1000>, + <0x0 0x12a02000 0x1000>, + <0x0 0x12a04000 0x2000>, + <0x0 0x12a06000 0x2000>; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <26000000>; + use-clocksource-only; + use-physical-timer; + }; + + clock: clock-controller@0x120e0000 { + compatible = "samsung,exynos850-clock"; + reg = <0x0 0x120e0000 0x8000>; + #clock-cells = <1>; + }; + + /* ALIVE */ + pinctrl_0: pinctrl@11850000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x0 0x11850000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + }; + }; + + /* CMGP */ + pinctrl_1: pinctrl@11c30000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x0 0x11c30000 0x1000>; + interrupts = + , + , + , + , + , + , + , + ; + + wakeup-interrupt-controller { + compatible = "samsung,exynos7-wakeup-eint"; + }; + }; + + /* AUD */ + pinctrl_2: pinctrl@14a60000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x0 0x14a60000 0x1000>; + }; + + /* HSI */ + pinctrl_3: pinctrl@13430000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x0 0x13430000 0x1000>; + interrupts = ; + }; + + /* CORE */ + pinctrl_4: pinctrl@12070000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x0 0x12070000 0x1000>; + interrupts = ; + }; + + /* PERI */ + pinctrl_5: pinctrl@139b0000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x0 0x139b0000 0x1000>; + interrupts = ; + }; +};