From patchwork Wed Jul 28 18:00:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 488954 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DFA8C432BE for ; Wed, 28 Jul 2021 18:00:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7FB6F60E09 for ; Wed, 28 Jul 2021 18:00:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229620AbhG1SBA (ORCPT ); Wed, 28 Jul 2021 14:01:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60530 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229556AbhG1SBA (ORCPT ); Wed, 28 Jul 2021 14:01:00 -0400 Received: from mail-qv1-xf2e.google.com (mail-qv1-xf2e.google.com [IPv6:2607:f8b0:4864:20::f2e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 43509C061764; Wed, 28 Jul 2021 11:00:58 -0700 (PDT) Received: by mail-qv1-xf2e.google.com with SMTP id g6so1983059qvj.8; Wed, 28 Jul 2021 11:00:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vXk/J4q5mPEjnLuepFqEKq93BJsZukmkkBYD3V+Z3Tk=; b=beFhaZVHfk7mxGVzvlrm0rAr2p1O/09MWnJmT0ut7HVMm6/cAi3kDjr9g+wxOuPF/w 59io64vS64AzA+1oeggt0h6Ua18feX03yXJj0NeUQlhAND2wrGoAqAaTsYoY6L9Udi3t 6u0Z//Phpn/Y9eC+AcrxmAiZvK2d39nkFcwoXMoH1+yE13kD0GdzyCU/21wTNchokQH8 2Kjn3hrmPGYQE0ah/xwM2u+yCSKCxXIFz4fCQjM3N5lkC+TdEfqDjsB5t/w2NqdkZjp3 6aQF8d45sVRRAWYJ7+qUXy26mY2vadhl3SV6kOnaHs+Se2R367o5v+B68PB0wOg15qo5 ZQMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vXk/J4q5mPEjnLuepFqEKq93BJsZukmkkBYD3V+Z3Tk=; b=aG8D7qZVT3/QcJ2NDxb156/MlH/82RLeM0k8njEs62KXsC5789rL5KzIB8UYqVjLFi 1dTntKSiwWlx/QuSqz7aMEr4V1Olghigl6sezHB1xaPyXfMwHGJ3ih0IVZ8BCxUsA5uV Au95sSbJFS50cZEUtypYJ6mZle3m8mjlCbcK88HSJFS/gF5RpXkX3jXP6aPdFxmXlYHL 3OPDyjUtpqm6vd2dDvbwZUqRyJdPBywyL+oe7sZ5hOKwkwySPvp6bSD/yVgIqhGvOCwR nzcJVQY1K/jpkRkSJUR7HOyAlVmztgKuRUI6y7yAtcireOiL59jxGCUoQc9TLCoCNIyn kU9A== X-Gm-Message-State: AOAM5327CzqDeTL/hmaNEBLysptgnW08YvoCQC6GkOTI1Ymw8Kgn6XUe r838yzApdMgx/qMkBXiwfxE= X-Google-Smtp-Source: ABdhPJxR95vQmYlTzhJ3BscYKr/cpb85sYBj4WPecIGS8wdPNanrwNCUsJga5A8c4jDPranJBAoFAw== X-Received: by 2002:ad4:5bee:: with SMTP id k14mr1411561qvc.10.1627495257347; Wed, 28 Jul 2021 11:00:57 -0700 (PDT) Received: from master-laptop.sparksnet ([2601:153:980:85b1:b58:2ae8:d75f:660a]) by smtp.gmail.com with ESMTPSA id r5sm223341qtm.75.2021.07.28.11.00.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jul 2021 11:00:57 -0700 (PDT) From: Peter Geis To: Rob Herring , Heiko Stuebner , Liang Chen Cc: Peter Geis , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/8] arm64: dts: rockchip: fix rk3568 mbi-alias Date: Wed, 28 Jul 2021 14:00:27 -0400 Message-Id: <20210728180034.717953-2-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210728180034.717953-1-pgwipeout@gmail.com> References: <20210728180034.717953-1-pgwipeout@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The mbi-alias incorrectly points to 0xfd100000 when it should point to 0xfd410000. This fixes MSIs on rk3568. Fixes: a3adc0b9071d ("arm64: dts: rockchip: add core dtsi for RK3568 SoC") Signed-off-by: Peter Geis --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 322971318d5a..f7ecdfd66f86 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -195,7 +195,7 @@ gic: interrupt-controller@fd400000 { interrupts = ; interrupt-controller; #interrupt-cells = <3>; - mbi-alias = <0x0 0xfd100000>; + mbi-alias = <0x0 0xfd410000>; mbi-ranges = <296 24>; msi-controller; }; From patchwork Wed Jul 28 18:00:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 488953 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDBC5C432BE for ; Wed, 28 Jul 2021 18:01:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B396460E09 for ; Wed, 28 Jul 2021 18:01:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231430AbhG1SBG (ORCPT ); Wed, 28 Jul 2021 14:01:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231316AbhG1SBC (ORCPT ); Wed, 28 Jul 2021 14:01:02 -0400 Received: from mail-qt1-x82a.google.com (mail-qt1-x82a.google.com [IPv6:2607:f8b0:4864:20::82a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ECDABC061757; Wed, 28 Jul 2021 11:00:59 -0700 (PDT) Received: by mail-qt1-x82a.google.com with SMTP id w10so1989453qtj.3; Wed, 28 Jul 2021 11:00:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S56htb9vVkDrFmzApk71DTCJizGCv0+IZp82FWSdz/g=; b=owtO4XXjj6P6Rjd77xgdGJq/s1cIXPoVSiO7zCI14o5x9HuPAsV6xo+swVDwOS+ZjA ztTe4uNIBTc2IaR7dWUrUEv444EXFIJZy6s7fTrzROo+SKHeTIC/APTaUUNqsptqAjQ0 JUJ7Ied3+YGJjFVtJZFOlQ2mF9N3Aj/vpGoCfzQNunvA4+Ik2Of+hjrHK/9J309xfIjj 4UZiSMt+4qDj7ULdB+HUEI9y8pczBhA2zLfvQb3AC8H3OjvkXjxnAWA23bVWvT6eJVOv qRg+DZQmQ+QZPnN8KEAEs1Fn2ik2CCzzm48pRw9jXBkq0vSSIyR7vvtheY675Yq5MJUB OgVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S56htb9vVkDrFmzApk71DTCJizGCv0+IZp82FWSdz/g=; b=McJVfxLRBNOKlnU20/CqP2MJpM0U9qnnZNb5KqzK+1YAhG25a3xRQIRdss64vW5Ebs VRYSAchdks6wBqGxHZImPrE1/Eg9gERnZBq3NvVphCLq+NGT5JkGe5rncGOFjk4+ccNw wLUWtNkwGGODeUEGZ9e00t7Q2mdzzBckghsxvAeD5wb2c+FSxoB0QQJHxGRmZSAk5EGM ao7q+8gMtA/1NdJpM2X1B1PNau9ZMBgqmPhwOHKwMS8z7YkrY/yTcGa3yGWNsh0jSv5f ZoqwdxmiEPbfro4uTzj9oxb5QREs06TLZYv3qgLVc+uOA9I8bNmqj0HaztD8MusFZN8h wFCw== X-Gm-Message-State: AOAM530VIOnS1738V1kPyGHpZxQMLmMu9eCSeDnByi2p2081ADUVFNfM +Rk32AenygrfQ5sD/6GySNQ= X-Google-Smtp-Source: ABdhPJwXiOweFs0EgI4O/K88VOjku0nSLXkG/t0a1JDtXJczLMHrFHl2a0of4XrY2CunDR50P4P/hg== X-Received: by 2002:ac8:4d9b:: with SMTP id a27mr688003qtw.351.1627495259053; Wed, 28 Jul 2021 11:00:59 -0700 (PDT) Received: from master-laptop.sparksnet ([2601:153:980:85b1:b58:2ae8:d75f:660a]) by smtp.gmail.com with ESMTPSA id r5sm223341qtm.75.2021.07.28.11.00.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jul 2021 11:00:58 -0700 (PDT) From: Peter Geis To: Rob Herring , Heiko Stuebner Cc: Peter Geis , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/8] arm64: dts: rockchip: add rk356x gpio debounce clocks Date: Wed, 28 Jul 2021 14:00:29 -0400 Message-Id: <20210728180034.717953-4-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210728180034.717953-1-pgwipeout@gmail.com> References: <20210728180034.717953-1-pgwipeout@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The rk356x added a debounce clock to the gpio devices. This clock is necessary for the new v2 gpio driver to bind. Add the clocks to the rk356x device tree. Signed-off-by: Peter Geis --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index f7ecdfd66f86..c2aa7aeec58d 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -750,7 +750,7 @@ gpio0: gpio@fdd60000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfdd60000 0x0 0x100>; interrupts = ; - clocks = <&pmucru PCLK_GPIO0>; + clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -761,7 +761,7 @@ gpio1: gpio@fe740000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfe740000 0x0 0x100>; interrupts = ; - clocks = <&cru PCLK_GPIO1>; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -772,7 +772,7 @@ gpio2: gpio@fe750000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfe750000 0x0 0x100>; interrupts = ; - clocks = <&cru PCLK_GPIO2>; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -783,7 +783,7 @@ gpio3: gpio@fe760000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfe760000 0x0 0x100>; interrupts = ; - clocks = <&cru PCLK_GPIO3>; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -794,7 +794,7 @@ gpio4: gpio@fe770000 { compatible = "rockchip,gpio-bank"; reg = <0x0 0xfe770000 0x0 0x100>; interrupts = ; - clocks = <&cru PCLK_GPIO4>; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; gpio-controller; #gpio-cells = <2>; interrupt-controller; From patchwork Wed Jul 28 18:00:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 488082 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FEB4C4320A for ; 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Wed, 28 Jul 2021 11:01:00 -0700 (PDT) Received: from master-laptop.sparksnet ([2601:153:980:85b1:b58:2ae8:d75f:660a]) by smtp.gmail.com with ESMTPSA id r5sm223341qtm.75.2021.07.28.11.00.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jul 2021 11:00:59 -0700 (PDT) From: Peter Geis To: Rob Herring , Heiko Stuebner Cc: Peter Geis , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/8] arm64: dts: rockchip: add rk356x gmac1 node Date: Wed, 28 Jul 2021 14:00:30 -0400 Message-Id: <20210728180034.717953-5-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210728180034.717953-1-pgwipeout@gmail.com> References: <20210728180034.717953-1-pgwipeout@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the gmac1 controller to the rk356x device tree. This is the controller common to both the rk3568 and rk3566. Signed-off-by: Peter Geis --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index c2aa7aeec58d..fbd9f1c366ff 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -344,6 +344,53 @@ sdmmc2: mmc@fe000000 { status = "disabled"; }; + gmac1: ethernet@fe010000 { + compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe010000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, + <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, + <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, + <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_refout", + "aclk_mac", "pclk_mac", + "clk_mac_speed", "ptp_ref"; + resets = <&cru SRST_A_GMAC1>; + reset-names = "stmmaceth"; + rockchip,grf = <&grf>; + snps,mixed-burst; + snps,tso; + snps,axi-config = <&gmac1_stmmac_axi_setup>; + snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + qos_gpu: qos@fe128000 { compatible = "rockchip,rk3568-qos", "syscon"; reg = <0x0 0xfe128000 0x0 0x20>; From patchwork Wed Jul 28 18:00:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 488952 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 416EEC4338F for ; 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Wed, 28 Jul 2021 11:01:01 -0700 (PDT) Received: from master-laptop.sparksnet ([2601:153:980:85b1:b58:2ae8:d75f:660a]) by smtp.gmail.com with ESMTPSA id r5sm223341qtm.75.2021.07.28.11.01.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jul 2021 11:01:00 -0700 (PDT) From: Peter Geis To: Rob Herring , Heiko Stuebner Cc: Peter Geis , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/8] arm64: dts: rockchip: add rk3568 tsadc nodes Date: Wed, 28 Jul 2021 14:00:31 -0400 Message-Id: <20210728180034.717953-6-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210728180034.717953-1-pgwipeout@gmail.com> References: <20210728180034.717953-1-pgwipeout@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the thermal and tsadc nodes to the rk3568 device tree. There are two sensors, one for the cpu, one for the gpu. Signed-off-by: Peter Geis --- .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 7 ++ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 70 +++++++++++++++++++ 2 files changed, 77 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi index a588ca95ace2..3b1efaf2646e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi @@ -2420,6 +2420,13 @@ spi3m1_cs1: spi3m1-cs1 { }; tsadc { + /omit-if-no-ref/ + tsadc_pin: tsadc-pin { + rockchip,pins = + /* tsadc_pin */ + <0 RK_PA1 0 &pcfg_pull_none>; + }; + /omit-if-no-ref/ tsadcm0_shut: tsadcm0-shut { rockchip,pins = diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index fbd9f1c366ff..c74072941da1 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -50,6 +50,7 @@ cpu0: cpu@0 { compatible = "arm,cortex-a55"; reg = <0x0 0x0>; clocks = <&scmi_clk 0>; + #cooling-cells = <2>; enable-method = "psci"; operating-points-v2 = <&cpu0_opp_table>; }; @@ -58,6 +59,7 @@ cpu1: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x100>; + #cooling-cells = <2>; enable-method = "psci"; operating-points-v2 = <&cpu0_opp_table>; }; @@ -66,6 +68,7 @@ cpu2: cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x200>; + #cooling-cells = <2>; enable-method = "psci"; operating-points-v2 = <&cpu0_opp_table>; }; @@ -74,6 +77,7 @@ cpu3: cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0 0x300>; + #cooling-cells = <2>; enable-method = "psci"; operating-points-v2 = <&cpu0_opp_table>; }; @@ -773,6 +777,72 @@ uart9: serial@fe6d0000 { status = "disabled"; }; + thermal_zones: thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <100>; + polling-delay = <1000>; + + thermal-sensors = <&tsadc 0>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_alert1: cpu_alert1 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + }; + }; + + tsadc: tsadc@fe710000 { + compatible = "rockchip,rk3568-tsadc"; + reg = <0x0 0xfe710000 0x0 0x100>; + interrupts = ; + assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; + assigned-clock-rates = <17000000>, <700000>; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, + <&cru SRST_TSADCPHY>; + reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; + rockchip,grf = <&grf>; + rockchip,hw-tshut-temp = <95000>; + pinctrl-names = "init", "default", "sleep"; + pinctrl-0 = <&tsadc_pin>; + pinctrl-1 = <&tsadc_shutorg>; + pinctrl-2 = <&tsadc_pin>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + saradc: saradc@fe720000 { compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; reg = <0x0 0xfe720000 0x0 0x100>; From patchwork Wed Jul 28 18:00:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 488951 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BC66C43216 for ; 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Wed, 28 Jul 2021 11:01:02 -0700 (PDT) Received: from master-laptop.sparksnet ([2601:153:980:85b1:b58:2ae8:d75f:660a]) by smtp.gmail.com with ESMTPSA id r5sm223341qtm.75.2021.07.28.11.01.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jul 2021 11:01:01 -0700 (PDT) From: Peter Geis To: Rob Herring , Heiko Stuebner Cc: Peter Geis , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/8] arm64: dts: rockchip: adjust rk3568 pll clocks Date: Wed, 28 Jul 2021 14:00:32 -0400 Message-Id: <20210728180034.717953-7-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210728180034.717953-1-pgwipeout@gmail.com> References: <20210728180034.717953-1-pgwipeout@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The rk3568 gpll should run at 1200mhz and the ppll should run at 200mhz. These are set incorrectly by the bootloader, so fix them here. Signed-off-by: Peter Geis --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index c74072941da1..66d1919dd7eb 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -226,6 +226,8 @@ cru: clock-controller@fdd20000 { reg = <0x0 0xfdd20000 0x0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; + assigned-clock-rates = <1200000000>, <200000000>; }; i2c0: i2c@fdd40000 { From patchwork Wed Jul 28 18:00:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 488081 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A081FC4320E for ; Wed, 28 Jul 2021 18:01:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 860556101E for ; Wed, 28 Jul 2021 18:01:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231389AbhG1SBI (ORCPT ); Wed, 28 Jul 2021 14:01:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231420AbhG1SBG (ORCPT ); Wed, 28 Jul 2021 14:01:06 -0400 Received: from mail-qk1-x731.google.com (mail-qk1-x731.google.com [IPv6:2607:f8b0:4864:20::731]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 42423C061765; Wed, 28 Jul 2021 11:01:04 -0700 (PDT) Received: by mail-qk1-x731.google.com with SMTP id f22so3080499qke.10; Wed, 28 Jul 2021 11:01:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OkK6x6zm6GWAYlSexAP9I420ulpovKLeZWcigiEH4qE=; b=rfa/0mI5PgYXeAiHADQGinO4cVfzsm2WrTDv0/QZj8NgCuAWcQaxNYTB5alyA4Dw+j qJLSw4gdjZ8yoZXH18o5NuSyG0N3G+sulL4Zj5HW8Ldvkf1x41jpi/jD2ravFQbCrPTb 3FUz+iO9FO9fNzctfNas7AsGyZpa0386kPqk8SHToxTJkZMGW+nrzJVlr++zxSdUQ5uE jwsM00xrqXmjfIvBTZeAs5HG15EW7U6kCUBEGpZpu46NipWZbDdZ9KjogLsBFmkP5o8O 7GC0Yq88iilX8Xn7epXTqF0ML6XMlb4cQFLf7NGxRNGoHSA/S1OXvcmtRCNpURHIOdAR aXJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OkK6x6zm6GWAYlSexAP9I420ulpovKLeZWcigiEH4qE=; b=QJCNB7TZGb/NqmrwRZeFvWe0HTpM4sPzG6mh2cuoca8nipUuU7lDpbAoDI+Ia1pgUF s+e06rIr2go1L4Mhyteq5rvg5NKcOIFNoct1/7YmICKZ/aPTTyjPcQe0h3paCzZkzEyq 4ZizJBPSxSND1fZcw0+bpiVwaC9xfvhyG0hJhRbYNNlSAoE62vXtq9KGX0f6CjFsb395 2786Y3QdHn+0hYqlAoOsAi1fiq1pArv5KZpeijm8dPeCEJvkt/VyXd10oSfJAeUPU985 CjvWtS9fM5HEsMucjB9Ge4rZ575m8RoN158gCOdbFBZu22EQd4BsjbOvTsmhQ+nPp0ob ZTGw== X-Gm-Message-State: AOAM530us5tQkFPEm/V20VYqH4weXBIMErHW+9YtZhmwgMcCMJH3w+rU vSB0j/0c4InuamHNNBZFXUs= X-Google-Smtp-Source: ABdhPJweete4r2BIayV6eiYOYWBt8ZtcIm0PWhCwh6+YQZB/vt+uFHtHFfdC+CjMTubMKuVK3Pileg== X-Received: by 2002:a37:7141:: with SMTP id m62mr922459qkc.496.1627495263435; Wed, 28 Jul 2021 11:01:03 -0700 (PDT) Received: from master-laptop.sparksnet ([2601:153:980:85b1:b58:2ae8:d75f:660a]) by smtp.gmail.com with ESMTPSA id r5sm223341qtm.75.2021.07.28.11.01.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jul 2021 11:01:02 -0700 (PDT) From: Peter Geis To: Rob Herring , Heiko Stuebner Cc: Peter Geis , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 7/8] arm64: dts: rockchip: enable gmac node on quartz64-a Date: Wed, 28 Jul 2021 14:00:33 -0400 Message-Id: <20210728180034.717953-8-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210728180034.717953-1-pgwipeout@gmail.com> References: <20210728180034.717953-1-pgwipeout@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable the gmac controller on the Pine64 Quartz64 Model A. Signed-off-by: Peter Geis --- .../boot/dts/rockchip/rk3566-quartz64-a.dts | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index a3cdb6c2bec6..b239f314b38a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -11,6 +11,7 @@ / { compatible = "pine64,quartz64-a", "rockchip,rk3566"; aliases { + ethernet0 = &gmac1; mmc0 = &sdmmc0; mmc1 = &sdhci; }; @@ -19,6 +20,13 @@ chosen: chosen { stdout-path = "serial2:1500000n8"; }; + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + leds { compatible = "gpio-leds"; @@ -116,6 +124,29 @@ &cpu3 { cpu-supply = <&vdd_cpu>; }; +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_3v3>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_clkinout + &gmac1m0_rgmii_bus>; + snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x30>; + rx_delay = <0x10>; + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + &i2c0 { status = "okay"; @@ -336,6 +367,13 @@ regulator-state-mem { }; }; +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + &pinctrl { bt { bt_enable_h: bt-enable-h { From patchwork Wed Jul 28 18:00:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Geis X-Patchwork-Id: 488080 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2354C432BE for ; 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Wed, 28 Jul 2021 11:01:04 -0700 (PDT) Received: from master-laptop.sparksnet ([2601:153:980:85b1:b58:2ae8:d75f:660a]) by smtp.gmail.com with ESMTPSA id r5sm223341qtm.75.2021.07.28.11.01.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jul 2021 11:01:04 -0700 (PDT) From: Peter Geis To: Rob Herring , Heiko Stuebner Cc: Peter Geis , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 8/8] arm64: dts: rockchip: add thermal support to Quartz64 Model A Date: Wed, 28 Jul 2021 14:00:34 -0400 Message-Id: <20210728180034.717953-9-pgwipeout@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210728180034.717953-1-pgwipeout@gmail.com> References: <20210728180034.717953-1-pgwipeout@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the thermal nodes for the Quartz64 Model A. The Model A supports a single speed gpio fan. Signed-off-by: Peter Geis --- .../boot/dts/rockchip/rk3566-quartz64-a.dts | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index b239f314b38a..a244f7b87e38 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -27,6 +27,14 @@ gmac1_clkin: external-gmac1-clock { #clock-cells = <0>; }; + fan: gpio_fan { + compatible = "gpio-fan"; + gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0 + 4500 1>; + #cooling-cells = <2>; + }; + leds { compatible = "gpio-leds"; @@ -124,6 +132,23 @@ &cpu3 { cpu-supply = <&vdd_cpu>; }; +&cpu_thermal { + trips { + cpu_hot: cpu_hot { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&cpu_hot>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + &gmac1 { assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; @@ -433,6 +458,14 @@ &sdmmc0 { status = "okay"; }; +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer>;