From patchwork Wed Sep 12 09:52:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 146528 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp4618074ljw; Wed, 12 Sep 2018 02:53:30 -0700 (PDT) X-Google-Smtp-Source: ANB0VdYuQiASMk8P3HjGtoxWl+r45B/0V+PtsU06Yz1az7HkhpMNcx8uhJKJiXkC6epYr+ofAiCp X-Received: by 2002:a62:1d54:: with SMTP id d81-v6mr1294441pfd.139.1536746009908; Wed, 12 Sep 2018 02:53:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1536746009; cv=none; d=google.com; s=arc-20160816; b=EL60nBxNOjuH85Dt/fgyls+odHyMb6wz3QhKL0BVLKyZH+X/zepHbQuMxkihKOosL9 lF+K8Au+njIaJdU8ITrpXwRyJAXMp+/pmoPKQkV4PzlIBe+CWhwAMYEG5B7+9gD+E260 FiUDKzy9FYUYu6O6Y3yXLDKn1Ia6udNHoNit9nEVISoPqtXt0l11tnxbgqJhcnPlQX9w kWqY3ALbqnQ9+PoMfmSO+avhHuB4hmuOkGH56yUvM2phLLM4tY8MIMSU8uIIIfaJCz7E j38gO8p74CtQLYmbAYCVgjy0DPEmEkIAOG6XFiGiRtOIoEsT6KtlSKxhI0A19mZqH18P 03gQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=ZveZRZ6ez2WFXt4vWZSNreLB4c6rXEn4jTnJUKvsQDk=; b=ORjfkfQAP6mWwL3RuylOyqsk8PksUgoXWre6O2DMCM6qJSIpg3WQ4wxTFH3SrikfJA OE5c5lFvkfuPw83eo7KxjcZzCoGvrdaixV9rtVe4HrxzRn3DlQbzTMqPp9bQ/gpEJHru CCLAj1DXYLyJquYafBzvQ/bB+9EZfIRLPBlo9aS68QPY0YuBOAzS3JYellh/pD/68P0+ Ct7WAawllaqq8ChfAv7Y4zx9tIpIT+7D+LTRWhbfZsgC85iVbEFpmg08/YpcEzexKlD/ 1zsFQEgFIT0B3UPAksR7rKpL7KjRMgzz+LpR+uu3QWBIMJAjflvUJAGlq9nkwIl3GmK+ HkGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QxsYTz7w; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k6-v6si427746pls.426.2018.09.12.02.53.29; Wed, 12 Sep 2018 02:53:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QxsYTz7w; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726819AbeILO5O (ORCPT + 13 others); Wed, 12 Sep 2018 10:57:14 -0400 Received: from mail-ed1-f66.google.com ([209.85.208.66]:44682 "EHLO mail-ed1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726810AbeILO5O (ORCPT ); Wed, 12 Sep 2018 10:57:14 -0400 Received: by mail-ed1-f66.google.com with SMTP id s10-v6so1233520edb.11 for ; Wed, 12 Sep 2018 02:53:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=ZveZRZ6ez2WFXt4vWZSNreLB4c6rXEn4jTnJUKvsQDk=; b=QxsYTz7wjLzAywPKeME/lb8Kr8KJSddcqY8CX2VtPjYdD8sXXSX1X4DuI0Rj7+/Ij1 LeU55vndWr0mBFKqCMwePkISgioxpm3ga2vVaqwJxehCslUgTO/6f3LPJqh8XdtJsG2D em7bAXoBOxPifhvgQrTGzKstdmo8MhwIUQlrQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=ZveZRZ6ez2WFXt4vWZSNreLB4c6rXEn4jTnJUKvsQDk=; b=GnXZ4+DRUcplf8aXIOVDClx0dhQasYHtlt+K3/s7+oYzQNz0UzCp1bZSaZsjCFb1iA 71fBUao61HkbQJGAbmVOAu2KXvqbaoZQ1WSmuKdRshfa45L4KjDzjfsrnW0WrjBWyBtU bTIe5ZqgQM8ulOwh9/0Sui5l5+Ek9kU/qgvNuquF5wswVVBTJuHkGkX1LZlWVzPsIJUb ivLaE+VLlsH1U/cZqVuIyVXwTOGdfoAbkDn7ZKTE5EbH1dotpKxkdD5e9fVbrmZooqGm oNdjADwjawphaMGKCQjB3FqZ3vFP++YNzbZcvwCexTVlyfpmcUKQGdeewbSuwGxUZEGk Zk2Q== X-Gm-Message-State: APzg51DZIWvhtbeQSppLAbT46ocMbYNkfbTlRguSDlVHWUGrVr5NWnx+ JiGbNrUodQ5YAYtatA/BLo9Dfw== X-Received: by 2002:a50:f297:: with SMTP id f23-v6mr1870386edm.40.1536746006441; Wed, 12 Sep 2018 02:53:26 -0700 (PDT) Received: from localhost ([49.248.190.214]) by smtp.gmail.com with ESMTPSA id a33-v6sm433189eda.2.2018.09.12.02.53.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 12 Sep 2018 02:53:25 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: rnayak@codeaurora.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, smohanad@codeaurora.org, andy.gross@linaro.org, dianders@chromium.org, mka@chromium.org, Zhang Rui , Daniel Lezcano , linux-pm@vger.kernel.org Subject: [PATCH v3 01/16] thermal: tsens: Prepare 8916 and 8974 tsens to use SROT and TM address space Date: Wed, 12 Sep 2018 15:22:46 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We've already converted over the devicetree of platforms using v2 version of the TSENS IP to use two address spaces. Now prepare to convert over the 8916 and 8974 platforms to use separate SROT and TM address spaces. This patch will work with device trees with one or two address spaces because we set the tm_offset in commit 5b1283984fa3 ("thermal: tsens: Add support to split up register address space into two"). Signed-off-by: Amit Kucheria Reviewed-by: Matthias Kaehlcke --- drivers/thermal/qcom/tsens-common.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index 6207d8d92351..478739543bbc 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -21,7 +21,7 @@ #include #include "tsens.h" -#define S0_ST_ADDR 0x1030 +#define STATUS_OFFSET 0x30 #define SN_ADDR_OFFSET 0x4 #define SN_ST_TEMP_MASK 0x3ff #define CAL_DEGC_PT1 30 @@ -107,8 +107,9 @@ int get_temp_common(struct tsens_device *tmdev, int id, int *temp) unsigned int status_reg; int last_temp = 0, ret; - status_reg = S0_ST_ADDR + s->hw_id * SN_ADDR_OFFSET; + status_reg = tmdev->tm_offset + STATUS_OFFSET + s->hw_id * SN_ADDR_OFFSET; ret = regmap_read(tmdev->map, status_reg, &code); + if (ret) return ret; last_temp = code & SN_ST_TEMP_MASK; From patchwork Wed Sep 12 09:52:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 146530 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp4618239ljw; Wed, 12 Sep 2018 02:53:42 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZjh8kdjBJ+t5fIfpMmRfk/qlb68bJUjQ9YhR0HUhKSfGA/jF1JYNR+NUfrpPvFWV4Hdzva X-Received: by 2002:a62:b20c:: with SMTP id x12-v6mr1273517pfe.201.1536746022150; Wed, 12 Sep 2018 02:53:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1536746022; cv=none; d=google.com; s=arc-20160816; b=OMrTgbJYVHTQjt7BvnBLzg5H04JpXwSqzfR3ZYOI1x4V6EBrwfcLNwLWTelvUYseB2 ZLuEpDOm1XOy0zYnAGtS+IG2b7+7Dpe3XXzUZIRisu2rxA4hCJV2lxVjzZD3DeWXZiSA ccI1FELxKwx6mlGMs44ZfGMGmZRIqBTgRqwnAou49u68mq4OX2BUMezaZpMIfb8HZUz0 CsVu46F5pN566TQehMBVL3QQB+TKov4RHro2hQPpU0Dijsef/fzUUO1xJ3uzvwNHYBFx 2yQAq9rHrFzeRtsyMaY0cD9IG+3wX5lXS5OdNSX1pnKBjhcqu6Bjn6Kn0QWQXTvzyFks 3zPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=RXDtbhIMyFAbtAg9tx8eCbbtVuDm61EOqgYh33KEgl8=; b=VWyKL57Dtcwwy6SQHzGiwBZ0Vj6j4YyhewFaAnym3Rda+Nwdqs2Cak6TwQ8ZBJeYq/ V4MdKqwUmuVgbus6Apvp/mtj7GeXNbEt/PjSNbxj18nkMjuMKa4bFH8J5zjjkuUt0ySk tMawlojWE/MmekcdIO9SGNdGhP4H8y+SyS60BgIYgv96Y00u7L3vVCpuymVKt0rF7HWS cJrxw/OGROBrWknzI0HTZ7TaKTIP9qbADS+CHorZ/qZ8CJ4/8trtRUheVNU2aTYIwXka YyoSt2yorFLB+Dtxu2Zqv8j2hJiBkA8ZDuMgojKnc2meYsx75qdk0vLnTrtQYw3BClYi 17Ww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OEbotGsS; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s10-v6si631341pgh.6.2018.09.12.02.53.41; Wed, 12 Sep 2018 02:53:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OEbotGsS; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726839AbeILO51 (ORCPT + 13 others); Wed, 12 Sep 2018 10:57:27 -0400 Received: from mail-ed1-f67.google.com ([209.85.208.67]:33398 "EHLO mail-ed1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726860AbeILO50 (ORCPT ); Wed, 12 Sep 2018 10:57:26 -0400 Received: by mail-ed1-f67.google.com with SMTP id d8-v6so1283138edv.0 for ; Wed, 12 Sep 2018 02:53:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=RXDtbhIMyFAbtAg9tx8eCbbtVuDm61EOqgYh33KEgl8=; b=OEbotGsSjoxEa2H9/50/GxFSgmVnTAOrcJRYC3xo0w08omETCoeu6rMeaVS14mbkKL pXKHYSn2IZReT9u3hUPQ401KMAu+qZDFMUzchNNrOxEnHRXF3VW7hssbdF7k6YhkhcSp 3TmTi2ykfyR4GwPfx4Ay+skd12teQHBTW+nYE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=RXDtbhIMyFAbtAg9tx8eCbbtVuDm61EOqgYh33KEgl8=; b=HspLqL19lqjq3z7qoUUSGPzm7PeWan+K1vbA6XPo8uQzRnV6rOsKbhIcqkCUcfmOf6 hLTXlVmC09lkWrhTOHGiX9vtdyRqcYAqiQlQcMh/dgHDRHakscc/HfJTB5FtsIvOfqKH wnDnFxuARVKqACaR6LHVKY2OvZDVM2APEBqIjTVY+xMrdP9PJ0/Q4uC8W3vHDcRt+GKt 4QEbZobMG/71QaZCvTAQip0Wixk5W/rFzm8a76zM6UQvGDFzPALW0y57ERTyEN7qnum9 0REbaasINB2glD4gmS0+3AqlnFDdV2Nr+VJLU/rK59/W2nZFRPa2PEqgC3T7UybHsWju egSg== X-Gm-Message-State: APzg51BJFZQqIEd3Hq/Ucrh4unVYgihId12aC15pyfMwvpCwb0IZnXMT SvKkI762d42PChXSF4v8hjbtlA== X-Received: by 2002:a50:d798:: with SMTP id w24-v6mr1883556edi.19.1536746019244; Wed, 12 Sep 2018 02:53:39 -0700 (PDT) Received: from localhost ([49.248.190.214]) by smtp.gmail.com with ESMTPSA id e30-v6sm390310ede.91.2018.09.12.02.53.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 12 Sep 2018 02:53:38 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: rnayak@codeaurora.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, smohanad@codeaurora.org, andy.gross@linaro.org, dianders@chromium.org, mka@chromium.org, Zhang Rui , Daniel Lezcano , linux-pm@vger.kernel.org Subject: [PATCH v3 03/16] thermal: tsens: Get rid of dead code Date: Wed, 12 Sep 2018 15:22:48 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org hw_id is dynamically allocated but not used anywhere. Get rid of dead code. Signed-off-by: Amit Kucheria Reviewed-by: Matthias Kaehlcke Reviewed-by: Bjorn Andersson --- drivers/thermal/qcom/tsens.c | 5 ----- 1 file changed, 5 deletions(-) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 90bb431cf740..9a8e8f7b4ae1 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -80,11 +80,6 @@ static int tsens_register(struct tsens_device *tmdev) { int i; struct thermal_zone_device *tzd; - u32 *hw_id, n = tmdev->num_sensors; - - hw_id = devm_kcalloc(tmdev->dev, n, sizeof(u32), GFP_KERNEL); - if (!hw_id) - return -ENOMEM; for (i = 0; i < tmdev->num_sensors; i++) { tmdev->sensor[i].tmdev = tmdev; From patchwork Wed Sep 12 09:52:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 146531 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp4618309ljw; Wed, 12 Sep 2018 02:53:48 -0700 (PDT) X-Google-Smtp-Source: ANB0VdYWp14q8S3u9sW93MoRFMtr+nhXBW9di/NRh5BA0QhTF+k4alzI7CXqRtUB0f4DcW88Cg/B X-Received: by 2002:a62:9bc9:: with SMTP id e70-v6mr1274075pfk.95.1536746028771; Wed, 12 Sep 2018 02:53:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1536746028; cv=none; d=google.com; s=arc-20160816; b=jaTlOIJV5yGd4/VM0VuABAFFwotgVHW9z50SHQ6wC7WO2/e4T6tC+CR0KtGACxlqIc sos8x1HYeP5Psm0BPxrfB937CxeBMIbATQZ09FRbMDuoXxcEaph26RPfQiZTR1m21Mli tdTkBO9V4cAhYUOrn8I4AvPB5EWTsRhQS6gNuR9KAMeX81NrmJoOsKFTVayfP5lZruLh g5mXJhbdZ8ShZ4JGguRUyIt07xj0np2tp20vt61+uVKf9yyyonXc/1bOyayXK0LhtSdY k7hnPlslgHYt0km3f0cu/Y9ZdU7RslTMqBYNLXMho46y1jndK+QokGJdE3hpsv19y3lT OpGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=oyVR9VDnhTvKXOKbw7Astf9ffMSp3grLTh5jlc+BE/A=; b=dbI4/7L/ahXekHKxYu0iifZ5heTkNsQ7R/8OvC4+QDIpEkr5aamtPxGKBw+YA4duFd nrJByeyMHgCY0wiV6dHYHyW5xnjrbJaHZRH1hJuVClcbNExXcUj75FcPIkdLjdheziWo O4py6J+Bevm/1sum0I5ucSZ2aBS2eI4VfF0gppXENRtDi2k8zFaZAheZZ+Q8xMAeq7aK kwBVfpnia+K9T6cqHwcXO+6MLpvbQDfBF/VKSdAVfiyC+hfm3P5Ja4QZEanq2hlEERhN Ms/GMyhnqummBb1jSrq6g/LVutP59RHDyAUd51wlIPQ4Fot3Rq3gxC89otlmIYheUmRY jTNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QU4pw6y9; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 13-v6si593025pgs.579.2018.09.12.02.53.48; Wed, 12 Sep 2018 02:53:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QU4pw6y9; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726552AbeILO5d (ORCPT + 13 others); Wed, 12 Sep 2018 10:57:33 -0400 Received: from mail-ed1-f66.google.com ([209.85.208.66]:34198 "EHLO mail-ed1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726876AbeILO5d (ORCPT ); Wed, 12 Sep 2018 10:57:33 -0400 Received: by mail-ed1-f66.google.com with SMTP id u1-v6so1276776eds.1 for ; Wed, 12 Sep 2018 02:53:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=oyVR9VDnhTvKXOKbw7Astf9ffMSp3grLTh5jlc+BE/A=; b=QU4pw6y9+0GKgLiHyhWPqMcNv2aMn2tDfMsI0xLKkwcdSIHWUrJFkKmu6dw2eA85M/ g55mMSWvV9x2zVc2encA1WZ4VAFistP1Vw/Q6omqgjtoKqWcT72wGEXCika0s7Cqw7uy jjqg/MTalyFk0acXBUuDfb/6/90Zx7IOrHsoE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=oyVR9VDnhTvKXOKbw7Astf9ffMSp3grLTh5jlc+BE/A=; b=iRnqhTkDd6hI7woyhfYh12f8QitIWxwpEJWcXdK0+NkYWDliTgYEGXdsym/EiI2esC ZV4e0PoEWTKZNxdlazPIU+ZXhJWJ3gepGiKYJJ5aoSNW0C7V3wBengWYcjjYz5Ujgv8V cTPi6Arbmg7i/lG1Ys1HtUohfnvhFC43h812UDoD6GRxx8HmVKprQSqucA06HCF3XKey t9a/38sQqL1fyyZSGZxOrSkIKGsYPKEQTxHvysV9pX8S5I20x9AoEDm/Piqd6Gip8/Ox p7dIHRllQhXCpxSkKPe/k4gTOqKsYKAB5ebQmnusPqYF8D+F9cZPTHIinG32pDhvj2xJ n7NQ== X-Gm-Message-State: APzg51DF26nmcLto+pPyNOUhMruiUHrfyHNDJDOWteMva9mCJOSTgJ6B tRDznd16Zrs2p/9qA8sf6vclug== X-Received: by 2002:a50:a3cb:: with SMTP id t11-v6mr1879712edb.238.1536746025572; Wed, 12 Sep 2018 02:53:45 -0700 (PDT) Received: from localhost ([49.248.190.214]) by smtp.gmail.com with ESMTPSA id z30-v6sm460597edb.4.2018.09.12.02.53.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 12 Sep 2018 02:53:44 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: rnayak@codeaurora.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, smohanad@codeaurora.org, andy.gross@linaro.org, dianders@chromium.org, mka@chromium.org, Zhang Rui , Daniel Lezcano , linux-pm@vger.kernel.org Subject: [PATCH v3 04/16] thermal: tsens: Rename map field in order to add a second address map Date: Wed, 12 Sep 2018 15:22:49 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The TSENS driver currently only uses a limited set of registers from the TM address space. So it was ok to map just that set of registers and call it "map". We'd now like to map a second set: SROT registers to introduce new functionality. Rename the "map" field to a more appropriate "tm_map". The 8960 doesn't have a clear split between TM and SROT registers. To avoid complicating the data structure, it will switchover to using tm_map for its maps. There is no functional change with this patch. Signed-off-by: Amit Kucheria Reviewed-by: Matthias Kaehlcke Reviewed-by: Bjorn Andersson --- drivers/thermal/qcom/tsens-8960.c | 30 ++++++++++++++--------------- drivers/thermal/qcom/tsens-common.c | 17 ++++++++-------- drivers/thermal/qcom/tsens-v2.c | 6 +++--- drivers/thermal/qcom/tsens.h | 2 +- 4 files changed, 27 insertions(+), 28 deletions(-) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index 4af76de7dc2e..0f0adb302a7b 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -60,7 +60,7 @@ static int suspend_8960(struct tsens_device *tmdev) { int ret; unsigned int mask; - struct regmap *map = tmdev->map; + struct regmap *map = tmdev->tm_map; ret = regmap_read(map, THRESHOLD_ADDR, &tmdev->ctx.threshold); if (ret) @@ -85,7 +85,7 @@ static int suspend_8960(struct tsens_device *tmdev) static int resume_8960(struct tsens_device *tmdev) { int ret; - struct regmap *map = tmdev->map; + struct regmap *map = tmdev->tm_map; ret = regmap_update_bits(map, CNTL_ADDR, SW_RST, SW_RST); if (ret) @@ -117,12 +117,12 @@ static int enable_8960(struct tsens_device *tmdev, int id) int ret; u32 reg, mask; - ret = regmap_read(tmdev->map, CNTL_ADDR, ®); + ret = regmap_read(tmdev->tm_map, CNTL_ADDR, ®); if (ret) return ret; mask = BIT(id + SENSOR0_SHIFT); - ret = regmap_write(tmdev->map, CNTL_ADDR, reg | SW_RST); + ret = regmap_write(tmdev->tm_map, CNTL_ADDR, reg | SW_RST); if (ret) return ret; @@ -131,7 +131,7 @@ static int enable_8960(struct tsens_device *tmdev, int id) else reg |= mask | SLP_CLK_ENA_8660 | EN; - ret = regmap_write(tmdev->map, CNTL_ADDR, reg); + ret = regmap_write(tmdev->tm_map, CNTL_ADDR, reg); if (ret) return ret; @@ -148,7 +148,7 @@ static void disable_8960(struct tsens_device *tmdev) mask <<= SENSOR0_SHIFT; mask |= EN; - ret = regmap_read(tmdev->map, CNTL_ADDR, ®_cntl); + ret = regmap_read(tmdev->tm_map, CNTL_ADDR, ®_cntl); if (ret) return; @@ -159,7 +159,7 @@ static void disable_8960(struct tsens_device *tmdev) else reg_cntl &= ~SLP_CLK_ENA_8660; - regmap_write(tmdev->map, CNTL_ADDR, reg_cntl); + regmap_write(tmdev->tm_map, CNTL_ADDR, reg_cntl); } static int init_8960(struct tsens_device *tmdev) @@ -167,8 +167,8 @@ static int init_8960(struct tsens_device *tmdev) int ret, i; u32 reg_cntl; - tmdev->map = dev_get_regmap(tmdev->dev, NULL); - if (!tmdev->map) + tmdev->tm_map = dev_get_regmap(tmdev->dev, NULL); + if (!tmdev->tm_map) return -ENODEV; /* @@ -184,14 +184,14 @@ static int init_8960(struct tsens_device *tmdev) } reg_cntl = SW_RST; - ret = regmap_update_bits(tmdev->map, CNTL_ADDR, SW_RST, reg_cntl); + ret = regmap_update_bits(tmdev->tm_map, CNTL_ADDR, SW_RST, reg_cntl); if (ret) return ret; if (tmdev->num_sensors > 1) { reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18); reg_cntl &= ~SW_RST; - ret = regmap_update_bits(tmdev->map, CONFIG_ADDR, + ret = regmap_update_bits(tmdev->tm_map, CONFIG_ADDR, CONFIG_MASK, CONFIG); } else { reg_cntl |= SLP_CLK_ENA_8660 | (MEASURE_PERIOD << 16); @@ -200,12 +200,12 @@ static int init_8960(struct tsens_device *tmdev) } reg_cntl |= GENMASK(tmdev->num_sensors - 1, 0) << SENSOR0_SHIFT; - ret = regmap_write(tmdev->map, CNTL_ADDR, reg_cntl); + ret = regmap_write(tmdev->tm_map, CNTL_ADDR, reg_cntl); if (ret) return ret; reg_cntl |= EN; - ret = regmap_write(tmdev->map, CNTL_ADDR, reg_cntl); + ret = regmap_write(tmdev->tm_map, CNTL_ADDR, reg_cntl); if (ret) return ret; @@ -252,12 +252,12 @@ static int get_temp_8960(struct tsens_device *tmdev, int id, int *temp) timeout = jiffies + usecs_to_jiffies(TIMEOUT_US); do { - ret = regmap_read(tmdev->map, INT_STATUS_ADDR, &trdy); + ret = regmap_read(tmdev->tm_map, INT_STATUS_ADDR, &trdy); if (ret) return ret; if (!(trdy & TRDY_MASK)) continue; - ret = regmap_read(tmdev->map, s->status, &code); + ret = regmap_read(tmdev->tm_map, s->status, &code); if (ret) return ret; *temp = code_to_mdegC(code, s); diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index 303e3fdaca98..0585084630b3 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -99,8 +99,7 @@ int get_temp_common(struct tsens_device *tmdev, int id, int *temp) int last_temp = 0, ret; status_reg = tmdev->tm_offset + STATUS_OFFSET + s->hw_id * SN_ADDR_OFFSET; - ret = regmap_read(tmdev->map, status_reg, &code); - + ret = regmap_read(tmdev->tm_map, status_reg, &code); if (ret) return ret; last_temp = code & SN_ST_TEMP_MASK; @@ -118,7 +117,7 @@ static const struct regmap_config tsens_config = { int __init init_common(struct tsens_device *tmdev) { - void __iomem *base; + void __iomem *tm_base; struct resource *res; struct platform_device *op = of_find_device_by_node(tmdev->dev->of_node); @@ -134,13 +133,13 @@ int __init init_common(struct tsens_device *tmdev) } res = platform_get_resource(op, IORESOURCE_MEM, 0); - base = devm_ioremap_resource(&op->dev, res); - if (IS_ERR(base)) - return PTR_ERR(base); + tm_base = devm_ioremap_resource(&op->dev, res); + if (IS_ERR(tm_base)) + return PTR_ERR(tm_base); - tmdev->map = devm_regmap_init_mmio(tmdev->dev, base, &tsens_config); - if (IS_ERR(tmdev->map)) - return PTR_ERR(tmdev->map); + tmdev->tm_map = devm_regmap_init_mmio(tmdev->dev, tm_base, &tsens_config); + if (IS_ERR(tmdev->tm_map)) + return PTR_ERR(tmdev->tm_map); return 0; } diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index 44da02f594ac..1bdef92e4521 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -21,7 +21,7 @@ static int get_temp_tsens_v2(struct tsens_device *tmdev, int id, int *temp) int ret; status_reg = tmdev->tm_offset + STATUS_OFFSET + s->hw_id * 4; - ret = regmap_read(tmdev->map, status_reg, &code); + ret = regmap_read(tmdev->tm_map, status_reg, &code); if (ret) return ret; last_temp = code & LAST_TEMP_MASK; @@ -29,7 +29,7 @@ static int get_temp_tsens_v2(struct tsens_device *tmdev, int id, int *temp) goto done; /* Try a second time */ - ret = regmap_read(tmdev->map, status_reg, &code); + ret = regmap_read(tmdev->tm_map, status_reg, &code); if (ret) return ret; if (code & STATUS_VALID_BIT) { @@ -40,7 +40,7 @@ static int get_temp_tsens_v2(struct tsens_device *tmdev, int id, int *temp) } /* Try a third/last time */ - ret = regmap_read(tmdev->map, status_reg, &code); + ret = regmap_read(tmdev->tm_map, status_reg, &code); if (ret) return ret; if (code & STATUS_VALID_BIT) { diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 8207610f326a..58e98c4d3a8b 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -69,7 +69,7 @@ struct tsens_context { struct tsens_device { struct device *dev; u32 num_sensors; - struct regmap *map; + struct regmap *tm_map; u32 tm_offset; struct tsens_context ctx; const struct tsens_ops *ops; From patchwork Wed Sep 12 09:52:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 146533 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp4618629ljw; Wed, 12 Sep 2018 02:54:10 -0700 (PDT) X-Google-Smtp-Source: ANB0VdanZmbgioIZBX9T2yp7EvzuCTlsVhDGjBPqtu+fPvSC2j/IUDeEIEpW+cucQWFV8hFT/1j8 X-Received: by 2002:a17:902:bb91:: with SMTP id m17-v6mr1264110pls.174.1536746050736; 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Miller" , Mauro Carvalho Chehab , Greg Kroah-Hartman , Andrew Morton , Arnd Bergmann Subject: [PATCH v3 06/16] MAINTAINERS: Add entry for Qualcomm TSENS thermal drivers Date: Wed, 12 Sep 2018 15:22:51 +0530 Message-Id: <1a671f3acaa95e53371243f66c93d7508bf7f529.1536744310.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Create an entry for the TSENS drivers and mark them as maintained Signed-off-by: Amit Kucheria Reviewed-by: Matthias Kaehlcke Acked-by: Rajendra Nayak Acked-by: Bjorn Andersson --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.17.1 diff --git a/MAINTAINERS b/MAINTAINERS index 9ad052aeac39..df6c5ce18b03 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12076,6 +12076,13 @@ L: linux-arm-msm@vger.kernel.org S: Maintained F: drivers/iommu/qcom_iommu.c +QUALCOMM TSENS THERMAL DRIVER +M: Amit Kucheria +L: linux-pm@vger.kernel.org +L: linux-arm-msm@vger.kernel.org +S: Maintained +F: drivers/thermal/qcom/ + QUALCOMM VENUS VIDEO ACCELERATOR DRIVER M: Stanimir Varbanov L: linux-media@vger.kernel.org From patchwork Wed Sep 12 09:52:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 146534 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp4618713ljw; Wed, 12 Sep 2018 02:54:17 -0700 (PDT) X-Google-Smtp-Source: ANB0VdaLJjqhPkNbdPVN8XWdZgW+ElPDcbLQUisJpSkeQhmTqV0u1oPpBCZNZRjrhY4DqdpkB9IK X-Received: by 2002:a62:2285:: with SMTP id p5-v6mr1303390pfj.53.1536746057149; Wed, 12 Sep 2018 02:54:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1536746057; cv=none; d=google.com; s=arc-20160816; b=0bwsMZsP3qWU9KhxpwqjYAb7MpVaQ3wza0DGU/j3qWMh4yiGyI58LbSuQv7Qcyvaqn eHriENaWLuohGmQr0aK4Hn1m9MNr8drmzwldKreElZEq+Uny8Nrjigpu+KsOmMajmNiN d45umZ5/luc4cGCmzmGycuAZPM+VOwIcfZj1EncqT7sV24+wXwQcx16ILbQa6FuG5AD7 XER770x8d9WereJID1J+omowrO6QsUMaEn3/ZN75p0OmH/7p0/wCbxPBJyXG//vJfc3I YLU5FxXgLaPGYkIbSgok5HIV4zRVaooeUjqCRwRHG+GJfn5pg3zmuEW2VVTfPgj9SB7r fl2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=f5bkI9k4W2c9XfxovD/lpb7m212pStl1rJ1cHBfU/w8=; b=iqXB9KINn1Z0IoYIIs9Yw6PrFKG/FW834j7M2KoefEIz7NeUoBYgNbDkBEn6ekltes Tt5z/pCuECk57WzQL6KMM/fMdv88VxEzPpYSRG/cqA/dnt7H/5SPWDeqzAzArFqpkUWk qpc2RThuhbqF7ihiSetDBl8/o2pCPP7jcMT+ibW4JlFzV0un+vD7ryVQ7Br72L6DXdRe T0nOW33TDrGdvJDDF4gATVl2C5xQLGtay/8gYpqQ7Dr4DGI73rJquE6r+0kBni6Kcv6z iHuLvjjFtjXDnGerpcoQ8RCqnm2il/IGfEx/1Rei6OlftopAKLWyYU6i4Z5UsSssjBVr fAdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VdS5xPkq; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a3-v6si552654plc.50.2018.09.12.02.54.16; Wed, 12 Sep 2018 02:54:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VdS5xPkq; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726855AbeILO6C (ORCPT + 13 others); Wed, 12 Sep 2018 10:58:02 -0400 Received: from mail-ed1-f66.google.com ([209.85.208.66]:37579 "EHLO mail-ed1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726606AbeILO6C (ORCPT ); Wed, 12 Sep 2018 10:58:02 -0400 Received: by mail-ed1-f66.google.com with SMTP id a20-v6so1267004edd.4 for ; Wed, 12 Sep 2018 02:54:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=f5bkI9k4W2c9XfxovD/lpb7m212pStl1rJ1cHBfU/w8=; b=VdS5xPkqWD6huuj6drH9txEG/ptP+bfjajMdOn+cz2qpUtJh5vgHCFhg8v7ObU0t1D OxcIdFHzjrQIscgwb1WYW5ZTRfRNEN0eFsNsLjpJJ2P5KLWhHBfCQyQRjagq5jxRMyMB DQLwd/g2rjIrv71lJ+mmjLQbtv3Z0mHGx+rys= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=f5bkI9k4W2c9XfxovD/lpb7m212pStl1rJ1cHBfU/w8=; b=sPjs8aJZs4d9OGaklSpi9vfTlwHO2DwTzS60UXIOruOxBAVl0PO5osCLkaGhTEQiD/ snLrgNHYhOVn+NggIbSWdr23YFrxsEP8O4aH0rs1KinBKhtweKxN38zJMVoKcCuAPaw1 Xh6Ka3Rx5N32OA2CdbQCFzPiSv7JqZT8TkuJAAhd98byXnL46VfKl+f+ViSKMgC8rJ1Z nebRbYwCSqV46EcNHknzscig8jIW1NLc2n46JNtVAWixd1qa5LGDnhGUiRLkf+hW5fPP YpcA4tnDxHi87REzwAct322k55QX4eNiPn5Jjf74C0Fe1onrfsePUCTszm+TDeOl4irK ILSw== X-Gm-Message-State: APzg51DRrmGjWwWPg+EXunlXc5SEjMbT3uqK220+zPI+ofI8KnqP7bnD Idm5Lklh0EQ//5XPDKTorb/zIg== X-Received: by 2002:a50:a804:: with SMTP id j4-v6mr1808568edc.105.1536746054401; Wed, 12 Sep 2018 02:54:14 -0700 (PDT) Received: from localhost ([49.248.190.214]) by smtp.gmail.com with ESMTPSA id h8-v6sm400574edi.68.2018.09.12.02.54.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 12 Sep 2018 02:54:13 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: rnayak@codeaurora.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, smohanad@codeaurora.org, andy.gross@linaro.org, dianders@chromium.org, mka@chromium.org, Zhang Rui , Daniel Lezcano , linux-pm@vger.kernel.org Subject: [PATCH v3 07/16] thermal: tsens: Pass register offsets as private data Date: Wed, 12 Sep 2018 15:22:52 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Registers have moved around across TSENS generations. For example, the CTRL register was at offset 0x0 in the SROT region on msm8916 but is at offset 0x4 in newer v2 based TSENS HW blocks. Allow passing offsets of important registers so that we can continue to use common functions. Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/tsens-8916.c | 1 + drivers/thermal/qcom/tsens-8974.c | 1 + drivers/thermal/qcom/tsens-v2.c | 2 ++ drivers/thermal/qcom/tsens.c | 3 +++ drivers/thermal/qcom/tsens.h | 9 +++++++++ 5 files changed, 16 insertions(+) -- 2.17.1 Reviewed-by: Bjorn Andersson diff --git a/drivers/thermal/qcom/tsens-8916.c b/drivers/thermal/qcom/tsens-8916.c index c4955c85e922..c6dd620ac029 100644 --- a/drivers/thermal/qcom/tsens-8916.c +++ b/drivers/thermal/qcom/tsens-8916.c @@ -100,5 +100,6 @@ static const struct tsens_ops ops_8916 = { const struct tsens_data data_8916 = { .num_sensors = 5, .ops = &ops_8916, + .reg_offsets = { [SROT_CTRL_OFFSET] = 0x0 }, .hw_ids = (unsigned int []){0, 1, 2, 4, 5 }, }; diff --git a/drivers/thermal/qcom/tsens-8974.c b/drivers/thermal/qcom/tsens-8974.c index 7e149edbfeb6..3d3fda3d731b 100644 --- a/drivers/thermal/qcom/tsens-8974.c +++ b/drivers/thermal/qcom/tsens-8974.c @@ -232,4 +232,5 @@ static const struct tsens_ops ops_8974 = { const struct tsens_data data_8974 = { .num_sensors = 11, .ops = &ops_8974, + .reg_offsets = { [SROT_CTRL_OFFSET] = 0x0 }, }; diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index 1bdef92e4521..381a212872bf 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -68,10 +68,12 @@ static const struct tsens_ops ops_generic_v2 = { const struct tsens_data data_tsens_v2 = { .ops = &ops_generic_v2, + .reg_offsets = { [SROT_CTRL_OFFSET] = 0x4 }, }; /* Kept around for backward compatibility with old msm8996.dtsi */ const struct tsens_data data_8996 = { .num_sensors = 13, .ops = &ops_generic_v2, + .reg_offsets = { [SROT_CTRL_OFFSET] = 0x4 }, }; diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 9a8e8f7b4ae1..f1ec9bbe4717 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -144,6 +144,9 @@ static int tsens_probe(struct platform_device *pdev) else tmdev->sensor[i].hw_id = i; } + for (i = 0; i < REG_ARRAY_SIZE; i++) { + tmdev->reg_offsets[i] = data->reg_offsets[i]; + } if (!tmdev->ops || !tmdev->ops->init || !tmdev->ops->get_temp) return -EINVAL; diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index b9c4bcf255fa..7b7feee5dc46 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -48,15 +48,23 @@ struct tsens_ops { int (*get_trend)(struct tsens_device *, int, enum thermal_trend *); }; +enum reg_list { + SROT_CTRL_OFFSET, + + REG_ARRAY_SIZE, +}; + /** * struct tsens_data - tsens instance specific data * @num_sensors: Max number of sensors supported by platform * @ops: operations the tsens instance supports * @hw_ids: Subset of sensors ids supported by platform, if not the first n + * @reg_offsets: Register offsets for commonly used registers */ struct tsens_data { const u32 num_sensors; const struct tsens_ops *ops; + const u16 reg_offsets[REG_ARRAY_SIZE]; unsigned int *hw_ids; }; @@ -72,6 +80,7 @@ struct tsens_device { struct regmap *tm_map; struct regmap *srot_map; u32 tm_offset; + u16 reg_offsets[REG_ARRAY_SIZE]; struct tsens_context ctx; const struct tsens_ops *ops; struct tsens_sensor sensor[0]; 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[209.132.180.67]) by mx.google.com with ESMTP id b10-v6si574588pgi.416.2018.09.12.02.54.36; Wed, 12 Sep 2018 02:54:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CSmf9G95; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727968AbeILO6V (ORCPT + 13 others); Wed, 12 Sep 2018 10:58:21 -0400 Received: from mail-ed1-f68.google.com ([209.85.208.68]:34258 "EHLO mail-ed1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727957AbeILO6V (ORCPT ); Wed, 12 Sep 2018 10:58:21 -0400 Received: by mail-ed1-f68.google.com with SMTP id u1-v6so1278479eds.1 for ; Wed, 12 Sep 2018 02:54:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=DdplkWwuGrY04uo9ngGJyb9h118OGPlbF94r8PIE8s4=; b=CSmf9G958OeJacKZorMKFy+xTfe9oydbq9gNkUDPxEal8PbfyZIbPdS+kRrsaO6L9W hcgNfWG/KSkLOnbaAFEc3WEOCU6mew8ReFBr/J3Kz1VTe+N0GC1aAGrT7G9KJZNzg5GU rUTG8WJqrzg4xmXK3CpXlTfHE+FGN121H87gg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=DdplkWwuGrY04uo9ngGJyb9h118OGPlbF94r8PIE8s4=; b=Z7f6dlhHKNBBBjfFUxGG+uGmPoDOskjvsyLA/1VpR3l1b5iU/RkyQMqmuIwuqkxSsX xgKgVZ4bn60I0U/mJO5ahfv3x7R5mAUO5j0rlmjIgP9+/uU8CLTzvv5MUZgrzkbtYvYT xRxEc1TfX8yrzrhPnraZuuYf5m6n8eibtveaTzpDUXL+W8JOzV+QUCW/dG643FIbY38m iIVd3gauP8L0eeW2iJtLX/rg3Opsw005/1au0pJOAou0K4N8meb11OHpGnHN8kh+YFUG i/dBsft75G4VaY87S5paNQwUIymztQk1J+bibzhNAfcsIo9DP+m6F+Mq2CHrZQFRenqE SICA== X-Gm-Message-State: APzg51BtjGI/SLb0wFm5B/0fRuOepLGvNl+8i2hUZtFxp5WaIxBQVd8J o1V8mYh9SpTChJOwuiXX3XxBFw== X-Received: by 2002:a50:de8e:: with SMTP id c14-v6mr1757958edl.196.1536746073097; Wed, 12 Sep 2018 02:54:33 -0700 (PDT) Received: from localhost ([49.248.190.214]) by smtp.gmail.com with ESMTPSA id a19-v6sm482112edd.69.2018.09.12.02.54.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 12 Sep 2018 02:54:32 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: rnayak@codeaurora.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, smohanad@codeaurora.org, andy.gross@linaro.org, dianders@chromium.org, mka@chromium.org, David Brown , Rob Herring , Mark Rutland , linux-soc@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 10/16] arm64: dts: msm8916: thermal: split address space into two Date: Wed, 12 Sep 2018 15:22:55 +0530 Message-Id: <226a3b61f23f27d54b4dad390d6796b429fad837.1536744310.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We've earlier added support to split the register address space into TM and SROT regions. Split up the regmap address space into two for msm8916 that has a similar register layout. Since tsens-common.c/init_common() currently only registers one address space, the order is important (TM before SROT). This is OK since the code doesn't really use the SROT functionality yet. Signed-off-by: Amit Kucheria Reviewed-by: Matthias Kaehlcke --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 7b32b8990d62..6a277fce3333 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -761,9 +761,10 @@ }; }; - tsens: thermal-sensor@4a8000 { + tsens: thermal-sensor@4a9000 { compatible = "qcom,msm8916-tsens"; - reg = <0x4a8000 0x2000>; + reg = <0x4a9000 0x1000>, /* TM */ + <0x4a8000 0x1000>; /* SROT */ nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; nvmem-cell-names = "calib", "calib_sel"; #thermal-sensor-cells = <1>; From patchwork Wed Sep 12 09:52:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 146541 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp4619273ljw; Wed, 12 Sep 2018 02:55:01 -0700 (PDT) X-Google-Smtp-Source: ANB0Vda7CS77RqnEW1jsk+4vLl2Kaxbay265+DxLz1G+pW9xEUpg+XcNIBXpTsCYnB3Ld3U0KMks X-Received: by 2002:a63:c245:: with SMTP id l5-v6mr1257266pgg.255.1536746101319; Wed, 12 Sep 2018 02:55:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1536746101; cv=none; d=google.com; s=arc-20160816; b=gHai5b5gNEUBxsin6VSJWBkY9VoFjcy2JxdU30w5vPvuQY7nQSFJmUMKNR/anEXlel U9DoDYONTOFFgxtSssP5hPf9tvgXV2tKOHqBJ9iAqCzQLLxKbvy2BUJmCfk7zr8zCcK8 E9wrTIY78uw34Q+slV6phn/yTBVUBp5a4rAzcLwgYElitx+vKvLJIfC6vsUUGNO8WOLU r4LpaPxYSknoqwQ1sGsTJefP4ZL/cv1AdgDn1WbvNZFDRm5zh/yVLPZmWlF/ZJ63FY/l C//fJLdFs/EJG7cT7Tc3AfSaqqU6CriVgPsA9LqEc0LgFWBI5Y29ins1Px+/aUAw6v3Y SX3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=9bJ7qSAUU7/5UhkQH/j21Wuybl3ji2CUnJgoFpqPBH8=; b=k1hl0ObtJG3uhJ/cNDOOLsqtHbjh8nV8p7mj8DCppNopyI6EUT6wVeFslaGR01jGH2 I2KPwlPeYRFzwFQ7oyGmZN0mw+4oTg9puTnjEBrsTCQcSWIo70PxQ0ncjDIWyBejhI+k 2phiMgADMy2G8Q9vh9dvsYan2wZDXNJPh3e6IOsTHGwNeVP5S+zehpCnPL8qosofI2CF ZPZHDSA1V21wx5s6LANB2CorHMTraEPN0axGuI6Rifc89IQvdEK9MS52NEZZoFk2gtcg yvSufQHeE7zFZH2Tl3prnowd4MGj2rwvkSw3KMtI2Z4Rqh33z0Gtrvy2P9c5Q2SZlZkv Xz3A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="E78Z/icE"; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Amit Kucheria --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index be27d8dc9e6b..62f079ae9ba3 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -237,6 +237,26 @@ }; }; + gpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 2>; + + trips { + gpu_alert: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; cpu_opp_table: cpu_opp_table {