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Tue, 27 Jul 2021 22:18:10 +0000 From: Sean Anderson To: Peter Korsgaard , Peter Korsgaard , linux-serial@vger.kernel.org Cc: Greg Kroah-Hartman , Michal Simek , Shubhrajyoti Datta , Alexander Sverdlin , Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v2 1/4] dt-bindings: serial: uartlite: Convert to json-schema Date: Tue, 27 Jul 2021 18:17:37 -0400 Message-Id: <20210727221740.1997731-2-sean.anderson@seco.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210727221740.1997731-1-sean.anderson@seco.com> References: <20210727221740.1997731-1-sean.anderson@seco.com> X-ClientProxiedBy: MN2PR06CA0008.namprd06.prod.outlook.com (2603:10b6:208:23d::13) To DB7PR03MB4523.eurprd03.prod.outlook.com (2603:10a6:10:19::27) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from plantagenet.inhand.com (50.195.82.171) by MN2PR06CA0008.namprd06.prod.outlook.com (2603:10b6:208:23d::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4352.26 via Frontend Transport; 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Signed-off-by: Sean Anderson Reviewed-by: Rob Herring --- (no changes since v1) .../bindings/serial/xlnx,opb-uartlite.txt | 23 -------- .../bindings/serial/xlnx,opb-uartlite.yaml | 53 +++++++++++++++++++ 2 files changed, 53 insertions(+), 23 deletions(-) delete mode 100644 Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt create mode 100644 Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml diff --git a/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt b/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt deleted file mode 100644 index c37deb44dead..000000000000 --- a/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.txt +++ /dev/null @@ -1,23 +0,0 @@ -Xilinx Axi Uartlite controller Device Tree Bindings ---------------------------------------------------------- - -Required properties: -- compatible : Can be either of - "xlnx,xps-uartlite-1.00.a" - "xlnx,opb-uartlite-1.00.b" -- reg : Physical base address and size of the Axi Uartlite - registers map. -- interrupts : Should contain the UART controller interrupt. - -Optional properties: -- port-number : Set Uart port number -- clock-names : Should be "s_axi_aclk" -- clocks : Input clock specifier. Refer to common clock bindings. - -Example: -serial@800c0000 { - compatible = "xlnx,xps-uartlite-1.00.a"; - reg = <0x0 0x800c0000 0x10000>; - interrupts = <0x0 0x6e 0x1>; - port-number = <0>; -}; diff --git a/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml b/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml new file mode 100644 index 000000000000..4ef29784ae97 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/xlnx,opb-uartlite.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Axi Uartlite + +maintainers: + - Peter Korsgaard + +properties: + compatible: + contains: + enum: + - xlnx,xps-uartlite-1.00.a + - xlnx,opb-uartlite-1.00.b + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + port-number: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Set Uart port number + + clocks: + maxItems: 1 + + clock-names: + const: s_axi_aclk + +required: + - compatible + - reg + - interrupts + +allOf: + - $ref: /schemas/serial.yaml# + +additionalProperties: true + +examples: + - | + serial@800c0000 { + compatible = "xlnx,xps-uartlite-1.00.a"; + reg = <0x800c0000 0x10000>; + interrupts = <0x0 0x6e 0x1>; + port-number = <0>; + }; +... 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Tue, 27 Jul 2021 22:18:12 +0000 From: Sean Anderson To: Peter Korsgaard , Peter Korsgaard , linux-serial@vger.kernel.org Cc: Greg Kroah-Hartman , Michal Simek , Shubhrajyoti Datta , Alexander Sverdlin , Sean Anderson , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v2 2/4] dt-bindings: serial: uartlite: Add properties for synthesis-time parameters Date: Tue, 27 Jul 2021 18:17:38 -0400 Message-Id: <20210727221740.1997731-3-sean.anderson@seco.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210727221740.1997731-1-sean.anderson@seco.com> References: <20210727221740.1997731-1-sean.anderson@seco.com> X-ClientProxiedBy: MN2PR06CA0008.namprd06.prod.outlook.com (2603:10b6:208:23d::13) To DB7PR03MB4523.eurprd03.prod.outlook.com (2603:10a6:10:19::27) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from plantagenet.inhand.com (50.195.82.171) by MN2PR06CA0008.namprd06.prod.outlook.com (2603:10b6:208:23d::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4352.26 via Frontend Transport; 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Many parameters, such as baud rate, data bits, and the presence of a parity bit are configured before synthesis and may not be changed (or discovered) at runtime. However, we must know what these settings are in order to properly calculate the uart timeout (and to inform the user about the actual baud of the uart). These properties are present for out-of-tree bindings generated by Xilinx's tools. However, they are also (mostly) present in in-tree bindings. I chose current-speed over xlnx,baudrate primarily because it seemed to be used by more existing bindings. Although these properties are marked as "required", note that only current-speed is required by the driver itself. Hopefully, this will allow for an easier transition. Signed-off-by: Sean Anderson --- (no changes since v1) .../bindings/serial/xlnx,opb-uartlite.yaml | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml b/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml index 4ef29784ae97..28859e70e60f 100644 --- a/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml +++ b/Documentation/devicetree/bindings/serial/xlnx,opb-uartlite.yaml @@ -32,13 +32,49 @@ properties: clock-names: const: s_axi_aclk + current-speed: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The fixed baud rate that the device was configured for. + + xlnx,data-bits: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [5, 6, 7, 8] + default: 8 + description: + The fixed number of data bits that the device was configured for. + + xlnx,use-parity: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + default: 0 + description: + Whether parity checking was enabled when the device was configured. + + xlnx,odd-parity: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + Whether odd parity was configured. + required: - compatible - reg - interrupts + - current-speed + - xlnx,data-bits + - xlnx,use-parity allOf: - $ref: /schemas/serial.yaml# + - if: + properties: + xlnx,use-parity: + contains: + const: 1 + then: + required: + - xlnx,odd-parity additionalProperties: true @@ -49,5 +85,8 @@ examples: reg = <0x800c0000 0x10000>; interrupts = <0x0 0x6e 0x1>; port-number = <0>; + current-speed = <115200>; + xlnx,data-bits = <8>; + xlnx,use-parity = <0>; }; ... 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Tue, 27 Jul 2021 22:18:14 +0000 From: Sean Anderson To: Peter Korsgaard , Peter Korsgaard , linux-serial@vger.kernel.org Cc: Greg Kroah-Hartman , Michal Simek , Shubhrajyoti Datta , Alexander Sverdlin , Sean Anderson , Rich Felker , Yoshinori Sato Subject: [PATCH v2 3/4] sh: j2: Update uartlite binding with data and parity properties Date: Tue, 27 Jul 2021 18:17:39 -0400 Message-Id: <20210727221740.1997731-4-sean.anderson@seco.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210727221740.1997731-1-sean.anderson@seco.com> References: <20210727221740.1997731-1-sean.anderson@seco.com> X-ClientProxiedBy: MN2PR06CA0008.namprd06.prod.outlook.com (2603:10b6:208:23d::13) To DB7PR03MB4523.eurprd03.prod.outlook.com (2603:10a6:10:19::27) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from plantagenet.inhand.com (50.195.82.171) by MN2PR06CA0008.namprd06.prod.outlook.com (2603:10b6:208:23d::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4352.26 via Frontend Transport; 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I inspected the J2 source code, and believe these values to be correct. Signed-off-by: Sean Anderson --- (no changes since v1) arch/sh/boot/dts/j2_mimas_v2.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/sh/boot/dts/j2_mimas_v2.dts b/arch/sh/boot/dts/j2_mimas_v2.dts index 9f4742fab329..fa9562f78d53 100644 --- a/arch/sh/boot/dts/j2_mimas_v2.dts +++ b/arch/sh/boot/dts/j2_mimas_v2.dts @@ -88,6 +88,8 @@ uart0: serial@100 { clock-frequency = <125000000>; compatible = "xlnx,xps-uartlite-1.00.a"; current-speed = <19200>; + xlnx,use-parity = <0>; + xlnx,data-bits = <8>; device_type = "serial"; interrupts = <0x12>; port-number = <0>; From patchwork Tue Jul 27 22:17:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Anderson X-Patchwork-Id: 487202 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MSGID_FROM_MTA_HEADER, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 824CCC4338F for ; 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dkim=none (message not signed) header.d=none; barco.com; dmarc=none action=none header.from=seco.com; Received: from DB7PR03MB4523.eurprd03.prod.outlook.com (2603:10a6:10:19::27) by DBBPR03MB5141.eurprd03.prod.outlook.com (2603:10a6:10:f4::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4352.29; Tue, 27 Jul 2021 22:18:15 +0000 Received: from DB7PR03MB4523.eurprd03.prod.outlook.com ([fe80::dc6c:815b:2062:d1f1]) by DB7PR03MB4523.eurprd03.prod.outlook.com ([fe80::dc6c:815b:2062:d1f1%7]) with mapi id 15.20.4352.032; Tue, 27 Jul 2021 22:18:15 +0000 From: Sean Anderson To: Peter Korsgaard , Peter Korsgaard , linux-serial@vger.kernel.org Cc: Greg Kroah-Hartman , Michal Simek , Shubhrajyoti Datta , Alexander Sverdlin , Sean Anderson Subject: [PATCH v2 4/4] tty: serial: uartlite: Prevent changing fixed parameters Date: Tue, 27 Jul 2021 18:17:40 -0400 Message-Id: <20210727221740.1997731-5-sean.anderson@seco.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210727221740.1997731-1-sean.anderson@seco.com> References: <20210727221740.1997731-1-sean.anderson@seco.com> X-ClientProxiedBy: MN2PR06CA0008.namprd06.prod.outlook.com (2603:10b6:208:23d::13) To DB7PR03MB4523.eurprd03.prod.outlook.com (2603:10a6:10:19::27) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from plantagenet.inhand.com (50.195.82.171) by MN2PR06CA0008.namprd06.prod.outlook.com (2603:10b6:208:23d::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4352.26 via Frontend Transport; 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Disable "changing" these settings to prevent their termios from diverging from the actual state of the uart. To inform users of these limitations, warn if the new termios change these parameters. We only do this once to avoid spamming the log. These warnings are inspired by those in the sifive driver. In order to determine the correct parameters to enforce, we read the various new devicetree parameters to discover how the uart was configured when it was synthesized. The defaults match ulite_console_setup. xlnx,use-parity, xlnx,odd-parity, and xlnx,data-bits are optional since there were in-tree users (and presumably out-of-tree users) who did not set them. Signed-off-by: Sean Anderson --- Changes in v2: - Compare the baud computed with uart_get_baud_rate to pdata->baud, instead of just checking c_cflag. This will catch anything that messes with ispeed and ospeed. - Don't bother trying to set the initial termios. Instead, just skip warning if old is NULL. - Because we no longer use uart_set_options, just convert the devicetree properties directly to clflags. - Merge with [PATCH 4/5] ("tty: serial: uartlite: Initialize termios with fixed synthesis parameters") to make it clearer what the properties we read are being used for. drivers/tty/serial/uartlite.c | 120 ++++++++++++++++++++++++++++++---- 1 file changed, 109 insertions(+), 11 deletions(-) diff --git a/drivers/tty/serial/uartlite.c b/drivers/tty/serial/uartlite.c index f42ccc40ffa6..87804abd436f 100644 --- a/drivers/tty/serial/uartlite.c +++ b/drivers/tty/serial/uartlite.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -60,9 +61,18 @@ static struct uart_port *console_port; #endif +/** + * struct uartlite_data: Driver private data + * reg_ops: Functions to read/write registers + * clk: Our parent clock, if present + * baud: The baud rate configured when this device was synthesized + * cflags: The cflags for parity and data bits + */ struct uartlite_data { const struct uartlite_reg_ops *reg_ops; struct clk *clk; + unsigned int baud; + tcflag_t cflags; }; struct uartlite_reg_ops { @@ -116,6 +126,8 @@ static inline void uart_out32(u32 val, u32 offset, struct uart_port *port) static struct uart_port ulite_ports[ULITE_NR_UARTS]; +static struct uart_driver ulite_uart_driver; + /* --------------------------------------------------------------------- * Core UART driver operations */ @@ -303,7 +315,42 @@ static void ulite_set_termios(struct uart_port *port, struct ktermios *termios, struct ktermios *old) { unsigned long flags; - unsigned int baud; + struct uartlite_data *pdata = port->private_data; + tcflag_t old_cflag; + + /* + * If old is NULL then we're being set up for the first time + * (before any user has touched the termios), so don't warn + * about unsupported features. + */ + if (old && termios->c_iflag & BRKINT) + dev_err_once(port->dev, "BREAK detection not supported\n"); + termios->c_iflag &= ~BRKINT; + + if (old && termios->c_cflag & CSTOPB && old) + dev_err_once(port->dev, "only one stop bit supported\n"); + termios->c_cflag &= ~CSTOPB; + + old_cflag = termios->c_cflag; + termios->c_cflag &= ~(PARENB | PARODD); + termios->c_cflag |= pdata->cflags & (PARENB | PARODD); + if (old && termios->c_cflag != old_cflag) + dev_err_once(port->dev, "only '%c' parity supported\n", + pdata->cflags & PARODD ? 'o' : + pdata->cflags & PARENB ? 'e' : 'n'); + + old_cflag = termios->c_cflag; + termios->c_cflag &= ~CSIZE; + termios->c_cflag |= pdata->cflags & CSIZE; + if (old && termios->c_cflag != old_cflag) + dev_err_once(port->dev, "only %d data bits supported\n", + FIELD_GET(CSIZE, pdata->cflags) + 5); + + if (old && + pdata->baud != uart_get_baud_rate(port, termios, old, 0, 460800)) + dev_err_once(port->dev, "only %d baud supported\n", + pdata->baud); + tty_termios_encode_baud_rate(termios, pdata->baud, pdata->baud); spin_lock_irqsave(&port->lock, flags); @@ -326,8 +373,7 @@ static void ulite_set_termios(struct uart_port *port, struct ktermios *termios, | ULITE_STATUS_FRAME | ULITE_STATUS_OVERRUN; /* update timeout */ - baud = uart_get_baud_rate(port, termios, old, 0, 460800); - uart_update_timeout(port, termios->c_cflag, baud); + uart_update_timeout(port, termios->c_cflag, pdata->baud); spin_unlock_irqrestore(&port->lock, flags); } @@ -532,8 +578,6 @@ static int ulite_console_setup(struct console *co, char *options) return uart_set_options(port, co, baud, parity, bits, flow); } -static struct uart_driver ulite_uart_driver; - static struct console ulite_console = { .name = ULITE_NAME, .write = ulite_console_write, @@ -756,18 +800,72 @@ static int ulite_probe(struct platform_device *pdev) struct uartlite_data *pdata; int irq, ret; int id = pdev->id; -#ifdef CONFIG_OF - const __be32 *prop; - prop = of_get_property(pdev->dev.of_node, "port-number", NULL); - if (prop) - id = be32_to_cpup(prop); -#endif pdata = devm_kzalloc(&pdev->dev, sizeof(struct uartlite_data), GFP_KERNEL); if (!pdata) return -ENOMEM; + if (IS_ENABLED(CONFIG_OF)) { + const char *prop; + struct device_node *np = pdev->dev.of_node; + u32 val; + + prop = "port-number"; + ret = of_property_read_u32(np, prop, &id); + if (ret && ret != -EINVAL) +of_err: + return dev_err_probe(&pdev->dev, ret, + "could not read %s\n", prop); + + prop = "current-speed"; + ret = of_property_read_u32(np, prop, &pdata->baud); + if (ret) + goto of_err; + + prop = "xlnx,use-parity"; + ret = of_property_read_u32(np, prop, &val); + if (ret && ret != -EINVAL) + goto of_err; + + if (val) { + prop = "xlnx,odd-parity"; + ret = of_property_read_u32(np, prop, &val); + if (ret) + goto of_err; + + if (val) + pdata->cflags |= PARODD; + pdata->cflags |= PARENB; + } + + prop = "xlnx,data-bits"; + ret = of_property_read_u32(np, prop, &val); + if (ret && ret != -EINVAL) + goto of_err; + + switch (val) { + case 5: + pdata->cflags |= CS5; + break; + case 6: + pdata->cflags |= CS6; + break; + case 7: + pdata->cflags |= CS7; + break; + case 8: + pdata->cflags |= CS8; + break; + default: + return dev_err_probe(&pdev->dev, -EINVAL, + "bad data bits %d\n", val); + } + } else { + pdata->baud = 9600; + pdata->cflags = CS8; + } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) return -ENODEV;