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[204.210.126.223]) by smtp.gmail.com with ESMTPSA id v23sm6904754pje.33.2021.07.23.13.33.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jul 2021 13:33:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 1/3] target/arm: Correctly bound length in sve_zcr_get_valid_len Date: Fri, 23 Jul 2021 10:33:42 -1000 Message-Id: <20210723203344.968563-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210723203344.968563-1-richard.henderson@linaro.org> References: <20210723203344.968563-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently, our only caller is sve_zcr_len_for_el, which has already masked the length extracted from ZCR_ELx, so the masking done here is a nop. But we will shortly have uses from other locations, where the length will be unmasked. Saturate the length to ARM_MAX_VQ instead of truncating to the low 4 bits. Signed-off-by: Richard Henderson --- target/arm/helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/target/arm/helper.c b/target/arm/helper.c index 0c07ca9837..8c1d8dbce3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6461,7 +6461,9 @@ static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) { uint32_t end_len; - end_len = start_len &= 0xf; + start_len = MIN(start_len, ARM_MAX_VQ - 1); + end_len = start_len; + if (!test_bit(start_len, cpu->sve_vq_map)) { end_len = find_last_bit(cpu->sve_vq_map, start_len); assert(end_len < start_len); From patchwork Fri Jul 23 20:33:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 484669 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp1666413jao; Fri, 23 Jul 2021 13:34:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwawWNDP4MDvYyvxxju66NYQB9+W0AwHbJQuX0yTU3gXPbqTKTQn1u4spwrmga0A6KMwrZu X-Received: by 2002:ab0:7216:: with SMTP id u22mr6553363uao.48.1627072486462; Fri, 23 Jul 2021 13:34:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627072486; cv=none; d=google.com; s=arc-20160816; b=jv1cPfeVPlVZQH0OVlJCLH72ME44KFeof+OltM92WhgleUeXa/lLJjQ0Y+6xiPCL8R dv3vnvZuXWUUQmvfiGLLdtwlNAOjNOFaqEF2g8V/oe3luF1Y9EV42LioIHagv+ZNR6DF 1lrGeGVi3iCSnEoVpXvWeZqMjo4mogHRCA2SJB9+gX7/NxTgSwI11IhClNQ6fAvxCePk jEinGpdUUjQShK+g4p+V6TGEj7bkjYdbwRZJZLQmie5MKaqe0o5sQqh08GNs8hektwsl AabEFvz5Zb7CqBw5dKauOETl7zK1sYM8mN7PPTDeZjQfzPsQ8zt8FJuNKWN+tvhRkh04 kjCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=n9uTWLvP9aAyzR+j1L+0x/gEwZ6THJXYrmtdZc8mvi8=; b=fEoaZiH6Grdud0N4uzjhc4fY/1AQzOtaGN2TOCohgRElmviBaViBqlGF/31nQNzjH2 sbXiR3Msrdrs6zAzLutMpOBYD7UxNkbFlZyYkXlT4y/w+7DgRT4gjWMHl30CWVey5Ahc 5x9EygeoKl/CNMSmR9N9jIG0EhIYjJd9Il+RoDZavZ2lGeDwoLTIiVbmu3rCr2VlrjHk 1BezR5eOhQ698GUZi1hvfKIv9ANCbNg4uR8UJmHZvTd2edC2eQspaXKMiOJ53dIiLXwU LAePvUsNgVwTBD1F6ylaHnqDamEEXiOPMzMxNDsUPDDP+9wVTdYHq3Fj2LAyh5+Ex9/a B1Tw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MoP1hGqP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[204.210.126.223]) by smtp.gmail.com with ESMTPSA id v23sm6904754pje.33.2021.07.23.13.33.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jul 2021 13:33:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 2/3] target/arm: Export aarch64_sve_zcr_get_valid_len Date: Fri, 23 Jul 2021 10:33:43 -1000 Message-Id: <20210723203344.968563-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210723203344.968563-1-richard.henderson@linaro.org> References: <20210723203344.968563-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rename from sve_zcr_get_valid_len and make accessible from outside of helper.c. Signed-off-by: Richard Henderson --- target/arm/internals.h | 10 ++++++++++ target/arm/helper.c | 4 ++-- 2 files changed, 12 insertions(+), 2 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/target/arm/internals.h b/target/arm/internals.h index 11a72013f5..cd2ea8a388 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -177,6 +177,16 @@ void arm_translate_init(void); void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); #endif /* CONFIG_TCG */ +/** + * aarch64_sve_zcr_get_valid_len: + * @cpu: cpu context + * @start_len: maximum len to consider + * + * Return the maximum supported sve vector length <= @start_len. + * Note that both @start_len and the return value are in units + * of ZCR_ELx.LEN, so the vector bit length is (x + 1) * 128. + */ +uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len); enum arm_fprounding { FPROUNDING_TIEEVEN, diff --git a/target/arm/helper.c b/target/arm/helper.c index 8c1d8dbce3..155d8bf239 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6457,7 +6457,7 @@ int sve_exception_el(CPUARMState *env, int el) return 0; } -static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) +uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) { uint32_t end_len; @@ -6489,7 +6489,7 @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); } - return sve_zcr_get_valid_len(cpu, zcr_len); + return aarch64_sve_zcr_get_valid_len(cpu, zcr_len); } static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, From patchwork Fri Jul 23 20:33:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 484670 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp1667648jao; Fri, 23 Jul 2021 13:36:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzE+E3GTnc1BcmFnNWWeW5TotHAVXVTwIpHUwL3qFMk2dem6CX9znrJ28LWOxA/xR46eOfb X-Received: by 2002:ab0:42d:: with SMTP id 42mr6537823uav.63.1627072615628; Fri, 23 Jul 2021 13:36:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1627072615; cv=none; d=google.com; s=arc-20160816; b=meaB0DwmjRdSENKa4G90sovT+rDQIg2aYHeGk+2DkTn15hUAfrZI5WAJdWTSPdgjQN INwU8x1H1c24aCQA/8JZ7Ook8VVp1NjRiOw7hUTnJHXXEJVke+vvSgTR9gezanSXC0N0 ibeHP4KX2uXL73Zzf6VV1i9ejZQXxIm5V+JDQkkTF0iP2KiWr4LWGU+wX1havRkO0kwz oJ3stlVJkvf9f2GwNoDieT0iRm4hcwVsTRRAVEy6R4gLlA0yPtyNYBkmuUrE6/gAbsKI GW3rVNe2n6FJkDaH1ZcnOi01uXISpCW0jWy1/OKYuC8KUYGRIiyvybHUwoy4H6PCb7k5 zRDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=0quSyCi9kfxfY1A8lHcxgbeKm6SRDXR67Drrk/c6Yu4=; b=X5mjjXUVKSPTFwgiRvaNPlDoV3thOJbTwgKfQ0o0qLCvrlFagdMc9hB9fr1SFze6+e A5s3kblBPiAyrQRJb8kkVFClDzMH+1i+tOSuI2u3oSltgwmKWnNYLB4liAA2u5LcR/YF HNQZW4ZzwbOGCBCUT5ZRxGCCGs1w8ODpW6kkZGkaeMtH0WjlhouyFCPjHO4fFJOTZkyM IZo9+NT5VzvSVVqdcH4ux8EQo2FzI4EJf4kPedGPfHcEMlAGGhorX3m1FpxZWhmM5pzE bEEcpgM0VaDLQno2wuOrWBdEgKOsIpXs6Eik6MiZL4kpoT/2nc7pxiH6NY/B1QfQdVnn Y/zg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OSBpaMGh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[204.210.126.223]) by smtp.gmail.com with ESMTPSA id v23sm6904754pje.33.2021.07.23.13.33.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Jul 2021 13:33:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 3/3] target/arm: Add sve-default-vector-length cpu property Date: Fri, 23 Jul 2021 10:33:44 -1000 Message-Id: <20210723203344.968563-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210723203344.968563-1-richard.henderson@linaro.org> References: <20210723203344.968563-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Mirror the behavour of /proc/sys/abi/sve_default_vector_length under the real linux kernel. We have no way of passing along a real default across exec like the kernel can, but this is a decent way of adjusting the startup vector length of a process. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/482 Signed-off-by: Richard Henderson --- docs/system/arm/cpu-features.rst | 11 ++++++ target/arm/cpu.h | 5 +++ target/arm/cpu.c | 14 ++++++-- target/arm/cpu64.c | 60 ++++++++++++++++++++++++++++++++ 4 files changed, 88 insertions(+), 2 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst index c455442eaf..4ff36cc83f 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -376,3 +376,14 @@ verbose command lines. However, the recommended way to select vector lengths is to explicitly enable each desired length. Therefore only example's (1), (4), and (6) exhibit recommended uses of the properties. +SVE User-mode Default Vector Length Property +-------------------------------------------- + +For qemu-aarch64, the cpu property `sve-default-vector-length=N` is +defined to mirror the Linux kernel parameter file +`/proc/sys/abi/sve_default_vector_length`. The default length, `N`, +is in units of bytes and must be between 16 and 8192. +If not specified, the default vector length is 64. + +If the default length is larger than the maximum vector length enabled +with `sve` properties, the actual vector length will be reduced. diff --git a/target/arm/cpu.h b/target/arm/cpu.h index be9a4dceae..9f0a5f84d5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1006,6 +1006,11 @@ struct ARMCPU { /* Used to set the maximum vector length the cpu will support. */ uint32_t sve_max_vq; +#ifdef CONFIG_USER_ONLY + /* Used to set the default vector length at process start. */ + uint32_t sve_default_vq; +#endif + /* * In sve_vq_map each set bit is a supported vector length of * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 752b15bb79..2866dd7658 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -201,7 +201,8 @@ static void arm_cpu_reset(DeviceState *dev) env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); /* with reasonable vector length */ if (cpu_isar_feature(aa64_sve, cpu)) { - env->vfp.zcr_el[1] = MIN(cpu->sve_max_vq - 1, 3); + env->vfp.zcr_el[1] = + aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1); } /* * Enable TBI0 but not TBI1. @@ -1051,7 +1052,16 @@ static void arm_cpu_initfn(Object *obj) QLIST_INIT(&cpu->pre_el_change_hooks); QLIST_INIT(&cpu->el_change_hooks); -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY +# ifdef TARGET_AARCH64 + /* + * The linux kernel defaults to 512-bit vectors, when sve is supported. + * See documentation for /proc/sys/abi/sve_default_vector_length, and + * our corresponding sve-default-vector-length cpu property. + */ + cpu->sve_default_vq = 4; +# endif +#else /* Our inbound IRQ and FIQ lines */ if (kvm_enabled()) { /* VIRQ and VFIQ are unused with KVM but we add them to maintain diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c7a1626bec..c690318a9b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -559,6 +559,59 @@ static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) cpu->isar.id_aa64pfr0 = t; } +#ifdef CONFIG_USER_ONLY +/* Mirror linux /proc/sys/abi/sve_default_vector_length. */ +static void cpu_arm_set_sve_default_vec_len(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + int32_t default_len, default_vq, remainder; + + if (!visit_type_int32(v, name, &default_len, errp)) { + return; + } + + /* Undocumented, but the kernel allows -1 to indicate "maximum". */ + if (default_len == -1) { + cpu->sve_default_vq = ARM_MAX_VQ; + return; + } + + default_vq = default_len / 16; + remainder = default_len % 16; + + /* + * Note that the 512 max comes from include/uapi/asm/sve_context.h + * and is the maximum architectural width of ZCR_ELx.LEN. + */ + if (remainder || default_vq < 1 || default_vq > 512) { + error_setg(errp, "cannot set sve-default-vector-length"); + if (remainder) { + error_append_hint(errp, "Vector length not a multiple of 16\n"); + } else if (default_vq < 1) { + error_append_hint(errp, "Vector length smaller than 16\n"); + } else { + error_append_hint(errp, "Vector length larger than %d\n", + 512 * 16); + } + return; + } + + cpu->sve_default_vq = default_vq; +} + +static void cpu_arm_get_sve_default_vec_len(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + int32_t value = cpu->sve_default_vq * 16; + + visit_type_int32(v, name, &value, errp); +} +#endif + void aarch64_add_sve_properties(Object *obj) { uint32_t vq; @@ -571,6 +624,13 @@ void aarch64_add_sve_properties(Object *obj) object_property_add(obj, name, "bool", cpu_arm_get_sve_vq, cpu_arm_set_sve_vq, NULL, NULL); } + +#ifdef CONFIG_USER_ONLY + /* Mirror linux /proc/sys/abi/sve_default_vector_length. */ + object_property_add(obj, "sve-default-vector-length", "int32", + cpu_arm_get_sve_default_vec_len, + cpu_arm_set_sve_default_vec_len, NULL, NULL); +#endif } void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)