From patchwork Wed May 17 14:46:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 99998 Delivered-To: patch@linaro.org Received: by 10.182.142.97 with SMTP id rv1csp254351obb; Wed, 17 May 2017 07:54:27 -0700 (PDT) X-Received: by 10.99.163.67 with SMTP id v3mr4420252pgn.210.1495032867324; Wed, 17 May 2017 07:54:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495032867; cv=none; d=google.com; s=arc-20160816; b=BGMnCQhP5gTcrvsGAhAixEgonUkSC2yRf4LPkCPXUwNfyzthPz+rWGlTVEVd2JaxR7 demnJEXcUaF97haSlW57cQ7i0hMcFyI8+NV5U23/E5VVbrzHT21g27nqTY37pJ3kpRLz WVzuOBVfInVTnQZ2EGUTWu3EWDzpA1Jv4+Q46rpHdMDd2K8muR2hc3kWuWMTTJCpCEpr 5+Oabmw1bbCbEluzztkwZkSL1u4Hy2t1CILkUm+BvK7mrAy3+yfsjirHad/Udd4m8Sow rhf9x1UgZR7JEmj0cjTnP+V3Jb0NcGOT08xRRAFRNjIVnjgvRN2JGtX+qYjQs6uslrnc qCWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=P/SXHXtpSNKmegsO3zZ6zNzqgxjr0cjgMVGHKFOUgcg=; b=whHmAxRJj/RIhPfLMvGq5XnrY1ZaQ07Jh4e+Wzb999DVFTObu+945UUsaVhlqfRhni SCaZUzN2P2dOiNS3IbRtujRAuRV6eqfnK19LlnjH+iZMBMZZ2Lz/qcpVRYE3u1ann2rQ iDb5Ykt3oJAaKmtBi5IT+dHY9+AQEFLLQUoWY3b1ZVanmL0NfgwNoCBz6qEgQoduwn0p O3dw2dKAUj8c8VBrUi/ou7ZkEcFMaX+f8uAg8zMXESAMPPNR2GksezuxFaPcIxwT2Yqj F1fFoqhZXlL+f2mqPI+N1kM90dt8faolc+1/1nKAnhBR3hcPKdLaQR50iChhBT3puAV6 NuOQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 88si2494821plf.60.2017.05.17.07.54.27; Wed, 17 May 2017 07:54:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754898AbdEQOyL (ORCPT + 6 others); Wed, 17 May 2017 10:54:11 -0400 Received: from mout.kundenserver.de ([217.72.192.74]:60775 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754468AbdEQOrv (ORCPT ); Wed, 17 May 2017 10:47:51 -0400 Received: from wuerfel.lan ([78.42.17.5]) by mrelayeu.kundenserver.de (mreue102 [212.227.15.145]) with ESMTPA (Nemesis) id 0LnBK1-1dcwek0pqv-00hM7g; Wed, 17 May 2017 16:47:23 +0200 From: Arnd Bergmann To: linux-wireless Cc: Arnd Bergmann , Stanislaw Gruszka , David Miller , Helmut Schaa , Kalle Valo , Daniel Golle , Mathias Kresin , Johannes Berg , Serge Vasilugin , Roman Yeryomin , Networking , Linux Kernel Mailing List , Jes Sorensen , Tom Psyborg Subject: [PATCH v2 03/10] rt2x00: convert rt2x00_rf_read return type Date: Wed, 17 May 2017 16:46:55 +0200 Message-Id: <20170517144702.1381136-4-arnd@arndb.de> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170517144702.1381136-1-arnd@arndb.de> References: <20170517144702.1381136-1-arnd@arndb.de> X-Provags-ID: V03:K0:ooiFlY7mZMvfcVDfjOd2mtF147ZczWT6sJqHJ96um9qTB6nCVh7 djNHqFj/e/u9TnywTBB5OjcTZaEyae/yYaKTgxw3/1Qy0VbPlGCmUJ92ugkagiD3JffyXBz wcKA2ZPCHET4chmqO/o3i9ShAlDIj2TwRg6rSZoal3YwOj7G2HNg4Flbv81DzlHrfJhkFQH CaP/t44bppbDno7uGbuRg== X-UI-Out-Filterresults: notjunk:1; V01:K0:1jebCT/XWgQ=:urHG/eMQMUYKw4IWoYY9QY Fp+QMlGa7DFrVMgEQ8NhTmO6SphOtYm3rtdsJtx1FyRJ33yglsdtKkXutvxdP9YUQdFZWf1Pj iCV8XgGFQqSBbPAcesTsaST30NeNN0Qt4ygcgq0CJMsJvefPhLQIarNZ8Cbyx4Do7gRddNYFf kJoNgWeATi+5Eja6gNtOtgeYWeNJVJ0kTnsSZgihtKA05Hh09qLaKMUUpVqbOD6z5/6yG9o7E OQCSblonihgtoUiQh8ErMaTaEaAsTWTEaQn+dbTYlzMuOK8KjCLOe1nQBP4ZUrDPwPk1ktuLf KI6ZEHw+Dgu74tE0jbUqVcWiAwHdSFaKxFCKagp9jvCm1NDNsiAbX9psfdSbqONz19LPGg7Gg Owdc4ZvUZEforHEEhKMFB8WGDCcFMYGm6aeMQrGRmM0MCepOm4SLGp/Tha3+ViX4QsE9sZd0G bMOz2IENk8Xkpm7k7O9qUouAtdzKLttFyhP84YBIu2ChEuntfTcnATuk7tlpvdAYZH0NE8i5N N1YCtQm2qny4Q3z4xZCx5eLhor8uJAwldla7WEHSkezjETmpr6SoI0IBiQPxeSajo5lOfhMLU YfFwz8eyp+uA+O0FmODjhmPT1OQKp6sNLi6KYuTbL//bqIQgxOTo4NJcVKLGlfUGOmrzY6cH2 wIT0LBSDAt8IogAQRQiA9Jl9knwxeBI+LAy2a/yXn5W4Xqmaf9tYojaG3ILXeCKpQXig= Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This is a semi-automated conversion to change rt2x00_rf_read() to return the register contents instead of passing them by value, resulting in much better object code. The majority of the patch was done using: sed -i 's:\(\(.*, .*\), &\(.*\));:\2 = \1);:' \ drivers/net/wireless/ralink/rt2x00/rt* Signed-off-by: Arnd Bergmann --- drivers/net/wireless/ralink/rt2x00/rt2400pci.c | 2 +- drivers/net/wireless/ralink/rt2x00/rt2500pci.c | 4 ++-- drivers/net/wireless/ralink/rt2x00/rt2500usb.c | 4 ++-- drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 2 +- drivers/net/wireless/ralink/rt2x00/rt2x00.h | 11 ++--------- drivers/net/wireless/ralink/rt2x00/rt61pci.c | 10 +++++----- drivers/net/wireless/ralink/rt2x00/rt73usb.c | 10 +++++----- 7 files changed, 18 insertions(+), 25 deletions(-) -- 2.9.0 diff --git a/drivers/net/wireless/ralink/rt2x00/rt2400pci.c b/drivers/net/wireless/ralink/rt2x00/rt2400pci.c index 3ba9a1674e1d..d41832292db2 100644 --- a/drivers/net/wireless/ralink/rt2x00/rt2400pci.c +++ b/drivers/net/wireless/ralink/rt2x00/rt2400pci.c @@ -199,7 +199,7 @@ static const struct rt2x00debug rt2400pci_rt2x00debug = { .word_count = BBP_SIZE / sizeof(u8), }, .rf = { - .read = _rt2x00_rf_read, + .read = rt2x00_rf_read, .write = rt2400pci_rf_write, .word_base = RF_BASE, .word_size = sizeof(u32), diff --git a/drivers/net/wireless/ralink/rt2x00/rt2500pci.c b/drivers/net/wireless/ralink/rt2x00/rt2500pci.c index d9b061b73e83..232feba0773f 100644 --- a/drivers/net/wireless/ralink/rt2x00/rt2500pci.c +++ b/drivers/net/wireless/ralink/rt2x00/rt2500pci.c @@ -199,7 +199,7 @@ static const struct rt2x00debug rt2500pci_rt2x00debug = { .word_count = BBP_SIZE / sizeof(u8), }, .rf = { - .read = _rt2x00_rf_read, + .read = rt2x00_rf_read, .write = rt2500pci_rf_write, .word_base = RF_BASE, .word_size = sizeof(u32), @@ -556,7 +556,7 @@ static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev, { u32 rf3; - rt2x00_rf_read(rt2x00dev, 3, &rf3); + rf3 = rt2x00_rf_read(rt2x00dev, 3); rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); rt2500pci_rf_write(rt2x00dev, 3, rf3); } diff --git a/drivers/net/wireless/ralink/rt2x00/rt2500usb.c b/drivers/net/wireless/ralink/rt2x00/rt2500usb.c index 5bd160f732de..9cff9ddafb72 100644 --- a/drivers/net/wireless/ralink/rt2x00/rt2500usb.c +++ b/drivers/net/wireless/ralink/rt2x00/rt2500usb.c @@ -268,7 +268,7 @@ static const struct rt2x00debug rt2500usb_rt2x00debug = { .word_count = BBP_SIZE / sizeof(u8), }, .rf = { - .read = _rt2x00_rf_read, + .read = rt2x00_rf_read, .write = rt2500usb_rf_write, .word_base = RF_BASE, .word_size = sizeof(u32), @@ -639,7 +639,7 @@ static void rt2500usb_config_txpower(struct rt2x00_dev *rt2x00dev, { u32 rf3; - rt2x00_rf_read(rt2x00dev, 3, &rf3); + rf3 = rt2x00_rf_read(rt2x00dev, 3); rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); rt2500usb_rf_write(rt2x00dev, 3, rf3); } diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c index 9b8c19dcdb2c..fef53d6a888a 100644 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c @@ -1265,7 +1265,7 @@ const struct rt2x00debug rt2800_rt2x00debug = { .word_count = BBP_SIZE / sizeof(u8), }, .rf = { - .read = _rt2x00_rf_read, + .read = rt2x00_rf_read, .write = rt2800_rf_write, .word_base = RF_BASE, .word_size = sizeof(u32), diff --git a/drivers/net/wireless/ralink/rt2x00/rt2x00.h b/drivers/net/wireless/ralink/rt2x00/rt2x00.h index f2ae33bf2ef2..36791f7ae2ce 100644 --- a/drivers/net/wireless/ralink/rt2x00/rt2x00.h +++ b/drivers/net/wireless/ralink/rt2x00/rt2x00.h @@ -1049,15 +1049,8 @@ struct rt2x00_bar_list_entry { * Generic RF access. * The RF is being accessed by word index. */ -static inline void rt2x00_rf_read(struct rt2x00_dev *rt2x00dev, - const unsigned int word, u32 *data) -{ - BUG_ON(word < 1 || word > rt2x00dev->ops->rf_size / sizeof(u32)); - *data = rt2x00dev->rf[word - 1]; -} - -static inline u32 _rt2x00_rf_read(struct rt2x00_dev *rt2x00dev, - const unsigned int word) +static inline u32 rt2x00_rf_read(struct rt2x00_dev *rt2x00dev, + const unsigned int word) { BUG_ON(word < 1 || word > rt2x00dev->ops->rf_size / sizeof(u32)); return rt2x00dev->rf[word - 1]; diff --git a/drivers/net/wireless/ralink/rt2x00/rt61pci.c b/drivers/net/wireless/ralink/rt2x00/rt61pci.c index efe8a766b251..147d1d2cc0a6 100644 --- a/drivers/net/wireless/ralink/rt2x00/rt61pci.c +++ b/drivers/net/wireless/ralink/rt2x00/rt61pci.c @@ -236,7 +236,7 @@ static const struct rt2x00debug rt61pci_rt2x00debug = { .word_count = BBP_SIZE / sizeof(u8), }, .rf = { - .read = _rt2x00_rf_read, + .read = rt2x00_rf_read, .write = rt61pci_rf_write, .word_base = RF_BASE, .word_size = sizeof(u32), @@ -922,10 +922,10 @@ static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev, { struct rf_channel rf; - rt2x00_rf_read(rt2x00dev, 1, &rf.rf1); - rt2x00_rf_read(rt2x00dev, 2, &rf.rf2); - rt2x00_rf_read(rt2x00dev, 3, &rf.rf3); - rt2x00_rf_read(rt2x00dev, 4, &rf.rf4); + rf.rf1 = rt2x00_rf_read(rt2x00dev, 1); + rf.rf2 = rt2x00_rf_read(rt2x00dev, 2); + rf.rf3 = rt2x00_rf_read(rt2x00dev, 3); + rf.rf4 = rt2x00_rf_read(rt2x00dev, 4); rt61pci_config_channel(rt2x00dev, &rf, txpower); } diff --git a/drivers/net/wireless/ralink/rt2x00/rt73usb.c b/drivers/net/wireless/ralink/rt2x00/rt73usb.c index 5db174922120..a36dee1a4f20 100644 --- a/drivers/net/wireless/ralink/rt2x00/rt73usb.c +++ b/drivers/net/wireless/ralink/rt2x00/rt73usb.c @@ -181,7 +181,7 @@ static const struct rt2x00debug rt73usb_rt2x00debug = { .word_count = BBP_SIZE / sizeof(u8), }, .rf = { - .read = _rt2x00_rf_read, + .read = rt2x00_rf_read, .write = rt73usb_rf_write, .word_base = RF_BASE, .word_size = sizeof(u32), @@ -805,10 +805,10 @@ static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev, { struct rf_channel rf; - rt2x00_rf_read(rt2x00dev, 1, &rf.rf1); - rt2x00_rf_read(rt2x00dev, 2, &rf.rf2); - rt2x00_rf_read(rt2x00dev, 3, &rf.rf3); - rt2x00_rf_read(rt2x00dev, 4, &rf.rf4); + rf.rf1 = rt2x00_rf_read(rt2x00dev, 1); + rf.rf2 = rt2x00_rf_read(rt2x00dev, 2); + rf.rf3 = rt2x00_rf_read(rt2x00dev, 3); + rf.rf4 = rt2x00_rf_read(rt2x00dev, 4); rt73usb_config_channel(rt2x00dev, &rf, txpower); } From patchwork Wed May 17 14:46:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 99988 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp267603qge; Wed, 17 May 2017 07:48:24 -0700 (PDT) X-Received: by 10.98.214.200 with SMTP id a69mr4287334pfl.40.1495032504332; Wed, 17 May 2017 07:48:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495032504; cv=none; d=google.com; s=arc-20160816; b=Lk9njZkp4GehfC+ymkWXgw+1W/b6R/y35FOu9sm0U0q6O868EGeV4vin8dPJ4V20Z9 nU7DIfvhsa0aornuPkjPPb8Jsx6ecz5JtE1ZSoZiRA2Yjtx9orgwUq0WWrm/BYGWo9JM lQN1jMSLWp1BzOv6jQ4nrE+4Ju/3oOJtgHxfRHgQovETOrqaspFrzmZyqb4GUFMHcXmI hVxiT3zlIj06HISMGmnXqYtkyoLS5NrMbBOvfR6GijXVByeeZpvhLuq/d73AKCKEszFG oAcqTIqaf7vsW7fVffGU0xDt2XfsrXq1vF+LXqhoE04FJzK67foU317GP2Llg6l3yVGo ju8g== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id v6si2256909plk.294.2017.05.17.07.48.24; Wed, 17 May 2017 07:48:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754733AbdEQOsE (ORCPT + 6 others); Wed, 17 May 2017 10:48:04 -0400 Received: from mout.kundenserver.de ([212.227.17.13]:59055 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754697AbdEQOr6 (ORCPT ); Wed, 17 May 2017 10:47:58 -0400 Received: from wuerfel.lan ([78.42.17.5]) by mrelayeu.kundenserver.de (mreue102 [212.227.15.145]) with ESMTPA (Nemesis) id 0LuMJr-1eAMTi1vKp-011kG6; Wed, 17 May 2017 16:47:25 +0200 From: Arnd Bergmann To: linux-wireless Cc: Arnd Bergmann , Stanislaw Gruszka , David Miller , Helmut Schaa , Kalle Valo , Daniel Golle , Mathias Kresin , Johannes Berg , Serge Vasilugin , Roman Yeryomin , Networking , Linux Kernel Mailing List , Jes Sorensen , Tom Psyborg Subject: [PATCH v2 06/10] rt2x00: convert rt2800_register_read return type Date: Wed, 17 May 2017 16:46:58 +0200 Message-Id: <20170517144702.1381136-7-arnd@arndb.de> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170517144702.1381136-1-arnd@arndb.de> References: <20170517144702.1381136-1-arnd@arndb.de> X-Provags-ID: V03:K0:8za8S2UvNImKlHAW43qITSF/RsFwotI9x/4ucJ1oo1Mn9aLD+1G T8ldRkwMYZ9k/bdPamWwKUMOC2/jp39ts7uLI8cX7VcQQDFH1i1nRC76WOR68r4GK+mXz3v 7PiZz/t+yovS57v0LUGswJilUVz/X6hS6b4u+QBbQjx4xssyqyJXufWbxM9AlotSOtnhTib QhGig36cBhB8RQyRl0Y3A== X-UI-Out-Filterresults: notjunk:1; V01:K0:aNA5Ao22gSA=:NpBOhV0onACzNMv1xus14s YncbJQhT2n22srhhfXh3S5DpqjDPdyDdMQWKhkJGyiwUoXYlipnwytRsfq+WFrogkDNe4X4Tr e0WmNzDyQM5qw0gvDoWcv/q/yBMkw2UNPIeAeLAbFMzTCsLcQOXX7pCZHauKxxOv7W7vzS8DM I05IOSPRw889Ej8OodRB7WDzX6WdNYlJGW8gzu7bh8aCjDyTtwu1Bm7opN6DlPQ7hAq/PQUYL Z/UsG9YMMZTL/EUEkRlZ9sJoakryd2CElh6FJ0e3kfw6ROry8QjtA3fAMYwsGHnTQZLdRVN7a UzuKyNe6OXdQfSntSqLjKffBAQ/pyPQ5LSWvSx0XQLSdAdk9Z6ekjuRkZATi9Ej5BGi9t2t1t eJPtrrIw04DDOA4b57+MKWYpeNkrkrqPQQHkQtgCl+vBShS8f+6J/gDm8eKQT+wrhveb9Ave5 A9ZvmSx4HY0C0Qz0hR8cGAtELSXAPxnp9Qy/oWbb7UELK25hIfqe5OlxPms8ttHY02L5f+hN5 zkz7/oKcOZt6nlExBb/TJEezSiXJpgOAvsEhIf+zowUix4ohA8hABg2FtmwZ29CodcSWYfkWr PPfH7p6WF2sC1+0F0Ng/jHY1ifvyfwxaWfRqIuAqTdjZQQOpAs7UFrZzOHzgSGlCi9iZBIphd 73UpQ2sQjaEHK4/VgxtbIvCFLtLX1ktbWjV3qZtgxzSF1GZ7Pkl1qG8GAX3C43WYH/GA= Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This is a semi-automated conversion to change rt2800_register_read to return the register contents instead of passing them by value, resulting in much better object code. The majority of the patch was done using: sed -i 's:\(rt2800_register_read(.*, .*\), &\(.*\));:\2 = \1);:' \ 's:\(rt2800_register_read_lock(.*, .*\), &\(.*\));:\2 = \1);:' \ drivers/net/wireless/ralink/rt2x00/rt2800lib.c The function itself was modified manually along with the one remaining multi-line caller that was not covered automatically and the indirect reference. Signed-off-by: Arnd Bergmann --- drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 291 ++++++++++++------------- drivers/net/wireless/ralink/rt2x00/rt2800lib.h | 22 +- 2 files changed, 151 insertions(+), 162 deletions(-) -- 2.9.0 diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c index fef53d6a888a..541e2692766a 100644 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c @@ -442,7 +442,7 @@ static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev) u32 reg; int i, count; - rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); rt2x00_set_field32(®, WLAN_CLK_EN, 0); @@ -457,7 +457,7 @@ static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev) * Check PLL_LD & XTAL_RDY. */ for (i = 0; i < REGISTER_BUSY_COUNT; i++) { - rt2800_register_read(rt2x00dev, CMB_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, CMB_CTRL); if (rt2x00_get_field32(reg, PLL_LD) && rt2x00_get_field32(reg, XTAL_RDY)) break; @@ -480,7 +480,7 @@ static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev) count = 0; } - rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); rt2x00_set_field32(®, WLAN_CLK_EN, 1); rt2x00_set_field32(®, WLAN_RESET, 1); @@ -535,7 +535,7 @@ int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev) u32 reg; for (i = 0; i < REGISTER_BUSY_COUNT; i++) { - rt2800_register_read(rt2x00dev, MAC_CSR0, ®); + reg = rt2800_register_read(rt2x00dev, MAC_CSR0); if (reg && reg != ~0) return 0; msleep(1); @@ -556,7 +556,7 @@ int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev) * before timing out. */ for (i = 0; i < REGISTER_BUSY_COUNT; i++) { - rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); + reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) return 0; @@ -573,7 +573,7 @@ void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev) { u32 reg; - rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); + reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); @@ -723,7 +723,7 @@ int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev, rt2x00_rt(rt2x00dev, RT3572) || rt2x00_rt(rt2x00dev, RT5390) || rt2x00_rt(rt2x00dev, RT5392)) { - rt2800_register_read(rt2x00dev, AUX_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, AUX_CTRL); rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); rt2800_register_write(rt2x00dev, AUX_CTRL, reg); @@ -742,7 +742,7 @@ int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev, * Wait for device to stabilize. */ for (i = 0; i < REGISTER_BUSY_COUNT; i++) { - rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL); if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) break; msleep(1); @@ -1096,7 +1096,7 @@ static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev) /* * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons. */ - rt2800_register_read(rt2x00dev, MAC_BSSID_DW1, &bssid_dw1); + bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1); rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM, bcn_num > 0 ? bcn_num - 1 : 0); rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1); @@ -1115,7 +1115,7 @@ void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) * Disable beaconing while we are reloading the beacon data, * otherwise we might be sending out invalid data. */ - rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); + reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); orig_reg = reg; rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); @@ -1205,7 +1205,7 @@ void rt2800_clear_beacon(struct queue_entry *entry) * Disable beaconing while we are reloading the beacon data, * otherwise we might be sending out invalid data. */ - rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &orig_reg); + orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); reg = orig_reg; rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); @@ -1240,7 +1240,7 @@ static u8 _rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word const struct rt2x00debug rt2800_rt2x00debug = { .owner = THIS_MODULE, .csr = { - .read = _rt2800_register_read, + .read = rt2800_register_read, .write = rt2800_register_write, .flags = RT2X00DEBUGFS_OFFSET, .word_base = CSR_REG_BASE, @@ -1287,10 +1287,10 @@ int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev) u32 reg; if (rt2x00_rt(rt2x00dev, RT3290)) { - rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0); } else { - rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); return rt2x00_get_field32(reg, GPIO_CTRL_VAL2); } } @@ -1315,7 +1315,7 @@ static void rt2800_brightness_set(struct led_classdev *led_cdev, /* Check for SoC (SOC devices don't support MCU requests) */ if (rt2x00_is_soc(led->rt2x00dev)) { - rt2800_register_read(led->rt2x00dev, LED_CFG, ®); + reg = rt2800_register_read(led->rt2x00dev, LED_CFG); /* Set LED Polarity */ rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); @@ -1404,7 +1404,7 @@ static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev, * The BSS Idx numbers is split in a main value of 3 bits, * and a extended field for adding one additional bit to the value. */ - rt2800_register_read(rt2x00dev, offset, ®); + reg = rt2800_register_read(rt2x00dev, offset); rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, (bssidx & 0x8) >> 3); @@ -1422,7 +1422,7 @@ static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev, offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx); if (crypto->cmd == SET_KEY) { - rt2800_register_read(rt2x00dev, offset, ®); + reg = rt2800_register_read(rt2x00dev, offset); rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)); /* @@ -1438,7 +1438,7 @@ static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev, rt2800_register_write(rt2x00dev, offset, reg); } else { /* Delete the cipher without touching the bssidx */ - rt2800_register_read(rt2x00dev, offset, ®); + reg = rt2800_register_read(rt2x00dev, offset); rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); @@ -1494,7 +1494,7 @@ int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev, offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8); - rt2800_register_read(rt2x00dev, offset, ®); + reg = rt2800_register_read(rt2x00dev, offset); rt2x00_set_field32(®, field, (crypto->cmd == SET_KEY) * crypto->cipher); rt2800_register_write(rt2x00dev, offset, reg); @@ -1560,7 +1560,7 @@ static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev) max_psdu = min(drv_data->max_psdu, i); - rt2800_register_read(rt2x00dev, MAX_LEN_CFG, ®); + reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, max_psdu); rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); } @@ -1652,7 +1652,7 @@ void rt2800_config_filter(struct rt2x00_dev *rt2x00dev, * and broadcast frames will always be accepted since * there is no filter for it at this time. */ - rt2800_register_read(rt2x00dev, RX_FILTER_CFG, ®); + reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG); rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, !(filter_flags & FIF_FCSFAIL)); rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, @@ -1696,7 +1696,7 @@ void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, /* * Enable synchronisation. */ - rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); + reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); @@ -1704,14 +1704,14 @@ void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf, /* * Tune beacon queue transmit parameters for AP mode */ - rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®); + reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); } else { - rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®); + reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG); rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); @@ -1830,22 +1830,22 @@ static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev, gf20_mode = gf40_mode = 1; /* Update HT protection config */ - rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); @@ -1857,14 +1857,14 @@ void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp, u32 reg; if (changed & BSS_CHANGED_ERP_PREAMBLE) { - rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); + reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, !!erp->short_preamble); rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); } if (changed & BSS_CHANGED_ERP_CTS_PROT) { - rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, erp->cts_protection ? 2 : 0); rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); @@ -1877,18 +1877,18 @@ void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp, } if (changed & BSS_CHANGED_ERP_SLOT) { - rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time); rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); - rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®); + reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); } if (changed & BSS_CHANGED_BEACON_INT) { - rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); + reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, erp->beacon_int * 16); rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); @@ -1905,7 +1905,7 @@ static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev) u16 eeprom; u8 led_ctrl, led_g_mode, led_r_mode; - rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); + reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { rt2x00_set_field32(®, GPIO_SWITCH_0, 1); rt2x00_set_field32(®, GPIO_SWITCH_1, 1); @@ -1915,7 +1915,7 @@ static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev) } rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); - rt2800_register_read(rt2x00dev, LED_CFG, ®); + reg = rt2800_register_read(rt2x00dev, LED_CFG); led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0; led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3; if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) || @@ -1941,14 +1941,14 @@ static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev, u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1; if (rt2x00_is_pci(rt2x00dev)) { - rt2800_register_read(rt2x00dev, E2PROM_CSR, ®); + reg = rt2800_register_read(rt2x00dev, E2PROM_CSR); rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); } else if (rt2x00_is_usb(rt2x00dev)) rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff, eesk_pin, 0); - rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); @@ -2411,7 +2411,7 @@ static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, rt2800_rfcsr_write(rt2x00dev, 29, 0x9f); } - rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); if (rf->channel <= 14) rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); @@ -2923,7 +2923,7 @@ static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev, const bool is_11b = false; const bool is_type_ep = false; - rt2800_register_read(rt2x00dev, LDO_CFG0, ®); + reg = rt2800_register_read(rt2x00dev, LDO_CFG0); rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0); rt2800_register_write(rt2x00dev, LDO_CFG0, reg); @@ -3362,7 +3362,7 @@ static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev, if (max_power > 0x2f) max_power = 0x2f; - rt2800_register_read(rt2x00dev, TX_ALC_CFG_0, ®); + reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0); rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, power_level); rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, power_level); rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_0, max_power); @@ -3378,18 +3378,17 @@ static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev, } rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg); - rt2800_register_read(rt2x00dev, TX_ALC_CFG_1, ®); + reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); rt2x00_set_field32(®, TX_ALC_CFG_1_TX_TEMP_COMP, 0); rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); /* Save MAC SYS CTRL registers */ - rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &mac_sys_ctrl); + mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); /* Disable Tx/Rx */ rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0); /* Check MAC Tx/Rx idle */ for (i = 0; i < 10000; i++) { - rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, - &mac_status); + mac_status = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); if (mac_status & 0x3) usleep_range(50, 200); else @@ -3702,7 +3701,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, rt2800_bbp_write(rt2x00dev, 75, 0x50); } - rt2800_register_read(rt2x00dev, TX_BAND_CFG, ®); + reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG); rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); @@ -3711,7 +3710,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, if (rt2x00_rt(rt2x00dev, RT3572)) rt2800_rfcsr_write(rt2x00dev, 8, 0); - rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin); + tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); switch (rt2x00dev->default_ant.tx_chain_num) { case 3: @@ -3777,7 +3776,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, } if (rt2x00_rt(rt2x00dev, RT3593)) { - rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); /* Band selection */ if (rt2x00_is_usb(rt2x00dev) || @@ -3869,9 +3868,9 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, /* * Clear channel statistic counters */ - rt2800_register_read(rt2x00dev, CH_IDLE_STA, ®); - rt2800_register_read(rt2x00dev, CH_BUSY_STA, ®); - rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, ®); + reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA); + reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA); + reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); /* * Clear update flag @@ -4613,26 +4612,26 @@ static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev, /* For OFDM 54MBS use value from OFDM 48MBS */ pwreg = 0; - rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, ®); + reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1); t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS); rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t); /* For MCS 7 use value from MCS 6 */ - rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, ®); + reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2); t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7); rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t); rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg); /* For MCS 15 use value from MCS 14 */ pwreg = 0; - rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, ®); + reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3); t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14); rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t); rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg); /* For STBC MCS 7 use value from STBC MCS 6 */ pwreg = 0; - rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, ®); + reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4); t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6); rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t); rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg); @@ -4725,7 +4724,7 @@ static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev, if (offset > TX_PWR_CFG_4) break; - rt2800_register_read(rt2x00dev, offset, ®); + reg = rt2800_register_read(rt2x00dev, offset); /* read the next four txpower values */ rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE, @@ -4865,7 +4864,7 @@ void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev) * periodically to adjust the frequency to be precision. */ - rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin); + tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); tx_pin &= TX_PIN_CFG_PA_PE_DISABLE; rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); @@ -4913,7 +4912,7 @@ void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev) if (min_sleep > 0) usleep_range(min_sleep, min_sleep * 2); - rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin); + tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG); if (rt2x00dev->rf_channel <= 14) { switch (rt2x00dev->default_ant.tx_chain_num) { case 3: @@ -4987,7 +4986,7 @@ static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev, { u32 reg; - rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®); + reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, libconf->conf->short_frame_max_tx_count); rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, @@ -5006,7 +5005,7 @@ static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev, if (state == STATE_SLEEP) { rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0); - rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); + reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, libconf->conf->listen_interval - 1); @@ -5015,7 +5014,7 @@ static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev, rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); } else { - rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); + reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG); rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); @@ -5058,7 +5057,7 @@ void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual) /* * Update FCS error count from register. */ - rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); + reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); } EXPORT_SYMBOL_GPL(rt2800_link_stats); @@ -5187,7 +5186,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000); - rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); + reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG); rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); @@ -5198,43 +5197,43 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2800_config_filter(rt2x00dev, FIF_ALLMULTI); - rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG); rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); if (rt2x00_rt(rt2x00dev, RT3290)) { - rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL); if (rt2x00_get_field32(reg, WLAN_EN) == 1) { rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1); rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); } - rt2800_register_read(rt2x00dev, CMB_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, CMB_CTRL); if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) { rt2x00_set_field32(®, LDO0_EN, 1); rt2x00_set_field32(®, LDO_BGSEL, 3); rt2800_register_write(rt2x00dev, CMB_CTRL, reg); } - rt2800_register_read(rt2x00dev, OSC_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, OSC_CTRL); rt2x00_set_field32(®, OSC_ROSC_EN, 1); rt2x00_set_field32(®, OSC_CAL_REQ, 1); rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27); rt2800_register_write(rt2x00dev, OSC_CTRL, reg); - rt2800_register_read(rt2x00dev, COEX_CFG0, ®); + reg = rt2800_register_read(rt2x00dev, COEX_CFG0); rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e); rt2800_register_write(rt2x00dev, COEX_CFG0, reg); - rt2800_register_read(rt2x00dev, COEX_CFG2, ®); + reg = rt2800_register_read(rt2x00dev, COEX_CFG2); rt2x00_set_field32(®, BT_COEX_CFG1, 0x00); rt2x00_set_field32(®, BT_COEX_CFG0, 0x17); rt2x00_set_field32(®, WL_COEX_CFG1, 0x93); rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f); rt2800_register_write(rt2x00dev, COEX_CFG2, reg); - rt2800_register_read(rt2x00dev, PLL_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, PLL_CTRL); rt2x00_set_field32(®, PLL_CONTROL, 1); rt2800_register_write(rt2x00dev, PLL_CTRL, reg); } @@ -5331,7 +5330,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 0x3630363A); rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT, 0x3630363A); - rt2800_register_read(rt2x00dev, TX_ALC_CFG_1, ®); + reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1); rt2x00_set_field32(®, TX_ALC_CFG_1_ROS_BUSY_EN, 0); rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg); } else { @@ -5339,7 +5338,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); } - rt2800_register_read(rt2x00dev, TX_LINK_CFG, ®); + reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG); rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); @@ -5350,13 +5349,13 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); - rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG); rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); - rt2800_register_read(rt2x00dev, MAX_LEN_CFG, ®); + reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG); rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); if (rt2x00_is_usb(rt2x00dev)) { drv_data->max_psdu = 3; @@ -5372,7 +5371,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 10); rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); - rt2800_register_read(rt2x00dev, LED_CFG, ®); + reg = rt2800_register_read(rt2x00dev, LED_CFG); rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); @@ -5384,7 +5383,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); - rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®); + reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG); rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 2); rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 2); rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); @@ -5393,7 +5392,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); - rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); + reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG); rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 1); @@ -5403,7 +5402,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); - rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); @@ -5416,7 +5415,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); @@ -5429,7 +5428,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 1); rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); @@ -5442,7 +5441,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 1); rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); @@ -5455,7 +5454,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 1); rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); @@ -5468,7 +5467,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 1); rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); @@ -5484,7 +5483,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) if (rt2x00_is_usb(rt2x00dev)) { rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006); - rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); + reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); @@ -5501,7 +5500,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1 * although it is reserved. */ - rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, ®); + reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG); rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); @@ -5517,7 +5516,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002; rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg); - rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); + reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7); rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, IEEE80211_MAX_RTS_THRESHOLD); @@ -5533,7 +5532,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) * connection problems with 11g + CTS protection. Hence, use the same * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS. */ - rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®); + reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG); rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); @@ -5563,16 +5562,16 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2800_clear_beacon_register(rt2x00dev, i); if (rt2x00_is_usb(rt2x00dev)) { - rt2800_register_read(rt2x00dev, US_CYC_CNT, ®); + reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); } else if (rt2x00_is_pcie(rt2x00dev)) { - rt2800_register_read(rt2x00dev, US_CYC_CNT, ®); + reg = rt2800_register_read(rt2x00dev, US_CYC_CNT); rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); } - rt2800_register_read(rt2x00dev, HT_FBK_CFG0, ®); + reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0); rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); @@ -5583,7 +5582,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); - rt2800_register_read(rt2x00dev, HT_FBK_CFG1, ®); + reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1); rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); @@ -5594,7 +5593,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); - rt2800_register_read(rt2x00dev, LG_FBK_CFG0, ®); + reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0); rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); @@ -5605,7 +5604,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); - rt2800_register_read(rt2x00dev, LG_FBK_CFG1, ®); + reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1); rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); @@ -5615,7 +5614,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) /* * Do not force the BA window size, we use the TXWI to set it */ - rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, ®); + reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE); rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg); @@ -5625,24 +5624,24 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) * These registers are cleared on read, * so we may pass a useless variable to store the value. */ - rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); - rt2800_register_read(rt2x00dev, RX_STA_CNT1, ®); - rt2800_register_read(rt2x00dev, RX_STA_CNT2, ®); - rt2800_register_read(rt2x00dev, TX_STA_CNT0, ®); - rt2800_register_read(rt2x00dev, TX_STA_CNT1, ®); - rt2800_register_read(rt2x00dev, TX_STA_CNT2, ®); + reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0); + reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1); + reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2); + reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0); + reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1); + reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2); /* * Setup leadtime for pre tbtt interrupt to 6ms */ - rt2800_register_read(rt2x00dev, INT_TIMER_CFG, ®); + reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG); rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg); /* * Set up channel statistics timer */ - rt2800_register_read(rt2x00dev, CH_TIME_CFG, ®); + reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG); rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); @@ -5659,7 +5658,7 @@ static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev) u32 reg; for (i = 0; i < REGISTER_BUSY_COUNT; i++) { - rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, ®); + reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG); if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY)) return 0; @@ -6212,7 +6211,7 @@ static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev) if (rt2x00_has_cap_bt_coexist(rt2x00dev)) { u32 reg; - rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0); rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0); @@ -6605,7 +6604,7 @@ static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev) { u32 reg; - rt2800_register_read(rt2x00dev, OPT_14_CSR, ®); + reg = rt2800_register_read(rt2x00dev, OPT_14_CSR); rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); } @@ -6938,7 +6937,7 @@ static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev) rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { - rt2800_register_read(rt2x00dev, LDO_CFG0, ®); + reg = rt2800_register_read(rt2x00dev, LDO_CFG0); rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); rt2800_register_write(rt2x00dev, LDO_CFG0, reg); @@ -6950,7 +6949,7 @@ static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev) rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); - rt2800_register_read(rt2x00dev, LDO_CFG0, ®); + reg = rt2800_register_read(rt2x00dev, LDO_CFG0); rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) || rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) { @@ -6963,7 +6962,7 @@ static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev) } rt2800_register_write(rt2x00dev, LDO_CFG0, reg); - rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); + reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); rt2x00_set_field32(®, GPIO_SWITCH_5, 0); rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); } @@ -7178,7 +7177,7 @@ static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev) rt2800_rfcsr_write(rt2x00dev, 30, 0x20); rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); - rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); + reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); rt2x00_set_field32(®, GPIO_SWITCH_5, 0); rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); @@ -7234,12 +7233,12 @@ static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev) rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); - rt2800_register_read(rt2x00dev, LDO_CFG0, ®); + reg = rt2800_register_read(rt2x00dev, LDO_CFG0); rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); rt2800_register_write(rt2x00dev, LDO_CFG0, reg); msleep(1); - rt2800_register_read(rt2x00dev, LDO_CFG0, ®); + reg = rt2800_register_read(rt2x00dev, LDO_CFG0); rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); rt2800_register_write(rt2x00dev, LDO_CFG0, reg); @@ -7303,7 +7302,7 @@ static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev) u8 rfcsr; /* Disable GPIO #4 and #7 function for LAN PE control */ - rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); + reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH); rt2x00_set_field32(®, GPIO_SWITCH_4, 0); rt2x00_set_field32(®, GPIO_SWITCH_7, 0); rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); @@ -7354,12 +7353,12 @@ static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev) rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1); rt2800_rfcsr_write(rt2x00dev, 18, rfcsr); - rt2800_register_read(rt2x00dev, LDO_CFG0, ®); + reg = rt2800_register_read(rt2x00dev, LDO_CFG0); rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); rt2800_register_write(rt2x00dev, LDO_CFG0, reg); usleep_range(1000, 1500); - rt2800_register_read(rt2x00dev, LDO_CFG0, ®); + reg = rt2800_register_read(rt2x00dev, LDO_CFG0); rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); rt2800_register_write(rt2x00dev, LDO_CFG0, reg); @@ -7773,8 +7772,8 @@ static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev, u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0; /* Save MAC registers */ - rt2800_register_read(rt2x00dev, RF_CONTROL0, &MAC_RF_CONTROL0); - rt2800_register_read(rt2x00dev, RF_BYPASS0, &MAC_RF_BYPASS0); + MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0); + MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0); /* save BBP registers */ rt2800_bbp_read(rt2x00dev, 23, &savebbpr23); @@ -8367,20 +8366,20 @@ int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev) /* * Enable RX. */ - rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); udelay(50); - rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); + reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG); rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); - rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); @@ -8413,7 +8412,7 @@ void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev) /* Wait for DMA, ignore error */ rt2800_wait_wpdma_ready(rt2x00dev); - rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL); rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); @@ -8430,7 +8429,7 @@ int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev) else efuse_ctrl_reg = EFUSE_CTRL; - rt2800_register_read(rt2x00dev, efuse_ctrl_reg, ®); + reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg); return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); } EXPORT_SYMBOL_GPL(rt2800_efuse_detect); @@ -8459,7 +8458,7 @@ static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) } mutex_lock(&rt2x00dev->csr_mutex); - rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, ®); + reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg); rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); @@ -8468,14 +8467,14 @@ static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) /* Wait until the EEPROM has been loaded */ rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®); /* Apparently the data is read from end to start */ - rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, ®); + reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg); /* The returned value is in CPU order, but eeprom is le */ *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg); - rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, ®); + reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg); *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg); - rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, ®); + reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg); *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg); - rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, ®); + reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg); *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg); mutex_unlock(&rt2x00dev->csr_mutex); @@ -9251,7 +9250,7 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) break; case RF5592: - rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, ®); + reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX); if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) { spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40); spec->channels = rf_vals_5592_xtal40; @@ -9390,9 +9389,9 @@ static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev) u32 rev; if (rt2x00_rt(rt2x00dev, RT3290)) - rt2800_register_read(rt2x00dev, MAC_CSR0_3290, ®); + reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290); else - rt2800_register_read(rt2x00dev, MAC_CSR0, ®); + reg = rt2800_register_read(rt2x00dev, MAC_CSR0); rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET); rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION); @@ -9452,7 +9451,7 @@ int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev) * Enable rfkill polling by setting GPIO direction of the * rfkill switch GPIO pin correctly. */ - rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); + reg = rt2800_register_read(rt2x00dev, GPIO_CTRL); rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1); rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); @@ -9527,31 +9526,31 @@ int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value) u32 reg; bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD); - rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); + reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG); rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); - rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG); rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG); rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG); rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG); rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG); rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); - rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); + reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG); rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); @@ -9594,7 +9593,7 @@ int rt2800_conf_tx(struct ieee80211_hw *hw, field.bit_offset = (queue_idx & 1) * 16; field.bit_mask = 0xffff << field.bit_offset; - rt2800_register_read(rt2x00dev, offset, ®); + reg = rt2800_register_read(rt2x00dev, offset); rt2x00_set_field32(®, field, queue->txop); rt2800_register_write(rt2x00dev, offset, reg); @@ -9602,22 +9601,22 @@ int rt2800_conf_tx(struct ieee80211_hw *hw, field.bit_offset = queue_idx * 4; field.bit_mask = 0xf << field.bit_offset; - rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, ®); + reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG); rt2x00_set_field32(®, field, queue->aifs); rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); - rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, ®); + reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG); rt2x00_set_field32(®, field, queue->cw_min); rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); - rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, ®); + reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG); rt2x00_set_field32(®, field, queue->cw_max); rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); /* Update EDCA registers */ offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx); - rt2800_register_read(rt2x00dev, offset, ®); + reg = rt2800_register_read(rt2x00dev, offset); rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); @@ -9634,9 +9633,9 @@ u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) u64 tsf; u32 reg; - rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, ®); + reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1); tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; - rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, ®); + reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0); tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); return tsf; @@ -9703,9 +9702,9 @@ int rt2800_get_survey(struct ieee80211_hw *hw, int idx, survey->channel = conf->chandef.chan; - rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle); - rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy); - rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext); + idle = rt2800_register_read(rt2x00dev, CH_IDLE_STA); + busy = rt2800_register_read(rt2x00dev, CH_BUSY_STA); + busy_ext = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC); if (idle || busy) { survey->filled = SURVEY_INFO_TIME | diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.h b/drivers/net/wireless/ralink/rt2x00/rt2800lib.h index 6bed0d5e930e..275e3969abdd 100644 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.h +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.h @@ -78,30 +78,20 @@ struct rt2800_ops { __le32 *(*drv_get_txwi)(struct queue_entry *entry); }; -static inline void rt2800_register_read(struct rt2x00_dev *rt2x00dev, - const unsigned int offset, - u32 *value) +static inline u32 rt2800_register_read(struct rt2x00_dev *rt2x00dev, + const unsigned int offset) { const struct rt2800_ops *rt2800ops = rt2x00dev->ops->drv; - *value = rt2800ops->register_read(rt2x00dev, offset); -} - -static inline void rt2800_register_read_lock(struct rt2x00_dev *rt2x00dev, - const unsigned int offset, - u32 *value) -{ - const struct rt2800_ops *rt2800ops = rt2x00dev->ops->drv; - - *value = rt2800ops->register_read_lock(rt2x00dev, offset); + return rt2800ops->register_read(rt2x00dev, offset); } -static inline u32 _rt2800_register_read(struct rt2x00_dev *rt2x00dev, - const unsigned int offset) +static inline u32 rt2800_register_read_lock(struct rt2x00_dev *rt2x00dev, + const unsigned int offset) { const struct rt2800_ops *rt2800ops = rt2x00dev->ops->drv; - return rt2800ops->register_read(rt2x00dev, offset); + return rt2800ops->register_read_lock(rt2x00dev, offset); } static inline void rt2800_register_write(struct rt2x00_dev *rt2x00dev, From patchwork Wed May 17 14:47:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 99999 Delivered-To: patch@linaro.org Received: by 10.182.142.97 with SMTP id rv1csp254355obb; Wed, 17 May 2017 07:54:27 -0700 (PDT) X-Received: by 10.84.214.150 with SMTP id j22mr4786011pli.133.1495032867700; Wed, 17 May 2017 07:54:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495032867; cv=none; d=google.com; s=arc-20160816; b=0vgtk1IESGlv6vj2/koR5XRsAtJutkzTYTLjvz0svN7yQGVOZmD1ZaNOq1RZGWuCh5 QvAa+G87PjbdeATdedMKmHx29iJfi50L8iFgSunmEPyjelDDb79I5DYgA+gHm57Tf9DN N5o8FSPMRyeb1GqR/q8eD6xzsAqNPPIRQmwFYKkUUVOKyOxz0pgOCrnCyizzkw25KpQP udvnxy20WrmnQLsY6lLuORfBgSOtohZ543j4IqD/gS2cpzJr9DOSuW7FTHxejMuaPFAm 7X1WpxMMVtbx2HWU3mgCFs2XsKiqCbiLAfX6gHgjbs1CjoZwh5n+gibX4Bvw3xpRPhTh +suw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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[209.132.180.67]) by mx.google.com with ESMTP id 88si2494821plf.60.2017.05.17.07.54.27; Wed, 17 May 2017 07:54:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of netdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=netdev-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753824AbdEQOyR (ORCPT + 6 others); Wed, 17 May 2017 10:54:17 -0400 Received: from mout.kundenserver.de ([212.227.17.13]:57848 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754435AbdEQOrv (ORCPT ); Wed, 17 May 2017 10:47:51 -0400 Received: from wuerfel.lan ([78.42.17.5]) by mrelayeu.kundenserver.de (mreue102 [212.227.15.145]) with ESMTPA (Nemesis) id 0LkPdb-1diyD51O4x-00cQR8; Wed, 17 May 2017 16:47:28 +0200 From: Arnd Bergmann To: linux-wireless Cc: Arnd Bergmann , Stanislaw Gruszka , David Miller , Helmut Schaa , Kalle Valo , Daniel Golle , Mathias Kresin , Johannes Berg , Serge Vasilugin , Roman Yeryomin , Networking , Linux Kernel Mailing List , Jes Sorensen , Tom Psyborg Subject: [PATCH v2 10/10] rt2x00: convert rt2x00_desc_read return type Date: Wed, 17 May 2017 16:47:02 +0200 Message-Id: <20170517144702.1381136-11-arnd@arndb.de> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20170517144702.1381136-1-arnd@arndb.de> References: <20170517144702.1381136-1-arnd@arndb.de> X-Provags-ID: V03:K0:V/eUx1tSJ2cWociv8b1/KqXNcUaa1gIf2CFHwe45xeR7OSGdNJy pA+vzuovjkPPPcsD+slBiP+hSAkWJQ0Ky8E26refI+SBhJ5Tm+Ri4+QdfPAuXI+t27YKuQK Kf25iM4PSprSqACbZQgAgq65LZZzsaR5dS2SwzbSH/MwRlA4CayhaixFp/PUHSWXNpWvuUy zWvjEgo0uhhyB84NqHE3A== X-UI-Out-Filterresults: notjunk:1; V01:K0:BSBPdfu3s7E=:Dam6rrH2AmTzfWRohauYHg 6RqpAjZoQuHe+Pgg+bR24fe/RkrcVVYmMs7wVWe+iK/ctZMWP66svK5e4dEy99TGFC+dI3omu OlnQqKuRrVNpEgcWjnamKGLrYL//IDMbQQ4yIbfJd3duyrqfaseyVNMxDpQbAVPag2WLpoNmR VnaWYh14Fb2UPMAedwHF/F1DiHZ8oTP8//mqkeVmR8GFQu/3jpef7Bjenuzpc/D2IrVMX3QtC phm/LdxvP0kaw3JC+q2QUF3DbW484l/w2nDDmpHYbdFnmfK0bMWZAsPZvnZhlL9mXwqp8bUao 9jKpZbuNUePCFps3Ox2ge2UBBcfVtcO2NV7LB0/JmmqSomfydPZm2ik9UW3kaI5LH8YBgV9sl SCPYr40p/LHQpvsOazoIDjweEN1SAnnT2kscj/iQki1bjTcHGonTKUHRY/PvzgJorfaWvI2g3 89ha+YQZTDGdd5fWbPi5isXks4AkBS9iIXAHoxaaTHZ2EXfX+soQZyPimEerFu+MOscxmJnwE uDRuMu2khcIdoHzqyv62qy3c/ZWBjIBC/SbIWHQwcGrH7SPYQT6K4FI341rNa2BJIF2ftG310 SCEw/BpWqB+6+fXaMocBCO7n42jIix1S5djEaBJtsUGjTnaCVjzLwE8pn+mOM4QlXky9srr3r 9dX9UQGMhuOSlfwxA5FvvPG9Jwhpzyz3tKDgG65uwcKc4N5qR8hxx3S2zv8x8/EuqnW4= Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org This is a semi-automated conversion to change rt2x00_desc_read to return the register contents instead of passing them by value, resulting in much better object code. The majority of the patch was done using: sed -i 's:\(\(.*, .*\), &\(.*\));:\2 = \1);:' \ -i 's:\(\<_rt2x00_desc_read\>(.*, .*\), &\(.*\));:\2 = \1);:' \ drivers/net/wireless/ralink/rt2x00/rt* Signed-off-by: Arnd Bergmann --- drivers/net/wireless/ralink/rt2x00/rt2400pci.c | 32 +++++++++++----------- drivers/net/wireless/ralink/rt2x00/rt2500pci.c | 26 +++++++++--------- drivers/net/wireless/ralink/rt2x00/rt2500usb.c | 14 +++++----- drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 12 ++++----- drivers/net/wireless/ralink/rt2x00/rt2800mmio.c | 14 +++++----- drivers/net/wireless/ralink/rt2x00/rt2800usb.c | 8 +++--- drivers/net/wireless/ralink/rt2x00/rt2x00queue.h | 12 +++------ drivers/net/wireless/ralink/rt2x00/rt61pci.c | 34 ++++++++++++------------ drivers/net/wireless/ralink/rt2x00/rt73usb.c | 18 ++++++------- 9 files changed, 83 insertions(+), 87 deletions(-) -- 2.9.0 diff --git a/drivers/net/wireless/ralink/rt2x00/rt2400pci.c b/drivers/net/wireless/ralink/rt2x00/rt2400pci.c index 73b919838a61..0bc8b0249c57 100644 --- a/drivers/net/wireless/ralink/rt2x00/rt2400pci.c +++ b/drivers/net/wireless/ralink/rt2x00/rt2400pci.c @@ -728,11 +728,11 @@ static bool rt2400pci_get_entry_state(struct queue_entry *entry) u32 word; if (entry->queue->qid == QID_RX) { - rt2x00_desc_read(entry_priv->desc, 0, &word); + word = rt2x00_desc_read(entry_priv->desc, 0); return rt2x00_get_field32(word, RXD_W0_OWNER_NIC); } else { - rt2x00_desc_read(entry_priv->desc, 0, &word); + word = rt2x00_desc_read(entry_priv->desc, 0); return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || rt2x00_get_field32(word, TXD_W0_VALID)); @@ -746,19 +746,19 @@ static void rt2400pci_clear_entry(struct queue_entry *entry) u32 word; if (entry->queue->qid == QID_RX) { - rt2x00_desc_read(entry_priv->desc, 2, &word); + word = rt2x00_desc_read(entry_priv->desc, 2); rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len); rt2x00_desc_write(entry_priv->desc, 2, word); - rt2x00_desc_read(entry_priv->desc, 1, &word); + word = rt2x00_desc_read(entry_priv->desc, 1); rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); rt2x00_desc_write(entry_priv->desc, 1, word); - rt2x00_desc_read(entry_priv->desc, 0, &word); + word = rt2x00_desc_read(entry_priv->desc, 0); rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); rt2x00_desc_write(entry_priv->desc, 0, word); } else { - rt2x00_desc_read(entry_priv->desc, 0, &word); + word = rt2x00_desc_read(entry_priv->desc, 0); rt2x00_set_field32(&word, TXD_W0_VALID, 0); rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); rt2x00_desc_write(entry_priv->desc, 0, word); @@ -1113,16 +1113,16 @@ static void rt2400pci_write_tx_desc(struct queue_entry *entry, /* * Start writing the descriptor words. */ - rt2x00_desc_read(txd, 1, &word); + word = rt2x00_desc_read(txd, 1); rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); rt2x00_desc_write(txd, 1, word); - rt2x00_desc_read(txd, 2, &word); + word = rt2x00_desc_read(txd, 2); rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length); rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length); rt2x00_desc_write(txd, 2, word); - rt2x00_desc_read(txd, 3, &word); + word = rt2x00_desc_read(txd, 3); rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal); rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5); rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1); @@ -1131,7 +1131,7 @@ static void rt2400pci_write_tx_desc(struct queue_entry *entry, rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1); rt2x00_desc_write(txd, 3, word); - rt2x00_desc_read(txd, 4, &word); + word = rt2x00_desc_read(txd, 4); rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->u.plcp.length_low); rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8); @@ -1147,7 +1147,7 @@ static void rt2400pci_write_tx_desc(struct queue_entry *entry, * the device, whereby the device may take hold of the TXD before we * finished updating it. */ - rt2x00_desc_read(txd, 0, &word); + word = rt2x00_desc_read(txd, 0); rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); rt2x00_set_field32(&word, TXD_W0_VALID, 1); rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, @@ -1228,10 +1228,10 @@ static void rt2400pci_fill_rxdone(struct queue_entry *entry, u32 rx_low; u32 rx_high; - rt2x00_desc_read(entry_priv->desc, 0, &word0); - rt2x00_desc_read(entry_priv->desc, 2, &word2); - rt2x00_desc_read(entry_priv->desc, 3, &word3); - rt2x00_desc_read(entry_priv->desc, 4, &word4); + word0 = rt2x00_desc_read(entry_priv->desc, 0); + word2 = rt2x00_desc_read(entry_priv->desc, 2); + word3 = rt2x00_desc_read(entry_priv->desc, 3); + word4 = rt2x00_desc_read(entry_priv->desc, 4); if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; @@ -1285,7 +1285,7 @@ static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, while (!rt2x00queue_empty(queue)) { entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); entry_priv = entry->priv_data; - rt2x00_desc_read(entry_priv->desc, 0, &word); + word = rt2x00_desc_read(entry_priv->desc, 0); if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || !rt2x00_get_field32(word, TXD_W0_VALID)) diff --git a/drivers/net/wireless/ralink/rt2x00/rt2500pci.c b/drivers/net/wireless/ralink/rt2x00/rt2500pci.c index 5fcee4855720..1ff5434798ec 100644 --- a/drivers/net/wireless/ralink/rt2x00/rt2500pci.c +++ b/drivers/net/wireless/ralink/rt2x00/rt2500pci.c @@ -817,11 +817,11 @@ static bool rt2500pci_get_entry_state(struct queue_entry *entry) u32 word; if (entry->queue->qid == QID_RX) { - rt2x00_desc_read(entry_priv->desc, 0, &word); + word = rt2x00_desc_read(entry_priv->desc, 0); return rt2x00_get_field32(word, RXD_W0_OWNER_NIC); } else { - rt2x00_desc_read(entry_priv->desc, 0, &word); + word = rt2x00_desc_read(entry_priv->desc, 0); return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || rt2x00_get_field32(word, TXD_W0_VALID)); @@ -835,15 +835,15 @@ static void rt2500pci_clear_entry(struct queue_entry *entry) u32 word; if (entry->queue->qid == QID_RX) { - rt2x00_desc_read(entry_priv->desc, 1, &word); + word = rt2x00_desc_read(entry_priv->desc, 1); rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); rt2x00_desc_write(entry_priv->desc, 1, word); - rt2x00_desc_read(entry_priv->desc, 0, &word); + word = rt2x00_desc_read(entry_priv->desc, 0); rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); rt2x00_desc_write(entry_priv->desc, 0, word); } else { - rt2x00_desc_read(entry_priv->desc, 0, &word); + word = rt2x00_desc_read(entry_priv->desc, 0); rt2x00_set_field32(&word, TXD_W0_VALID, 0); rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); rt2x00_desc_write(entry_priv->desc, 0, word); @@ -1266,18 +1266,18 @@ static void rt2500pci_write_tx_desc(struct queue_entry *entry, /* * Start writing the descriptor words. */ - rt2x00_desc_read(txd, 1, &word); + word = rt2x00_desc_read(txd, 1); rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); rt2x00_desc_write(txd, 1, word); - rt2x00_desc_read(txd, 2, &word); + word = rt2x00_desc_read(txd, 2); rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER); rt2x00_set_field32(&word, TXD_W2_AIFS, entry->queue->aifs); rt2x00_set_field32(&word, TXD_W2_CWMIN, entry->queue->cw_min); rt2x00_set_field32(&word, TXD_W2_CWMAX, entry->queue->cw_max); rt2x00_desc_write(txd, 2, word); - rt2x00_desc_read(txd, 3, &word); + word = rt2x00_desc_read(txd, 3); rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal); rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service); rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, @@ -1286,7 +1286,7 @@ static void rt2500pci_write_tx_desc(struct queue_entry *entry, txdesc->u.plcp.length_high); rt2x00_desc_write(txd, 3, word); - rt2x00_desc_read(txd, 10, &word); + word = rt2x00_desc_read(txd, 10); rt2x00_set_field32(&word, TXD_W10_RTS, test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)); rt2x00_desc_write(txd, 10, word); @@ -1296,7 +1296,7 @@ static void rt2500pci_write_tx_desc(struct queue_entry *entry, * the device, whereby the device may take hold of the TXD before we * finished updating it. */ - rt2x00_desc_read(txd, 0, &word); + word = rt2x00_desc_read(txd, 0); rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); rt2x00_set_field32(&word, TXD_W0_VALID, 1); rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, @@ -1371,8 +1371,8 @@ static void rt2500pci_fill_rxdone(struct queue_entry *entry, u32 word0; u32 word2; - rt2x00_desc_read(entry_priv->desc, 0, &word0); - rt2x00_desc_read(entry_priv->desc, 2, &word2); + word0 = rt2x00_desc_read(entry_priv->desc, 0); + word2 = rt2x00_desc_read(entry_priv->desc, 2); if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; @@ -1413,7 +1413,7 @@ static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, while (!rt2x00queue_empty(queue)) { entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); entry_priv = entry->priv_data; - rt2x00_desc_read(entry_priv->desc, 0, &word); + word = rt2x00_desc_read(entry_priv->desc, 0); if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || !rt2x00_get_field32(word, TXD_W0_VALID)) diff --git a/drivers/net/wireless/ralink/rt2x00/rt2500usb.c b/drivers/net/wireless/ralink/rt2x00/rt2500usb.c index 4497385a4fea..529e05999abb 100644 --- a/drivers/net/wireless/ralink/rt2x00/rt2500usb.c +++ b/drivers/net/wireless/ralink/rt2x00/rt2500usb.c @@ -1074,7 +1074,7 @@ static void rt2500usb_write_tx_desc(struct queue_entry *entry, /* * Start writing the descriptor words. */ - rt2x00_desc_read(txd, 0, &word); + word = rt2x00_desc_read(txd, 0); rt2x00_set_field32(&word, TXD_W0_RETRY_LIMIT, txdesc->retry_limit); rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); @@ -1092,14 +1092,14 @@ static void rt2500usb_write_tx_desc(struct queue_entry *entry, rt2x00_set_field32(&word, TXD_W0_KEY_ID, txdesc->key_idx); rt2x00_desc_write(txd, 0, word); - rt2x00_desc_read(txd, 1, &word); + word = rt2x00_desc_read(txd, 1); rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset); rt2x00_set_field32(&word, TXD_W1_AIFS, entry->queue->aifs); rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min); rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max); rt2x00_desc_write(txd, 1, word); - rt2x00_desc_read(txd, 2, &word); + word = rt2x00_desc_read(txd, 2); rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal); rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service); rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, @@ -1247,8 +1247,8 @@ static void rt2500usb_fill_rxdone(struct queue_entry *entry, /* * It is now safe to read the descriptor on all architectures. */ - rt2x00_desc_read(rxd, 0, &word0); - rt2x00_desc_read(rxd, 1, &word1); + word0 = rt2x00_desc_read(rxd, 0); + word1 = rt2x00_desc_read(rxd, 1); if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; @@ -1260,8 +1260,8 @@ static void rt2500usb_fill_rxdone(struct queue_entry *entry, rxdesc->cipher_status = RX_CRYPTO_FAIL_KEY; if (rxdesc->cipher != CIPHER_NONE) { - _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]); - _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]); + rxdesc->iv[0] = _rt2x00_desc_read(rxd, 2); + rxdesc->iv[1] = _rt2x00_desc_read(rxd, 3); rxdesc->dev_flags |= RXDONE_CRYPTO_IV; /* ICV is located at the end of frame */ diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c index 5063169b7794..6e2e760d98b1 100644 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c @@ -785,7 +785,7 @@ void rt2800_write_tx_data(struct queue_entry *entry, /* * Initialize TX Info descriptor */ - rt2x00_desc_read(txwi, 0, &word); + word = rt2x00_desc_read(txwi, 0); rt2x00_set_field32(&word, TXWI_W0_FRAG, test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, @@ -807,7 +807,7 @@ void rt2800_write_tx_data(struct queue_entry *entry, rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); rt2x00_desc_write(txwi, 0, word); - rt2x00_desc_read(txwi, 1, &word); + word = rt2x00_desc_read(txwi, 1); rt2x00_set_field32(&word, TXWI_W1_ACK, test_bit(ENTRY_TXD_ACK, &txdesc->flags)); rt2x00_set_field32(&word, TXWI_W1_NSEQ, @@ -885,12 +885,12 @@ void rt2800_process_rxwi(struct queue_entry *entry, __le32 *rxwi = (__le32 *) entry->skb->data; u32 word; - rt2x00_desc_read(rxwi, 0, &word); + word = rt2x00_desc_read(rxwi, 0); rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF); rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT); - rt2x00_desc_read(rxwi, 1, &word); + word = rt2x00_desc_read(rxwi, 1); if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI)) rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI; @@ -911,7 +911,7 @@ void rt2800_process_rxwi(struct queue_entry *entry, if (rxdesc->rate_mode == RATE_MODE_CCK) rxdesc->signal &= ~0x8; - rt2x00_desc_read(rxwi, 2, &word); + word = rt2x00_desc_read(rxwi, 2); /* * Convert descriptor AGC value to RSSI value. @@ -972,7 +972,7 @@ void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi, * Obtain the status about this packet. */ txdesc.flags = 0; - rt2x00_desc_read(txwi, 0, &word); + word = rt2x00_desc_read(txwi, 0); mcs = rt2x00_get_field32(word, TXWI_W0_MCS); ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU); diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800mmio.c b/drivers/net/wireless/ralink/rt2x00/rt2800mmio.c index 70ad20691bff..ee5276e233fa 100644 --- a/drivers/net/wireless/ralink/rt2x00/rt2800mmio.c +++ b/drivers/net/wireless/ralink/rt2x00/rt2800mmio.c @@ -109,7 +109,7 @@ void rt2800mmio_fill_rxdone(struct queue_entry *entry, __le32 *rxd = entry_priv->desc; u32 word; - rt2x00_desc_read(rxd, 3, &word); + word = rt2x00_desc_read(rxd, 3); if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR)) rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; @@ -175,7 +175,7 @@ static bool rt2800mmio_txdone_entry_check(struct queue_entry *entry, u32 status) wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID); txwi = rt2800_drv_get_txwi(entry); - rt2x00_desc_read(txwi, 1, &word); + word = rt2x00_desc_read(txwi, 1); tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID); return (tx_wcid == wcid); @@ -696,11 +696,11 @@ bool rt2800mmio_get_entry_state(struct queue_entry *entry) u32 word; if (entry->queue->qid == QID_RX) { - rt2x00_desc_read(entry_priv->desc, 1, &word); + word = rt2x00_desc_read(entry_priv->desc, 1); return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE)); } else { - rt2x00_desc_read(entry_priv->desc, 1, &word); + word = rt2x00_desc_read(entry_priv->desc, 1); return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE)); } @@ -715,11 +715,11 @@ void rt2800mmio_clear_entry(struct queue_entry *entry) u32 word; if (entry->queue->qid == QID_RX) { - rt2x00_desc_read(entry_priv->desc, 0, &word); + word = rt2x00_desc_read(entry_priv->desc, 0); rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma); rt2x00_desc_write(entry_priv->desc, 0, word); - rt2x00_desc_read(entry_priv->desc, 1, &word); + word = rt2x00_desc_read(entry_priv->desc, 1); rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0); rt2x00_desc_write(entry_priv->desc, 1, word); @@ -730,7 +730,7 @@ void rt2800mmio_clear_entry(struct queue_entry *entry) rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx); } else { - rt2x00_desc_read(entry_priv->desc, 1, &word); + word = rt2x00_desc_read(entry_priv->desc, 1); rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1); rt2x00_desc_write(entry_priv->desc, 1, word); } diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800usb.c b/drivers/net/wireless/ralink/rt2x00/rt2800usb.c index 75555f806905..04a7debddb64 100644 --- a/drivers/net/wireless/ralink/rt2x00/rt2800usb.c +++ b/drivers/net/wireless/ralink/rt2x00/rt2800usb.c @@ -456,7 +456,7 @@ static void rt2800usb_write_tx_desc(struct queue_entry *entry, /* * Initialize TXINFO descriptor */ - rt2x00_desc_read(txi, 0, &word); + word = rt2x00_desc_read(txi, 0); /* * The size of TXINFO_W0_USB_DMA_TX_PKT_LEN is @@ -527,7 +527,7 @@ static bool rt2800usb_txdone_entry_check(struct queue_entry *entry, u32 reg) */ txwi = rt2800usb_get_txwi(entry); - rt2x00_desc_read(txwi, 1, &word); + word = rt2x00_desc_read(txwi, 1); tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID); tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK); tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID); @@ -652,7 +652,7 @@ static void rt2800usb_fill_rxdone(struct queue_entry *entry, * | RXINFO | RXWI | header | L2 pad | payload | pad | RXD | USB pad | * |<------------ rx_pkt_len -------------->| */ - rt2x00_desc_read(rxi, 0, &word); + word = rt2x00_desc_read(rxi, 0); rx_pkt_len = rt2x00_get_field32(word, RXINFO_W0_USB_DMA_RX_PKT_LEN); /* @@ -676,7 +676,7 @@ static void rt2800usb_fill_rxdone(struct queue_entry *entry, /* * It is now safe to read the descriptor on all architectures. */ - rt2x00_desc_read(rxd, 0, &word); + word = rt2x00_desc_read(rxd, 0); if (rt2x00_get_field32(word, RXD_W0_CRC_ERROR)) rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; diff --git a/drivers/net/wireless/ralink/rt2x00/rt2x00queue.h b/drivers/net/wireless/ralink/rt2x00/rt2x00queue.h index 6055f36211b9..a15bae29917b 100644 --- a/drivers/net/wireless/ralink/rt2x00/rt2x00queue.h +++ b/drivers/net/wireless/ralink/rt2x00/rt2x00queue.h @@ -642,11 +642,10 @@ static inline int rt2x00queue_dma_timeout(struct queue_entry *entry) * _rt2x00_desc_read - Read a word from the hardware descriptor. * @desc: Base descriptor address * @word: Word index from where the descriptor should be read. - * @value: Address where the descriptor value should be written into. */ -static inline void _rt2x00_desc_read(__le32 *desc, const u8 word, __le32 *value) +static inline __le32 _rt2x00_desc_read(__le32 *desc, const u8 word) { - *value = desc[word]; + return desc[word]; } /** @@ -654,13 +653,10 @@ static inline void _rt2x00_desc_read(__le32 *desc, const u8 word, __le32 *value) * function will take care of the byte ordering. * @desc: Base descriptor address * @word: Word index from where the descriptor should be read. - * @value: Address where the descriptor value should be written into. */ -static inline void rt2x00_desc_read(__le32 *desc, const u8 word, u32 *value) +static inline u32 rt2x00_desc_read(__le32 *desc, const u8 word) { - __le32 tmp; - _rt2x00_desc_read(desc, word, &tmp); - *value = le32_to_cpu(tmp); + return le32_to_cpu(_rt2x00_desc_read(desc, word)); } /** diff --git a/drivers/net/wireless/ralink/rt2x00/rt61pci.c b/drivers/net/wireless/ralink/rt2x00/rt61pci.c index d5b8051466b4..234310200759 100644 --- a/drivers/net/wireless/ralink/rt2x00/rt61pci.c +++ b/drivers/net/wireless/ralink/rt2x00/rt61pci.c @@ -1386,11 +1386,11 @@ static bool rt61pci_get_entry_state(struct queue_entry *entry) u32 word; if (entry->queue->qid == QID_RX) { - rt2x00_desc_read(entry_priv->desc, 0, &word); + word = rt2x00_desc_read(entry_priv->desc, 0); return rt2x00_get_field32(word, RXD_W0_OWNER_NIC); } else { - rt2x00_desc_read(entry_priv->desc, 0, &word); + word = rt2x00_desc_read(entry_priv->desc, 0); return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || rt2x00_get_field32(word, TXD_W0_VALID)); @@ -1404,16 +1404,16 @@ static void rt61pci_clear_entry(struct queue_entry *entry) u32 word; if (entry->queue->qid == QID_RX) { - rt2x00_desc_read(entry_priv->desc, 5, &word); + word = rt2x00_desc_read(entry_priv->desc, 5); rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS, skbdesc->skb_dma); rt2x00_desc_write(entry_priv->desc, 5, word); - rt2x00_desc_read(entry_priv->desc, 0, &word); + word = rt2x00_desc_read(entry_priv->desc, 0); rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1); rt2x00_desc_write(entry_priv->desc, 0, word); } else { - rt2x00_desc_read(entry_priv->desc, 0, &word); + word = rt2x00_desc_read(entry_priv->desc, 0); rt2x00_set_field32(&word, TXD_W0_VALID, 0); rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0); rt2x00_desc_write(entry_priv->desc, 0, word); @@ -1879,7 +1879,7 @@ static void rt61pci_write_tx_desc(struct queue_entry *entry, /* * Start writing the descriptor words. */ - rt2x00_desc_read(txd, 1, &word); + word = rt2x00_desc_read(txd, 1); rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid); rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs); rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min); @@ -1890,7 +1890,7 @@ static void rt61pci_write_tx_desc(struct queue_entry *entry, rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1); rt2x00_desc_write(txd, 1, word); - rt2x00_desc_read(txd, 2, &word); + word = rt2x00_desc_read(txd, 2); rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal); rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service); rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, @@ -1904,7 +1904,7 @@ static void rt61pci_write_tx_desc(struct queue_entry *entry, _rt2x00_desc_write(txd, 4, skbdesc->iv[1]); } - rt2x00_desc_read(txd, 5, &word); + word = rt2x00_desc_read(txd, 5); rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid); rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx); rt2x00_set_field32(&word, TXD_W5_TX_POWER, @@ -1913,12 +1913,12 @@ static void rt61pci_write_tx_desc(struct queue_entry *entry, rt2x00_desc_write(txd, 5, word); if (entry->queue->qid != QID_BEACON) { - rt2x00_desc_read(txd, 6, &word); + word = rt2x00_desc_read(txd, 6); rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, skbdesc->skb_dma); rt2x00_desc_write(txd, 6, word); - rt2x00_desc_read(txd, 11, &word); + word = rt2x00_desc_read(txd, 11); rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, txdesc->length); rt2x00_desc_write(txd, 11, word); @@ -1929,7 +1929,7 @@ static void rt61pci_write_tx_desc(struct queue_entry *entry, * the device, whereby the device may take hold of the TXD before we * finished updating it. */ - rt2x00_desc_read(txd, 0, &word); + word = rt2x00_desc_read(txd, 0); rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); rt2x00_set_field32(&word, TXD_W0_VALID, 1); rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, @@ -2095,8 +2095,8 @@ static void rt61pci_fill_rxdone(struct queue_entry *entry, u32 word0; u32 word1; - rt2x00_desc_read(entry_priv->desc, 0, &word0); - rt2x00_desc_read(entry_priv->desc, 1, &word1); + word0 = rt2x00_desc_read(entry_priv->desc, 0); + word1 = rt2x00_desc_read(entry_priv->desc, 1); if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; @@ -2105,11 +2105,11 @@ static void rt61pci_fill_rxdone(struct queue_entry *entry, rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR); if (rxdesc->cipher != CIPHER_NONE) { - _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]); - _rt2x00_desc_read(entry_priv->desc, 3, &rxdesc->iv[1]); + rxdesc->iv[0] = _rt2x00_desc_read(entry_priv->desc, 2); + rxdesc->iv[1] = _rt2x00_desc_read(entry_priv->desc, 3); rxdesc->dev_flags |= RXDONE_CRYPTO_IV; - _rt2x00_desc_read(entry_priv->desc, 4, &rxdesc->icv); + rxdesc->icv = _rt2x00_desc_read(entry_priv->desc, 4); rxdesc->dev_flags |= RXDONE_CRYPTO_ICV; /* @@ -2198,7 +2198,7 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev) entry = &queue->entries[index]; entry_priv = entry->priv_data; - rt2x00_desc_read(entry_priv->desc, 0, &word); + word = rt2x00_desc_read(entry_priv->desc, 0); if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) || !rt2x00_get_field32(word, TXD_W0_VALID)) diff --git a/drivers/net/wireless/ralink/rt2x00/rt73usb.c b/drivers/net/wireless/ralink/rt2x00/rt73usb.c index b736982c0126..fd913222abd1 100644 --- a/drivers/net/wireless/ralink/rt2x00/rt73usb.c +++ b/drivers/net/wireless/ralink/rt2x00/rt73usb.c @@ -1462,7 +1462,7 @@ static void rt73usb_write_tx_desc(struct queue_entry *entry, /* * Start writing the descriptor words. */ - rt2x00_desc_read(txd, 0, &word); + word = rt2x00_desc_read(txd, 0); rt2x00_set_field32(&word, TXD_W0_BURST, test_bit(ENTRY_TXD_BURST, &txdesc->flags)); rt2x00_set_field32(&word, TXD_W0_VALID, 1); @@ -1488,7 +1488,7 @@ static void rt73usb_write_tx_desc(struct queue_entry *entry, rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher); rt2x00_desc_write(txd, 0, word); - rt2x00_desc_read(txd, 1, &word); + word = rt2x00_desc_read(txd, 1); rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid); rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs); rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min); @@ -1498,7 +1498,7 @@ static void rt73usb_write_tx_desc(struct queue_entry *entry, test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); rt2x00_desc_write(txd, 1, word); - rt2x00_desc_read(txd, 2, &word); + word = rt2x00_desc_read(txd, 2); rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal); rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service); rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, @@ -1512,7 +1512,7 @@ static void rt73usb_write_tx_desc(struct queue_entry *entry, _rt2x00_desc_write(txd, 4, skbdesc->iv[1]); } - rt2x00_desc_read(txd, 5, &word); + word = rt2x00_desc_read(txd, 5); rt2x00_set_field32(&word, TXD_W5_TX_POWER, TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power)); rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1); @@ -1694,8 +1694,8 @@ static void rt73usb_fill_rxdone(struct queue_entry *entry, /* * It is now safe to read the descriptor on all architectures. */ - rt2x00_desc_read(rxd, 0, &word0); - rt2x00_desc_read(rxd, 1, &word1); + word0 = rt2x00_desc_read(rxd, 0); + word1 = rt2x00_desc_read(rxd, 1); if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; @@ -1704,11 +1704,11 @@ static void rt73usb_fill_rxdone(struct queue_entry *entry, rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR); if (rxdesc->cipher != CIPHER_NONE) { - _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]); - _rt2x00_desc_read(rxd, 3, &rxdesc->iv[1]); + rxdesc->iv[0] = _rt2x00_desc_read(rxd, 2); + rxdesc->iv[1] = _rt2x00_desc_read(rxd, 3); rxdesc->dev_flags |= RXDONE_CRYPTO_IV; - _rt2x00_desc_read(rxd, 4, &rxdesc->icv); + rxdesc->icv = _rt2x00_desc_read(rxd, 4); rxdesc->dev_flags |= RXDONE_CRYPTO_ICV; /*