From patchwork Wed Jul 21 11:36:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 483491 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02276C07E9B for ; Wed, 21 Jul 2021 11:40:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AF86C6120A for ; Wed, 21 Jul 2021 11:40:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238099AbhGUK67 (ORCPT ); Wed, 21 Jul 2021 06:58:59 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:34386 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237773AbhGUK4E (ORCPT ); Wed, 21 Jul 2021 06:56:04 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 16LBaXeC058743; Wed, 21 Jul 2021 06:36:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1626867393; bh=BrYp/NL15Aj44S8+xgk5v85ywLu8jggNxu+gcJm/iQo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=n5eEDfBMxKR89V+AnTJYYLFFM6dOj8xIxmJysAva5rpefoqmtfgmlbTZAvOOVwh6P 8q9luuFkq5IXGNf9Nk/z2XqrYZC+ejqOU778poBZzgKHHcuckq1HbaCN6hOx5ADybR 8WeOYwYcbFzYlfaKGAOWQ3AnMA8A/Z1O9oqRSheU= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 16LBaXtx076824 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 21 Jul 2021 06:36:33 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 21 Jul 2021 06:36:33 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 21 Jul 2021 06:36:33 -0500 Received: from lokesh-ssd.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 16LBaQBm115096; Wed, 21 Jul 2021 06:36:30 -0500 From: Lokesh Vutla To: Nishanth Menon , CC: Device Tree Mailing List , Rob Herring , Linux ARM Mailing List , , Vignesh R , Lokesh Vutla Subject: [PATCH v2 1/4] arm64: dts: ti: k3-am64-main: Add epwm nodes Date: Wed, 21 Jul 2021 17:06:22 +0530 Message-ID: <20210721113625.17299-2-lokeshvutla@ti.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210721113625.17299-1-lokeshvutla@ti.com> References: <20210721113625.17299-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT nodes for all epwm instances present in AM64 SoC. Signed-off-by: Lokesh Vutla --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 87 ++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 02c3fdf9cc46..9e762f64b631 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -217,6 +217,12 @@ phy_gmii_sel: phy@4044 { reg = <0x4044 0x8>; #phy-cells = <1>; }; + + epwm_tbclk: clock@4140 { + compatible = "ti,am64-epwm-tbclk", "syscon"; + reg = <0x4130 0x4>; + #clock-cells = <1>; + }; }; main_uart0: serial@2800000 { @@ -859,4 +865,85 @@ pcie0_ep: pcie-ep@f102000 { clock-names = "fck"; max-functions = /bits/ 8 <1>; }; + + epwm0: pwm@23000000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x0 0x23000000 0x0 0x100>; + power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; + clock-names = "tbclk", "fck"; + }; + + epwm1: pwm@23010000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x0 0x23010000 0x0 0x100>; + power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; + clock-names = "tbclk", "fck"; + }; + + epwm2: pwm@23020000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x0 0x23020000 0x0 0x100>; + power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; + clock-names = "tbclk", "fck"; + }; + + epwm3: pwm@23030000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x0 0x23030000 0x0 0x100>; + power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>; + clock-names = "tbclk", "fck"; + }; + + epwm4: pwm@23040000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x0 0x23040000 0x0 0x100>; + power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>; + clock-names = "tbclk", "fck"; + }; + + epwm5: pwm@23050000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x0 0x23050000 0x0 0x100>; + power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>; + clock-names = "tbclk", "fck"; + }; + + epwm6: pwm@23060000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x0 0x23060000 0x0 0x100>; + power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>; + clock-names = "tbclk", "fck"; + }; + + epwm7: pwm@23070000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x0 0x23070000 0x0 0x100>; + power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>; + clock-names = "tbclk", "fck"; + }; + + epwm8: pwm@23080000 { + compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x0 0x23080000 0x0 0x100>; + power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>; + clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>; + clock-names = "tbclk", "fck"; + }; }; From patchwork Wed Jul 21 11:36:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 484110 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61E57C12002 for ; Wed, 21 Jul 2021 11:40:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 38D846109F for ; Wed, 21 Jul 2021 11:40:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238057AbhGUK64 (ORCPT ); Wed, 21 Jul 2021 06:58:56 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:34390 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237783AbhGUK4E (ORCPT ); Wed, 21 Jul 2021 06:56:04 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 16LBaa1u058757; Wed, 21 Jul 2021 06:36:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1626867396; bh=zTc0+d5by1yn2c2oxZDaWLTqDtg1JcqD65QZC9tn/98=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=EH/xpLCSywfg1GlSxcvWScXzqutR0Kele8XTwoQazKl+vTub/HRw2yNwVvL4iS4qa pDXZLua3Hqac7F8FMTxNOEwZsJxPIptXQVqA3v2tuC9zpytrrYbstMbLICnAcCe0qn guyoFvGGI6s1SYIWDnrvIJHcya6nNn99Vf7Jejvg= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 16LBaaB7109213 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 21 Jul 2021 06:36:36 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 21 Jul 2021 06:36:36 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 21 Jul 2021 06:36:36 -0500 Received: from lokesh-ssd.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 16LBaQBn115096; Wed, 21 Jul 2021 06:36:33 -0500 From: Lokesh Vutla To: Nishanth Menon , CC: Device Tree Mailing List , Rob Herring , Linux ARM Mailing List , , Vignesh R , Lokesh Vutla Subject: [PATCH v2 2/4] arm64: dts: ti: k3-am64-main: Add ecap pwm nodes Date: Wed, 21 Jul 2021 17:06:23 +0530 Message-ID: <20210721113625.17299-3-lokeshvutla@ti.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210721113625.17299-1-lokeshvutla@ti.com> References: <20210721113625.17299-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org There are 3 instances of ecap modules that are capable of generating a pwm when configured in apwm mode. Add DT nodes for these 3 ecap instances. Signed-off-by: Lokesh Vutla --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 27 ++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 9e762f64b631..42d1d219a3fd 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -946,4 +946,31 @@ epwm8: pwm@23080000 { clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>; clock-names = "tbclk", "fck"; }; + + ecap0: pwm@23100000 { + compatible = "ti,am64-ecap", "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x0 0x23100000 0x0 0x60>; + power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 51 0>; + clock-names = "fck"; + }; + + ecap1: pwm@23110000 { + compatible = "ti,am64-ecap", "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x0 0x23110000 0x0 0x60>; + power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 52 0>; + clock-names = "fck"; + }; + + ecap2: pwm@23120000 { + compatible = "ti,am64-ecap", "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x0 0x23120000 0x0 0x60>; + power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 53 0>; + clock-names = "fck"; + }; }; From patchwork Wed Jul 21 11:36:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 483492 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C464FC07E9B for ; Wed, 21 Jul 2021 11:40:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A187061208 for ; Wed, 21 Jul 2021 11:40:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238180AbhGUK7E (ORCPT ); Wed, 21 Jul 2021 06:59:04 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:34392 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238076AbhGUK4F (ORCPT ); Wed, 21 Jul 2021 06:56:05 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 16LBad7k058772; Wed, 21 Jul 2021 06:36:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1626867399; bh=uePKf1OmyD6OW0Cttfy3/pVQXaBFYXSb4x30lPq/Iu4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=aVa/JL+sAkp1YLYA5RNLP4P49vZXWpMi43qsqcc12rLrEXiHr3DwfxtqOxU+7YpBq SLYkkRh3TA7BI+IsZveH5lXsy3vTB+GrVktFZEGhKoYJIIkKTC2DJglEohHddXPUzG jG4ovdugTCd7wipHjR9wRm76cAkHZcBQXsbPGBjs= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 16LBadDS109237 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 21 Jul 2021 06:36:39 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 21 Jul 2021 06:36:38 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 21 Jul 2021 06:36:39 -0500 Received: from lokesh-ssd.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 16LBaQBo115096; Wed, 21 Jul 2021 06:36:36 -0500 From: Lokesh Vutla To: Nishanth Menon , CC: Device Tree Mailing List , Rob Herring , Linux ARM Mailing List , , Vignesh R , Lokesh Vutla Subject: [PATCH v2 3/4] arm64: dts: ti: k3-am642-evm: Add pwm nodes Date: Wed, 21 Jul 2021 17:06:24 +0530 Message-ID: <20210721113625.17299-4-lokeshvutla@ti.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210721113625.17299-1-lokeshvutla@ti.com> References: <20210721113625.17299-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org ecap0 can be configured to use pad ECAP0_IN_APWM_OUT (D18) which has a signal connected to Pin 1 of J12 on EVM. Add support for adding this pinmux so that pwm can be observed on pin 1 of Header J12 Also mark all un-used epwm and ecap pwm nodes as disabled. Signed-off-by: Lokesh Vutla --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 56 +++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 030712221188..24ce4942618d 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -288,6 +288,12 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ >; }; + + main_ecap0_pins_default: main-ecap0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ + >; + }; }; &main_uart0 { @@ -574,3 +580,53 @@ &pcie0_ep { num-lanes = <1>; status = "disabled"; }; + +&ecap0 { + /* PWM is available on Pin 1 of header J12 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap0_pins_default>; +}; + +&ecap1 { + status = "disabled"; +}; + +&ecap2 { + status = "disabled"; +}; + +&epwm0 { + status = "disabled"; +}; + +&epwm1 { + status = "disabled"; +}; + +&epwm2 { + status = "disabled"; +}; + +&epwm3 { + status = "disabled"; +}; + +&epwm4 { + status = "disabled"; +}; + +&epwm5 { + status = "disabled"; +}; + +&epwm6 { + status = "disabled"; +}; + +&epwm7 { + status = "disabled"; +}; + +&epwm8 { + status = "disabled"; +}; From patchwork Wed Jul 21 11:36:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 484109 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F26A7C636C9 for ; Wed, 21 Jul 2021 11:40:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BB8E26109F for ; Wed, 21 Jul 2021 11:40:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238222AbhGUK7G (ORCPT ); Wed, 21 Jul 2021 06:59:06 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:34402 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238268AbhGUK4I (ORCPT ); Wed, 21 Jul 2021 06:56:08 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 16LBagsh058786; Wed, 21 Jul 2021 06:36:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1626867402; bh=D4NmLUs3UlfPiqgvotqTScLaeN1iSSzMQoE9snEy5vo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ttfALl4zNzI1NzT9gHciOr5yujy57KlJl9sWZJ247t3eRMT1O+Dd6GmEB9ZCSC4Sc O0mPtCeuEzBmWo6oXma5QR6KbeJIDIex45rX2ud+JftZ+MyaKts2xq6n9BDtZo0BZC aklVVyVwkuJER7iEvIqhEL7896N7GqtBkQnT0Ysw= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 16LBagJD089847 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 21 Jul 2021 06:36:42 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 21 Jul 2021 06:36:42 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 21 Jul 2021 06:36:41 -0500 Received: from lokesh-ssd.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 16LBaQBp115096; Wed, 21 Jul 2021 06:36:39 -0500 From: Lokesh Vutla To: Nishanth Menon , CC: Device Tree Mailing List , Rob Herring , Linux ARM Mailing List , , Vignesh R , Lokesh Vutla Subject: [PATCH v2 4/4] arm64: dts: ti: k3-am642-sk: Add pwm nodes Date: Wed, 21 Jul 2021 17:06:25 +0530 Message-ID: <20210721113625.17299-5-lokeshvutla@ti.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210721113625.17299-1-lokeshvutla@ti.com> References: <20210721113625.17299-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org ecap0 can be configured to use pad ECAP0_IN_APWM_OUT (D18) which has a signal connected to Pin 1 of J3. Add support for adding this pinmux so that pwm can be observed on pin 1 of Header J3 Also mark all un-used epwm and ecap pwm nodes as disabled. Signed-off-by: Lokesh Vutla --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 64 ++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index d3aa2901e6fd..6b45cdeeeefa 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -210,6 +210,12 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ >; }; + + main_ecap0_pins_default: main-ecap0-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ + >; + }; }; &mcu_uart0 { @@ -453,3 +459,61 @@ &pcie0_rc { &pcie0_ep { status = "disabled"; }; + +&ecap0 { + /* PWM is available on Pin 1 of header J3 */ + pinctrl-names = "default"; + pinctrl-0 = <&main_ecap0_pins_default>; +}; + +&ecap1 { + status = "disabled"; +}; + +&ecap2 { + status = "disabled"; +}; + +&epwm0 { + status = "disabled"; +}; + +&epwm1 { + status = "disabled"; +}; + +&epwm2 { + status = "disabled"; +}; + +&epwm3 { + status = "disabled"; +}; + +&epwm4 { + /* + * EPWM4_A, EPWM4_B is available on Pin 32 and 33 on J4 (RPi hat) + * But RPi Hat will be used for other use cases, so marking epwm4 as disabled. + */ + status = "disabled"; +}; + +&epwm5 { + /* + * EPWM5_A, EPWM5_B is available on Pin 29 and 31 on J4 (RPi hat) + * But RPi Hat will be used for other use cases, so marking epwm5 as disabled. + */ + status = "disabled"; +}; + +&epwm6 { + status = "disabled"; +}; + +&epwm7 { + status = "disabled"; +}; + +&epwm8 { + status = "disabled"; +};