From patchwork Wed May 17 10:49:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 99947 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp159579qge; Wed, 17 May 2017 03:19:44 -0700 (PDT) X-Received: by 10.98.2.85 with SMTP id 82mr2870149pfc.52.1495016384735; Wed, 17 May 2017 03:19:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495016384; cv=none; d=google.com; s=arc-20160816; b=H2g2feBYVeQxGornBXNI9nBAHh9Gj5A9Z0e7Xi5/rE25eWl9nptiyKNFVyas98Drsw hb7KIjZPAed4kECjcgMX8nzPLVe6wKeKTmpDtdl3o8zNoSU94apL37O7rGLI3cZKcUL6 TisvoPWiwg/YKXIndH15jDxeWhxpOl0Ve59X4Nn37W0+T5Yj+XHFkww+CGa3OuLMGeyS ulC4lQlIweZZRlucz7jStqpuBOlyXMYHqAU33nGA8feTT0vVyuZYAHAfQIbnE4BMtD+2 //5mCy5XypZTElE69rcv2pu9W2CMTV2EobB4++Z2emz9qdt8/UPgR3h7mbocDnaU04rZ MN4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=Us+A426uMq7XGQ+3i3+LHy/7M813ZY4dQi9JtBUP2wo=; b=fuc7EjfQkZpuB2M+LvSdTxni1sjpYLEVhC3xnf6v9dfwtcQnQn0hphHQRvvtOOC8xb 1C/rTzwbB4O8XM/rx5Mhh8AOb8Z8fJ5Tf9bmOx5F0Kr7K1YqZoHSxixTZsViOa5Icmnx CeA98m9CS0VMuIDKgnZ0JlBzW9gDmGw0Xm24Ja9FVoUXS+7raakjoagBgi37dtmDh+6q mSIijBTBsd3QDikLprLU5tgfnVGMUTKF1KF195slX5wcFiYk00j0lxwulHY9TDEWIsA9 Prb2eLHfUPX6my9k8x3yOxhYDy6o0Lo4hhbrbWMqs5yaWJmVlRBs2i0Xb5WdELgyW391 N1bQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f79si1678041pfd.308.2017.05.17.03.19.44; Wed, 17 May 2017 03:19:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754170AbdEQKTn (ORCPT + 1 other); Wed, 17 May 2017 06:19:43 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:6309 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752913AbdEQKTl (ORCPT ); Wed, 17 May 2017 06:19:41 -0400 Received: from 172.30.72.57 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.57]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOT12408; Wed, 17 May 2017 18:19:37 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Wed, 17 May 2017 18:19:31 +0800 From: John Garry To: , CC: , , , , , Xiang Chen , John Garry Subject: [PATCH 01/22] scsi: hisi_sas: fix timeout check in hisi_sas_internal_task_abort() Date: Wed, 17 May 2017 18:49:36 +0800 Message-ID: <1495018197-120535-2-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495018197-120535-1-git-send-email-john.garry@huawei.com> References: <1495018197-120535-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020203.591C23BA.002F, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: b27ed3aa20296f3e60cae0bed2744b43 Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Xiang Chen We need to check for timeout before task status, or the task will be mistook as completed internal abort command. Also add protection for sas_task.task_state_flags in hisi_sas_tmf_timedout(). Signed-off-by: Xiang Chen Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_main.c | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index d622db5..98535aa 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -691,8 +691,13 @@ static void hisi_sas_task_done(struct sas_task *task) static void hisi_sas_tmf_timedout(unsigned long data) { struct sas_task *task = (struct sas_task *)data; + unsigned long flags; + + spin_lock_irqsave(&task->task_state_lock, flags); + if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) + task->task_state_flags |= SAS_TASK_STATE_ABORTED; + spin_unlock_irqrestore(&task->task_state_lock, flags); - task->task_state_flags |= SAS_TASK_STATE_ABORTED; complete(&task->slow_task->completion); } @@ -1247,6 +1252,17 @@ static int hisi_sas_query_task(struct sas_task *task) wait_for_completion(&task->slow_task->completion); res = TMF_RESP_FUNC_FAILED; + /* Internal abort timed out */ + if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) { + if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) { + struct hisi_sas_slot *slot = task->lldd_task; + + if (slot) + slot->task = NULL; + dev_err(dev, "internal task abort: timeout.\n"); + } + } + if (task->task_status.resp == SAS_TASK_COMPLETE && task->task_status.stat == TMF_RESP_FUNC_COMPLETE) { res = TMF_RESP_FUNC_COMPLETE; @@ -1259,13 +1275,6 @@ static int hisi_sas_query_task(struct sas_task *task) goto exit; } - /* Internal abort timed out */ - if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) { - if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) { - dev_err(dev, "internal task abort: timeout.\n"); - } - } - exit: dev_dbg(dev, "internal task abort: task to dev %016llx task=%p " "resp: 0x%x sts 0x%x\n", From patchwork Wed May 17 10:49:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 99967 Delivered-To: patch@linaro.org Received: by 10.182.142.97 with SMTP id rv1csp141110obb; Wed, 17 May 2017 03:24:02 -0700 (PDT) X-Received: by 10.98.9.92 with SMTP id e89mr2904200pfd.177.1495016642685; Wed, 17 May 2017 03:24:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495016642; cv=none; d=google.com; s=arc-20160816; b=bVH9zbqJZHH/IacRVRiK8dnfntibsTwwjUHZxvEv3gDKxO1c3d0Mtc34ybiw5sza40 wD0tClgLeJ9yf3PyNTVXf6WUDVsWaTka0fJ4O8kHVTW9jylsWs4gtEg5vurVhpCQ+l9i hZeMkU1Q8Cy9DPYtOp24Iit2PnBrT+yzFKZflOtX1sIL80GVddkHUp/Qan/CU2HJwDVo j7zrVMzsDlZGaN3IyWtg0dhygkuIHvJy7yVt3yXCoqnEP2ShpIoI3ws35n+VRiu/+lMh JeGp6jTe+2Oab/OIrxRSSylRmjGMqDqh3nEfHDljSzxH2LiCqYf7+yORZS6Oqr7LsfeK rcbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=DZQIidEvHHDOO8QjPk6/ONxAyk6mlWVcaFQyRoTNfQ8=; b=JuceVvgw1CfZU3ch9NwitmzadsRHZjNkNhygqFvqAlIJ8YOCdGwot9cBlHG/N1xbtH 1J6tngsCWhf1ZPAKy0jYf3hZqi3sgrRSDcSWr497Rf4AcTBF26kUGWOTb+mww+pwS2tG DgRlYiu9762majaVQBO5YriLXAHkPIgIrsJYarq/TnIZjSygGr3lwsWiVL73M0w9Qtgq oXBonpceuwEYDf6CSRB8FNhdi/CNTuGZrQT5/amShAAJRvqSNb88P37xmO//B27kimr4 fp76zBQ48df8PCC0hnOYYvlLHL9LrSH8xXnZReNmvIJqInFDLhKv/BMGcO/4zesHMpaF oDdg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q12si1768108pgf.56.2017.05.17.03.24.02; Wed, 17 May 2017 03:24:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932104AbdEQKXv (ORCPT + 1 other); Wed, 17 May 2017 06:23:51 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:6311 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754183AbdEQKTp (ORCPT ); Wed, 17 May 2017 06:19:45 -0400 Received: from 172.30.72.55 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.55]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOT12424; Wed, 17 May 2017 18:19:42 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Wed, 17 May 2017 18:19:34 +0800 From: John Garry To: , CC: , , , , , Xiang Chen , John Garry Subject: [PATCH 11/22] scsi: hisi_sas: add v3 hw PHY init Date: Wed, 17 May 2017 18:49:46 +0800 Message-ID: <1495018197-120535-12-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495018197-120535-1-git-send-email-john.garry@huawei.com> References: <1495018197-120535-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020206.591C23BF.0087, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 4f1d68d32fdbfbb166d0e6060f2b0aa0 Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Xiang Chen Add code to configure PHYs for v3 hw. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 126 +++++++++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index f2ea8c8..ea18582 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -19,6 +19,10 @@ #define ITCT_BASE_ADDR_HI 0x14 #define IO_BROKEN_MSG_ADDR_LO 0x18 #define IO_BROKEN_MSG_ADDR_HI 0x1c +#define PHY_CONTEXT 0x20 +#define PHY_STATE 0x24 +#define PHY_PORT_NUM_MA 0x28 +#define PHY_CONN_RATE 0x30 #define AXI_AHB_CLK_CFG 0x3c #define AXI_USER1 0x48 #define AXI_USER2 0x4c @@ -42,6 +46,7 @@ #define CFG_SET_ABORTED_IPTT_OFF 0 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) #define CFG_1US_TIMER_TRSH 0xcc +#define CHNL_INT_STATUS 0x148 #define INT_COAL_EN 0x19c #define OQ_INT_COAL_TIME 0x1a0 #define OQ_INT_COAL_CNT 0x1a4 @@ -68,9 +73,11 @@ #define ENT_INT_SRC_MSK1 0x1c4 #define ENT_INT_SRC_MSK2 0x1c8 #define ENT_INT_SRC_MSK3 0x1cc +#define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0 #define CHNL_ENT_INT_MSK 0x1d4 #define HGC_COM_INT_MSK 0x1d8 +#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) #define SAS_ECC_INTR 0x1e8 #define SAS_ECC_INTR_MSK 0x1ec #define HGC_ERR_STAT_EN 0x238 @@ -91,11 +98,33 @@ /* phy registers requiring init */ #define PORT_BASE (0x2000) +#define PHY_CFG (PORT_BASE + 0x0) +#define HARD_PHY_LINKRATE (PORT_BASE + 0x4) +#define PHY_CFG_ENA_OFF 0 +#define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) +#define PHY_CFG_DC_OPT_OFF 2 +#define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) #define PHY_CTRL (PORT_BASE + 0x14) #define PHY_CTRL_RESET_OFF 0 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) #define SL_CFG (PORT_BASE + 0x84) +#define SL_CONTROL (PORT_BASE + 0x94) +#define SL_CONTROL_NOTIFY_EN_OFF 0 +#define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) +#define SL_CTA_OFF 17 +#define SL_CTA_MSK (0x1 << SL_CTA_OFF) +#define TX_ID_DWORD0 (PORT_BASE + 0x9c) +#define TX_ID_DWORD1 (PORT_BASE + 0xa0) +#define TX_ID_DWORD2 (PORT_BASE + 0xa4) +#define TX_ID_DWORD3 (PORT_BASE + 0xa8) +#define TX_ID_DWORD4 (PORT_BASE + 0xaC) +#define TX_ID_DWORD5 (PORT_BASE + 0xb0) +#define TX_ID_DWORD6 (PORT_BASE + 0xb4) +#define TXID_AUTO (PORT_BASE + 0xb8) +#define CT3_OFF 1 +#define CT3_MSK (0x1 << CT3_OFF) +#define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138) @@ -135,6 +164,13 @@ struct hisi_sas_complete_v3_hdr { }; #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096 +#define HISI_SAS_MSI_COUNT_V3_HW 32 + +enum { + HISI_SAS_PHY_PHY_UPDOWN, + HISI_SAS_PHY_CHNL_INT, + HISI_SAS_PHY_INT_NR +}; static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) { @@ -151,6 +187,14 @@ static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, writel(val, regs); } +static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, + int phy_no, u32 off) +{ + void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; + + return readl(regs); +} + static void init_reg_v3_hw(struct hisi_hba *hisi_hba) { int i; @@ -265,6 +309,45 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) upper_32_bits(hisi_hba->initial_fis_dma)); } +static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); + + cfg &= ~PHY_CFG_DC_OPT_MSK; + cfg |= 1 << PHY_CFG_DC_OPT_OFF; + hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); +} + +static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + struct sas_identify_frame identify_frame; + u32 *identify_buffer; + + memset(&identify_frame, 0, sizeof(identify_frame)); + identify_frame.dev_type = SAS_END_DEVICE; + identify_frame.frame_type = 0; + identify_frame._un1 = 1; + identify_frame.initiator_bits = SAS_PROTOCOL_ALL; + identify_frame.target_bits = SAS_PROTOCOL_NONE; + memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); + memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); + identify_frame.phy_id = phy_no; + identify_buffer = (u32 *)(&identify_frame); + + hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, + __swab32(identify_buffer[0])); + hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, + __swab32(identify_buffer[1])); + hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, + __swab32(identify_buffer[2])); + hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, + __swab32(identify_buffer[3])); + hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, + __swab32(identify_buffer[4])); + hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, + __swab32(identify_buffer[5])); +} + static int hw_init_v3_hw(struct hisi_hba *hisi_hba) { init_reg_v3_hw(hisi_hba); @@ -272,6 +355,47 @@ static int hw_init_v3_hw(struct hisi_hba *hisi_hba) return 0; } +static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); + + cfg |= PHY_CFG_ENA_MSK; + hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); +} + +static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + config_id_frame_v3_hw(hisi_hba, phy_no); + config_phy_opt_mode_v3_hw(hisi_hba, phy_no); + enable_phy_v3_hw(hisi_hba, phy_no); +} + +static void start_phys_v3_hw(struct hisi_hba *hisi_hba) +{ + int i; + + for (i = 0; i < hisi_hba->n_phy; i++) + start_phy_v3_hw(hisi_hba, i); +} + +static void phys_init_v3_hw(struct hisi_hba *hisi_hba) +{ + start_phys_v3_hw(hisi_hba); +} + +static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + u32 sl_control; + + sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); + sl_control |= SL_CONTROL_NOTIFY_EN_MSK; + hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); + msleep(1); + sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); + sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; + hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); +} + static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) { int rc; @@ -286,7 +410,9 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) static const struct hisi_sas_hw hisi_sas_v3_hw = { .hw_init = hisi_sas_v3_init, .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, + .sl_notify = sl_notify_v3_hw, .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), + .phys_init = phys_init_v3_hw, }; enum { From patchwork Wed May 17 10:49:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 99956 Delivered-To: patch@linaro.org Received: by 10.182.142.97 with SMTP id rv1csp140287obb; Wed, 17 May 2017 03:21:24 -0700 (PDT) X-Received: by 10.99.178.11 with SMTP id x11mr3005377pge.68.1495016484406; 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[209.132.180.67]) by mx.google.com with ESMTP id e70si1656986pfd.278.2017.05.17.03.21.24; Wed, 17 May 2017 03:21:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754611AbdEQKVT (ORCPT + 1 other); Wed, 17 May 2017 06:21:19 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:6760 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753715AbdEQKTt (ORCPT ); Wed, 17 May 2017 06:19:49 -0400 Received: from 172.30.72.55 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.55]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOT12446; Wed, 17 May 2017 18:19:46 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Wed, 17 May 2017 18:19:35 +0800 From: John Garry To: , CC: , , , , , Xiang Chen , John Garry Subject: [PATCH 14/22] scsi: hisi_sas: add v3 code to send SSP frame Date: Wed, 17 May 2017 18:49:49 +0800 Message-ID: <1495018197-120535-15-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495018197-120535-1-git-send-email-john.garry@huawei.com> References: <1495018197-120535-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.591C23C3.00F0, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 233028b5a0ed62fd4cc310391e54a906 Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Xiang Chen Add code to prepare SSP frame and deliver it to hardware. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 209 +++++++++++++++++++++++++++++++++ 1 file changed, 209 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index b33781b..77616ff 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -157,6 +157,41 @@ #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) +/* HW dma structures */ +/* Delivery queue header */ +/* dw0 */ +#define CMD_HDR_RESP_REPORT_OFF 5 +#define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) +#define CMD_HDR_TLR_CTRL_OFF 6 +#define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) +#define CMD_HDR_PORT_OFF 18 +#define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) +#define CMD_HDR_PRIORITY_OFF 27 +#define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) +#define CMD_HDR_CMD_OFF 29 +#define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) +/* dw1 */ +#define CMD_HDR_DIR_OFF 5 +#define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) +#define CMD_HDR_VDTL_OFF 10 +#define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) +#define CMD_HDR_FRAME_TYPE_OFF 11 +#define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) +#define CMD_HDR_DEV_ID_OFF 16 +#define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) +/* dw2 */ +#define CMD_HDR_CFL_OFF 0 +#define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) +#define CMD_HDR_MRFL_OFF 15 +#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) +#define CMD_HDR_SG_MOD_OFF 24 +#define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) +/* dw6 */ +#define CMD_HDR_DIF_SGL_LEN_OFF 0 +#define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) +#define CMD_HDR_DATA_SGL_LEN_OFF 16 +#define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) + /* Completion header */ /* dw0 */ #define CMPLT_HDR_CMPLT_OFF 0 @@ -201,6 +236,11 @@ enum { HISI_SAS_PHY_INT_NR }; +#define DIR_NO_DATA 0 +#define DIR_TO_INI 1 +#define DIR_TO_DEVICE 2 +#define DIR_RESERVED 3 + static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) { void __iomem *regs = hisi_hba->regs + off; @@ -208,6 +248,13 @@ static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) return readl(regs); } +static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) +{ + void __iomem *regs = hisi_hba->regs + off; + + return readl_relaxed(regs); +} + static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) { void __iomem *regs = hisi_hba->regs + off; @@ -432,6 +479,163 @@ static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no) hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); } +/** + * The callpath to this function and upto writing the write + * queue pointer should be safe from interruption. + */ +static int +get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) +{ + struct device *dev = hisi_hba->dev; + int queue = dq->id; + u32 r, w; + + w = dq->wr_point; + r = hisi_sas_read32_relaxed(hisi_hba, + DLVRY_Q_0_RD_PTR + (queue * 0x14)); + if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { + dev_warn(dev, "full queue=%d r=%d w=%d\n\n", + queue, r, w); + return -EAGAIN; + } + + return 0; +} + +static void start_delivery_v3_hw(struct hisi_sas_dq *dq) +{ + struct hisi_hba *hisi_hba = dq->hisi_hba; + int dlvry_queue = dq->slot_prep->dlvry_queue; + int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot; + + dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS; + hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), + dq->wr_point); +} + +static int prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba, + struct hisi_sas_slot *slot, + struct hisi_sas_cmd_hdr *hdr, + struct scatterlist *scatter, + int n_elem) +{ + struct device *dev = hisi_hba->dev; + struct scatterlist *sg; + int i; + + if (n_elem > HISI_SAS_SGE_PAGE_CNT) { + dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT", + n_elem); + return -EINVAL; + } + + slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC, + &slot->sge_page_dma); + if (!slot->sge_page) + return -ENOMEM; + + for_each_sg(scatter, sg, n_elem, i) { + struct hisi_sas_sge *entry = &slot->sge_page->sge[i]; + + entry->addr = cpu_to_le64(sg_dma_address(sg)); + entry->page_ctrl_0 = entry->page_ctrl_1 = 0; + entry->data_len = cpu_to_le32(sg_dma_len(sg)); + entry->data_off = 0; + } + + hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma); + hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); + + return 0; +} + +static int prep_ssp_v3_hw(struct hisi_hba *hisi_hba, + struct hisi_sas_slot *slot, int is_tmf, + struct hisi_sas_tmf_task *tmf) +{ + struct sas_task *task = slot->task; + struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; + struct domain_device *device = task->dev; + struct hisi_sas_device *sas_dev = device->lldd_dev; + struct hisi_sas_port *port = slot->port; + struct sas_ssp_task *ssp_task = &task->ssp_task; + struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; + int has_data = 0, rc, priority = is_tmf; + u8 *buf_cmd; + u32 dw1 = 0, dw2 = 0; + + hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | + (2 << CMD_HDR_TLR_CTRL_OFF) | + (port->id << CMD_HDR_PORT_OFF) | + (priority << CMD_HDR_PRIORITY_OFF) | + (1 << CMD_HDR_CMD_OFF)); /* ssp */ + + dw1 = 1 << CMD_HDR_VDTL_OFF; + if (is_tmf) { + dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; + dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; + } else { + dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; + switch (scsi_cmnd->sc_data_direction) { + case DMA_TO_DEVICE: + has_data = 1; + dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; + break; + case DMA_FROM_DEVICE: + has_data = 1; + dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; + break; + default: + dw1 &= ~CMD_HDR_DIR_MSK; + } + } + + /* map itct entry */ + dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; + hdr->dw1 = cpu_to_le32(dw1); + + dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) + + 3) / 4) << CMD_HDR_CFL_OFF) | + ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | + (2 << CMD_HDR_SG_MOD_OFF); + hdr->dw2 = cpu_to_le32(dw2); + hdr->transfer_tags = cpu_to_le32(slot->idx); + + if (has_data) { + rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, + slot->n_elem); + if (rc) + return rc; + } + + hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); + hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma); + hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma); + + buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr); + memcpy(buf_cmd, ssp_task->LUN, 8); + + if (!is_tmf) { + buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3); + memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len); + } else { + buf_cmd[10] = tmf->tmf; + switch (tmf->tmf) { + case TMF_ABORT_TASK: + case TMF_QUERY_TASK: + buf_cmd[12] = + (tmf->tag_of_task_to_be_managed >> 8) & 0xff; + buf_cmd[13] = + tmf->tag_of_task_to_be_managed & 0xff; + break; + default: + break; + } + } + + return 0; +} + static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) { int i, res = 0; @@ -1020,11 +1224,16 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) return 0; } + static const struct hisi_sas_hw hisi_sas_v3_hw = { .hw_init = hisi_sas_v3_init, .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, .sl_notify = sl_notify_v3_hw, .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), + .prep_ssp = prep_ssp_v3_hw, + .get_free_slot = get_free_slot_v3_hw, + .start_delivery = start_delivery_v3_hw, + .slot_complete = slot_complete_v3_hw, .phys_init = phys_init_v3_hw, }; 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[209.132.180.67]) by mx.google.com with ESMTP id q12si1768108pgf.56.2017.05.17.03.24.02; Wed, 17 May 2017 03:24:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754404AbdEQKXu (ORCPT + 1 other); Wed, 17 May 2017 06:23:50 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:6312 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754396AbdEQKTp (ORCPT ); Wed, 17 May 2017 06:19:45 -0400 Received: from 172.30.72.55 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.55]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOT12425; Wed, 17 May 2017 18:19:43 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Wed, 17 May 2017 18:19:36 +0800 From: John Garry To: , CC: , , , , , Xiang Chen , John Garry Subject: [PATCH 17/22] scsi: hisi_sas: add v3 code for itct setup and free Date: Wed, 17 May 2017 18:49:52 +0800 Message-ID: <1495018197-120535-18-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495018197-120535-1-git-send-email-john.garry@huawei.com> References: <1495018197-120535-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.591C23BF.00DE, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 40f2d6a92d24550babd4f55fd702eed5 Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Xiang Chen Add code for itct setup and free for v3 hw. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 115 +++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 976c6e6..cbc2640 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -24,6 +24,11 @@ #define PHY_PORT_NUM_MA 0x28 #define PHY_CONN_RATE 0x30 #define AXI_AHB_CLK_CFG 0x3c +#define ITCT_CLR 0x44 +#define ITCT_CLR_EN_OFF 16 +#define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) +#define ITCT_DEV_OFF 0 +#define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) #define AXI_USER1 0x48 #define AXI_USER2 0x4c #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 @@ -226,6 +231,27 @@ #define CMPLT_HDR_IO_IN_TARGET_OFF 17 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF) +/* ITCT header */ +/* qw0 */ +#define ITCT_HDR_DEV_TYPE_OFF 0 +#define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) +#define ITCT_HDR_VALID_OFF 2 +#define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) +#define ITCT_HDR_MCR_OFF 5 +#define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) +#define ITCT_HDR_VLN_OFF 9 +#define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) +#define ITCT_HDR_SMP_TIMEOUT_OFF 16 +#define ITCT_HDR_AWT_CONTINUE_OFF 25 +#define ITCT_HDR_PORT_ID_OFF 28 +#define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) +/* qw2 */ +#define ITCT_HDR_INLT_OFF 0 +#define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) +#define ITCT_HDR_RTOLT_OFF 48 +#define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) + + struct hisi_sas_complete_v3_hdr { __le32 dw0; __le32 dw1; @@ -444,6 +470,93 @@ static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) __swab32(identify_buffer[5])); } +static void setup_itct_v3_hw(struct hisi_hba *hisi_hba, + struct hisi_sas_device *sas_dev) +{ + struct domain_device *device = sas_dev->sas_device; + struct device *dev = hisi_hba->dev; + u64 qw0, device_id = sas_dev->device_id; + struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; + struct domain_device *parent_dev = device->parent; + struct asd_sas_port *sas_port = device->port; + struct hisi_sas_port *port = to_hisi_sas_port(sas_port); + + memset(itct, 0, sizeof(*itct)); + + /* qw0 */ + qw0 = 0; + switch (sas_dev->dev_type) { + case SAS_END_DEVICE: + case SAS_EDGE_EXPANDER_DEVICE: + case SAS_FANOUT_EXPANDER_DEVICE: + qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; + break; + case SAS_SATA_DEV: + case SAS_SATA_PENDING: + if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) + qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; + else + qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; + break; + default: + dev_warn(dev, "setup itct: unsupported dev type (%d)\n", + sas_dev->dev_type); + } + + qw0 |= ((1 << ITCT_HDR_VALID_OFF) | + (device->linkrate << ITCT_HDR_MCR_OFF) | + (1 << ITCT_HDR_VLN_OFF) | + (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) | + (1 << ITCT_HDR_AWT_CONTINUE_OFF) | + (port->id << ITCT_HDR_PORT_ID_OFF)); + itct->qw0 = cpu_to_le64(qw0); + + /* qw1 */ + memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE); + itct->sas_addr = __swab64(itct->sas_addr); + + /* qw2 */ + if (!dev_is_sata(device)) + itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) | + (0x1ULL << ITCT_HDR_RTOLT_OFF)); +} + +static void free_device_v3_hw(struct hisi_hba *hisi_hba, + struct hisi_sas_device *sas_dev) +{ + u64 dev_id = sas_dev->device_id; + struct device *dev = hisi_hba->dev; + struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; + u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); + + /* clear the itct interrupt state */ + if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) + hisi_sas_write32(hisi_hba, ENT_INT_SRC3, + ENT_INT_SRC3_ITC_INT_MSK); + + /* clear the itct table*/ + reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); + reg_val |= ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); + hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); + + udelay(10); + reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); + if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) { + dev_dbg(dev, "got clear ITCT done interrupt\n"); + + /* invalid the itct state*/ + memset(itct, 0, sizeof(struct hisi_sas_itct)); + hisi_sas_write32(hisi_hba, ENT_INT_SRC3, + ENT_INT_SRC3_ITC_INT_MSK); + hisi_hba->devices[dev_id].dev_type = SAS_PHY_UNUSED; + hisi_hba->devices[dev_id].dev_status = HISI_SAS_DEV_NORMAL; + + /* clear the itct */ + hisi_sas_write32(hisi_hba, ITCT_CLR, 0); + dev_dbg(dev, "clear ITCT ok\n"); + } +} + static int hw_init_v3_hw(struct hisi_hba *hisi_hba) { init_reg_v3_hw(hisi_hba); @@ -1405,9 +1518,11 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) static const struct hisi_sas_hw hisi_sas_v3_hw = { .hw_init = hisi_sas_v3_init, + .setup_itct = setup_itct_v3_hw, .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, .sl_notify = sl_notify_v3_hw, .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), + .free_device = free_device_v3_hw, .prep_ssp = prep_ssp_v3_hw, .prep_smp = prep_smp_v3_hw, .prep_stp = prep_ata_v3_hw, From patchwork Wed May 17 10:49:56 2017 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id e70si1656986pfd.278.2017.05.17.03.21.24; Wed, 17 May 2017 03:21:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754439AbdEQKVS (ORCPT + 1 other); Wed, 17 May 2017 06:21:18 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:6761 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754438AbdEQKTu (ORCPT ); Wed, 17 May 2017 06:19:50 -0400 Received: from 172.30.72.53 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.53]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOT12448; Wed, 17 May 2017 18:19:47 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Wed, 17 May 2017 18:19:37 +0800 From: John Garry To: , CC: , , , , , Xiang Chen , John Garry Subject: [PATCH 21/22] scsi: hisi_sas: add v3 code to fill some more hw function pointers Date: Wed, 17 May 2017 18:49:56 +0800 Message-ID: <1495018197-120535-22-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1495018197-120535-1-git-send-email-john.garry@huawei.com> References: <1495018197-120535-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.591C23C3.0153, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: b152b9cc6f930a711e0a5350262da6c7 Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Xiang Chen Add code to fill the interface of phy_hard_reset, phy_get_max_linkrate, and phy enable/disable. Signed-off-by: John Garry Signed-off-by: Xiang Chen --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 39 ++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 195276b..766455a 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -195,6 +195,8 @@ #define TXID_AUTO (PORT_BASE + 0xb8) #define CT3_OFF 1 #define CT3_MSK (0x1 << CT3_OFF) +#define TX_HARDRST_OFF 2 +#define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF) #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) @@ -648,6 +650,14 @@ static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); } +static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); + + cfg &= ~PHY_CFG_ENA_MSK; + hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); +} + static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) { config_id_frame_v3_hw(hisi_hba, phy_no); @@ -655,6 +665,11 @@ static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) enable_phy_v3_hw(hisi_hba, phy_no); } +static void stop_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + disable_phy_v3_hw(hisi_hba, phy_no); +} + static void start_phys_v3_hw(struct hisi_hba *hisi_hba) { int i; @@ -663,6 +678,22 @@ static void start_phys_v3_hw(struct hisi_hba *hisi_hba) start_phy_v3_hw(hisi_hba, i); } +static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no) +{ + struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; + u32 txid_auto; + + stop_phy_v3_hw(hisi_hba, phy_no); + if (phy->identify.device_type == SAS_END_DEVICE) { + txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); + hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, + txid_auto | TX_HARDRST_MSK); + } + msleep(100); + start_phy_v3_hw(hisi_hba, phy_no); +} + + static void phys_init_v3_hw(struct hisi_hba *hisi_hba) { start_phys_v3_hw(hisi_hba); @@ -1961,6 +1992,10 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) return 0; } +enum sas_linkrate phy_get_max_linkrate_v3_hw(void) +{ + return SAS_LINK_RATE_12_0_GBPS; +} static const struct hisi_sas_hw hisi_sas_v3_hw = { .hw_init = hisi_sas_v3_init, @@ -1978,6 +2013,10 @@ static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) .start_delivery = start_delivery_v3_hw, .slot_complete = slot_complete_v3_hw, .phys_init = phys_init_v3_hw, + .phy_enable = enable_phy_v3_hw, + .phy_disable = disable_phy_v3_hw, + .phy_hard_reset = phy_hard_reset_v3_hw, + .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw, }; enum {