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[209.132.180.67]) by mx.google.com with ESMTP id g6si1531601pln.178.2017.05.17.01.38.47; Wed, 17 May 2017 01:38:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754199AbdEQIic (ORCPT + 25 others); Wed, 17 May 2017 04:38:32 -0400 Received: from mail-pg0-f44.google.com ([74.125.83.44]:34911 "EHLO mail-pg0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754147AbdEQIiZ (ORCPT ); Wed, 17 May 2017 04:38:25 -0400 Received: by mail-pg0-f44.google.com with SMTP id q125so3782329pgq.2 for ; Wed, 17 May 2017 01:38:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VECSL3eyXwae2+QGMvWuHFhPI+xQmxiN+jPwaTdtHCU=; b=U65YBS8XTtTZXTaUwbsXME8gs3Lzf090aOpKjyZxx1c8ffnPBIS1eLEHB/F2fPj8+v /MGQ0B66KX4w/h+s0nZepcjROOT+RUGAXYSNOdjs9YE1cPe9agp3UVJENtCW515ZTLC0 0As/K5sI1+NeDFuGGDJ1fWlmBnUiAw4cKztt0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VECSL3eyXwae2+QGMvWuHFhPI+xQmxiN+jPwaTdtHCU=; b=KIzgmPSskImGHoCx6j/bGbV7K/Xb1cAzQXxZWP40fandhGheW8yGXJHHXn+AyGlVb2 4s22MM/2sbC3Wb/obc9OIlqn8A9mdVqUD5QJxuIuE6EET4gx9h66kFvALb3kjEaUAkHf OKxCdFz7NOpED2kFt3JkKqSRTiOqQhlYy5Gi3rNsnkxlxObCOYTfKVGqm260etXagQPB 4WbIVFHXLfbhOAt4A2oceda/vLu7SEM+vYlvO4GQgankwTGeWawjhCOyFk/g1K+qYrJ5 x0auZeVq79e8L+cA9YxNjz7Y0Ot13iQLt964fPGdlj3ZE70CR+1Y4hCm8kEuHd3mTgks lREw== X-Gm-Message-State: AODbwcDk1DS3/qWM9aylcfl7x4N4CHNAS8RrznW7JTg7ZT5ZtbGBChsF A2z4NJsRNaKalzp2 X-Received: by 10.84.132.2 with SMTP id 2mr2982294ple.46.1495010304686; Wed, 17 May 2017 01:38:24 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.164]) by smtp.gmail.com with ESMTPSA id u9sm3029519pgn.55.2017.05.17.01.38.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 17 May 2017 01:38:24 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, puck.chen@hisilicon.com, xuejiancheng@hisilicon.com, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Guodong Xu Subject: [PATCH 02/12] arm64: dts: hisilicon: update compatible string for hikey960 Date: Wed, 17 May 2017 16:37:35 +0800 Message-Id: <20170517083745.24479-3-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170517083745.24479-1-guodong.xu@linaro.org> References: <20170517083745.24479-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update compatible string for hikey960. HiKey960 is a develpment board built with SoC Hi3660. Signed-off-by: Guodong Xu Signed-off-by: Chen Feng --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 186251f..64875a5 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -12,7 +12,7 @@ / { model = "HiKey960"; - compatible = "hisilicon,hi3660"; + compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; aliases { serial5 = &uart5; /* console UART */ From patchwork Wed May 17 08:37:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 99912 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp127334qge; Wed, 17 May 2017 01:38:55 -0700 (PDT) X-Received: by 10.98.236.150 with SMTP id e22mr2485736pfm.48.1495010335863; Wed, 17 May 2017 01:38:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495010335; cv=none; d=google.com; s=arc-20160816; b=ZHJCrDpk1fulPoAFYd2Fa/tbc2mZvsNwQf1wDtw+Cb9dn3/uksZRUW0acalL4ik2de BmQhb3gjBul0CP5Zwb/p+J9FmX5MuzGolDhQiiaZsVsYNyGYbJ+tWgWxTBkStUfflMbd jOOlYPRTTfr9lXGvrvlylJLLfixUC5Uy1U2tg/9uz2HWuXy8WjQoTVUP7u1AiSNHBNKM hdF8KS0Xbbm/656QKKpSi8OO/19duOHB/IJyKKLCDn/egJ6+dqTV+eje72edjq4sUD5D qs7BQ5KDrHWkomxFr1SkioV2R2nmTvKSzT4jRUwgguh+GbzFve6YaP8LYhVIW0LDsIHA 30RQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=YXGDPUIr3x2i+v7o2ABcZSNcYkfSci85agOgnkAxROI=; b=GCnEXuZMDMAu7YuaUlZPCZqsYYN6pnK5qs0oS2+suZgqlJIK7RJ9teR0QE/UOH4CGY Wf5hZBcxTElO42wl2slyXsJWC4ePp4y6Wy4p6xwyEsfeYOBOay6Pi3vELSWr4+vqiD8K VfbaQKTScT4+G9LxbfGR6hX2KBTWDXRxOBIYuQ5SDH/9YN8ngv/VgLBOmeMPhEfLrT0+ r8XnQKraDdoNCoVHdHk17U3ctrO13wJwNUQBOaAe/XeAd1zD7SqJP5bf36/F1zU9Y8kM L4EcxsHwViDIuB4zo2jT2TejvgjX9wACNFy4d74XnFMqNFpmp2myzp98WMHKE07fX4uB q4ng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 77si1468153pfy.107.2017.05.17.01.38.55; Wed, 17 May 2017 01:38:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932085AbdEQIiu (ORCPT + 25 others); Wed, 17 May 2017 04:38:50 -0400 Received: from mail-pf0-f179.google.com ([209.85.192.179]:32770 "EHLO mail-pf0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752023AbdEQIip (ORCPT ); Wed, 17 May 2017 04:38:45 -0400 Received: by mail-pf0-f179.google.com with SMTP id e193so4005623pfh.0 for ; Wed, 17 May 2017 01:38:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YXGDPUIr3x2i+v7o2ABcZSNcYkfSci85agOgnkAxROI=; b=LJaq3IOtWDmJ2Kl62/MJaxlpNLNMs+g21GCRTaWcc6pU+3uhDQbFe36CCjPdML6I22 asRSV3rdt7TmBBclJ0xpEI9YtO97+nvfyAs/OY1sW7OAyOR2VUJB8Ko9mevUeeTVWPKL iKNNQ/+89xwvG36T7l7NWJMHf90tXCMlKDeyA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YXGDPUIr3x2i+v7o2ABcZSNcYkfSci85agOgnkAxROI=; b=liGb21VHipWeCeO0at74wkMGlXBRyB3EhRh0cki9YKHlKBwPEeV8hSyu44RjCdVAuY m1gz6024evComjI/OeczLpNuZ7RqLQiSeCsSWDvwEVHVNH/oqbeLsrTBqvNbJPCCYS+9 2HtghZlCbvpCn2vM+w8D2q//IdgP5lIu72xHIeDB9vf9ci6TBbNsOCQHGVAfebsmQ8Is eAIjeZup2ii/zFXqGBBDE+1j9crTeLFjsJRFwfU+7nmPdGrpYyuORo2DoRwPIRaewCVH HQS4zzAtrbG/bNGO71mbqZMtciQTfwRIhdWWFknwbT1J91W+t7w1zz1dgKQa4o2YX3sA IWuQ== X-Gm-Message-State: AODbwcCsaJwc4fCHxlNZQzoddGqnREzZX24x9j/wXhkcWckcrOHOisEi cS0h6kvSZAIfkcpT X-Received: by 10.84.133.132 with SMTP id f4mr2936903plf.94.1495010309691; Wed, 17 May 2017 01:38:29 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.164]) by smtp.gmail.com with ESMTPSA id u9sm3029519pgn.55.2017.05.17.01.38.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 17 May 2017 01:38:29 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, puck.chen@hisilicon.com, xuejiancheng@hisilicon.com, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Wang Xiaoyin , Chen Jun , Guodong Xu Subject: [PATCH 03/12] arm64: dts: hikey960: pinctrl: add more pinmux and pinconfig Date: Wed, 17 May 2017 16:37:36 +0800 Message-Id: <20170517083745.24479-4-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170517083745.24479-1-guodong.xu@linaro.org> References: <20170517083745.24479-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Wang Xiaoyin This commit adds more pinmux and pinctrl information for devices on HiKey960, including i2c, spi, cam, uart, ufs, pcie, csi, pwr_key, isp, sd/sdio, i2s, and usb. Signed-off-by: Wang Xiaoyin Signed-off-by: Chen Jun Signed-off-by: Guodong Xu --- .../arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi | 779 +++++++++++++++++++-- 1 file changed, 719 insertions(+), 60 deletions(-) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi index 719c4bc..b52a687 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey960-pinctrl.dtsi @@ -24,6 +24,27 @@ &range 0 7 0 &range 8 116 0>; + pmu_pmx_func: pmu_pmx_func { + pinctrl-single,pins = < + 0x008 MUX_M1 /* PMU1_SSI */ + 0x00c MUX_M1 /* PMU2_SSI */ + 0x010 MUX_M1 /* PMU_CLKOUT */ + 0x100 MUX_M1 /* PMU_HKADC_SSI */ + >; + }; + + csi0_pwd_n_pmx_func: csi0_pwd_n_pmx_func { + pinctrl-single,pins = < + 0x044 MUX_M0 /* CSI0_PWD_N */ + >; + }; + + csi1_pwd_n_pmx_func: csi1_pwd_n_pmx_func { + pinctrl-single,pins = < + 0x04c MUX_M0 /* CSI1_PWD_N */ + >; + }; + isp0_pmx_func: isp0_pmx_func { pinctrl-single,pins = < 0x058 MUX_M1 /* ISP_CLK0 */ @@ -40,6 +61,12 @@ >; }; + pwr_key_pmx_func: pwr_key_pmx_func { + pinctrl-single,pins = < + 0x080 MUX_M0 /* GPIO_034 */ + >; + }; + i2c3_pmx_func: i2c3_pmx_func { pinctrl-single,pins = < 0x02c MUX_M1 /* I2C3_SCL */ @@ -67,21 +94,10 @@ >; }; - spi1_pmx_func: spi1_pmx_func { - pinctrl-single,pins = < - 0x034 MUX_M1 /* SPI1_CLK */ - 0x038 MUX_M1 /* SPI1_DI */ - 0x03c MUX_M1 /* SPI1_DO */ - 0x040 MUX_M1 /* SPI1_CS_N */ - >; - }; - uart0_pmx_func: uart0_pmx_func { pinctrl-single,pins = < 0x0cc MUX_M2 /* UART0_RXD */ 0x0d0 MUX_M2 /* UART0_TXD */ - 0x0d4 MUX_M2 /* UART0_RXD_M */ - 0x0d8 MUX_M2 /* UART0_TXD_M */ >; }; @@ -138,6 +154,18 @@ 0x0d8 MUX_M1 /* UART6_TXD */ >; }; + + cam0_rst_pmx_func: cam0_rst_pmx_func { + pinctrl-single,pins = < + 0x0c8 MUX_M0 /* CAM0_RST */ + >; + }; + + cam1_rst_pmx_func: cam1_rst_pmx_func { + pinctrl-single,pins = < + 0x124 MUX_M0 /* CAM1_RST */ + >; + }; }; /* [IOMG_MMC0_000, IOMG_MMC0_005] */ @@ -174,6 +202,13 @@ /* pin base, nr pins & gpio function */ pinctrl-single,gpio-range = <&range 0 12 0>; + ufs_pmx_func: ufs_pmx_func { + pinctrl-single,pins = < + 0x000 MUX_M1 /* UFS_REF_CLK */ + 0x004 MUX_M1 /* UFS_RST_N */ + >; + }; + spi3_pmx_func: spi3_pmx_func { pinctrl-single,pins = < 0x008 MUX_M1 /* SPI3_CLK */ @@ -248,17 +283,17 @@ >; }; - i2c2_pmx_func: i2c2_pmx_func { + i2c7_pmx_func: i2c7_pmx_func { pinctrl-single,pins = < - 0x024 MUX_M1 /* I2C2_SCL */ - 0x028 MUX_M1 /* I2C2_SDA */ + 0x024 MUX_M3 /* I2C7_SCL */ + 0x028 MUX_M3 /* I2C7_SDA */ >; }; - i2c7_pmx_func: i2c7_pmx_func { + pcie_pmx_func: pcie_pmx_func { pinctrl-single,pins = < - 0x024 MUX_M3 /* I2C7_SCL */ - 0x028 MUX_M3 /* I2C7_SDA */ + 0x084 MUX_M1 /* PCIE_CLKREQ_N */ + 0x088 MUX_M1 /* PCIE_WAKE_N */ >; }; @@ -271,15 +306,6 @@ >; }; - spi4_pmx_func: spi4_pmx_func { - pinctrl-single,pins = < - 0x08c MUX_M4 /* SPI4_CLK */ - 0x090 MUX_M4 /* SPI4_DI */ - 0x094 MUX_M4 /* SPI4_DO */ - 0x098 MUX_M4 /* SPI4_CS0_N */ - >; - }; - i2s0_pmx_func: i2s0_pmx_func { pinctrl-single,pins = < 0x034 MUX_M1 /* I2S0_DI */ @@ -290,17 +316,20 @@ }; }; - pmx5: pinmux@ff3fd800 { + pmx5: pinmux@e896c800 { compatible = "pinconf-single"; - reg = <0x0 0xff3fd800 0x0 0x18>; + reg = <0x0 0xe896c800 0x0 0x200>; #pinctrl-cells = <1>; #address-cells = <1>; #size-cells = <1>; pinctrl-single,register-width = <32>; - sdio_clk_cfg_func: sdio_clk_cfg_func { + pmu_cfg_func: pmu_cfg_func { pinctrl-single,pins = < - 0x000 0x0 /* SDIO_CLK */ + 0x010 0x0 /* PMU1_SSI */ + 0x014 0x0 /* PMU2_SSI */ + 0x018 0x0 /* PMU_CLKOUT */ + 0x10c 0x0 /* PMU_HKADC_SSI */ >; pinctrl-single,bias-pulldown = < PULL_DIS @@ -315,18 +344,35 @@ PULL_UP >; pinctrl-single,drive-strength = < - DRIVE6_32MA - DRIVE6_MASK + DRIVE7_06MA DRIVE6_MASK >; }; - sdio_cfg_func: sdio_cfg_func { + i2c3_cfg_func: i2c3_cfg_func { pinctrl-single,pins = < - 0x004 0x0 /* SDIO_CMD */ - 0x008 0x0 /* SDIO_DATA0 */ - 0x00c 0x0 /* SDIO_DATA1 */ - 0x010 0x0 /* SDIO_DATA2 */ - 0x014 0x0 /* SDIO_DATA3 */ + 0x038 0x0 /* I2C3_SCL */ + 0x03c 0x0 /* I2C3_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + csi0_pwd_n_cfg_func: csi0_pwd_n_cfg_func { + pinctrl-single,pins = < + 0x050 0x0 /* CSI0_PWD_N */ >; pinctrl-single,bias-pulldown = < PULL_DIS @@ -335,29 +381,64 @@ PULL_DOWN >; pinctrl-single,bias-pullup = < + PULL_DIS PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + csi1_pwd_n_cfg_func: csi1_pwd_n_cfg_func { + pinctrl-single,pins = < + 0x058 0x0 /* CSI1_PWD_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS PULL_UP PULL_DIS PULL_UP >; pinctrl-single,drive-strength = < - DRIVE6_19MA - DRIVE6_MASK + DRIVE7_04MA DRIVE6_MASK >; }; - }; - pmx6: pinmux@ff37e800 { - compatible = "pinconf-single"; - reg = <0x0 0xff37e800 0x0 0x18>; - #pinctrl-cells = <1>; - #address-cells = <1>; - #size-cells = <1>; - pinctrl-single,register-width = <32>; + isp0_cfg_func: isp0_cfg_func { + pinctrl-single,pins = < + 0x064 0x0 /* ISP_CLK0 */ + 0x070 0x0 /* ISP_SCL0 */ + 0x074 0x0 /* ISP_SDA0 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK>; + }; - sd_clk_cfg_func: sd_clk_cfg_func { + isp1_cfg_func: isp1_cfg_func { pinctrl-single,pins = < - 0x000 0x0 /* SD_CLK */ + 0x068 0x0 /* ISP_CLK1 */ + 0x078 0x0 /* ISP_SCL1 */ + 0x07c 0x0 /* ISP_SDA1 */ >; pinctrl-single,bias-pulldown = < PULL_DIS @@ -372,18 +453,61 @@ PULL_UP >; pinctrl-single,drive-strength = < - DRIVE6_32MA - DRIVE6_MASK + DRIVE7_04MA DRIVE6_MASK >; }; - sd_cfg_func: sd_cfg_func { + pwr_key_cfg_func: pwr_key_cfg_func { pinctrl-single,pins = < - 0x004 0x0 /* SD_CMD */ - 0x008 0x0 /* SD_DATA0 */ - 0x00c 0x0 /* SD_DATA1 */ - 0x010 0x0 /* SD_DATA2 */ - 0x014 0x0 /* SD_DATA3 */ + 0x08c 0x0 /* GPIO_034 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart1_cfg_func: uart1_cfg_func { + pinctrl-single,pins = < + 0x0b4 0x0 /* UART1_RXD */ + 0x0b8 0x0 /* UART1_TXD */ + 0x0bc 0x0 /* UART1_CTS_N */ + 0x0c0 0x0 /* UART1_RTS_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart2_cfg_func: uart2_cfg_func { + pinctrl-single,pins = < + 0x0c8 0x0 /* UART2_CTS_N */ + 0x0cc 0x0 /* UART2_RTS_N */ + 0x0d0 0x0 /* UART2_TXD */ + 0x0d4 0x0 /* UART2_RXD */ >; pinctrl-single,bias-pulldown = < PULL_DIS @@ -392,14 +516,549 @@ PULL_DOWN >; pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart5_cfg_func: uart5_cfg_func { + pinctrl-single,pins = < + 0x0c8 0x0 /* UART5_RXD */ + 0x0cc 0x0 /* UART5_TXD */ + 0x0d0 0x0 /* UART5_CTS_N */ + 0x0d4 0x0 /* UART5_RTS_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS PULL_UP PULL_DIS PULL_UP >; pinctrl-single,drive-strength = < - DRIVE6_19MA - DRIVE6_MASK + DRIVE7_02MA DRIVE6_MASK + >; + }; + + cam0_rst_cfg_func: cam0_rst_cfg_func { + pinctrl-single,pins = < + 0x0d4 0x0 /* CAM0_RST */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + + uart0_cfg_func: uart0_cfg_func { + pinctrl-single,pins = < + 0x0d8 0x0 /* UART0_RXD */ + 0x0dc 0x0 /* UART0_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart6_cfg_func: uart6_cfg_func { + pinctrl-single,pins = < + 0x0d8 0x0 /* UART6_CTS_N */ + 0x0dc 0x0 /* UART6_RTS_N */ + 0x0e0 0x0 /* UART6_RXD */ + 0x0e4 0x0 /* UART6_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart3_cfg_func: uart3_cfg_func { + pinctrl-single,pins = < + 0x0e8 0x0 /* UART3_CTS_N */ + 0x0ec 0x0 /* UART3_RTS_N */ + 0x0f0 0x0 /* UART3_RXD */ + 0x0f4 0x0 /* UART3_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + uart4_cfg_func: uart4_cfg_func { + pinctrl-single,pins = < + 0x0f8 0x0 /* UART4_CTS_N */ + 0x0fc 0x0 /* UART4_RTS_N */ + 0x100 0x0 /* UART4_RXD */ + 0x104 0x0 /* UART4_TXD */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + cam1_rst_cfg_func: cam1_rst_cfg_func { + pinctrl-single,pins = < + 0x130 0x0 /* CAM1_RST */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_04MA DRIVE6_MASK + >; + }; + }; + + pmx6: pinmux@ff3b6800 { + compatible = "pinconf-single"; + reg = <0x0 0xff3b6800 0x0 0x18>; + #address-cells = <1>; + #size-cells = <1>; + pinctrl-single,register-width = <32>; + + ufs_cfg_func: ufs_cfg_func { + pinctrl-single,pins = < + 0x000 0x0 /* UFS_REF_CLK */ + 0x004 0x0 /* UFS_RST_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_08MA DRIVE6_MASK + >; + }; + + spi3_cfg_func: spi3_cfg_func { + pinctrl-single,pins = < + 0x008 0x0 /* SPI3_CLK */ + 0x0 /* SPI3_DI */ + 0x010 0x0 /* SPI3_DO */ + 0x014 0x0 /* SPI3_CS0_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + }; + + pmx7: pinmux@ff3fd800 { + compatible = "pinconf-single"; + reg = <0x0 0xff3fd800 0x0 0x18>; + #address-cells = <1>; + #size-cells = <1>; + pinctrl-single,register-width = <32>; + + sdio_clk_cfg_func: sdio_clk_cfg_func { + pinctrl-single,pins = < + 0x000 0x0 /* SDIO_CLK */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE6_32MA DRIVE6_MASK + >; + }; + + sdio_cfg_func: sdio_cfg_func { + pinctrl-single,pins = < + 0x004 0x0 /* SDIO_CMD */ + 0x008 0x0 /* SDIO_DATA0 */ + 0x00c 0x0 /* SDIO_DATA1 */ + 0x010 0x0 /* SDIO_DATA2 */ + 0x014 0x0 /* SDIO_DATA3 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE6_19MA DRIVE6_MASK + >; + }; + }; + + pmx8: pinmux@ff37e800 { + compatible = "pinconf-single"; + reg = <0x0 0xff37e800 0x0 0x18>; + #pinctrl-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + pinctrl-single,register-width = <32>; + + sd_clk_cfg_func: sd_clk_cfg_func { + pinctrl-single,pins = < + 0x000 0x0 /* SD_CLK */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_DIS + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE6_32MA + DRIVE6_MASK + >; + }; + + sd_cfg_func: sd_cfg_func { + pinctrl-single,pins = < + 0x004 0x0 /* SD_CMD */ + 0x008 0x0 /* SD_DATA0 */ + 0x00c 0x0 /* SD_DATA1 */ + 0x010 0x0 /* SD_DATA2 */ + 0x014 0x0 /* SD_DATA3 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE6_19MA + DRIVE6_MASK + >; + }; + }; + + pmx9: pinmux@fff11800 { + compatible = "pinconf-single"; + reg = <0x0 0xfff11800 0x0 0xbc>; + #address-cells = <1>; + #size-cells = <1>; + pinctrl-single,register-width = <32>; + + i2c0_cfg_func: i2c0_cfg_func { + pinctrl-single,pins = < + 0x01c 0x0 /* I2C0_SCL */ + 0x020 0x0 /* I2C0_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + i2c1_cfg_func: i2c1_cfg_func { + pinctrl-single,pins = < + 0x024 0x0 /* I2C1_SCL */ + 0x028 0x0 /* I2C1_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + i2c7_cfg_func: i2c7_cfg_func { + pinctrl-single,pins = < + 0x02c 0x0 /* I2C7_SCL */ + 0x030 0x0 /* I2C7_SDA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + slimbus_cfg_func: slimbus_cfg_func { + pinctrl-single,pins = < + 0x034 0x0 /* SLIMBUS_CLK */ + 0x038 0x0 /* SLIMBUS_DATA */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + i2s0_cfg_func: i2s0_cfg_func { + pinctrl-single,pins = < + 0x040 0x0 /* I2S0_DI */ + 0x044 0x0 /* I2S0_DO */ + 0x048 0x0 /* I2S0_XCLK */ + 0x04c 0x0 /* I2S0_XFS */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + i2s2_cfg_func: i2s2_cfg_func { + pinctrl-single,pins = < + 0x050 0x0 /* I2S2_DI */ + 0x054 0x0 /* I2S2_DO */ + 0x058 0x0 /* I2S2_XCLK */ + 0x05c 0x0 /* I2S2_XFS */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + pcie_cfg_func: pcie_cfg_func { + pinctrl-single,pins = < + 0x094 0x0 /* PCIE_CLKREQ_N */ + 0x098 0x0 /* PCIE_WAKE_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + spi2_cfg_func: spi2_cfg_func { + pinctrl-single,pins = < + 0x09c 0x0 /* SPI2_CLK */ + 0x0a0 0x0 /* SPI2_DI */ + 0x0a4 0x0 /* SPI2_DO */ + 0x0a8 0x0 /* SPI2_CS0_N */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK + >; + }; + + usb_cfg_func: usb_cfg_func { + pinctrl-single,pins = < + 0x0ac 0x0 /* GPIO_219 */ + >; + pinctrl-single,bias-pulldown = < + PULL_DIS + PULL_DOWN + PULL_DIS + PULL_DOWN + >; + pinctrl-single,bias-pullup = < + PULL_UP + PULL_UP + PULL_DIS + PULL_UP + >; + pinctrl-single,drive-strength = < + DRIVE7_02MA DRIVE6_MASK >; }; }; From patchwork Wed May 17 08:37:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 99919 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp127930qge; Wed, 17 May 2017 01:40:51 -0700 (PDT) X-Received: by 10.99.113.75 with SMTP id b11mr2480209pgn.173.1495010451623; Wed, 17 May 2017 01:40:51 -0700 (PDT) ARC-Seal: i=1; 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Wed, 17 May 2017 01:38:33 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.164]) by smtp.gmail.com with ESMTPSA id u9sm3029519pgn.55.2017.05.17.01.38.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 17 May 2017 01:38:33 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, puck.chen@hisilicon.com, xuejiancheng@hisilicon.com, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Zhangfei Gao Subject: [PATCH 04/12] arm64: dts: hi3660: add resources for clock and reset Date: Wed, 17 May 2017 16:37:37 +0800 Message-Id: <20170517083745.24479-5-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170517083745.24479-1-guodong.xu@linaro.org> References: <20170517083745.24479-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Zhangfei Gao Add some resource nodes for clock and reset Signed-off-by: Zhangfei Gao --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 53 +++++++++++++++++++++++++++---- 1 file changed, 46 insertions(+), 7 deletions(-) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 3983086..f55710a 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -5,6 +5,7 @@ */ #include +#include / { compatible = "hisilicon,hi3660"; @@ -141,18 +142,56 @@ #size-cells = <2>; ranges; - fixed_uart5: fixed_19_2M { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <19200000>; - clock-output-names = "fixed:uart5"; + crg_ctrl: crg_ctrl@fff35000 { + compatible = "hisilicon,hi3660-crgctrl", "syscon"; + reg = <0x0 0xfff35000 0x0 0x1000>; + #clock-cells = <1>; }; - uart5: uart@fdf05000 { + crg_rst: crg_rst_controller { + compatible = "hisilicon,hi3660-reset"; + #reset-cells = <2>; + hisi,rst-syscon = <&crg_ctrl>; + }; + + + pctrl: pctrl@e8a09000 { + compatible = "hisilicon,hi3660-pctrl", "syscon"; + reg = <0x0 0xe8a09000 0x0 0x2000>; + #clock-cells = <1>; + }; + + pmuctrl: crg_ctrl@fff34000 { + compatible = "hisilicon,hi3660-pmuctrl", "syscon"; + reg = <0x0 0xfff34000 0x0 0x1000>; + #clock-cells = <1>; + }; + + sctrl: sctrl@fff0a000 { + compatible = "hisilicon,hi3660-sctrl", "syscon"; + reg = <0x0 0xfff0a000 0x0 0x1000>; + #clock-cells = <1>; + }; + + iomcu: iomcu@ffd7e000 { + compatible = "hisilicon,hi3660-iomcu", "syscon"; + reg = <0x0 0xffd7e000 0x0 0x1000>; + #clock-cells = <1>; + + }; + + iomcu_rst: reset { + compatible = "hisilicon,hi3660-reset"; + hisi,rst-syscon = <&iomcu>; + #reset-cells = <2>; + }; + + uart5: serial@fdf05000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfdf05000 0x0 0x1000>; interrupts = ; - clocks = <&fixed_uart5 &fixed_uart5>; + clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, + <&crg_ctrl HI3660_CLK_GATE_UART5>; clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; From patchwork Wed May 17 08:37:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 99911 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp127303qge; Wed, 17 May 2017 01:38:48 -0700 (PDT) X-Received: by 10.84.131.229 with SMTP id d92mr2960992pld.16.1495010328520; Wed, 17 May 2017 01:38:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495010328; cv=none; d=google.com; s=arc-20160816; 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[209.132.180.67]) by mx.google.com with ESMTP id g6si1531601pln.178.2017.05.17.01.38.48; Wed, 17 May 2017 01:38:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754221AbdEQIip (ORCPT + 25 others); Wed, 17 May 2017 04:38:45 -0400 Received: from mail-pg0-f49.google.com ([74.125.83.49]:36299 "EHLO mail-pg0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752023AbdEQIij (ORCPT ); Wed, 17 May 2017 04:38:39 -0400 Received: by mail-pg0-f49.google.com with SMTP id x64so3753199pgd.3 for ; Wed, 17 May 2017 01:38:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=R/slF/fdOeWZ43T8E80kJQcFp8IH7sRLB8INbfV2NkY=; b=jh5P8lSKH+dnXQ6p1ryvXvff4vvRCRD3vS3cbEO1eYNgmJHySnq/DFmII8/QZWa5BF ShneYPaU6O8zIPvW3tTTQPgXHXIG14OqGGU1X2ao02nXSiof+Pos0qS/qgTzonOkMRhZ ObEbmTuhWeaUito8zzE+kT7vHhHnbr+VnMKco= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=R/slF/fdOeWZ43T8E80kJQcFp8IH7sRLB8INbfV2NkY=; b=BibIfMd/RHYxoUU0+XieT0lvNfArpFFSUgvFtNFhcFwdiN72Q1oWa9MxB7I1TgjDb+ 4GUW2ClzpwoxtvGf/2G1GaLYA48hBHqYc6wRRUSwtgw6znbIdIU9Mofguh+HQY2FqbkZ a3EXUgo/r6L3hRfL7Okd8AIoIlnZBa77ROzuyiW+B42FeoTKKZm8O5r3pw1rU45MjLzm B6fHIUFI3yApwvvxhx/I8YXezmzeO8qIZex+mVIGcFKr0WqvFA52EOvmid9D2u+UpGiI CfQHKngmfytEFY5HDNdxF4IPE/ocndI/ZKjNnldZpJY6mekzYnhbmUHlC6FRc97Z6fnp bZEA== X-Gm-Message-State: AODbwcCkAZl/mKlYkWooAeF+v52YZXO9KFhxAQ20ukKovgyZc0svqpDq MIhxxCIQ8akoZVDX X-Received: by 10.98.95.193 with SMTP id t184mr2494301pfb.191.1495010318344; Wed, 17 May 2017 01:38:38 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.164]) by smtp.gmail.com with ESMTPSA id u9sm3029519pgn.55.2017.05.17.01.38.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 17 May 2017 01:38:37 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, puck.chen@hisilicon.com, xuejiancheng@hisilicon.com, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Zhangfei Gao , Guodong Xu Subject: [PATCH 05/12] arm64: dts: Add I2C nodes for Hi3660 Date: Wed, 17 May 2017 16:37:38 +0800 Message-Id: <20170517083745.24479-6-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170517083745.24479-1-guodong.xu@linaro.org> References: <20170517083745.24479-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Zhangfei Gao Add I2C nodes for Hi3660-hikey960. On HiKey960, I2C0, I2C7 is connected to Low Speed Expansion Connector. I2C1 is connected to ADV7535. I2C3 is connected to USB5734. Signed-off-by: Zhangfei Gao Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 18 ++++++++ arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 56 +++++++++++++++++++++++ 2 files changed, 74 insertions(+) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 64875a5..f685b1e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -29,6 +29,24 @@ }; }; +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + adv7533: adv7533@39 { + status = "ok"; + compatible = "adi,adv7533"; + reg = <0x39>; + }; +}; + +&i2c7 { + status = "okay"; +}; + &uart5 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index f55710a..f217c9d 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -186,6 +186,62 @@ #reset-cells = <2>; }; + i2c0: i2c@FFD71000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xFFD71000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; + resets = <&iomcu_rst 0x20 3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; + status = "disabled"; + }; + + i2c1: i2c@FFD72000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xFFD72000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; + resets = <&iomcu_rst 0x20 4>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; + status = "disabled"; + }; + + i2c3: i2c@FDF0C000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xFDF0C000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; + resets = <&crg_rst 0x78 7>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; + status = "disabled"; + }; + + i2c7: i2c@FDF0B000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0xFDF0B000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; + resets = <&crg_rst 0x60 14>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; + status = "disabled"; + }; + uart5: serial@fdf05000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfdf05000 0x0 0x1000>; From patchwork Wed May 17 08:37:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 99914 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp127455qge; Wed, 17 May 2017 01:39:17 -0700 (PDT) X-Received: by 10.84.148.134 with SMTP id k6mr2858489pla.55.1495010357028; Wed, 17 May 2017 01:39:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495010357; cv=none; d=google.com; s=arc-20160816; b=nRwu3IOCO6zfb/XUIwB8rk0NSQVD3oIVo5g2bYrRD42JkbHpL6adL8651BKI5xOoU2 6ot0vIKfuRHetkmDAB30zg7cU3xVd9o6KHYkt8WddBeXr6AiNCVhQsJUFkHlqmzxgXRH CVjN1BIRaFgHAlr9+ngRkj3nCqkjubCFqp8i7SXY+Y+KaU3u9xDSqcLg6f4FJLV3yPG5 L2JG7d+hS6rIZhC8KhLvibZW1QmCwgICcIvndywhmusvvgGZx1sZJk7j+55vTWtcVh6K m28lJgY61QXTJ321H9lFrHlfpZqSILBbhtgk62W80L3bSz0Q71ff9AYsOqnT0Os6xXzv +4xA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=CSvqOQ76OxlEcKBZ+wzH3Ianwnym8TM5pp1M1nzBsyc=; b=xMq8Q2unJs/OXP2xr+6ekr/ckSYWfjPyleufauNsk7ypIXJ/0TEMG4+wYO9Pg7NhAF 0VrcWlVm/bLLqVnCsHB87nGs/gCdOPsPI9LDdAgF68HJCdXTOp0LIdH4BoWjtCawiIWA HLKh/UqKCQqCVWct3DZagSVwXlVN6216Gd0HucBqsYsbeHEhE/HhGLKC71OjmvAa/dgu eysR/xEVRRc0mjXDS5uZTMWEkbYh8GDA9mQGJZjfTeWgMuvGXDX7A0UgfuypNJLoVXOz jWWSw09jY3u052fI49PjbcbJwdBFBEwKRGxir/iCHvmtYKW7517WRMsm7WGC5ewbDX57 coww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3si1477579pgn.278.2017.05.17.01.39.16; Wed, 17 May 2017 01:39:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932111AbdEQIjA (ORCPT + 25 others); Wed, 17 May 2017 04:39:00 -0400 Received: from mail-pg0-f49.google.com ([74.125.83.49]:35019 "EHLO mail-pg0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932093AbdEQIiw (ORCPT ); Wed, 17 May 2017 04:38:52 -0400 Received: by mail-pg0-f49.google.com with SMTP id q125so3786663pgq.2 for ; Wed, 17 May 2017 01:38:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CSvqOQ76OxlEcKBZ+wzH3Ianwnym8TM5pp1M1nzBsyc=; b=PTN4Z/sqzCxOM/D5h64zQP7zrIjwxVhIjD6r42LYf1YtFJ8pv6NvPXHa/OfW7PvIiw u3LybnnTpMA38/Zb/km5m/9Gka7SMXSqJu4+4JhP0TXbudji8Bgb9DxGSOhtVdWC+WE4 E6mpevIStCRsU/Ww2rJAQN6z+NDcKA/eVmtdk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CSvqOQ76OxlEcKBZ+wzH3Ianwnym8TM5pp1M1nzBsyc=; b=a/af6RNYPdbQHvhnmIebV59YEPwN1bpf5yWQTQBxED8jlfeT6+pGm25UN3W7kIMJfn g63WmxyI1GdapxFr4d5XShgoX3UYP+Np5ROjdUKSZx1LbICXKUqZiO/CvJ+4/kQxkXAj Z5bva3m8IZzr/lGx3YgoP2Oj+Hz2i27Rx5kSSoeCmC28/iGskZ4vYEor02PAKVKCCGyV MnglXyGhMgB8I+SMArFhzeGVg0Aer9Rrj0k/8tK2OjZpYLY031onQssoy0ffvqxAVBRv MYLqQIQGIfzhFMYBCji76UuuS1tOCy3nnBsTfWfqEAmoZSaLwcYTXpRC3H/vPVGEiT85 8uYQ== X-Gm-Message-State: AODbwcAZ4rdMYdfZ8HluxuF5ZRBs1bwJ/lXWtS7VzR/SYNJAZrxuNRtC CuIVZgfIir01wo/8 X-Received: by 10.98.159.135 with SMTP id v7mr2458088pfk.57.1495010327051; Wed, 17 May 2017 01:38:47 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.164]) by smtp.gmail.com with ESMTPSA id u9sm3029519pgn.55.2017.05.17.01.38.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 17 May 2017 01:38:46 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, puck.chen@hisilicon.com, xuejiancheng@hisilicon.com, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Wang Xiaoyin , Guodong Xu Subject: [PATCH 07/12] arm64: dts: hi3660: Add uarts nodes Date: Wed, 17 May 2017 16:37:40 +0800 Message-Id: <20170517083745.24479-8-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170517083745.24479-1-guodong.xu@linaro.org> References: <20170517083745.24479-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chen Feng Add nodes uart0 to uart4 and uart6 for hi3660 SoC. Enable uart3 and uart6, disable uart5, in hikey960 board dts. On HiKey960: - UART6 is used as default console, and is wired out through low speed expansion connector. - UART3 has RTS/CTS hardware handshake, and is wired out through low speed expansion connector. - UART5 is not used in commercial launched boards. So disable it. - UART4 is connected to Bluetooth, WL1837. Signed-off-by: Chen Feng Signed-off-by: Wang Xiaoyin Signed-off-by: Guodong Xu Reviewed-by: Zhangfei Gao --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 18 +++++-- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 60 +++++++++++++++++++++++ 2 files changed, 73 insertions(+), 5 deletions(-) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index f685b1e..513c496 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -15,12 +15,16 @@ compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; aliases { - serial5 = &uart5; /* console UART */ + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; }; - chosen { - stdout-path = "serial5:115200n8"; - }; + chosen {}; memory@0 { device_type = "memory"; @@ -47,6 +51,10 @@ status = "okay"; }; -&uart5 { +&uart3 { + status = "okay"; +}; + +&uart6 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 3bea0d2..0951a29 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -242,6 +242,56 @@ status = "disabled"; }; + uart0: serial@fdf02000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf02000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart1: serial@fdf00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf00000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, + <&crg_ctrl HI3660_CLK_GATE_UART1>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart2: serial@fdf03000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf03000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart3: serial@ffd74000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xffd74000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_FACTOR_UART3>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + uart4: serial@fdf01000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfdf01000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, + <&crg_ctrl HI3660_CLK_GATE_UART4>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + uart5: serial@fdf05000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0 0xfdf05000 0x0 0x1000>; @@ -252,6 +302,16 @@ status = "disabled"; }; + uart6: serial@fff32000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0xfff32000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_UART6>, + <&crg_ctrl HI3660_PCLK>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + gpio0: gpio@e8a0b000 { compatible = "arm,pl061", "arm,primecell"; reg = <0 0xe8a0b000 0 0x1000>; From patchwork Wed May 17 08:37:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 99913 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp127453qge; Wed, 17 May 2017 01:39:16 -0700 (PDT) X-Received: by 10.84.175.129 with SMTP id t1mr2930242plb.190.1495010356651; Wed, 17 May 2017 01:39:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495010356; cv=none; d=google.com; s=arc-20160816; b=KEEnbEMeMpiU74SiY/9Lx8JQ4P1ICSePF4ZSMjsc0vXMu6uTYrrdu1OFcbn9U3a86/ uIYjsAgY8Br9UXdlT5Sn7UWOA9BrZhgd2DcUc6jgLTWoizciXVudd6/LYUCYBlxo1i7b kbMvEL0PswVeE0TxFA2yeeRSlbwZRhhjpxiXJWImyJjA4nZN1JCH/6/naCrgV2gEITrz Y9M91elN6rOqyhc8OWWUB2YpGnR+bwHypSsVOPCSkdCeLhflPU8+M8rYjh6XNKwLvzGB +uqkcb1anQJsNWHq2P5g69n7DyHtPUsA3l8QM1tYQoF0nECN4L4kOmnWuyh9FvvIAKi9 +w5g== ARC-Message-Signature: i=1; a=rsa-sha256; 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[209.132.180.67]) by mx.google.com with ESMTP id r3si1477579pgn.278.2017.05.17.01.39.16; Wed, 17 May 2017 01:39:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754238AbdEQIi5 (ORCPT + 25 others); Wed, 17 May 2017 04:38:57 -0400 Received: from mail-pf0-f181.google.com ([209.85.192.181]:35421 "EHLO mail-pf0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932092AbdEQIiv (ORCPT ); Wed, 17 May 2017 04:38:51 -0400 Received: by mail-pf0-f181.google.com with SMTP id n23so3959874pfb.2 for ; Wed, 17 May 2017 01:38:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fQshrb9aF1ZbRBmbE7CS6q74+kGMPZNwW+BLzts7ygE=; b=RBWzPCsFBddDtBZ+OobKSfHbZDctpnjdPZNLRra1QQjymd1WHuW/94jllSXlZkQQT4 IhiRcrwYZt1dPj6/c7JrP/iIENSirmZQvFQm6+1BxIZiWMyfwB13jzAXeKbxeEiiTd7e xYz22VMM5uL8jdFT4xxjIPn/PXKtoW4KTxGlw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fQshrb9aF1ZbRBmbE7CS6q74+kGMPZNwW+BLzts7ygE=; b=ICljg/eS4udMVVcS6Vm+KbI5ptsYr8Bl7ubkD5Dul9KB2azzHMHf4I+zwEoiGb3Sjj 1ZfpxZcVmELBTrtqlxWZqo0DGmdhp5zdhYn+1n8jfPEEJlSllIJXos/p+b/7HRCcgK0Y oHXg4p7146JV2FECEeMrlE7zhqBtOWqCkGlPTM5tof5j5Rua/VH5DGS5kQuzus7nIMT6 LCkQB46rk3Ad9swcmzkDvFeJXyrg5fWkMh1Gmq9HrmRIU0odDj16bxNmOtZBvf9JMX0J DFts0O3pRKx+63LdhT+0kGW6Wrwwc6EI+0PYQV0oZoNGdV49f+taUthR0Im2a7zdRiw2 /sIg== X-Gm-Message-State: AODbwcBOP57OAoceNd+imO4SyN6A7947gyVRaBM7GMEr1Vll6b5lQy18 Imk/AtYjYTSZsbW4 X-Received: by 10.99.143.69 with SMTP id r5mr2450912pgn.77.1495010331136; Wed, 17 May 2017 01:38:51 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.164]) by smtp.gmail.com with ESMTPSA id u9sm3029519pgn.55.2017.05.17.01.38.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 17 May 2017 01:38:50 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, puck.chen@hisilicon.com, xuejiancheng@hisilicon.com, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Guodong Xu Subject: [PATCH 08/12] arm64: dts: hikey960: add WL1837 Bluetooth device node Date: Wed, 17 May 2017 16:37:41 +0800 Message-Id: <20170517083745.24479-9-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170517083745.24479-1-guodong.xu@linaro.org> References: <20170517083745.24479-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This adds the serial slave device for the WL1837 Bluetooth interface. Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 513c496..69aa207 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -9,6 +9,7 @@ #include "hi3660.dtsi" #include "hikey960-pinctrl.dtsi" +#include / { model = "HiKey960"; @@ -55,6 +56,16 @@ status = "okay"; }; +&uart4 { + status = "okay"; + max-speed = <921600>; + + bluetooth { + compatible = "ti,wl1837-st"; + enable-gpios = <&gpio15 6 GPIO_ACTIVE_HIGH>; + }; +}; + &uart6 { status = "okay"; }; From patchwork Wed May 17 08:37:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guodong Xu X-Patchwork-Id: 99915 Delivered-To: patch@linaro.org Received: by 10.140.96.100 with SMTP id j91csp127457qge; Wed, 17 May 2017 01:39:17 -0700 (PDT) X-Received: by 10.84.129.99 with SMTP id 90mr2855004plb.134.1495010357399; Wed, 17 May 2017 01:39:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1495010357; cv=none; d=google.com; s=arc-20160816; b=FI1ygRUbux8JzPBfnPDXK0cWqwderwgnI0Mj9uagVnb55FFITn1Fqd5EmIFr6hBnx3 lohgs860GM6oMxTPMfB/dwzjsGFNW3q4Ti+mcgz+RMJuVUWgdseKCjBhY0jeuiqvVVcf eozOTU7mzocJLvsU0d27OTPcOFbJJrChp/2T9vMR8I81tMmwkyiVNFUjdDQdfmkIh3tV VDIxuBaj5HRnKp5Bv51y6AA6qjAfEBJkIZ0fRpgXyJYVc8QvkrbrLpm3o++i6rqsfAD9 AacQ+qsN4tXQK82MdqyXKKbsjUZtUJ4RP7t6DSdK95K7baFmmmTKYQxl4H4yRBQeoiY/ J+FQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=vfDjHX293So3G2mdRY3yAUp8IVSJKZ24RbDr0ba+bkA=; b=W27Y+TqyLLF7FP++nB688ax74IXkOYRolLmW6xt0ZFd3LUbVcWezv2S4n35Usudpad AJ8mbGJDtmKEltGk1MfQlEgr1ExiRvOR7dQu1u3N7sVE5r6LNGa3g6NPnzAnrF3evKn4 2CRUJracF7oYLUvXC+uSSeowfps5dOEgTIogDvww0uS74JiZtAdknJKxzIC+MKHTC/cl GE9kjwhhj0H9rBvzhN+Ysqx2c6BwNo/obEsb8TtEkRujWCTKI+qqtFxw01JOzS40GpiN QDQVL+NcNTOs8go9/OYjwxSqrvcdf0NkygdYMa4Wl8gXfixcKz98y2sZrwIlYGB8pwD/ Umrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r3si1477579pgn.278.2017.05.17.01.39.17; Wed, 17 May 2017 01:39:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754254AbdEQIjF (ORCPT + 25 others); Wed, 17 May 2017 04:39:05 -0400 Received: from mail-pf0-f174.google.com ([209.85.192.174]:35455 "EHLO mail-pf0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932100AbdEQIjA (ORCPT ); Wed, 17 May 2017 04:39:00 -0400 Received: by mail-pf0-f174.google.com with SMTP id n23so3961422pfb.2 for ; Wed, 17 May 2017 01:38:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vfDjHX293So3G2mdRY3yAUp8IVSJKZ24RbDr0ba+bkA=; b=B8rnaR5YdXhcgiHZGYh/sBuZlZ0pgn0oh4CrZGhju5BU3BCIICR50s/za5jKK8jLBV Lx1WByePldsoBE4/6I/rA7VNbrRmftzd1ya6Q6o/uOdrWS2KNeB2D01rVwnvRhMPXi7C wsyHZtOLpK+xVIultk2uvUvuNbEfVEwtzJVv0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vfDjHX293So3G2mdRY3yAUp8IVSJKZ24RbDr0ba+bkA=; b=UQEE+Wo37rSYM/1FpAvQ5H0A896koUhFD1HOCRvXuMXPDut73QVHcucthCUKUHWfK1 b/loat/4k/nKxxcgi9joU40xsJa0V4i2yUIQ/ZR67RWYsHuU51gpWsCUihZ6K8P1FYsO yI2ShM9RPpfFn7pGkGsKRR9h4d4PznhvtEYLGq2TLUa1ROI64S2vrYUYmvAGffpg7MJH qZ++soAfPszfrzEx1pyN/UtMiFOWfFx7VIeQrLliqoDun4y70+jtIwssCvDAJLZBey2c QVxm6A2SiSoGdY8nDrbFDK/PZ4E+QXwg0n54yb11f7SZxwygYFKNTS4O9/EHkBI4J4Ao BsbQ== X-Gm-Message-State: AODbwcCEA79575xJhgjWHC5i0FQO20KWmQotw3rn66YQdfeFXAHE/kwY OmkCSjb7VPIQQtdg X-Received: by 10.99.55.68 with SMTP id g4mr1960631pgn.115.1495010339404; Wed, 17 May 2017 01:38:59 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.56.159.164]) by smtp.gmail.com with ESMTPSA id u9sm3029519pgn.55.2017.05.17.01.38.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 17 May 2017 01:38:58 -0700 (PDT) From: Guodong Xu To: robh+dt@kernel.org, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, puck.chen@hisilicon.com, xuejiancheng@hisilicon.com, devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Wang Xiaoyin , Guodong Xu Subject: [PATCH 10/12] arm64: dts: hi3660: add spi device nodes Date: Wed, 17 May 2017 16:37:43 +0800 Message-Id: <20170517083745.24479-11-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170517083745.24479-1-guodong.xu@linaro.org> References: <20170517083745.24479-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Wang Xiaoyin Add spi2 and spi3 device nodes for hi3660, and enable them for hikey960. On HiKey960: - SPI2 is wired out through low speed expansion connector. - SPI3 is wired out through high speed expansion connector. Signed-off-by: Wang Xiaoyin Signed-off-by: Guodong Xu --- arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 8 ++++++ arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 30 +++++++++++++++++++++++ 2 files changed, 38 insertions(+) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts index 69aa207..79735ee 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts @@ -69,3 +69,11 @@ &uart6 { status = "okay"; }; + +&spi2 { + status = "okay"; +}; + +&spi3 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index c2bca5d..48da97f 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -728,5 +728,35 @@ clock-names = "apb_pclk"; status = "ok"; }; + + spi2: spi@ffd68000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xffd68000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; + clock-names = "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pmx_func>; + num-cs = <1>; + cs-gpios = <&gpio27 2 0>; + status = "disabled"; + }; + + spi3: spi@ff3b3000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0xff3b3000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; + clock-names = "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pmx_func>; + num-cs = <1>; + cs-gpios = <&gpio18 5 0>; + status = "disabled"; + }; }; };