From patchwork Wed Sep 5 09:49:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 145979 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp4719365ljw; Wed, 5 Sep 2018 02:49:56 -0700 (PDT) X-Google-Smtp-Source: ANB0Vda/UIUhheIpT/qUQY7dqrKeZvBDcEldokAC6jmpMHYMIRxJMzFkPR8KKBxpcyLQrDr86Omw X-Received: by 2002:a63:4106:: with SMTP id o6-v6mr24158930pga.80.1536140996265; Wed, 05 Sep 2018 02:49:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1536140996; cv=none; d=google.com; s=arc-20160816; b=pvhSGeSW8MkX6W2Zz1aUYkotdElXyopOEubVR6bdOctEr5DoKi9OY2dKMj5h0BCd8o gCn9/Yv7N/DsjfFNxLjTW9WTYVKAauqzVzp+MPppTGn6UW2vvKD+S7hOC/LOnti/K1qB esBRUpS5ipSjncmeB8YGd1FfVBXevOMW2MtUUklAU8ulpjR/+Rb7gpKGJFjLDfQErG7b aCV9gjVu6IkEDhBc4dqJKLV1mJve6sZ6kKDhhKyDSGkWuO4fjNZ6aSL5LxSjtl3b515M 8ODsIktg/XUYfH3SxNodsGkfbyvruR/wBgciLgXab7g9e05Uj8GT8dCCMmiOWFmHWcc6 mexQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=qn6UpFmXCudWZSLClz63rFlAuYledj5I/oi/6T0TT4Q=; b=Dsxtz2LYrub9UfIsQP/ByOX5IgpYbx84VZH1iM23otzzMXQ7br0vgW4Tjlc6KB9RL7 afxTACI+AguI8Ag6bLBTHHKtC4Tr4jrXplX7MxWGL8YMjw9Vd3Zps8GNjEqnzkBz/S4B jdU3OS9MuPg1LrS3g4kzWRUz9maJcMLU/y8nl5OQbcFo6FzZ81E0aoYT49O1WDFsHWL6 dXKkHEcUQlmR0/egYGWvd4AtPIYPlA6gbfkZ1JSte6WnxcvaPgASrE+zuINh+SqdLwaj dXDUe5X4Xad9SRXA9usr1bXtEbzGX0ATpX/W+QXv5My+Yl0qqGeJARlwz160iOiZdYZ8 d+mw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g66-v6si1639344pfk.53.2018.09.05.02.49.55; Wed, 05 Sep 2018 02:49:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728109AbeIEOTT (ORCPT + 32 others); Wed, 5 Sep 2018 10:19:19 -0400 Received: from mx.socionext.com ([202.248.49.38]:54956 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726272AbeIEOTT (ORCPT ); Wed, 5 Sep 2018 10:19:19 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 05 Sep 2018 18:49:52 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 33D431800E0; Wed, 5 Sep 2018 18:49:52 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 5 Sep 2018 18:49:52 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 765761A16F7; Wed, 5 Sep 2018 18:49:51 +0900 (JST) From: Kunihiko Hayashi To: Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Masahiro Yamada Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH 1/2] dt-bindings: phy: add UniPhier PCIe PHY description Date: Wed, 5 Sep 2018 18:49:44 +0900 Message-Id: <1536140985-6058-2-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1536140985-6058-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1536140985-6058-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add DT bindings for PHY interface built into PCIe controller implemented in UniPhier SoCs. Signed-off-by: Kunihiko Hayashi --- .../devicetree/bindings/phy/uniphier-pcie-phy.txt | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt -- 2.7.4 diff --git a/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt b/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt new file mode 100644 index 0000000..1889d3b --- /dev/null +++ b/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt @@ -0,0 +1,31 @@ +Socionext UniPhier PCIe PHY bindings + +This describes the devicetree bindings for PHY interface built into +PCIe controller implemented on Socionext UniPhier SoCs. + +Required properties: +- compatible: Should contain one of the following: + "socionext,uniphier-ld20-pcie-phy" - for LD20 PHY + "socionext,uniphier-pxs3-pcie-phy" - for PXs3 PHY +- reg: Specifies offset and length of the register set for the device. +- #phy-cells: Must be zero. +- clocks: A phandle to the clock gate for PCIe glue layer including + this phy. +- resets: A phandle to the reset line for PCIe glue layer including + this phy. + +Optional properties: +- socionext,syscon: A phandle to system control to set configurations + for phy. + +Refer to phy/phy-bindings.txt for the generic PHY binding properties. + +Example: + pcie_phy: phy@66038000 { + compatible = "socionext,uniphier-ld20-pcie-phy"; + reg = <0x66038000 0x4000>; + #phy-cells = <0>; + clocks = <&sys_clk 24>; + resets = <&sys_rst 24>; + socionext,syscon = <&soc_glue>; + }; From patchwork Wed Sep 5 09:49:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 145980 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp4719389ljw; Wed, 5 Sep 2018 02:49:58 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZ0Zp2XU7P2tNVoK9mOjzrACTgSy4rnxmewt6/Hb9RNftFHzakm4FhgsJsduecCuT6bITkA X-Received: by 2002:a63:550b:: with SMTP id j11-v6mr34679572pgb.167.1536140998005; Wed, 05 Sep 2018 02:49:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1536140997; cv=none; d=google.com; s=arc-20160816; b=AXbIpyXhsoVtHVWsn/IJAu8jEsSo+btYupzbzUDcxqCqFIh696TA0ciAFIkM78UO85 fMjLAFKMCVwDHrCZeb9fAr8LiSWbBk1GEaVq+Xzx33BhJciKUGh6vZ3xWjd9koiOlVRe tjtU9p5s5pkKhoulNF6YdcG6OQUXOti/6F05lSeg4UbWw7cKVYKX+qAOv02U8XvKO5M7 S490YF5XrVttKPDooyoT9upbC9mrMEKl4SJg5HyuB3g/xJDo7Cj3w5mt/e37BxO9Nv34 JH49AQE7zbLaO5px7i3Nw9yHqk5ueoub9uNWZTA/1gEjJhI3KgeBAQP6GVi8/P2Nedlq /24g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=C5yi9kBN1nsqIFkOMvDrw5axDSAEUgxA4cAe/1VleJ4=; b=BMs9+/6sXBhwldEXO7dJKnvQTHBjsPV7ukFlsajx12J5QthhJPxxsjs/Wk4Z2APcC1 MUmpJLV4Xq71r2yw+UFAObHhyooLr1x5xnnTORB1K1lQreEqnfo+rbeew/LDJgMXEHdz Fli99hHibhxNjH4jlZqQutpaxS5auoC5ii35oOMLzFoV0j5yVhagEHAaiMerXByr/mL/ gD4fvzc5mZe975r5z2pfn1oMTB7ONjddReeOM2LuPXBmzBeBgTHRocG+228E6ZVGkWoB WBDW4HKkw0223Q38MPwjpTIGC5sh1SBQ3wOfo7YaNRI+vLgBKfjVbjqXZilHseRaHJPX ADVQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v6-v6si1438456plo.264.2018.09.05.02.49.57; Wed, 05 Sep 2018 02:49:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728160AbeIEOTV (ORCPT + 32 others); Wed, 5 Sep 2018 10:19:21 -0400 Received: from mx.socionext.com ([202.248.49.38]:54948 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727951AbeIEOTU (ORCPT ); Wed, 5 Sep 2018 10:19:20 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 05 Sep 2018 18:49:53 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 9CDBB600AA; Wed, 5 Sep 2018 18:49:53 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 5 Sep 2018 18:49:53 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id E24AD1A03A2; Wed, 5 Sep 2018 18:49:52 +0900 (JST) From: Kunihiko Hayashi To: Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Masahiro Yamada Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH 2/2] phy: socionext: add PCIe PHY driver support Date: Wed, 5 Sep 2018 18:49:45 +0900 Message-Id: <1536140985-6058-3-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1536140985-6058-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1536140985-6058-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a driver for PHY interface built into PCIe controller implemented in UniPhier SoCs. Signed-off-by: Kunihiko Hayashi --- drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/socionext/Kconfig | 12 ++ drivers/phy/socionext/Makefile | 6 + drivers/phy/socionext/phy-uniphier-pcie.c | 240 ++++++++++++++++++++++++++++++ 5 files changed, 260 insertions(+) create mode 100644 drivers/phy/socionext/Kconfig create mode 100644 drivers/phy/socionext/Makefile create mode 100644 drivers/phy/socionext/phy-uniphier-pcie.c -- 2.7.4 diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 5c8d452..b752589 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -53,6 +53,7 @@ source "drivers/phy/ralink/Kconfig" source "drivers/phy/renesas/Kconfig" source "drivers/phy/rockchip/Kconfig" source "drivers/phy/samsung/Kconfig" +source "drivers/phy/socionext/Kconfig" source "drivers/phy/st/Kconfig" source "drivers/phy/tegra/Kconfig" source "drivers/phy/ti/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 84e3bd9..5539cde 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -21,5 +21,6 @@ obj-y += broadcom/ \ qualcomm/ \ ralink/ \ samsung/ \ + socionext/ \ st/ \ ti/ diff --git a/drivers/phy/socionext/Kconfig b/drivers/phy/socionext/Kconfig new file mode 100644 index 0000000..20a1195 --- /dev/null +++ b/drivers/phy/socionext/Kconfig @@ -0,0 +1,12 @@ +# +# PHY drivers for Socionext platforms. +# + +config PHY_UNIPHIER_PCIE + tristate "Uniphier PHY driver for PCIe controller" + depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF + default PCIE_UNIPHIER + select GENERIC_PHY + help + Enable this to support PHY implemented in PCIe controller + on UniPhier SoCs. This driver supports LD20 and PXs3 SoCs. diff --git a/drivers/phy/socionext/Makefile b/drivers/phy/socionext/Makefile new file mode 100644 index 0000000..5484360 --- /dev/null +++ b/drivers/phy/socionext/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for the phy drivers. +# + +obj-$(CONFIG_PHY_UNIPHIER_PCIE) += phy-uniphier-pcie.o diff --git a/drivers/phy/socionext/phy-uniphier-pcie.c b/drivers/phy/socionext/phy-uniphier-pcie.c new file mode 100644 index 0000000..93ffbd2 --- /dev/null +++ b/drivers/phy/socionext/phy-uniphier-pcie.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * phy-uniphier-pcie.c - PHY driver for UniPhier PCIe controller + * Copyright 2018, Socionext Inc. + * Author: Kunihiko Hayashi + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* PHY */ +#define PCL_PHY_TEST_I 0x2000 +#define PCL_PHY_TEST_O 0x2004 +#define TESTI_DAT_MASK GENMASK(13, 6) +#define TESTI_ADR_MASK GENMASK(5, 1) +#define TESTI_WR_EN BIT(0) + +#define PCL_PHY_RESET 0x200c +#define PCL_PHY_RESET_N_MNMODE BIT(8) /* =1:manual */ +#define PCL_PHY_RESET_N BIT(0) /* =1:deasssert */ + +/* SG */ +#define SG_USBPCIESEL 0x590 +#define SG_USBPCIESEL_PCIE BIT(0) + +#define PCL_PHY_R00 0 +#define RX_EQ_ADJ_EN BIT(3) /* enable for EQ adjustment */ +#define PCL_PHY_R06 6 +#define RX_EQ_ADJ GENMASK(5, 0) /* EQ adjustment value */ +#define RX_EQ_ADJ_VAL 0 +#define PCL_PHY_R26 26 +#define VCO_CTRL GENMASK(7, 4) /* Tx VCO adjustment value */ +#define VCO_CTRL_INIT_VAL 5 + +struct uniphier_pciephy_priv { + void __iomem *base; + struct device *dev; + struct clk *clk; + struct reset_control *rst; + const struct uniphier_pciephy_soc_data *data; +}; + +struct uniphier_pciephy_soc_data { + bool has_syscon; +}; + +static void uniphier_pciephy_testio_write(struct uniphier_pciephy_priv *priv, + u32 data) +{ + /* need to read TESTO twice after accessing TESTI */ + writel(data, priv->base + PCL_PHY_TEST_I); + readl(priv->base + PCL_PHY_TEST_O); + readl(priv->base + PCL_PHY_TEST_O); +} + +static void uniphier_pciephy_set_param(struct uniphier_pciephy_priv *priv, + u32 reg, u32 mask, u32 param) +{ + u32 val; + + /* read previous data */ + val = FIELD_PREP(TESTI_DAT_MASK, 1); + val |= FIELD_PREP(TESTI_ADR_MASK, reg); + uniphier_pciephy_testio_write(priv, val); + val = readl(priv->base + PCL_PHY_TEST_O); + + /* update value */ + val &= ~FIELD_PREP(TESTI_DAT_MASK, mask); + val = FIELD_PREP(TESTI_DAT_MASK, mask & param); + val |= FIELD_PREP(TESTI_ADR_MASK, reg); + uniphier_pciephy_testio_write(priv, val); + uniphier_pciephy_testio_write(priv, val | TESTI_WR_EN); + uniphier_pciephy_testio_write(priv, val); + + /* read current data as dummy */ + val = FIELD_PREP(TESTI_DAT_MASK, 1); + val |= FIELD_PREP(TESTI_ADR_MASK, reg); + uniphier_pciephy_testio_write(priv, val); + readl(priv->base + PCL_PHY_TEST_O); +} + +static void uniphier_pciephy_assert(struct uniphier_pciephy_priv *priv) +{ + u32 val; + + val = readl(priv->base + PCL_PHY_RESET); + val &= ~PCL_PHY_RESET_N; + val |= PCL_PHY_RESET_N_MNMODE; + writel(val, priv->base + PCL_PHY_RESET); +} + +static void uniphier_pciephy_deassert(struct uniphier_pciephy_priv *priv) +{ + u32 val; + + val = readl(priv->base + PCL_PHY_RESET); + val |= PCL_PHY_RESET_N_MNMODE | PCL_PHY_RESET_N; + writel(val, priv->base + PCL_PHY_RESET); +} + +static int uniphier_pciephy_init(struct phy *phy) +{ + struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = clk_prepare_enable(priv->clk); + if (ret) + return ret; + + ret = reset_control_deassert(priv->rst); + if (ret) + goto out_clk_disable; + + uniphier_pciephy_set_param(priv, PCL_PHY_R00, + RX_EQ_ADJ_EN, RX_EQ_ADJ_EN); + uniphier_pciephy_set_param(priv, PCL_PHY_R06, RX_EQ_ADJ, + FIELD_PREP(RX_EQ_ADJ, RX_EQ_ADJ_VAL)); + uniphier_pciephy_set_param(priv, PCL_PHY_R26, VCO_CTRL, + FIELD_PREP(VCO_CTRL, VCO_CTRL_INIT_VAL)); + usleep_range(1, 10); + + uniphier_pciephy_deassert(priv); + usleep_range(1, 10); + + return 0; + +out_clk_disable: + clk_disable_unprepare(priv->clk); + + return ret; +} + +static int uniphier_pciephy_exit(struct phy *phy) +{ + struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy); + + uniphier_pciephy_assert(priv); + reset_control_assert(priv->rst); + clk_disable_unprepare(priv->clk); + + return 0; +} + +static const struct phy_ops uniphier_pciephy_ops = { + .init = uniphier_pciephy_init, + .exit = uniphier_pciephy_exit, + .owner = THIS_MODULE, +}; + +static int uniphier_pciephy_probe(struct platform_device *pdev) +{ + struct uniphier_pciephy_priv *priv; + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct regmap *regmap; + struct resource *res; + struct phy *phy; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->data = of_device_get_match_data(dev); + if (WARN_ON(!priv->data)) + return -EINVAL; + + priv->dev = dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->base = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) + return PTR_ERR(priv->clk); + + priv->rst = devm_reset_control_get_shared(dev, NULL); + if (IS_ERR(priv->rst)) + return PTR_ERR(priv->rst); + + phy = devm_phy_create(dev, dev->of_node, &uniphier_pciephy_ops); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + regmap = syscon_regmap_lookup_by_phandle(dev->of_node, + "socionext,syscon"); + if (!IS_ERR(regmap) && priv->data->has_syscon) + regmap_update_bits(regmap, SG_USBPCIESEL, + SG_USBPCIESEL_PCIE, SG_USBPCIESEL_PCIE); + + phy_set_drvdata(phy, priv); + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct uniphier_pciephy_soc_data uniphier_ld20_data = { + .has_syscon = true, +}; + +static const struct uniphier_pciephy_soc_data uniphier_pxs3_data = { + .has_syscon = false, +}; + +static const struct of_device_id uniphier_pciephy_match[] = { + { + .compatible = "socionext,uniphier-ld20-pcie-phy", + .data = &uniphier_ld20_data, + }, + { + .compatible = "socionext,uniphier-pxs3-pcie-phy", + .data = &uniphier_pxs3_data, + }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, uniphier_pciephy_match); + +static struct platform_driver uniphier_pciephy_driver = { + .probe = uniphier_pciephy_probe, + .driver = { + .name = "uniphier-pcie-phy", + .of_match_table = uniphier_pciephy_match, + }, +}; +module_platform_driver(uniphier_pciephy_driver); + +MODULE_AUTHOR("Kunihiko Hayashi "); +MODULE_DESCRIPTION("UniPhier PHY driver for PCIe controller"); +MODULE_LICENSE("GPL v2");