From patchwork Mon Sep 3 21:50:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 145828 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp2942601ljw; Mon, 3 Sep 2018 14:50:49 -0700 (PDT) X-Google-Smtp-Source: ANB0VdYUhINHy46/7Q17FhnUXNIjeX6YZGX23RQqsSe/K3xG74G+G16qpz8dBgVHsMapnMcWKKiE X-Received: by 2002:a62:1219:: with SMTP id a25-v6mr31509757pfj.104.1536011449588; Mon, 03 Sep 2018 14:50:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1536011449; cv=none; d=google.com; s=arc-20160816; b=XerKIR/7PmCGPVs7rtT+OXjP1TVvKzqs9VaIr+gOgg8co8jFCere3Sff7iUWM2t0W6 jG7dGaf7iF4592GtH6sDwyW73KbmQi8AbmyXyl98VrYYxaNnhQ3DBYBA0YAEzDy8gwBF xsaZ3W5AJhJN7xHPi3pnLabFVGVc6S4pAVs/I7J1tqtGz85UfZ/wzrkZyG/C07C6Z4K2 0kSvUNpizy5AOghVftIto6R4kXsytAHCbksMMqEFOPhkW2uX3NZcStu6LxKApdZo0UA/ I2oG7ex12lo49vSEImvauI9iLjq0QObYcSoeYwfLwo4WmFo/JhrWu/CeRRItQXLjtj5q DeEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=SJuFv+lF2yIIAer5KVTofLqD35pnm/sU6RwnGCbRx2M=; b=bF8PnqaTtFJjVg048sk/0dsoYNMM+iKErYuW/8/tZ2D/Mjymf4fepKN6b184mGzgQ7 Fv3E9ld67OMPGm0Oodk5mBkXm9ySK33gZA3HMShagguru5I7swMfZNHxISmDHalOVJtj FsFo4owxuf3Yu/huRVd6wMeO52TlwJQkauupK7V0YKz7fRZiF5Lig77xI3b0XXHf4tsE BT0JnNwx7IYGXVaeJ2Tul96rHtzoTA6uT+Np/GyK1lq58FUaQdEgtpEAjfcq0CRMPiYE KtRN1Dtax1wMLeuYStmrIY6JnO1HpkiaIl00+TUAOPGDjckVI8ehN/kcqmCHuT1isqef yUSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CvGlONwH; spf=pass (google.com: best guess record for domain of linux-spi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-spi-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 3-v6si18146466plr.488.2018.09.03.14.50.49; Mon, 03 Sep 2018 14:50:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-spi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CvGlONwH; spf=pass (google.com: best guess record for domain of linux-spi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-spi-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726183AbeIDCMy (ORCPT + 1 other); Mon, 3 Sep 2018 22:12:54 -0400 Received: from mail-lj1-f196.google.com ([209.85.208.196]:35124 "EHLO mail-lj1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727100AbeIDCMy (ORCPT ); Mon, 3 Sep 2018 22:12:54 -0400 Received: by mail-lj1-f196.google.com with SMTP id p10-v6so1454692ljg.2 for ; Mon, 03 Sep 2018 14:50:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SJuFv+lF2yIIAer5KVTofLqD35pnm/sU6RwnGCbRx2M=; b=CvGlONwHxxbyI6lTsJ4VCTtDyUVP7Q6VQIb00iqfuc64cCo5N893tUTcSRit7GlDoo cwDb7mrs0BeF/wBiZzKnyOZgqb86VY9MKCDAMy8wM9oXiU6XPIDYDfiME4dHHlHIyLdl WRQFCyXFc1WQ9GX3cFieGO6ADjnW3vlXCtk+8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SJuFv+lF2yIIAer5KVTofLqD35pnm/sU6RwnGCbRx2M=; b=hI0oxfGLVldSq51NT983bcqz0QbJlax+VJ2rTqh4+mm7woOyNg3cjPO0wHx27nfqxC hfLZ8ymCFM/6cMuHUD6AwL0QnIaPNekhpjBhS7kuU+ZjoHp4M6q24hYwuLqkj0CTwOsH Qf/5BkCnwSArQpQq67N61vXlepx7281Zu12WdNuuWMuStQAFEVqgt7YUBkvnSFyzzocK 0som3uCtZhG7vqEmBzmPS0vIIirOXFG4Rc55gjOGuzagZPc3STOoaN/i0lY1nn88Lek3 2en2k3Czd8gRv+QOWIxIyfkQb1bvxSQj5xqpXnK3K0baDZtw+XcVwejZ2Mb15P2lZSDa Xu6A== X-Gm-Message-State: APzg51BGDF31kZUw2dIMG4YI4FPqIrOkAefGyvc7DNZgWfMelUtrbIt7 MeReqzZmPBJXjovwSV/5/iiiVg== X-Received: by 2002:a2e:291c:: with SMTP id u28-v6mr18207089lje.70.1536011446939; Mon, 03 Sep 2018 14:50:46 -0700 (PDT) Received: from localhost.bredbandsbolaget (c-ae7b71d5.014-348-6c756e10.bbcust.telenor.se. [213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm3665503ljq.72.2018.09.03.14.50.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Sep 2018 14:50:45 -0700 (PDT) From: Linus Walleij To: Mark Brown , linux-spi@vger.kernel.org, Andrzej Hajda , Lorenzo Bianconi Cc: linux-gpio@vger.kernel.org, Rob Herring , Linus Walleij Subject: [PATCH 1/4] spi: core: Allow both TX and RX transfers in 3WIRE Date: Mon, 3 Sep 2018 23:50:32 +0200 Message-Id: <20180903215035.17265-2-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180903215035.17265-1-linus.walleij@linaro.org> References: <20180903215035.17265-1-linus.walleij@linaro.org> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The SPI message validation code in __spi_validate() is too restrictive on 3WIRE transfers: the core bitbanging code, for example, will gladly switch direction of the line inbetween transfers. Allow 3WIRE messages even if there is both TX and RX transfers in the message. Transfers with TX and RX at the same time will not work however (just one wire after all), so be sure to disallow those. Cc: Andrzej Hajda Cc: Lorenzo Bianconi Signed-off-by: Linus Walleij --- drivers/spi/spi.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) -- 2.17.1 Acked-by: Lorenzo Bianconi diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index ec395a6baf9c..f6f9314e9a18 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -2841,10 +2841,17 @@ static int __spi_validate(struct spi_device *spi, struct spi_message *message) list_for_each_entry(xfer, &message->transfers, transfer_list) { if (xfer->rx_buf && xfer->tx_buf) return -EINVAL; - if ((flags & SPI_CONTROLLER_NO_TX) && xfer->tx_buf) - return -EINVAL; - if ((flags & SPI_CONTROLLER_NO_RX) && xfer->rx_buf) - return -EINVAL; + /* + * 3WIRE can indeed do a write message followed by a + * read message, the direction of the line will be + * switched between the two messages. + */ + if (spi->mode & SPI_CONTROLLER_HALF_DUPLEX) { + if ((flags & SPI_CONTROLLER_NO_TX) && xfer->tx_buf) + return -EINVAL; + if ((flags & SPI_CONTROLLER_NO_RX) && xfer->rx_buf) + return -EINVAL; + } } } From patchwork Mon Sep 3 21:50:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 145829 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp2942626ljw; Mon, 3 Sep 2018 14:50:52 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZB9kN5AQmuxQRd0sZJBCJr5rJZvr6NAfB6DrrzK4JVH7i5E4VTnDKMDt5VB8N6fjtE84Qi X-Received: by 2002:a17:902:6808:: with SMTP id h8-v6mr30721563plk.27.1536011452425; Mon, 03 Sep 2018 14:50:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1536011452; cv=none; d=google.com; s=arc-20160816; b=kNH558tGnCjIetLYKlpjQjHgOlKR1uq+i11Bw7438B8T9e88g/c1+zgywBAvunJFJ1 Me982t/1oFpCMP1ZIWp4RzywPa7eDLxGa+UshublPSLfW3OLWO/jayBpdcbK17riNsb2 mWpN9EOQnbz+vgF8mk4GCHa8FPiS8iEvjRWpXwgCyY0HYjKsvPw0CSr8vPKXOEmMYUzy YMfj2Lsh2mXFjsOHUhS56nAsoELspKhd9/9za56JQ9yvEdz1Bx6fMuKrpJGhwcV48bge fomL+2BnrkwHpSx4QcGQ6OLc5hngSWsBQIlFpgHSsMk5xVnCMKMC19xoNIxcaSr6uENO vW8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=z0JAMZTPBOk70wPnOcW/n1U02PRHWoOYXYXqO3F0FD0=; b=EUGXpDgpkjTx6hg4ql/EJr9jn7pzmdX6OVq9TwnirTs8h7ZCGEICxJP6mRWx/plyqm RSHfKCzVWWnXNg7IVkeEyEDnhU+WzCIO/eH4UNCriYP2D8N9y3ZnAbaV9m/wN1SzmNRJ vhKPwpSoXPSaUaH9BCqpQDBx9UZPxx98DFlFeWmfndOde32XoL0QWsGfs0TNlRl8B/66 FFXc5NeseELCstZ7pBPrCfjCeQBxo4P6D1FUh5HBTta90kj+2/unlNRKTozQNooC1n27 LWd7i7WitU08hhDwCRhdw6+EQATQ1yaXOMKsjlQw8HFsv9kcOsrSxPGsOcLqp0MUWT8w V1Hw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aHquJOgX; spf=pass (google.com: best guess record for domain of linux-spi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-spi-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 3-v6si18146466plr.488.2018.09.03.14.50.52; Mon, 03 Sep 2018 14:50:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-spi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aHquJOgX; spf=pass (google.com: best guess record for domain of linux-spi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-spi-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727212AbeIDCM5 (ORCPT + 1 other); Mon, 3 Sep 2018 22:12:57 -0400 Received: from mail-lf1-f68.google.com ([209.85.167.68]:45629 "EHLO mail-lf1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727100AbeIDCM5 (ORCPT ); Mon, 3 Sep 2018 22:12:57 -0400 Received: by mail-lf1-f68.google.com with SMTP id r4-v6so1319556lff.12 for ; Mon, 03 Sep 2018 14:50:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=z0JAMZTPBOk70wPnOcW/n1U02PRHWoOYXYXqO3F0FD0=; b=aHquJOgXggxxFbce46YP+0HD7iSUp/9NaeGHmZ2MsYFJhU5gYZj1Fy3fKTAoinG4fu 3rY9J/NvopLU15xRvx2y1dcFTjWZQDdDgQkXmYNEKKl0aqv8EZfi47dREiJVA88BWRH/ otGajQAsE+Rt6s+sVHqQnlMj0wnlAB/AfM1wA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=z0JAMZTPBOk70wPnOcW/n1U02PRHWoOYXYXqO3F0FD0=; b=ibOasMNyz62+MoFO+XnNhUNjH2VYPqpHjzyqw6u1LXI5V7QciZMEj/sl7rcX7PbwAS 9IWnwC2tYnVRFbT3LY25ke/Puvn2XBWL1qXdKuaVUhcCIA7EdQ+GD5f7RSG85hZn0/0X m/e6fGEXguT5/9WqTirfWO/8fen5WvlTg/b0LXr39ZIHOo4VGzMoYponMiCtMpv9vZSw Osm/+JofWpV0cxpPLPmtZZiMX9gePAHUhSzaTc8P2Hw2qSGyP10nLpxHqO7eKXq4OuGr Jl3Pa5dVqgT+76t0PmaZg0/6/hIhRhgj1uemyKhx5Oc59vgzZolq1e3wUCOEGDOYjgXc BomA== X-Gm-Message-State: APzg51DdPo4TeL3bPiztLtDOoxEpyAIN0Wbyx6ZxH7uyPQ6tPIaFwbTK fwcLh1jTyqisibpFrWShzBklDw== X-Received: by 2002:a19:8c8:: with SMTP id 191-v6mr984383lfi.152.1536011449766; Mon, 03 Sep 2018 14:50:49 -0700 (PDT) Received: from localhost.bredbandsbolaget (c-ae7b71d5.014-348-6c756e10.bbcust.telenor.se. [213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm3665503ljq.72.2018.09.03.14.50.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Sep 2018 14:50:48 -0700 (PDT) From: Linus Walleij To: Mark Brown , linux-spi@vger.kernel.org, Andrzej Hajda , Lorenzo Bianconi Cc: linux-gpio@vger.kernel.org, Rob Herring , Linus Walleij Subject: [PATCH 2/4] spi: gpio: Fix reading for 3WIRE Date: Mon, 3 Sep 2018 23:50:33 +0200 Message-Id: <20180903215035.17265-3-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180903215035.17265-1-linus.walleij@linaro.org> References: <20180903215035.17265-1-linus.walleij@linaro.org> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org If he GPIO bitbanged host is registered using just one line, MISO, naturally the DT parser will flag the host as SPI_MASTER_NO_RX. This makes the GPIO SPI driver assign word transfer functions that enforce the SPI master flags SPI_MASTER_NO_RX (or SPI_MASTER_NO_TX) to the flags on each call down to the inlined bitbang functions such as bitbang_txrx_be_cpha0(). In the 3WIRE case, enforcing this flag is wrong, because the master can then do both TX and RX (albeit not at the same time) using the same line, by just switching the direction of the line and keep clocking in bits. Augment spi_gpio_spec_txrx_word_mode[0123] to account for this. Cc: Andrzej Hajda Cc: Lorenzo Bianconi Signed-off-by: Linus Walleij --- drivers/spi/spi-gpio.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/spi/spi-gpio.c b/drivers/spi/spi-gpio.c index 9f4882f82c3c..6bd692304b92 100644 --- a/drivers/spi/spi-gpio.c +++ b/drivers/spi/spi-gpio.c @@ -183,33 +183,42 @@ static u32 spi_gpio_txrx_word_mode3(struct spi_device *spi, * speed in the generic case (when both MISO and MOSI lines are * available), as optimiser will remove the checks when argument is * constant. + * + * A special kludge is needed for 3WIRE SPI, as this mode can use + * the same line for RX and TX and should not enforce the host + * flag - we will just switch MISO from output to input mode when + * needed. */ static u32 spi_gpio_spec_txrx_word_mode0(struct spi_device *spi, unsigned nsecs, u32 word, u8 bits, unsigned flags) { - flags = spi->master->flags; + if (!(spi->mode & SPI_3WIRE)) + flags = spi->master->flags; return bitbang_txrx_be_cpha0(spi, nsecs, 0, flags, word, bits); } static u32 spi_gpio_spec_txrx_word_mode1(struct spi_device *spi, unsigned nsecs, u32 word, u8 bits, unsigned flags) { - flags = spi->master->flags; + if (!(spi->mode & SPI_3WIRE)) + flags = spi->master->flags; return bitbang_txrx_be_cpha1(spi, nsecs, 0, flags, word, bits); } static u32 spi_gpio_spec_txrx_word_mode2(struct spi_device *spi, unsigned nsecs, u32 word, u8 bits, unsigned flags) { - flags = spi->master->flags; + if (!(spi->mode & SPI_3WIRE)) + flags = spi->master->flags; return bitbang_txrx_be_cpha0(spi, nsecs, 1, flags, word, bits); } static u32 spi_gpio_spec_txrx_word_mode3(struct spi_device *spi, unsigned nsecs, u32 word, u8 bits, unsigned flags) { - flags = spi->master->flags; + if (!(spi->mode & SPI_3WIRE)) + flags = spi->master->flags; return bitbang_txrx_be_cpha1(spi, nsecs, 1, flags, word, bits); } From patchwork Mon Sep 3 21:50:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 145830 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp2942652ljw; Mon, 3 Sep 2018 14:50:55 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZhxH4R5WrsNt4cDBsZN/rAE8kg3fzh9BYOuFuN8/S8H1DMI513C0yqNhGcOjczCR3+VcJA X-Received: by 2002:a63:f043:: with SMTP id s3-v6mr27291365pgj.94.1536011455306; Mon, 03 Sep 2018 14:50:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1536011455; cv=none; d=google.com; s=arc-20160816; b=OIB7z/9yebGr7QI/eUJBPuoq3QBbTgxMlkdu5aChlXMZPHT/y6MlR6hwpMlgNcGInv VlsvXS/EMDa1JwhJaJ0SqBrPHA+uSvfH/5OZ3iUKl3v0hOl/2kEmqbqhffIWpSGpPLTS MZe3yXaeSCbSgmXKCLNNv9RxPyC3yeopI3TP2BmY8ktCKy0ukXdxGNsS2Z/Ecp8JLyfj fVVFVOUHSMg5b2z2j2r3rCNg5DIC4ffY6JjGjNbvFYsoZLruoUHY1zabY+Xa8wQjhkBx 2j59B6Qv07Rt7TnFalPlyILhr1zs0zmKM1bkDQ6kK26tsgaysOkM34AUFykdpLZ9kjTi 5OGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=NodyPtFTeyWEqtACo59e0OsLQRfFpgaLAwpAkqdVh9c=; b=O4bB013M0fcZVP56QHpejCj9O7sCBEeQLQC2ouCD0JBz3V0qQY3oRw13xe9q+JUjoT r/usvtphlYg2P/5XgfQyULXa4EpI9GlDPfgVVAFmKBtHch7wOP2GRR71TJX4gn6n80Xi dkPH5nocswp+WwUYQ560DAGTxOID09RoQH1E7EZiwZwqGEhqDOLj4c7aeSkkxaF/UnpN +k8oL/bWpXXjQsCQF1c48Rpili3IOmkvqldPltzjxkweOLuhJrAE0jwdLijL27NSX2e8 foQ6pD8FOjwumNDdfc594m5RQEOOYFzIRO9KjG7ucRPsH0NHDOlmk5m5TETA6TbB03AA xivw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dKtzxHPs; spf=pass (google.com: best guess record for domain of linux-spi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-spi-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm3665503ljq.72.2018.09.03.14.50.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Sep 2018 14:50:51 -0700 (PDT) From: Linus Walleij To: Mark Brown , linux-spi@vger.kernel.org, Andrzej Hajda , Lorenzo Bianconi Cc: linux-gpio@vger.kernel.org, Rob Herring , Linus Walleij , devicetree@vger.kernel.org Subject: [PATCH 3/4] spi: Add a DT binding for high impedance turnaround Date: Mon, 3 Sep 2018 23:50:34 +0200 Message-Id: <20180903215035.17265-4-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180903215035.17265-1-linus.walleij@linaro.org> References: <20180903215035.17265-1-linus.walleij@linaro.org> Sender: linux-spi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Some 3WIRE SPI devices require the host to insert a "high impedance turnaround" essentially a clock pulse after switching the one line from output to input. This is needed to support the TPO TPG110 panel to use the 3WIRE SPI bindings. Cc: devicetree@vger.kernel.org Cc: Andrzej Hajda Cc: Lorenzo Bianconi Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/spi/spi-bus.txt | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt b/Documentation/devicetree/bindings/spi/spi-bus.txt index 1f6e86f787ef..ee08be2894eb 100644 --- a/Documentation/devicetree/bindings/spi/spi-bus.txt +++ b/Documentation/devicetree/bindings/spi/spi-bus.txt @@ -70,6 +70,10 @@ All slave nodes can contain the following optional properties: - spi-cs-high - Empty property indicating device requires chip select active high. - spi-3wire - Empty property indicating device requires 3-wire mode. +- spi-3wire-high-impedance-turnaround - Empty property indicating that a + 3wire host need to insert a high impedance turn-around + clock cycle after turning the one output line into an + input line. - spi-lsb-first - Empty property indicating device requires LSB first mode. - spi-tx-bus-width - The bus width (number of data wires) that is used for MOSI. Defaults to 1 if not present.