From patchwork Tue Jul 20 17:22:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Perier X-Patchwork-Id: 481700 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7D83C07E9B for ; Tue, 20 Jul 2021 17:24:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 858C261165 for ; Tue, 20 Jul 2021 17:24:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232284AbhGTQnY (ORCPT ); Tue, 20 Jul 2021 12:43:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232324AbhGTQmq (ORCPT ); Tue, 20 Jul 2021 12:42:46 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F750C0613E0; Tue, 20 Jul 2021 10:23:12 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id u1so26890990wrs.1; Tue, 20 Jul 2021 10:23:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zhLiMJZRNY6qUDk4IIbiRtvY/5CeP3owVFf8Rh0foos=; b=c7ZsQEReXTuJMEibJsFZnTOqVmK4iaqbAXocjphBZKhR4EIAWSr8lK1YMZtsLvOlFf 9EaJ2bRTt+9ZN56hL7nEyi1Xwse4BhfWzioHmeY7NE272x0c23LvSuhepcYRVP4v3/f5 T+MaRN5VHFzyyVhn2muBzl/FQCvLRGfHfH7CrezRhY+qGFFPxfteT4F+BplHVQ64VrCh YdLqoEK73t2pwye9yR7eNPFZB1mppp7zXDkfLUEvDlPYzNj+QS6XLg3EJxNOcSE9gsVv vsUZSIHPRE+gw6LUF7fhuZvfokWOu6OGkgbNosDtwtIiNsnFBCE7LIqqKCn+or5df1Ob dcaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zhLiMJZRNY6qUDk4IIbiRtvY/5CeP3owVFf8Rh0foos=; b=EhH+JYbiTBKGou23En6AQzHyaoVnIIdcKdOXbfovp99WpMXFtNDqvSEe/gs5LNeHaE /eDreybUL+9SkdLhe6KlDSWSM/HbEAtcpolVe5m5/LY8clS1d9QA/CPHKxCHg2ZEFqjG b99tfpnub5X2sfb1vW5PROtbKBeDnEHBnNkdHGNPz5ezAVIrLlFHw27Ah2snx2+X0GaP RW4VgLlZUJTrdgji+FB5fc6wR0RIH97iHRq0Aq/zJx1h4hXdIuonOdyRQ1Ka0QO+Kz5w fvP91jhHF66RDwFa91eLcFLlp9hwsg+h+FSLPBh2U62vktbN6pjxo6L4lhGvrj0o45Le 6dXw== X-Gm-Message-State: AOAM533dGqkBBeFkMKL0qPw1uCfuchctREdcYXtyfO+ms8S5C6SYbggQ RC5ZZG95tZ/pxEOCcCnys9zIJmY0Mxk= X-Google-Smtp-Source: ABdhPJwkskpxG+Uu6ZM1dtd9EQWOfgynMHFAOU3QVeTkNsxtOPoX2tS4zH7DbxsanYPBBRIK6gUVDQ== X-Received: by 2002:a05:6000:18ae:: with SMTP id b14mr36272495wri.427.1626801790789; Tue, 20 Jul 2021 10:23:10 -0700 (PDT) Received: from debby (176-141-241-253.abo.bbox.fr. [176.141.241.253]) by smtp.gmail.com with ESMTPSA id d29sm29755232wrb.63.2021.07.20.10.23.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jul 2021 10:23:10 -0700 (PDT) From: Romain Perier To: Alessandro Zummo , Alexandre Belloni , Daniel Palmer , Rob Herring Cc: linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/3] dt-bindings: rtc: Add Mstar MSC313e RTC devicetree bindings documentation Date: Tue, 20 Jul 2021 19:22:49 +0200 Message-Id: <20210720172251.4504-2-romain.perier@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210720172251.4504-1-romain.perier@gmail.com> References: <20210720172251.4504-1-romain.perier@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds the documentation for the devicetree bindings of the Mstar MSC313e RTC driver, found from MSC313e SoCs and newer. Signed-off-by: Romain Perier --- .../bindings/rtc/mstar,msc313-rtc.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/mstar,msc313-rtc.yaml diff --git a/Documentation/devicetree/bindings/rtc/mstar,msc313-rtc.yaml b/Documentation/devicetree/bindings/rtc/mstar,msc313-rtc.yaml new file mode 100644 index 000000000000..978c28bc3da5 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/mstar,msc313-rtc.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/mstar,msc313-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mstar MSC313e RTC Device Tree Bindings + +allOf: + - $ref: "rtc.yaml#" + +maintainers: + - Daniel Palmer + - Romain Perier + +properties: + compatible: + enum: + - mstar,msc313-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + rtc@2400 { + compatible = "mstar,msc313-rtc"; + reg = <0x2400 0x40>; + clocks = <&xtal_div2>; + interrupts-extended = <&intc_irq GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + }; +... From patchwork Tue Jul 20 17:22:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Perier X-Patchwork-Id: 483530 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC472C07E95 for ; Tue, 20 Jul 2021 17:23:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8FB0D60FED for ; Tue, 20 Jul 2021 17:23:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230037AbhGTQnH (ORCPT ); Tue, 20 Jul 2021 12:43:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54056 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231200AbhGTQms (ORCPT ); Tue, 20 Jul 2021 12:42:48 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9188C0613E1; Tue, 20 Jul 2021 10:23:13 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id i94so26836971wri.4; Tue, 20 Jul 2021 10:23:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0IkyZqRreuwE9J9yjlIIZcVDBYbaXsmqTw79COm7KlE=; b=RRX+dOq5/Ur/pr1XT+p6ErrbgTpQg7OD7axgzFBOw38e4CWDmgqu6Q2iNKBg05HYvD UvLRgHoCEs8UtR8gTgP2xZZ7Bad2q5m1u3MgFk1GGeHJcw06x/JKX1W1wQcfdqWWuAxr T4HNSjBrWN9luEkFkD6dJ1d/zH5ZnLsS0GrqwaMUeSUUsxmzyrrg9ckP7lTSjiUMRQzc 9ZYiGlJIUj+eEuLU+5npNR4xWdrqvqdHIbHVRzAhh/fNIvSr73q3/vE2jfMgVo00+Leg 9bNN3s8bo+ABHntOYj3JAudQwEOhuG7/RJPRw/zGnqwPcVSmg/QRStHOaivOeZxWK7cT aVsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0IkyZqRreuwE9J9yjlIIZcVDBYbaXsmqTw79COm7KlE=; b=VJq0XUNUb8zUSPwN7voPxMjoSA12iYJ8Nwnxf9k86oYdpO2PnaDBszq8J9RFcDS4PV hg59rEOHkoUjbnusC4HMtVwlBU3VTGOHe3dW1Gud1pdcxMP9H44VFDfaawvWUSdpuPc+ UzJtMW04S8OJfSvMjwj4Kd7VQ2cea/M3e/2eTxEyse60+nyCfzqbUOU5A5KSjzGcQD4c AdMVYnq1CJXxCpC/PJHIRHV7Mds30RhFWwxV5Pb8a/UmCcNUWGfFqZNltgX0FwuQXJEn +U2rEKhjzfbkB+AV39/vOj65SvpO/EBsfAgO4IBDItkPSg7zZ/hwN7DMByHvanmqQvpj PLvQ== X-Gm-Message-State: AOAM532Y9Oj+uvsy1Uj7zz4LjQ9pp2wylg+7q67bZUmMaF8X1TIu1K9m 2J32OQmklBkWK1sNiFtu1rs= X-Google-Smtp-Source: ABdhPJyNvW08DO9eHBqU7e87S6WJcaupk43dolDMfVRK8cPtc6KBrJ4m88EPUcJwRsnab84XdWteCw== X-Received: by 2002:a5d:4a85:: with SMTP id o5mr36917148wrq.410.1626801792229; Tue, 20 Jul 2021 10:23:12 -0700 (PDT) Received: from debby (176-141-241-253.abo.bbox.fr. [176.141.241.253]) by smtp.gmail.com with ESMTPSA id r67sm3025690wma.6.2021.07.20.10.23.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jul 2021 10:23:11 -0700 (PDT) From: Romain Perier To: Alessandro Zummo , Alexandre Belloni , Daniel Palmer , Rob Herring Cc: linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/3] rtc: Add support for the MSTAR MSC313 RTC Date: Tue, 20 Jul 2021 19:22:50 +0200 Message-Id: <20210720172251.4504-3-romain.perier@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210720172251.4504-1-romain.perier@gmail.com> References: <20210720172251.4504-1-romain.perier@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Daniel Palmer This adds support for the RTC block on the Mstar MSC313e SoCs and newer. Signed-off-by: Daniel Palmer Co-developed-by: Romain Perier Signed-off-by: Romain Perier --- MAINTAINERS | 1 + drivers/rtc/Kconfig | 10 ++ drivers/rtc/Makefile | 1 + drivers/rtc/rtc-msc313.c | 246 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 258 insertions(+) create mode 100644 drivers/rtc/rtc-msc313.c diff --git a/MAINTAINERS b/MAINTAINERS index 6c8be735cc91..7e8d1a375e0d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2220,6 +2220,7 @@ F: arch/arm/boot/dts/mstar-* F: arch/arm/mach-mstar/ F: drivers/clk/mstar/ F: drivers/gpio/gpio-msc313.c +F: drivers/rtc/rtc-msc313.c F: drivers/watchdog/msc313e_wdt.c F: include/dt-bindings/clock/mstar-* F: include/dt-bindings/gpio/msc313-gpio.h diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 12153d5801ce..67870b422bc5 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1925,4 +1925,14 @@ config RTC_DRV_WILCO_EC This can also be built as a module. If so, the module will be named "rtc_wilco_ec". +config RTC_DRV_MSC313 + tristate "MStar MSC313 RTC" + depends on ARCH_MSTARV7 + help + If you say yes here you get support for the Mstar MSC313e On-Chip + Real Time Clock. + + This driver can also be built as a module, if so, the module + will be called "rtc-msc313". + endif # RTC_CLASS diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 2dd0dd956b0e..5efda8a60cee 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -101,6 +101,7 @@ obj-$(CONFIG_RTC_DRV_MCP795) += rtc-mcp795.o obj-$(CONFIG_RTC_DRV_MESON) += rtc-meson.o obj-$(CONFIG_RTC_DRV_MOXART) += rtc-moxart.o obj-$(CONFIG_RTC_DRV_MPC5121) += rtc-mpc5121.o +obj-$(CONFIG_RTC_DRV_MSC313) += rtc-msc313.o obj-$(CONFIG_RTC_DRV_MSM6242) += rtc-msm6242.o obj-$(CONFIG_RTC_DRV_MT2712) += rtc-mt2712.o obj-$(CONFIG_RTC_DRV_MT6397) += rtc-mt6397.o diff --git a/drivers/rtc/rtc-msc313.c b/drivers/rtc/rtc-msc313.c new file mode 100644 index 000000000000..b1102e3c93ba --- /dev/null +++ b/drivers/rtc/rtc-msc313.c @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Real time clocks driver for MStar/SigmaStar ARMv7 SoCs. + * Based on "Real Time Clock driver for msb252x." that was contained + * in various MStar kernels. + * + * (C) 2019 Daniel Palmer + * (C) 2021 Romain Perier + */ + +#include +#include +#include +#include +#include +#include + +/* Registers */ +#define REG_RTC_CTRL 0x00 +#define REG_RTC_FREQ_CW_L 0x04 +#define REG_RTC_FREQ_CW_H 0x08 +#define REG_RTC_LOAD_VAL_L 0x0C +#define REG_RTC_LOAD_VAL_H 0x10 +#define REG_RTC_MATCH_VAL_L 0x14 +#define REG_RTC_MATCH_VAL_H 0x18 +#define REG_RTC_CNT_VAL_L 0x20 +#define REG_RTC_CNT_VAL_H 0x24 + +#define SOFT_RSTZ_BIT BIT(0) +#define CNT_EN_BIT BIT(1) +#define WRAP_EN_BIT BIT(2) +#define LOAD_EN_BIT BIT(3) +#define READ_EN_BIT BIT(4) +#define INT_MASK_BIT BIT(5) +#define INT_FORCE_BIT BIT(6) +#define INT_CLEAR_BIT BIT(7) + +struct msc313_rtc { + struct rtc_device *rtc_dev; + void __iomem *rtc_base; + struct clk *clk; +}; + +static int msc313_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) +{ + struct msc313_rtc *priv = dev_get_drvdata(dev); + unsigned long seconds; + + seconds = readw(priv->rtc_base + REG_RTC_MATCH_VAL_L) + | (readw(priv->rtc_base + REG_RTC_MATCH_VAL_H) << 16); + + rtc_time64_to_tm(seconds, &alarm->time); + + if (!(readw(priv->rtc_base + REG_RTC_CTRL) & INT_MASK_BIT)) + alarm->enabled = 1; + + return 0; +} + +static int msc313_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) +{ + struct msc313_rtc *priv = dev_get_drvdata(dev); + u16 reg; + + reg = readw(priv->rtc_base + REG_RTC_CTRL); + if (enabled) + reg &= ~INT_MASK_BIT; + else + reg |= INT_MASK_BIT; + writew(reg, priv->rtc_base + REG_RTC_CTRL); + return 0; +} + +static int msc313_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) +{ + struct msc313_rtc *priv = dev_get_drvdata(dev); + unsigned long seconds; + + seconds = rtc_tm_to_time64(&alarm->time); + writew((seconds & 0xFFFF), priv->rtc_base + REG_RTC_MATCH_VAL_L); + writew((seconds >> 16) & 0xFFFF, priv->rtc_base + REG_RTC_MATCH_VAL_H); + + msc313_rtc_alarm_irq_enable(dev, alarm->enabled); + + return 0; +} + +static int msc313_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct msc313_rtc *priv = dev_get_drvdata(dev); + u32 seconds; + u16 reg; + + reg = readw(priv->rtc_base + REG_RTC_CTRL); + writew(reg | READ_EN_BIT, priv->rtc_base + REG_RTC_CTRL); + + /* Wait for HW latch done */ + while (readw(priv->rtc_base + REG_RTC_CTRL) & READ_EN_BIT) + udelay(1); + + seconds = readw(priv->rtc_base + REG_RTC_CNT_VAL_L) + | (readw(priv->rtc_base + REG_RTC_CNT_VAL_H) << 16); + + rtc_time64_to_tm(seconds, tm); + + return rtc_valid_tm(tm); +} + +static int msc313_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct msc313_rtc *priv = dev_get_drvdata(dev); + unsigned long seconds; + u16 reg; + + seconds = rtc_tm_to_time64(tm); + writew(seconds & 0xFFFF, priv->rtc_base + REG_RTC_LOAD_VAL_L); + writew((seconds >> 16) & 0xFFFF, priv->rtc_base + REG_RTC_LOAD_VAL_H); + reg = readw(priv->rtc_base + REG_RTC_CTRL); + writew(reg | LOAD_EN_BIT, priv->rtc_base + REG_RTC_CTRL); + + /* need to check carefully if we want to clear REG_RTC_LOAD_VAL_H for customer*/ + while (readw(priv->rtc_base + REG_RTC_CTRL) & LOAD_EN_BIT) + udelay(1); + writew(0, priv->rtc_base + REG_RTC_LOAD_VAL_H); + + return 0; +} + +static const struct rtc_class_ops msc313_rtc_ops = { + .read_time = msc313_rtc_read_time, + .set_time = msc313_rtc_set_time, + .read_alarm = msc313_rtc_read_alarm, + .set_alarm = msc313_rtc_set_alarm, + .alarm_irq_enable = msc313_rtc_alarm_irq_enable, +}; + +static irqreturn_t msc313_rtc_interrupt(s32 irq, void *dev_id) +{ + struct msc313_rtc *priv = dev_get_drvdata(dev_id); + u16 reg; + + reg = readw_relaxed(priv->rtc_base + REG_RTC_CTRL); + reg |= INT_CLEAR_BIT; + reg &= ~INT_FORCE_BIT; + writew_relaxed(reg, priv->rtc_base + REG_RTC_CTRL); + + rtc_update_irq(priv->rtc_dev, 1, RTC_IRQF | RTC_AF); + + return IRQ_HANDLED; +} + +static int msc313_rtc_remove(struct platform_device *pdev) +{ + struct msc313_rtc *priv = platform_get_drvdata(pdev); + + clk_disable_unprepare(priv->clk); + + return 0; +} + +static int msc313_rtc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct msc313_rtc *priv; + int ret; + int irq; + unsigned long rate; + u16 reg; + + priv = devm_kzalloc(&pdev->dev, sizeof(struct msc313_rtc), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->rtc_base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->rtc_base)) + return PTR_ERR(priv->rtc_base); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return -EINVAL; + + ret = devm_request_irq(dev, irq, msc313_rtc_interrupt, IRQF_SHARED, + dev_name(&pdev->dev), &pdev->dev); + if (ret) { + dev_err(dev, "Unable to request irq\n"); + return ret; + } + + priv->clk = devm_clk_get(dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(dev, "No input reference clock\n"); + return PTR_ERR(priv->clk); + } + + ret = clk_prepare_enable(priv->clk); + if (ret) { + dev_err(dev, "Failed to enable the reference clock, %d\n", ret); + return ret; + } + + rate = clk_get_rate(priv->clk); + + reg = readw(priv->rtc_base + REG_RTC_CTRL); + if (!(reg & SOFT_RSTZ_BIT)) { + reg |= SOFT_RSTZ_BIT; + writew(reg, priv->rtc_base + REG_RTC_CTRL); + } + + writew(rate & 0xFFFF, priv->rtc_base + REG_RTC_FREQ_CW_L); + writew((rate >> 16) & 0xFFFF, priv->rtc_base + REG_RTC_FREQ_CW_H); + + reg |= CNT_EN_BIT; + writew(reg, priv->rtc_base + REG_RTC_CTRL); + + platform_set_drvdata(pdev, priv); + + priv->rtc_dev = devm_rtc_device_register(dev, dev_name(dev), &msc313_rtc_ops, THIS_MODULE); + if (IS_ERR(priv->rtc_dev)) { + dev_err(dev, "Failed to register rtc device\n"); + return PTR_ERR(priv->rtc_dev); + } + + return 0; +} + +static const struct of_device_id msc313_rtc_of_match_table[] = { + { .compatible = "mstar,msc313-rtc" }, + { } +}; +MODULE_DEVICE_TABLE(of, ms_rtc_of_match_table); + +static struct platform_driver msc313_rtc_driver = { + .remove = msc313_rtc_remove, + .probe = msc313_rtc_probe, + .driver = { + .name = "msc313-rtc", + .of_match_table = msc313_rtc_of_match_table, + }, +}; + +module_platform_driver(msc313_rtc_driver); + +MODULE_AUTHOR("Daniel Palmer "); +MODULE_AUTHOR("Romain Perier "); +MODULE_DESCRIPTION("MStar RTC Driver"); +MODULE_LICENSE("GPL v2"); From patchwork Tue Jul 20 17:22:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Romain Perier X-Patchwork-Id: 481701 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D9F5C07E9B for ; Tue, 20 Jul 2021 17:24:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 201F961106 for ; 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[176.141.241.253]) by smtp.gmail.com with ESMTPSA id a7sm13899964wru.67.2021.07.20.10.23.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jul 2021 10:23:13 -0700 (PDT) From: Romain Perier To: Alessandro Zummo , Alexandre Belloni , Daniel Palmer , Rob Herring Cc: linux-rtc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/3] ARM: dts: mstar: Add rtc device node Date: Tue, 20 Jul 2021 19:22:51 +0200 Message-Id: <20210720172251.4504-4-romain.perier@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210720172251.4504-1-romain.perier@gmail.com> References: <20210720172251.4504-1-romain.perier@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds the definition of the rtc device node. The RTC being able to work with the oscillator at 12Mhz for now, it shares the same xtal than the watchdog. Signed-off-by: Romain Perier --- arch/arm/boot/dts/mstar-v7.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 982dba9d28eb..1d4419aee67d 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -116,6 +116,13 @@ watchdog@6000 { clocks = <&xtal_div2>; }; + rtc@2400 { + compatible = "mstar,msc313-rtc"; + reg = <0x2400 0x40>; + clocks = <&xtal_div2>; + interrupts-extended = <&intc_irq GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + }; + intc_fiq: interrupt-controller@201310 { compatible = "mstar,mst-intc"; reg = <0x201310 0x40>;