From patchwork Tue Jul 20 08:09:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 483548 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5FF9C07E95 for ; Tue, 20 Jul 2021 08:10:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 887FE611C1 for ; Tue, 20 Jul 2021 08:10:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233890AbhGTHaB (ORCPT ); Tue, 20 Jul 2021 03:30:01 -0400 Received: from mail.kernel.org ([198.145.29.99]:49268 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233304AbhGTH2r (ORCPT ); Tue, 20 Jul 2021 03:28:47 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 8C5766120C; Tue, 20 Jul 2021 08:09:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1626768559; bh=JQBY01HlySg61KGcooyIwhgyIlhQj6EZr5kggVNvmjA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jdHUJJSQ9sU889uO4Igp4v41iWFN2sUuD72j+vsTYGwimETafguk5wZrK2EMnhL7f 2UYb520wEouChfss0CbdVkdEHP2byc2qHnwO2TBQhvmh6DsykKFUcziqK3wG/Y3IiM rePCS9JI1KQCHz3x/EIN55htSMgSHO2kEL9y64jaFpzqqTIavpM5NbuCOACkT0xZy4 idsDJpG4oSG+K+IydlNIN8faR7frl24dcLXzKn3yYHyBZ0YK/MoXPiM8X+QzngtySh WYc2XqJQeQyjfCEwk9E1m++lWJe9H6IhcRV70o+eJlwKjtyS7smfwlznVlOlQ3q0RM sSpHrftnL+pag== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1m5koX-000eTN-Jk; Tue, 20 Jul 2021 10:09:17 +0200 From: Mauro Carvalho Chehab To: Bjorn Helgaas , Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , Bjorn Helgaas , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v6 4/9] dt-bindings: PCI: kirin: Fix compatible string Date: Tue, 20 Jul 2021 10:09:06 +0200 Message-Id: <5e5b6d276b0b155cdee8d6c7866ca2db23c5a7c6.1626768323.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The pcie-kirin driver doesn't declare a hisilicon,kirin-pcie. Also, remove the useless comment after the description, as other compat will be supported by the same driver in the future. Acked-by: Rob Herring Signed-off-by: Mauro Carvalho Chehab --- Documentation/devicetree/bindings/pci/kirin-pcie.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt index 7db30534498f..7adab8999a6a 100644 --- a/Documentation/devicetree/bindings/pci/kirin-pcie.txt +++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt @@ -9,7 +9,7 @@ Additional properties are described here: Required properties - compatible: - "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC + "hisilicon,kirin960-pcie" - reg: Should contain rc_dbi, apb, phy, config registers location and length. - reg-names: Must include the following entries: "dbi": controller configuration registers; @@ -23,7 +23,7 @@ Optional properties: Example based on kirin960: pcie@f4000000 { - compatible = "hisilicon,kirin-pcie"; + compatible = "hisilicon,kirin960-pcie"; reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>; reg-names = "dbi","apb","phy", "config"; From patchwork Tue Jul 20 08:09:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 483549 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8574AC636C8 for ; Tue, 20 Jul 2021 08:10:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6C68A611ED for ; Tue, 20 Jul 2021 08:10:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232332AbhGTH3y (ORCPT ); Tue, 20 Jul 2021 03:29:54 -0400 Received: from mail.kernel.org ([198.145.29.99]:49058 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233097AbhGTH2l (ORCPT ); Tue, 20 Jul 2021 03:28:41 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 73681611ED; Tue, 20 Jul 2021 08:09:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1626768559; bh=69owpJSeKLLbkKV1UESYM8I5uYDlltnRXTuUGkqjmK8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZmeraAygguXGQpxcwp72aIVVCk5NtCeP+IXsDnyPV28hyH+fVBVASHqM0knnH/8Hh EEzTZ5QgTt2Co85dm78hXqQZWiJnS+9X5pigfywnqtl9Ejex4yAp/EEL0TrQLTb8VS pwpVDWwwCX/2dFKiCny0bdbV2lkIDhdWvrs4hfocj9I07sCSo4PQTnkHdCLRcXJfTx my/78SylQrGlb2XNneOWTTqo0h6qDv9OTjP3xRYnZ7GEfboaq0ISzjoKZjctt2qHWK qVDFn0sMPqwa2LKmsvH0KRB5tQDyU5M7SHvpO9Vwj3TWe0gfRmer7FJU3ONGP8TV5a iu0OIjUqL/Chw== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1m5koX-000eTR-L3; Tue, 20 Jul 2021 10:09:17 +0200 From: Mauro Carvalho Chehab To: Bjorn Helgaas , Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , Kishon Vijay Abraham I , Rob Herring , Vinod Koul , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v6 5/9] dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY Date: Tue, 20 Jul 2021 10:09:07 +0200 Message-Id: <04943d3dff73e2fd5c9336540cb31d70ccf7b9cf.1626768323.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the bindings for HiKey 970 (hi3670) PCIe PHY interface, supported via the pcie-kirin driver. Signed-off-by: Mauro Carvalho Chehab --- .../phy/hisilicon,phy-hi3670-pcie.yaml | 98 +++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml diff --git a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml new file mode 100644 index 000000000000..f88b6b7496bb --- /dev/null +++ b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Kirin970 PCIe PHY + +maintainers: + - Mauro Carvalho Chehab + +description: |+ + Bindings for PCIe PHY on HiSilicon Kirin 970. + +properties: + compatible: + const: hisilicon,hi970-pcie-phy + + "#phy-cells": + const: 0 + + reg: + maxItems: 1 + description: PHY Control registers + + phy-supply: + description: The PCIe PHY power supply + + clocks: + items: + - description: PCIe PHY clock + - description: PCIe AUX clock + - description: PCIe APB PHY clock + - description: PCIe APB SYS clock + - description: PCIe ACLK clock + + clock-names: + items: + - const: phy_ref + - const: aux + - const: apb_phy + - const: apb_sys + - const: aclk + + reset-gpios: + description: PCI PERST reset GPIOs + maxItems: 4 + + clkreq-gpios: + description: Clock request GPIOs + maxItems: 3 + + hisilicon,eye-diagram-param: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Eye diagram for phy. + +required: + - "#phy-cells" + - compatible + - reg + - reg-names + - clocks + - clock-names + - reset-gpios + - clkreq-gpios + - hisilicon,eye-diagram-param + - phy-supply + +additionalProperties: false + +examples: + - | + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + pcie_phy: pcie-phy@fc000000 { + compatible = "hisilicon,hi970-pcie-phy"; + reg = <0x0 0xfc000000 0x0 0x80000>; + reg-names = "phy"; + #phy-cells = <0>; + phy-supply = <&ldo33>; + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + clock-names = "phy_ref", "aux", + "apb_phy", "apb_sys", "aclk"; + reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, + <&gpio3 1 0 >, <&gpio27 4 0 >; + clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >, <&gpio17 0 0 >; + hisilicon,eye-diagram-param = <0xFFFFFFFF 0xFFFFFFFF + 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF>; + }; + }; +... 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[23.128.96.18]) by mx.google.com with ESMTP id x13si18600945edq.603.2021.07.20.01.11.15; Tue, 20 Jul 2021 01:11:15 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=cskzJO8W; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232460AbhGTH34 (ORCPT + 7 others); Tue, 20 Jul 2021 03:29:56 -0400 Received: from mail.kernel.org ([198.145.29.99]:49072 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233139AbhGTH2l (ORCPT ); Tue, 20 Jul 2021 03:28:41 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 7DE61611EF; Tue, 20 Jul 2021 08:09:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1626768559; bh=hFWGGPOo8IffrLf2mAyywYfMVp92Yc9SBhf1dfFMTcw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cskzJO8Wsov2c4ra3deXGnRxhUJ99gXPfQ9TR9REzInKuig+awftl8pwt6MVRn2r9 7TDNmOxeoOVR9s6c2giHXTdo05wVQr5puhSprwM8XG0vjl0IZc0Uru/8G3u5kJKL9v YJQeFvKAqbhwk9ON6jHDsdEMZSKcs+62Euuud+Q1ZhtwLi8Y371XSbW04nQbdPmORD FnFCf6D+4W8xt1HGmndiJWX82JiRlPSRtxaSNHxBLKNT2906gcr2LqPsoWflzFQQgS /Pa9dOIBPyg+mRidgpOimmY13JiUS1xGwxQDOGyr99dSfn1vNIzW1fG2Mi4S+oVFCJ RH5v2bUeJAA3Q== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1m5koX-000eTZ-Ou; Tue, 20 Jul 2021 10:09:17 +0200 From: Mauro Carvalho Chehab To: Bjorn Helgaas , Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Manivannan Sadhasivam , =?utf-8?q?Krzysztof_Wilczy=C5=84s?= =?utf-8?q?ki?= , Binghui Wang , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Wei Xu , Xiaowei Song , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Mauro Carvalho Chehab Subject: [PATCH v6 7/9] arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller hardware Date: Tue, 20 Jul 2021 10:09:09 +0200 Message-Id: <7ede6693e5cc2bbd23c1a68cbc571b5f4876917d.1626768323.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Manivannan Sadhasivam Add DTS bindings for the HiKey 970 board's PCIe hardware. Co-developed-by: Mauro Carvalho Chehab Signed-off-by: Manivannan Sadhasivam Signed-off-by: Mauro Carvalho Chehab --- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 71 +++++++++++++++++++ .../boot/dts/hisilicon/hikey970-pmic.dtsi | 1 - drivers/pci/controller/dwc/pcie-kirin.c | 12 ---- 3 files changed, 71 insertions(+), 13 deletions(-) -- 2.31.1 diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 1f228612192c..6dfcfcfeedae 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -177,6 +177,12 @@ sctrl: sctrl@fff0a000 { #clock-cells = <1>; }; + pmctrl: pmctrl@fff31000 { + compatible = "hisilicon,hi3670-pmctrl", "syscon"; + reg = <0x0 0xfff31000 0x0 0x1000>; + #clock-cells = <1>; + }; + iomcu: iomcu@ffd7e000 { compatible = "hisilicon,hi3670-iomcu", "syscon"; reg = <0x0 0xffd7e000 0x0 0x1000>; @@ -660,6 +666,71 @@ gpio28: gpio@fff1d000 { clock-names = "apb_pclk"; }; + its_pcie: interrupt-controller@f4000000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0xf5100000 0x0 0x100000>; + }; + + pcie_phy: pcie-phy@fc000000 { + compatible = "hisilicon,hi970-pcie-phy"; + reg = <0x0 0xfc000000 0x0 0x80000>; + + phy-supply = <&ldo33>; + + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, + <&crg_ctrl HI3670_ACLK_GATE_PCIE>; + clock-names = "phy_ref", "aux", + "apb_phy", "apb_sys", + "aclk"; + + reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, + <&gpio3 1 0 >, <&gpio27 4 0 >; + + clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >, + <&gpio17 0 0 >; + + /* vboost iboost pre post main */ + hisilicon,eye-diagram-param = <0xFFFFFFFF 0xFFFFFFFF + 0xFFFFFFFF 0xFFFFFFFF + 0xFFFFFFFF>; + + #phy-cells = <0>; + }; + + pcie@f4000000 { + compatible = "hisilicon,kirin970-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000000>, + <0x0 0xfc180000 0x0 0x1000>, + <0x0 0xf5000000 0x0 0x2000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x0 0x1>; + msi-parent = <&its_pcie>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + phys = <&pcie_phy>; + ranges = <0x02000000 0x0 0x00000000 + 0x0 0xf6000000 + 0x0 0x02000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupts = <0 283 4>; + interrupt-names = "msi"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0x0 0 0 1 + &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 + &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 + &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 + &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + }; + /* UFS */ ufs: ufs@ff3c0000 { compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1"; diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi index 48c739eacba0..03452e627641 100644 --- a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi @@ -73,7 +73,6 @@ ldo33: LDO33 { /* PEX8606 */ regulator-name = "ldo33"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <3300000>; - regulator-boot-on; }; ldo34: LDO34 { /* GPS AUX IN VDD */ diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index 7a92f633d746..4657a6d33f6f 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -347,18 +347,6 @@ static const struct regmap_config pcie_kirin_regmap_conf = { .reg_stride = 4, }; -/* Registers in PCIeCTRL */ -static inline void kirin_apb_ctrl_writel(struct kirin_pcie *kirin_pcie, - u32 val, u32 reg) -{ - writel(val, kirin_pcie->apb_base + reg); -} - -static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie, u32 reg) -{ - return readl(kirin_pcie->apb_base + reg); -} - static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie, struct platform_device *pdev) { From patchwork Tue Jul 20 08:09:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 481722 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7257CC636C8 for ; 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Tue, 20 Jul 2021 10:09:17 +0200 From: Mauro Carvalho Chehab To: Bjorn Helgaas , Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , Binghui Wang , Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Rob Herring , Xiaowei Song , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v6 8/9] dt-bindings: PCI: kirin-pcie.txt: Convert it to yaml Date: Tue, 20 Jul 2021 10:09:10 +0200 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the file into a JSON description at the yaml format. Signed-off-by: Mauro Carvalho Chehab --- .../bindings/pci/hisilicon,kirin-pcie.yaml | 87 +++++++++++++++++++ .../devicetree/bindings/pci/kirin-pcie.txt | 50 ----------- .../devicetree/bindings/pci/snps,dw-pcie.yaml | 2 +- MAINTAINERS | 2 +- 4 files changed, 89 insertions(+), 52 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml delete mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt diff --git a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml new file mode 100644 index 000000000000..eabc651c9766 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: HiSilicon Kirin SoCs PCIe host DT description + +maintainers: + - Xiaowei Song + - Binghui Wang + +description: | + Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. + It shares common functions with the PCIe DesignWare core driver and + inherits common properties defined in + Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + contains: + enum: + - hisilicon,kirin960-pcie + - hisilicon,kirin970-pcie + + reg: + description: | + Should contain rc_dbi, apb, config registers location and length. + minItems: 3 + maxItems: 4 + + reg-names: + items: + - const: dbi # controller configuration registers + - const: apb # apb Ctrl register defined by Kirin + - const: config # PCIe configuration space registers + - const: phy # apb PHY register used on Kirin 960 PHY + minItems: 3 + maxItems: 4 + + reset-gpios: + description: The GPIO(s) to generate PCIe PERST# assert and deassert signal. + minItems: 1 + maxItems: 4 + +required: + - compatible + - reg + - reg-names + +unevaluatedProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie: pcie@f4000000 { + compatible = "hisilicon,kirin970-pcie"; + reg = <0x0 0xf4000000 0x0 0x1000>, + <0x0 0xff3fe000 0x0 0x1000>, + <0x0 0xf4000000 0 0x2000>; + reg-names = "dbi", "apb", "config"; + bus-range = <0x0 0x1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; + num-lanes = <1>; + #interrupt-cells = <1>; + interrupts = <0 283 4>; + interrupt-names = "msi"; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, + <&gpio3 1 0 >, <&gpio27 4 0 >; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt deleted file mode 100644 index 7adab8999a6a..000000000000 --- a/Documentation/devicetree/bindings/pci/kirin-pcie.txt +++ /dev/null @@ -1,50 +0,0 @@ -HiSilicon Kirin SoCs PCIe host DT description - -Kirin PCIe host controller is based on the Synopsys DesignWare PCI core. -It shares common functions with the PCIe DesignWare core driver and -inherits common properties defined in -Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. - -Additional properties are described here: - -Required properties -- compatible: - "hisilicon,kirin960-pcie" -- reg: Should contain rc_dbi, apb, phy, config registers location and length. -- reg-names: Must include the following entries: - "dbi": controller configuration registers; - "apb": apb Ctrl register defined by Kirin; - "phy": apb PHY register defined by Kirin; - "config": PCIe configuration space registers. -- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. - -Optional properties: - -Example based on kirin960: - - pcie@f4000000 { - compatible = "hisilicon,kirin960-pcie"; - reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, - <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>; - reg-names = "dbi","apb","phy", "config"; - bus-range = <0x0 0x1>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>; - num-lanes = <1>; - #interrupt-cells = <1>; - interrupt-map-mask = <0xf800 0 0 7>; - interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>, - <0x0 0 0 2 &gic 0 0 0 283 4>, - <0x0 0 0 3 &gic 0 0 0 284 4>, - <0x0 0 0 4 &gic 0 0 0 285 4>; - clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, - <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, - <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, - <&crg_ctrl HI3660_ACLK_GATE_PCIE>; - clock-names = "pcie_phy_ref", "pcie_aux", - "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; - reset-gpios = <&gpio11 1 0 >; - }; diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml index a8c1db879fb9..d80894a5abf5 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml @@ -34,7 +34,7 @@ properties: minItems: 2 maxItems: 5 items: - enum: [dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link] + enum: [dbi, dbi2, config, atu, apb, app, elbi, mgmt, ctrl, parf, cfg, link] num-lanes: description: | diff --git a/MAINTAINERS b/MAINTAINERS index b54bd9dd07ec..d5f53b2d3f9c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14420,7 +14420,7 @@ M: Xiaowei Song M: Binghui Wang L: linux-pci@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/pci/kirin-pcie.txt +F: Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml F: drivers/pci/controller/dwc/pcie-kirin.c PCIE DRIVER FOR HISILICON STB From patchwork Tue Jul 20 08:09:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 481721 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-25.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 777B0C07E9B for ; Tue, 20 Jul 2021 08:10:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6162E611ED for ; Tue, 20 Jul 2021 08:10:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231305AbhGTHaE (ORCPT ); Tue, 20 Jul 2021 03:30:04 -0400 Received: from mail.kernel.org ([198.145.29.99]:49266 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233320AbhGTH2r (ORCPT ); Tue, 20 Jul 2021 03:28:47 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 8E1296120D; Tue, 20 Jul 2021 08:09:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1626768559; bh=Xude9cwci3VpqzmecTiQj1FEp3C3XgXWTqdJsqWC8u4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EDw8M4Dow7htjwcfh13nNwkd5p0ECDSfU+jaYepYUqsSghERSH1C492/l8DHX5vqe 6dKADV4PdZL0y5+2txYgdTohJZG+qZh4+NLKBMWhoGdD1661+tdxlk5hq6CTndw+bx v3l1J+MUf2TXFG73R9NqiEzJqwXS1wTWixhx8lVF3SvwHHJnmMZ6jC2vLLMvq17k9m FxysrU0j03D+cPoH62eo3urAa/yMwHO/J8wBYNx3dYjqe/CeIA/M9mCI9mZSR8YpFL Ivvt7NLQG9K9CUEUI6BbGRcPoU4hWxyeUD86SuOaPi8bmZ2eCP4O3RjIIBx3GDVm2x XC1HezMf44pCQ== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1m5koX-000eTh-SC; Tue, 20 Jul 2021 10:09:17 +0200 From: Mauro Carvalho Chehab To: Bjorn Helgaas , Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , Kishon Vijay Abraham I , Manivannan Sadhasivam , Rob Herring , Vinod Koul , Wei Xu , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v6 9/9] phy-hi3670-pcie: move reset-gpios to the PCIe DT schema Date: Tue, 20 Jul 2021 10:09:11 +0200 Message-Id: X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The PHY interface as found on HiKey 970 uses 4 reset-gpios instead of just one. That seems to be due to electrical requirements, as, on HiKey 970, the PERST# signal is provided via one GPIO per connected/available PCIe device: - GPIO 56 has a pullup logic from 1V8 to 2V5 connected to a PCIe bridge chip (PEX 8606); - GPIO 25 has a pullup logic from 1V8 to 3V3 connected to the PERST# pin at the M.2 slot; - GPIO 220 has a pullup logic from 1V8 to 3V3 connected to the PERST# pin at the PCIe mini slot; - GPIO 203 has a pullup logic from 1V8 to 3V3 connected to the PERST# pin at the Ethernet chipset. Originally, this was mapped via the PHY interface, but, as such design may also be used with different hardware, remap this to use the pcie-bus DT schema. This patch depends on a DT schema patch submitted at: https://github.com/devicetree-org/dt-schema/pull/56 Signed-off-by: Mauro Carvalho Chehab --- .../phy/hisilicon,phy-hi3670-pcie.yaml | 4 -- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 5 +- drivers/phy/hisilicon/phy-hi3670-pcie.c | 54 ++++++++++--------- 3 files changed, 31 insertions(+), 32 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml index f88b6b7496bb..112a982ee258 100644 --- a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml +++ b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml @@ -42,10 +42,6 @@ properties: - const: apb_sys - const: aclk - reset-gpios: - description: PCI PERST reset GPIOs - maxItems: 4 - clkreq-gpios: description: Clock request GPIOs maxItems: 3 diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 6dfcfcfeedae..a07790c76b72 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -687,9 +687,6 @@ pcie_phy: pcie-phy@fc000000 { "apb_phy", "apb_sys", "aclk"; - reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, - <&gpio3 1 0 >, <&gpio27 4 0 >; - clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >, <&gpio17 0 0 >; @@ -729,6 +726,8 @@ &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >, + <&gpio3 1 0 >, <&gpio27 4 0 >; }; /* UFS */ diff --git a/drivers/phy/hisilicon/phy-hi3670-pcie.c b/drivers/phy/hisilicon/phy-hi3670-pcie.c index e80143df0217..77bf5bb07ba2 100644 --- a/drivers/phy/hisilicon/phy-hi3670-pcie.c +++ b/drivers/phy/hisilicon/phy-hi3670-pcie.c @@ -553,11 +553,13 @@ static int hi3670_pcie_noc_power(struct hi3670_pcie_phy *phy, bool enable) return 0; } -static int hi3670_pcie_get_apb(struct hi3670_pcie_phy *phy) +static int hi3670_pcie_get_resources_from_pcie(struct hi3670_pcie_phy *phy) { struct device_node *pcie_port; struct device *dev = phy->dev; struct device *pcie_dev; + char name[32]; + int i; pcie_port = of_get_child_by_name(dev->parent->of_node, "pcie"); if (!pcie_port) { @@ -586,6 +588,27 @@ static int hi3670_pcie_get_apb(struct hi3670_pcie_phy *phy) return -ENODEV; } + /* perst reset gpios */ + phy->n_gpio_resets = of_gpio_named_count(pcie_dev->of_node, + "reset-gpios"); + if (phy->n_gpio_resets > MAX_GPIO_RESETS) { + dev_err(dev, "Too many GPIO resets!\n"); + return -EINVAL; + } + for (i = 0; i < phy->n_gpio_resets; i++) { + phy->gpio_id_reset[i] = of_get_named_gpio(pcie_dev->of_node, + "reset-gpios", i); + if (phy->gpio_id_reset[i] < 0) + return phy->gpio_id_reset[i]; + + sprintf(name, "pcie_perst_%d", i); + + phy->reset_names[i] = devm_kstrdup_const(dev, name, + GFP_KERNEL); + if (!phy->reset_names[i]) + return -ENOMEM; + } + return 0; } @@ -644,16 +667,17 @@ static int hi3670_pcie_phy_init(struct phy *generic_phy) int ret; /* - * The code under hi3670_pcie_get_apb() need to access the - * DWC APB registers. So, get them from - * the pcie driver's regmap (see pcie-kirin regmap). + * The code under hi3670_pcie_get_resources_from_pcie() need to + * access the reset-gpios and the APB registers, both from the + * pcie-kirin driver. * + * The APB is obtained via the pcie driver's regmap * Such kind of resource can only be obtained during the PCIe * power_on sequence, as the code inside pcie-kirin needs to * be already probed, as it needs to register the APB regmap. */ - ret = hi3670_pcie_get_apb(phy); + ret = hi3670_pcie_get_resources_from_pcie(phy); if (ret) return ret; @@ -800,26 +824,6 @@ static int hi3670_pcie_phy_get_resources(struct hi3670_pcie_phy *phy, if (IS_ERR(phy->base)) return PTR_ERR(phy->base); - /* perst reset gpios */ - phy->n_gpio_resets = of_gpio_named_count(np, "reset-gpios"); - if (phy->n_gpio_resets > MAX_GPIO_RESETS) { - dev_err(dev, "Too many GPIO resets!\n"); - return -EINVAL; - } - for (i = 0; i < phy->n_gpio_resets; i++) { - phy->gpio_id_reset[i] = of_get_named_gpio(dev->of_node, - "reset-gpios", i); - if (phy->gpio_id_reset[i] < 0) - return phy->gpio_id_reset[i]; - - sprintf(name, "pcie_perst_%d", i); - - phy->reset_names[i] = devm_kstrdup_const(dev, name, - GFP_KERNEL); - if (!phy->reset_names[i]) - return -ENOMEM; - } - /* clock request gpios */ phy->n_gpio_clkreq = of_gpio_named_count(np, "clkreq-gpios"); if (phy->n_gpio_clkreq > MAX_GPIO_CLKREQ) {