From patchwork Tue Jul 20 06:38:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ChiaWei Wang X-Patchwork-Id: 481491 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp4837614jao; Mon, 19 Jul 2021 23:39:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwWIBQNYmecG906CHPCv5TZui1tUqLw0Qz6tjBt+mV7X9XUQA4k6ZdqwRg2sqIk3iprwKcV X-Received: by 2002:a05:6402:1acf:: with SMTP id ba15mr38200269edb.167.1626763159604; Mon, 19 Jul 2021 23:39:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626763159; cv=none; d=google.com; s=arc-20160816; b=sD0Q60ovDOWQikjhEOKotEgc49EnJcCfnOj+q1qbqPo2KvCslMEA9g6ThU5XGd7Hy0 doQbPr7JrlN6Z4RYiWcpUG8zikka6zME6ytU0emELbG1Yfc8jRYi9/gsA0XDyCorS7vq vDmLveghqOU0WPhYkFismN4Mh2/oq20V3zggaowh6lXIz84kLiWiiTp2t9kXo2zRADEL luFVwOlik0tOHreGKTEIRw65hJtnE/h4ap4/+GgwaKNqzd7jd8uNkGPgtqASPiFmtEJC C2s9YaiF6oMC7uK+JSXP++OWAC1hFBzXZxYpluthnaB+HB5KNREhBm766VioYsZDIFQV md4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from; bh=WIzbJ1F4j4niM9YHvIakuiMIjGj9mROphRB55ASHg5U=; b=wcWX6sCbN07ifTWdjq8MDJyv8Fdqqi649kqcomQyoiWk+zQBz1KKKgBOt0Qz5DhDK6 h3kzWYrVqc110lySgOrgEH7oLRE2NioCj6AXXlJ/WjeFSvMkZiFmbGL5aclXkfmMHnqU XLBicwSVfwbC34aeDQlOe+o3V9JU4yQplk6goYYSgd5hx0YAt07bLa7B2hoDhUQnjT4K zLV6RTTpP9Sn098bMBtYB1qFNSDcoQorOatZPIfRApUmG0SwsIBn26CdJdf4E5vRl+it y1yZ2KJItKcl27XrzMhLNxGv3RoRrUqGAFmRh9BywXICIGyYuWHAXvqzNc0LqqdxahHu IY7w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id i18si23875310edr.261.2021.07.19.23.39.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 23:39:19 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2CF0E82C45; Tue, 20 Jul 2021 08:39:16 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=aspeedtech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id E419982C30; Tue, 20 Jul 2021 08:39:05 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A8D92829E4 for ; Tue, 20 Jul 2021 08:38:55 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=aspeedtech.com Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=chiawei_wang@aspeedtech.com Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 16K6M6Nd039584; Tue, 20 Jul 2021 14:22:06 +0800 (GMT-8) (envelope-from chiawei_wang@aspeedtech.com) Received: from ChiaWeiWang-PC.aspeed.com (192.168.2.66) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 20 Jul 2021 14:38:31 +0800 From: Chia-Wei Wang To: , , , CC: , Subject: [PATCH v3 02/14] clk: ast2600: Add YCLK control for HACE Date: Tue, 20 Jul 2021 14:38:27 +0800 Message-ID: <20210720063839.1518-3-chiawei_wang@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210720063839.1518-1-chiawei_wang@aspeedtech.com> References: <20210720063839.1518-1-chiawei_wang@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.2.66] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 16K6M6Nd039584 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean From: Joel Stanley Add YCLK enable for HACE, the HW hash engine of ASPEED AST2600 SoCs. Signed-off-by: Joel Stanley Signed-off-by: Chia-Wei Wang --- .../arm/include/asm/arch-aspeed/scu_ast2600.h | 5 +++-- drivers/clk/aspeed/clk_ast2600.c | 20 +++++++++++++++++++ 2 files changed, 23 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h b/arch/arm/include/asm/arch-aspeed/scu_ast2600.h index a205fb1f76..d7b500f656 100644 --- a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2600.h @@ -10,8 +10,9 @@ #define SCU_CLKGATE1_EMMC BIT(27) #define SCU_CLKGATE1_MAC2 BIT(21) #define SCU_CLKGATE1_MAC1 BIT(20) -#define SCU_CLKGATE1_USB_HUB BIT(14) -#define SCU_CLKGATE1_USB_HOST2 BIT(7) +#define SCU_CLKGATE1_USB_HUB BIT(14) +#define SCU_CLKGATE1_HACE BIT(13) +#define SCU_CLKGATE1_USB_HOST2 BIT(7) #define SCU_CLKGATE2_FSI BIT(30) #define SCU_CLKGATE2_MAC4 BIT(21) diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c index 3a92739f5c..69128fd3c4 100644 --- a/drivers/clk/aspeed/clk_ast2600.c +++ b/drivers/clk/aspeed/clk_ast2600.c @@ -1013,6 +1013,23 @@ static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu) return 0; } +static ulong ast2600_enable_haceclk(struct ast2600_scu *scu) +{ + uint32_t reset_bit; + uint32_t clkgate_bit; + + reset_bit = BIT(ASPEED_RESET_HACE); + clkgate_bit = SCU_CLKGATE1_HACE; + + writel(reset_bit, &scu->modrst_ctrl1); + udelay(100); + writel(clkgate_bit, &scu->clkgate_clr1); + mdelay(20); + writel(reset_bit, &scu->modrst_clr1); + + return 0; +} + static int ast2600_clk_enable(struct clk *clk) { struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); @@ -1051,6 +1068,9 @@ static int ast2600_clk_enable(struct clk *clk) case ASPEED_CLK_GATE_USBPORT2CLK: ast2600_enable_usbbhclk(priv->scu); break; + case ASPEED_CLK_GATE_YCLK: + ast2600_enable_haceclk(priv->scu); + break; default: pr_err("can't enable clk\n"); return -ENOENT; From patchwork Tue Jul 20 06:38:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ChiaWei Wang X-Patchwork-Id: 481492 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp4837809jao; Mon, 19 Jul 2021 23:39:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyBgJy3K+6W68/UeR5J1MVFpTp4i8H1B+khOdWKlA97HuBK9tcjFGmpaQYcgEvOsxzm86fn X-Received: by 2002:a05:6402:1011:: with SMTP id c17mr11488532edu.144.1626763180043; Mon, 19 Jul 2021 23:39:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626763180; cv=none; d=google.com; s=arc-20160816; b=cNXwElCwlZviQ3nRgaPd6svzTnPhCGUfLEuMK+/l4fVBO/HRJtCuPzdOIBFk+j6/Cj J4brldNSM5UfnwFS8+NARVk6CG13/SsMYLdsvIfu/5q1mSqIBlhi9klqjkOAupmV+bcT nYcI0HO0afQsYEq1xCd8foqIRFNkvHYfkKgeE0j48hjpTrQN89/pzw6dq2yIJrRBexYG H2AqMVceiOtfZhcbW0u20VHfrjhbdvTQrT4vw5AZPoU3gKW9r9UWunUsZQXCsrs1hpuW e1uVpaoE0H6urk2yRhUgVJDDkKjH0b4RxeTM5ahxpguHR5UGNFXAxZmQCV7hMmZmtjO+ sAqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from; bh=/ksKQ0yBNERgu2Sys8nrt7DktBGN4Iar/FSmGGi9Wxc=; b=vgWWaK3p5YSMxKfepAf4cE/hOOXHpS3Zj1vdlfsnZFQpww/aOm/yI2XljKElsUbfgE r6JvJq/qTrX+CsYsZ6C1pziVnztIDIzQxB2DJzFzXmlNYpTAjiNEiu21UUSRZf0Hd8qS PP+24mGYNjRzqRGR+f4lsXkVEZD4yv8UN1tp2o8qoEmxz4o8gwN94djhUWp0RXXrnJXW JCRxXrMQ2WBp5tIu0W40HRR9dDduifV6PlNbHG5nHtipXs8n/KssNjtUBgGYySiEHgvW T/CIbBozSG8fL1o6CRAeKcS0TXkcVr+vcsXmU94oc3HFfx+aedv0AC0NM2yCsFfherz3 78lw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id 18si26386182ejc.508.2021.07.19.23.39.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 23:39:40 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C4B6682C57; Tue, 20 Jul 2021 08:39:25 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=aspeedtech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id F255082C47; Tue, 20 Jul 2021 08:39:16 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 80D3B82C26 for ; Tue, 20 Jul 2021 08:39:05 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=aspeedtech.com Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=chiawei_wang@aspeedtech.com Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 16K6M66U039585; Tue, 20 Jul 2021 14:22:06 +0800 (GMT-8) (envelope-from chiawei_wang@aspeedtech.com) Received: from ChiaWeiWang-PC.aspeed.com (192.168.2.66) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 20 Jul 2021 14:38:31 +0800 From: Chia-Wei Wang To: , , , CC: , Subject: [PATCH v3 03/14] crypto: aspeed: Add AST2600 HACE support Date: Tue, 20 Jul 2021 14:38:28 +0800 Message-ID: <20210720063839.1518-4-chiawei_wang@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210720063839.1518-1-chiawei_wang@aspeedtech.com> References: <20210720063839.1518-1-chiawei_wang@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.2.66] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 16K6M66U039585 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean From: Joel Stanley Hash and Crypto Engine (HACE) is designed to accelerate the throughput of hash data digest, and symmetric-key encryption. Signed-off-by: Joel Stanley Signed-off-by: Chia-Wei Wang --- drivers/crypto/Kconfig | 2 + drivers/crypto/Makefile | 1 + drivers/crypto/aspeed/Kconfig | 12 ++ drivers/crypto/aspeed/Makefile | 1 + drivers/crypto/aspeed/aspeed_hace.c | 308 ++++++++++++++++++++++++++++ 5 files changed, 324 insertions(+) create mode 100644 drivers/crypto/aspeed/Kconfig create mode 100644 drivers/crypto/aspeed/Makefile create mode 100644 drivers/crypto/aspeed/aspeed_hace.c -- 2.17.1 diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 1ea116be75..422d01403e 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -2,4 +2,6 @@ menu "Hardware crypto devices" source drivers/crypto/fsl/Kconfig +source drivers/crypto/aspeed/Kconfig + endmenu diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index efbd1d3fca..0442067e5e 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.o obj-y += rsa_mod_exp/ obj-y += fsl/ +obj-y += aspeed/ diff --git a/drivers/crypto/aspeed/Kconfig b/drivers/crypto/aspeed/Kconfig new file mode 100644 index 0000000000..299efc223f --- /dev/null +++ b/drivers/crypto/aspeed/Kconfig @@ -0,0 +1,12 @@ +config ASPEED_HACE + bool "ASPEED Hash and Crypto Engine" + depends on ASPEED_AST2600 + imply SHA_HW_ACCEL + imply SHA_PROG_HW_ACCEL + imply CMD_HASH + help + Select this option to enable a driver for using the SHA engine in + the ASPEED BMC SoCs. + + Enabling this allows the use of SHA operations in hardware without requiring the + SHA software implementations. It also improves performance and saves code size. diff --git a/drivers/crypto/aspeed/Makefile b/drivers/crypto/aspeed/Makefile new file mode 100644 index 0000000000..84e6bfe82a --- /dev/null +++ b/drivers/crypto/aspeed/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_ASPEED_HACE) += aspeed_hace.o diff --git a/drivers/crypto/aspeed/aspeed_hace.c b/drivers/crypto/aspeed/aspeed_hace.c new file mode 100644 index 0000000000..896e1f1a3b --- /dev/null +++ b/drivers/crypto/aspeed/aspeed_hace.c @@ -0,0 +1,308 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright 2021 IBM Corp. + * Copyright 2021 ASPEED Technology Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* register offsets*/ +#define HACE_STS 0x1C +#define HACE_HASH_DATA_OVF BIT(23) +#define HACE_HASH_INT BIT(9) +#define HACE_HASH_BUSY BIT(0) +#define HACE_HASH_DATA 0x20 +#define HACE_HASH_DIGEST 0x24 +#define HACE_HASH_HMAC_KEY 0x28 +#define HACE_HASH_DATA_LEN 0x2C +#define HACE_SG_LAST BIT(31) +#define HACE_HASH_CMD 0x30 +#define HACE_SG_EN BIT(18) +#define HACE_ALGO_SHA384 (BIT(10) | BIT(6) | BIT(5)) +#define HACE_ALGO_SHA512 (BIT(6) | BIT(5)) +#define HACE_ALGO_SHA256 (BIT(6) | BIT(4)) +#define HACE_ALGO_SHA224 BIT(6) +#define HACE_ALGO_SHA1 BIT(5) +#define HACE_SHA_BE_EN BIT(3) +#define HACE_MD5_LE_EN BIT(2) + +#define HACE_MAX_SG 32 + +struct aspeed_sg { + u32 len; + u32 addr; +}; + +struct aspeed_hash_ctx { + u32 method; + u32 digest_size; + u32 len; + u32 count; + struct aspeed_sg list[HACE_MAX_SG]; /* Must be 8 byte aligned */ +}; + +struct aspeed_hace { + phys_addr_t base; + struct clk clk; + struct reset_ctl rst; +}; + +static int aspeed_hace_wait_completion(u32 reg, u32 flag, int timeout_us) +{ + u32 val; + + return readl_poll_timeout(reg, val, (val & flag) == flag, timeout_us); +} + +static int digest_object(const void *data, unsigned int length, void *digest, + u32 method) +{ + int rc; + u32 sts; + struct udevice *dev; + struct aspeed_hace *hace; + + if (!((u32)data & BIT(31))) { + debug("HACE src out of bounds: can only copy from SDRAM\n"); + return -EINVAL; + } + + if (!((u32)digest & BIT(31))) { + debug("HACE dst out of bounds: can only copy to SDRAM\n"); + return -EINVAL; + } + + if ((u32)digest & 0x7) { + debug("HACE dst alignment incorrect: %p\n", digest); + return -EINVAL; + } + + /* get HACE device as crypto code does not pass us device/driver state */ + rc = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(aspeed_hace), + &dev); + if (rc) { + debug("Can't get HACE device, rc=%d\n", rc); + return -ENODEV; + } + + hace = dev_get_priv(dev); + + sts = readl(hace->base + HACE_STS); + if (sts & HACE_HASH_BUSY) { + debug("HACE error: engine busy\n"); + return -EBUSY; + } + + /* Clear pending completion status */ + writel(HACE_HASH_INT, hace->base + HACE_STS); + writel((u32)data, hace->base + HACE_HASH_DATA); + writel((u32)digest, hace->base + HACE_HASH_DIGEST); + writel(length, hace->base + HACE_HASH_DATA_LEN); + writel(HACE_SHA_BE_EN | method, hace->base + HACE_HASH_CMD); + + /* SHA512 hashing appears to have a througput of about 12MB/s */ + rc = aspeed_hace_wait_completion(hace->base + HACE_STS, + HACE_HASH_INT, + 1000 + (length >> 3)); + + /* + * Reset HACE to work around unexpected hash input data + * buffer overflow caused by certain combinations of DMA + * base and length, even though they are valid. + */ + sts = readl(hace->base + HACE_STS); + if (sts & HACE_HASH_DATA_OVF) { + debug("HACE error: status=0x%08x, resetting\n", sts); + reset_assert(&hace->rst); + mdelay(5); + reset_deassert(&hace->rst); + } + + return rc; +} + +void hw_sha1(const unsigned char *pbuf, unsigned int buf_len, + unsigned char *pout, unsigned int chunk_size) +{ + int rc; + + rc = digest_object(pbuf, buf_len, pout, HACE_ALGO_SHA1); + if (rc) + debug("HACE failure: %d\n", rc); +} + +void hw_sha256(const unsigned char *pbuf, unsigned int buf_len, + unsigned char *pout, unsigned int chunk_size) +{ + int rc; + + rc = digest_object(pbuf, buf_len, pout, HACE_ALGO_SHA256); + if (rc) + debug("HACE failure: %d\n", rc); +} + +void hw_sha384(const unsigned char *pbuf, unsigned int buf_len, + unsigned char *pout, unsigned int chunk_size) +{ + int rc; + + rc = digest_object(pbuf, buf_len, pout, HACE_ALGO_SHA384); + if (rc) + debug("HACE failure: %d\n", rc); +} + +void hw_sha512(const unsigned char *pbuf, unsigned int buf_len, + unsigned char *pout, unsigned int chunk_size) +{ + int rc; + + rc = digest_object(pbuf, buf_len, pout, HACE_ALGO_SHA512); + if (rc) + debug("HACE failure: %d\n", rc); +} + +int hw_sha_init(struct hash_algo *algo, void **ctxp) +{ + struct aspeed_hash_ctx *ctx; + u32 method; + + if (!strcmp(algo->name, "sha1")) + method = HACE_ALGO_SHA1; + else if (!strcmp(algo->name, "sha256")) + method = HACE_ALGO_SHA256; + else if (!strcmp(algo->name, "sha384")) + method = HACE_ALGO_SHA384; + else if (!strcmp(algo->name, "sha512")) + method = HACE_ALGO_SHA512; + else + return -ENOTSUPP; + + ctx = memalign(8, sizeof(*ctx)); + if (!ctx) { + debug("HACE error: Cannot allocate memory for context\n"); + return -ENOMEM; + } + + memset(ctx, '\0', sizeof(*ctx)); + + if (((uintptr_t)ctx->list & 0x3) != 0) { + debug("HACE error: Invalid alignment for input data\n"); + return -EINVAL; + } + + ctx->method = method | HACE_SG_EN; + ctx->digest_size = algo->digest_size; + + *ctxp = ctx; + + return 0; +} + +int hw_sha_update(struct hash_algo *algo, void *hash_ctx, const void *buf, + unsigned int size, int is_last) +{ + struct aspeed_hash_ctx *ctx = hash_ctx; + struct aspeed_sg *sg = &ctx->list[ctx->count]; + + if (ctx->count >= ARRAY_SIZE(ctx->list)) { + debug("HACE error: Reached maximum number of hash segments\n"); + free(ctx); + return -EINVAL; + } + + sg->addr = (u32)buf; + sg->len = size; + + if (is_last) + sg->len |= HACE_SG_LAST; + + ctx->count++; + ctx->len += size; + + return 0; +} + +int hw_sha_finish(struct hash_algo *algo, void *hash_ctx, void *dest_buf, int size) +{ + struct aspeed_hash_ctx *ctx = hash_ctx; + int rc; + + if (size < ctx->digest_size) { + debug("HACE error: insufficient size on destination buffer\n"); + free(ctx); + return -EINVAL; + } + + rc = digest_object(ctx->list, ctx->len, dest_buf, ctx->method); + if (rc) + debug("HACE Scatter-Gather failure\n"); + + free(ctx); + + return rc; +} + +static int aspeed_hace_probe(struct udevice *dev) +{ + struct aspeed_hace *hace = dev_get_priv(dev); + int ret; + + ret = clk_get_by_index(dev, 0, &hace->clk); + if (ret < 0) { + debug("Can't get clock for %s: %d\n", dev->name, ret); + return ret; + } + + ret = reset_get_by_index(dev, 0, &hace->rst); + if (ret < 0) { + debug("Can't get reset for %s: %d\n", dev->name, ret); + return ret; + } + + ret = clk_enable(&hace->clk); + if (ret) { + debug("Failed to enable fsi clock (%d)\n", ret); + return ret; + } + + hace->base = devfdt_get_addr(dev); + + return ret; +} + +static int aspeed_hace_remove(struct udevice *dev) +{ + struct aspeed_hace *hace = dev_get_priv(dev); + + clk_disable(&hace->clk); + + return 0; +} + +static const struct udevice_id aspeed_hace_ids[] = { + { .compatible = "aspeed,ast2600-hace" }, + { } +}; + +U_BOOT_DRIVER(aspeed_hace) = { + .name = "aspeed_hace", + .id = UCLASS_MISC, + .of_match = aspeed_hace_ids, + .probe = aspeed_hace_probe, + .remove = aspeed_hace_remove, + .priv_auto = sizeof(struct aspeed_hace), + .flags = DM_FLAG_PRE_RELOC, +}; From patchwork Tue Jul 20 06:38:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ChiaWei Wang X-Patchwork-Id: 481493 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp4838073jao; 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[85.214.62.61]) by mx.google.com with ESMTPS id qc25si15517818ejb.324.2021.07.19.23.40.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 23:40:05 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3B78882C44; Tue, 20 Jul 2021 08:39:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=aspeedtech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 30ADB82C24; Tue, 20 Jul 2021 08:39:22 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B6C55829F8 for ; Tue, 20 Jul 2021 08:39:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=aspeedtech.com Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=chiawei_wang@aspeedtech.com Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 16K6M66V039585; Tue, 20 Jul 2021 14:22:06 +0800 (GMT-8) (envelope-from chiawei_wang@aspeedtech.com) Received: from ChiaWeiWang-PC.aspeed.com (192.168.2.66) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 20 Jul 2021 14:38:32 +0800 From: Chia-Wei Wang To: , , , CC: , Subject: [PATCH v3 04/14] ast2600: spl: Add HACE probing Date: Tue, 20 Jul 2021 14:38:29 +0800 Message-ID: <20210720063839.1518-5-chiawei_wang@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210720063839.1518-1-chiawei_wang@aspeedtech.com> References: <20210720063839.1518-1-chiawei_wang@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.2.66] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 16K6M66V039585 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean From: Joel Stanley Probe HACE driver in SPL board init if enabled. Signed-off-by: Joel Stanley Signed-off-by: Chia-Wei Wang --- arch/arm/mach-aspeed/ast2600/spl.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.17.1 diff --git a/arch/arm/mach-aspeed/ast2600/spl.c b/arch/arm/mach-aspeed/ast2600/spl.c index 0d8cb29678..a0fc420ff1 100644 --- a/arch/arm/mach-aspeed/ast2600/spl.c +++ b/arch/arm/mach-aspeed/ast2600/spl.c @@ -38,6 +38,20 @@ struct image_header *spl_get_load_buffer(ssize_t offset, size_t size) return (struct image_header *)(CONFIG_SYS_TEXT_BASE); } +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void) +{ + int rc; + struct udevice *dev; + + rc = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(aspeed_hace), + &dev); + if (rc) + debug("HACE initialization failure, rc=%d\n", rc); +} +#endif + #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { From patchwork Tue Jul 20 06:38:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ChiaWei Wang X-Patchwork-Id: 481490 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp4837530jao; Mon, 19 Jul 2021 23:39:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxefzySwXvYUpVBKQb2N1z/giKOJU8XjPnTfOpHTLPUDSa9K2wPLSRcBlexE2ZIgHygc9dC X-Received: by 2002:a50:cdcb:: with SMTP id h11mr38911346edj.366.1626763150859; Mon, 19 Jul 2021 23:39:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626763150; cv=none; d=google.com; s=arc-20160816; b=EydcEr642NTqnGPdCh4zIHrrzgbNCZo8oI07D1FvsU9Ra7vu55gDl8ueQIW5F9eBGH u3omULT/0RBai19iACGBkE1YU8N8Uglsk6DmtNtiEYL3Z0zI6LMLrfXMMeT251lZry2R FFeQyehBDXU15luZ/mwWDBH3iZbc9dMP+xF9kcRbL8+MJNb6TOHCW+yfKRlyQQm5FbQZ SS8taPaATUlwEv6Ov/MKr8vF1yTPAUuJ/smRgL4oxFdX8FyjdeBUF97u76uXzh9h0jq6 70M/tNe6G3vy28xWHdSDyfDityVUnWY/qoD0JGWfwxJgvdTSeT0py3GXDnxm/5bKkVMc qvMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from; bh=58zK2714NeEtRmSBOxiU2KbBpm/+SwDNlmeUOicenMo=; b=rvk2kmNAwiduZDm7QnMkpmX7zKUDmEZlHna5AeEVS5iZagLD+sL3XXP2grTuORWPwz Knf/xuG/uX4LuJJ09pOc76E18kCD5MudzSVnefY4abI8+iPkitu/Ikd2IsAalQl0WBpE hAcVGz+kx2+I3fv5L6DHBCaHTvwf5U+QRs4wN8Fj6FfVjm+NsoqPmcH40pSnGKbQPU8D uDVheqr3Bc4LNGCvvHC0elgKLuSjXAHkzYxmsQxJ9jtnHjZe6SP9Ns2I5+bY4sZr89/z QkwKV2/GB3PAfrd8Cq9EukAc/VCD+wfLsk7tRQdX6dmSlQ4u4Pi/gSrDT86/dvxhT8bU meKw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id w3si20661068edc.112.2021.07.19.23.39.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 23:39:10 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2F2C282BB4; Tue, 20 Jul 2021 08:39:02 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=aspeedtech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 8A79680FBE; Tue, 20 Jul 2021 08:38:54 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id AB05D80FBE for ; Tue, 20 Jul 2021 08:38:50 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=aspeedtech.com Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=chiawei_wang@aspeedtech.com Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 16K6M68T039588; Tue, 20 Jul 2021 14:22:06 +0800 (GMT-8) (envelope-from chiawei_wang@aspeedtech.com) Received: from ChiaWeiWang-PC.aspeed.com (192.168.2.66) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 20 Jul 2021 14:38:32 +0800 From: Chia-Wei Wang To: , , , CC: , Subject: [PATCH v3 05/14] ARM: dts: ast2600: Add HACE to device tree Date: Tue, 20 Jul 2021 14:38:30 +0800 Message-ID: <20210720063839.1518-6-chiawei_wang@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210720063839.1518-1-chiawei_wang@aspeedtech.com> References: <20210720063839.1518-1-chiawei_wang@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.2.66] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 16K6M68T039588 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean From: Joel Stanley Add HACE DTS node and enable it for AST2600 EVB. Signed-off-by: Joel Stanley Signed-off-by: Chia-Wei Wang --- arch/arm/dts/ast2600-evb.dts | 5 +++++ arch/arm/dts/ast2600.dtsi | 9 +++++++++ 2 files changed, 14 insertions(+) -- 2.17.1 diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts index 2abd31341c..adb80a30ef 100644 --- a/arch/arm/dts/ast2600-evb.dts +++ b/arch/arm/dts/ast2600-evb.dts @@ -177,3 +177,8 @@ 0x08 0x04 0x08 0x04>; }; + +&hace { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi index ac0f08b7ea..3061649205 100644 --- a/arch/arm/dts/ast2600.dtsi +++ b/arch/arm/dts/ast2600.dtsi @@ -187,6 +187,15 @@ }; }; + hace: hace@1e6d0000 { + compatible = "aspeed,ast2600-hace"; + reg = <0x1e6d0000 0x200>; + interrupts = ; + clocks = <&scu ASPEED_CLK_GATE_YCLK>; + resets = <&rst ASPEED_RESET_HACE>; + status = "disabled"; + }; + edac: sdram@1e6e0000 { compatible = "aspeed,ast2600-sdram-edac"; reg = <0x1e6e0000 0x174>; From patchwork Tue Jul 20 06:38:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ChiaWei Wang X-Patchwork-Id: 481494 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp4838633jao; Mon, 19 Jul 2021 23:41:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzXcKzzs++hNooB0aUKOOeYiM2BUevUb/MtiTt7fnQ6zWX8UoV/I7UG8Ejo3XqdfthMPc9Y X-Received: by 2002:aa7:da13:: with SMTP id r19mr39251013eds.252.1626763262042; Mon, 19 Jul 2021 23:41:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626763262; cv=none; d=google.com; s=arc-20160816; b=YsRvspQfUmQvkLqtPLApdDa08XYAa6V0R4Sunlp5l/LsfKxwPnCoFzgl+0Ho334oPn aC+Nq+QF20ReCcDVj27BPMvrTwuVw6hyYH/7OKO6tGAl7qNzXwLF73crx7x+pZOXpZOm BxFSI01QuYdQyAj1/FJZJWzzElC0F90nqUzspeGyEjCh99+Jy+lR/xVWZ/6arDUx/gnb fiYMJn4+68pj8Q+wsKQA3A/EALnoVb/qYWeh9jJV1trXkyCiHh+QFU9D7C28+rJUNEvk z6q4hTTiM1OcQdM81Le+hIv4E/RC3jrbLarZmaQRdJmxllhbiKd2IBSHEU0LqbnkH4RY NOmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:mime-version:references :in-reply-to:message-id:date:subject:cc:to:from; bh=ARthw3mW/dMnAPs+OytOHSZiC158rh2+OeOPaQkzkIQ=; b=tkhVjLfLYlOQAkCRvoX4ZoKlvDHIb+fTo9mgfMjjSiM4t8taZ8imk9aIOjcMcWPjy+ pGwSblw0JMPzyXSvIrDMAaEyduYGkrR5QrIWOFlai5VELcDnAl3D0HkYzaJ7hUHWTaPZ n0Uz3XqObOwOXuebGAWt+QtYijgdc13bI2uC4Rd/+PFs+HgZTLJqYzqhL81nLM2yr51f R2JbXYzHJWCyDMZBRbTM2nkXdKEaR3bltAhw4M5qX9WcWNGWs22xh8vC28M3/oPrqIyZ SmBC7MzeQo5/mxoHMYTNSa14lTlZxs1nh5M8UIv6t1BgpX9NZYvhgCA+CkzaoePXvunz yTFQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id u13si14249636ejz.673.2021.07.19.23.41.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 23:41:02 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 264F282C67; Tue, 20 Jul 2021 08:40:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=aspeedtech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 481F58262E; Tue, 20 Jul 2021 08:39:37 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3A6B9829E4 for ; Tue, 20 Jul 2021 08:39:20 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=aspeedtech.com Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=chiawei_wang@aspeedtech.com Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 16K6M68U039588; Tue, 20 Jul 2021 14:22:07 +0800 (GMT-8) (envelope-from chiawei_wang@aspeedtech.com) Received: from ChiaWeiWang-PC.aspeed.com (192.168.2.66) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 20 Jul 2021 14:38:32 +0800 From: Chia-Wei Wang To: , , , CC: , Subject: [PATCH v3 06/14] common: fit: Use hash.c to call CRC/SHA function Date: Tue, 20 Jul 2021 14:38:31 +0800 Message-ID: <20210720063839.1518-7-chiawei_wang@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210720063839.1518-1-chiawei_wang@aspeedtech.com> References: <20210720063839.1518-1-chiawei_wang@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.2.66] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 16K6M68U039588 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean From: Joel Stanley Currently the FIT verification calls directly into SW implemented functions to get a CRC/SHA/MD5 hash. This patch removes duplcated algorithm lookup and use hash_lookup_algo to get the hashing function with HW accelearation supported if configured. The MD5 direct call remains as it is not included in the hash lookup table of hash.c. Signed-off-by: Joel Stanley Signed-off-by: Chia-Wei Wang --- common/image-fit.c | 35 ++++++++++------------------------- 1 file changed, 10 insertions(+), 25 deletions(-) -- 2.17.1 diff --git a/common/image-fit.c b/common/image-fit.c index 0c5a05948d..e52ff47bc3 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -1196,7 +1196,7 @@ int fit_set_timestamp(void *fit, int noffset, time_t timestamp) * calculate_hash - calculate and return hash for provided input data * @data: pointer to the input data * @data_len: data length - * @algo: requested hash algorithm + * @algo_name: requested hash algorithm * @value: pointer to the char, will hold hash value data (caller must * allocate enough free space) * value_len: length of the calculated hash @@ -1210,37 +1210,22 @@ int fit_set_timestamp(void *fit, int noffset, time_t timestamp) * 0, on success * -1, when algo is unsupported */ -int calculate_hash(const void *data, int data_len, const char *algo, - uint8_t *value, int *value_len) +int calculate_hash(const void *data, int data_len, const char *algo_name, + uint8_t *value, int *value_len) { - if (IMAGE_ENABLE_CRC32 && strcmp(algo, "crc32") == 0) { - *((uint32_t *)value) = crc32_wd(0, data, data_len, - CHUNKSZ_CRC32); - *((uint32_t *)value) = cpu_to_uimage(*((uint32_t *)value)); - *value_len = 4; - } else if (IMAGE_ENABLE_SHA1 && strcmp(algo, "sha1") == 0) { - sha1_csum_wd((unsigned char *)data, data_len, - (unsigned char *)value, CHUNKSZ_SHA1); - *value_len = 20; - } else if (IMAGE_ENABLE_SHA256 && strcmp(algo, "sha256") == 0) { - sha256_csum_wd((unsigned char *)data, data_len, - (unsigned char *)value, CHUNKSZ_SHA256); - *value_len = SHA256_SUM_LEN; - } else if (IMAGE_ENABLE_SHA384 && strcmp(algo, "sha384") == 0) { - sha384_csum_wd((unsigned char *)data, data_len, - (unsigned char *)value, CHUNKSZ_SHA384); - *value_len = SHA384_SUM_LEN; - } else if (IMAGE_ENABLE_SHA512 && strcmp(algo, "sha512") == 0) { - sha512_csum_wd((unsigned char *)data, data_len, - (unsigned char *)value, CHUNKSZ_SHA512); - *value_len = SHA512_SUM_LEN; - } else if (IMAGE_ENABLE_MD5 && strcmp(algo, "md5") == 0) { + struct hash_algo *algo; + + if (IMAGE_ENABLE_MD5 && strcmp(algo_name, "md5") == 0) { md5_wd((unsigned char *)data, data_len, value, CHUNKSZ_MD5); *value_len = 16; + } else if (hash_lookup_algo(algo_name, &algo) == 0) { + algo->hash_func_ws(data, data_len, value, algo->chunk_size); + *value_len = algo->digest_size; } else { debug("Unsupported hash alogrithm\n"); return -1; } + return 0; }