From patchwork Sun Jul 18 11:40:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 479651 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BF47C636CE for ; Sun, 18 Jul 2021 11:41:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3A45A611BE for ; Sun, 18 Jul 2021 11:41:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233071AbhGRLn5 (ORCPT ); Sun, 18 Jul 2021 07:43:57 -0400 Received: from mail.kernel.org ([198.145.29.99]:60816 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232716AbhGRLn4 (ORCPT ); Sun, 18 Jul 2021 07:43:56 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id B4A0C6108B; Sun, 18 Jul 2021 11:40:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1626608458; bh=Yxg6f6Vl7O5HHJp418DNs74biL5Q8SHGgoxNBhxuF/c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EItQsymLmRgQje+Sximp2sA51G07ycSl7pHA9zhaVDs8InEHOwKSir8Yy1X/qDQhC iSJOpTbWSS7cXrYCib7jFgxHB4fy6iDfULSwUOL8wjd0pk/7AB2zciRbzqD+/Vb4D2 lk6eNUshu4Ec2E50dqpW26czWwscYY1CinbaT/WXbwxdaxu8jTWt5KiYbw00YCeJdi 4xPpRmilm7UFoGFn8s//SsIllBnsXe3qP5JWUki4B+yr+TG0OHJ4dBJT//DLZhao6H mYkYiQs2F3oEsJBzoWTnB7L9TnoFp0ZgPtN64pEIRT7wFD8TuZUR9cgGKc2wkFUgmf 6+CmKmEmcraPA== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1m55AE-001Dvw-7W; Sun, 18 Jul 2021 13:40:54 +0200 From: Mauro Carvalho Chehab To: Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v5 1/5] dt-bindings: PCI: add snps,dw-pcie.yaml Date: Sun, 18 Jul 2021 13:40:48 +0200 Message-Id: <53363a7609176ca56c47ef57287466ee84087dc5.1626608375.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Currently, the designware schema is defined on a text file: designware-pcie.txt Convert the pci-bus part into a schema. Signed-off-by: Mauro Carvalho Chehab --- .../devicetree/bindings/pci/snps,dw-pcie.yaml | 102 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 103 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml new file mode 100644 index 000000000000..d4441d822b91 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare PCIe interface + +maintainers: + - Jingoo Han + - Gustavo Pimentel + +description: | + Synopsys DesignWare PCIe host controller + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + anyOf: + - {} + - const: snps,dw-pcie + + reg: + description: | + It should contain Data Bus Interface (dbi) and config registers for all + versions. + For designware core version >= 4.80, it may contain ATU address space. + minItems: 2 + maxItems: 5 + + reg-names: + minItems: 2 + maxItems: 5 + items: + enum: [dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link] + + num-lanes: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + number of lanes to use (this property should be specified unless + the link is brought already up in BIOS) + maximum: 16 + + reset-gpio: + description: GPIO pin number of PERST# signal + maxItems: 1 + deprecated: true + + reset-gpios: + description: GPIO controlled connection to PERST# signal + maxItems: 1 + + interrupts: true + + interrupt-names: true + + clocks: true + + snps,enable-cdm-check: + type: boolean + description: | + This is a boolean property and if present enables + automatic checking of CDM (Configuration Dependent Module) registers + for data corruption. CDM registers include standard PCIe configuration + space registers, Port Logic registers, DMA and iATU (internal Address + Translation Unit) registers. + + num-viewport: + description: | + number of view ports configured in hardware. If a platform + does not specify it, the driver autodetects it. + deprecated: true + +unevaluatedProperties: false + +required: + - reg + - reg-names + - compatible + +examples: + - | + bus { + #address-cells = <1>; + #size-cells = <1>; + pcie@dfc00000 { + device_type = "pci"; + compatible = "snps,dw-pcie"; + reg = <0xdfc00000 0x0001000>, /* IP registers */ + <0xd0000000 0x0002000>; /* Configuration space */ + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>, + <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>; + interrupts = <25>, <24>; + #interrupt-cells = <1>; + num-lanes = <1>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index fb6971bc28c5..c88f6cb37e47 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14306,6 +14306,7 @@ M: Gustavo Pimentel L: linux-pci@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/pci/designware-pcie.txt +F: Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml F: drivers/pci/controller/dwc/*designware* PCI DRIVER FOR TI DRA7XX/J721E From patchwork Sun Jul 18 11:40:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mauro Carvalho Chehab X-Patchwork-Id: 479649 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E89CCC6377C for ; Sun, 18 Jul 2021 11:41:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D108A6108B for ; Sun, 18 Jul 2021 11:41:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232685AbhGRLn7 (ORCPT ); Sun, 18 Jul 2021 07:43:59 -0400 Received: from mail.kernel.org ([198.145.29.99]:60848 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232851AbhGRLn4 (ORCPT ); Sun, 18 Jul 2021 07:43:56 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id C29DB611AD; Sun, 18 Jul 2021 11:40:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1626608458; bh=3r+ZJ2a/sCjL++ntc+WZnrTk0ubp8K3+zZZ4PPnoCDs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cX0vEmyFJvWdDz2GDub0q5Evrfuz5TWhTAO4PTTcSIjo3PN8Htz3NmYRq8yxhEys0 kBW/bZOE2ziuzNJ+uGSvJ3Pj42C/5QpDtxIzf+zmDHk4E2jwmmj4JJnqPkaeQgiHRK 2OHxCf+oz2UTpW6xywqJX07AcfzP78deOuElK1lwy2tralsQH8iZ0r8Z8Tj2oX+SoA wplTKiKOcsLf28NuhozUJ58o9afWIJiLlsDuiajbknMYrtcS5YDyY0e8KXe37qE5/c Vgc97DkRz4wnw2Ul7FJips9qLI+MpWd9Ik1mQppTynMXSMC/BBdGr0rA7sghxZJib1 P0KvWzvE1EewQ== Received: by mail.kernel.org with local (Exim 4.94.2) (envelope-from ) id 1m55AE-001DwD-DS; Sun, 18 Jul 2021 13:40:54 +0200 From: Mauro Carvalho Chehab To: Rob Herring Cc: linuxarm@huawei.com, mauro.chehab@huawei.com, Mauro Carvalho Chehab , Bjorn Helgaas , JC Kuo , Jonathan Hunter , Rob Herring , Sameer Pujar , Sowjanya Komatineni , Thierry Reding , Vidya Sagar , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v5 5/5] dt-bindings: arm64: tegra: fix pcie-ep DT nodes Date: Sun, 18 Jul 2021 13:40:52 +0200 Message-Id: <15cf5067c0567614d5b186d006ebd88395d56b63.1626608375.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: MIME-Version: 1.0 Sender: Mauro Carvalho Chehab Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As defined by Documentation/devicetree/bindings/pci/pci-ep.yaml, PCIe endpoints match this pattern: properties: $nodename: pattern: "^pcie-ep@" Change the existing ones in order to avoid those warnings: arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dt.yaml: pcie_ep@14160000: $nodename:0: 'pcie_ep@14160000' does not match '^pcie-ep@' From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dt.yaml: pcie_ep@14180000: $nodename:0: 'pcie_ep@14180000' does not match '^pcie-ep@' From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dt.yaml: pcie_ep@141a0000: $nodename:0: 'pcie_ep@141a0000' does not match '^pcie-ep@' From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dt.yaml: pcie_ep@14160000: $nodename:0: 'pcie_ep@14160000' does not match '^pcie-ep@' From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dt.yaml: pcie_ep@14180000: $nodename:0: 'pcie_ep@14180000' does not match '^pcie-ep@' From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dt.yaml: pcie_ep@141a0000: $nodename:0: 'pcie_ep@141a0000' does not match '^pcie-ep@' From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dt.yaml: pcie_ep@14160000: $nodename:0: 'pcie_ep@14160000' does not match '^pcie-ep@' From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dt.yaml: pcie_ep@14180000: $nodename:0: 'pcie_ep@14180000' does not match '^pcie-ep@' From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dt.yaml: pcie_ep@141a0000: $nodename:0: 'pcie_ep@141a0000' does not match '^pcie-ep@' From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml Signed-off-by: Mauro Carvalho Chehab Acked-by: Rob Herring --- .../devicetree/bindings/pci/nvidia,tegra194-pcie.txt | 2 +- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 6 +++--- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt index 6a99d2aa8075..8e4f9bfb316d 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt @@ -197,7 +197,7 @@ Tegra194 RC mode: Tegra194 EP mode: ----------------- - pcie_ep@141a0000 { + pcie-ep@141a0000 { compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 96bd01cadb18..542bf761c097 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -764,7 +764,7 @@ pcie@141a0000 { "p2u-5", "p2u-6", "p2u-7"; }; - pcie_ep@141a0000 { + pcie-ep@141a0000 { status = "disabled"; vddio-pex-ctl-supply = <&vdd_1v8ao>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 836a7e0a4267..a71848177849 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -741,7 +741,7 @@ pcie@141a0000 { "p2u-5", "p2u-6", "p2u-7"; }; - pcie_ep@141a0000 { + pcie-ep@141a0000 { status = "disabled"; vddio-pex-ctl-supply = <&vdd_1v8ao>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 5ba7a4519b95..606065fc373f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2121,7 +2121,7 @@ pcie@141a0000 { dma-coherent; }; - pcie_ep@14160000 { + pcie-ep@14160000 { compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ @@ -2161,7 +2161,7 @@ pcie_ep@14160000 { dma-coherent; }; - pcie_ep@14180000 { + pcie-ep@14180000 { compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ @@ -2201,7 +2201,7 @@ pcie_ep@14180000 { dma-coherent; }; - pcie_ep@141a0000 { + pcie-ep@141a0000 { compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */