From patchwork Sat Jul 17 04:56:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 479693 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4C3CC636CE for ; Sat, 17 Jul 2021 04:57:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 980B3613E7 for ; Sat, 17 Jul 2021 04:57:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231331AbhGQE7z (ORCPT ); Sat, 17 Jul 2021 00:59:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230216AbhGQE7l (ORCPT ); Sat, 17 Jul 2021 00:59:41 -0400 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C553DC061762 for ; Fri, 16 Jul 2021 21:56:44 -0700 (PDT) Received: by mail-pl1-x62d.google.com with SMTP id o8so6310955plg.11 for ; Fri, 16 Jul 2021 21:56:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8e6XlbKC+KjOCVkxo+Eb2tDouy+mshYsdsUVUAEu5P0=; b=gTkFAmbiJ1QVkJ2Vm7kvTo2ZOBk4PVmQMN6bdqkEpl5SDEB0Nw/ioy0AzHHOiyzU+/ S9R/X+DOAAl1hiTV0UvPhv1kCGUAt+ZNLQdKGk8zt93hzzuVM8eV9B5dOt+infBlHK+Q KkEFLJv29N2/Zm7Db64oozASkYgNlD5DaWdG0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8e6XlbKC+KjOCVkxo+Eb2tDouy+mshYsdsUVUAEu5P0=; b=YZdUZybVNjfN0UoUw/7pzFn5m+gxb22/Lzp9NIzrkmN/RtMqLXnjcds/ilXrt3un+a f9E15LsIiZKHSh69/tpHJVrMbr7XFw/6CiZEOYI+O5MGfXfJBnr7szCSdF8Q9RirRh6E LDgmddHa9vNk3EG3pcWpUaAixQVQ71ic+CjuIzT3hgBgJfM56my1yIJpFp4ibXPG7Rkd OZdkpBCgWe7nntW0bZKR636sfajGNt/Ls0eCsZREV6UwxufrSJGKIfPPsTbCI13k2qKf qUYKLpYI+tQaMaJfHTlRs+cXL8aaof1N3H0ONw2cj5wS40LInXz3ic6TUsTLJzrHIYJh ksHw== X-Gm-Message-State: AOAM531qaMDE84J94QcH9oV32DVQ6j5pYLFgz3xu75EfgKLbxsdzMtZC FTmyMe+AvkTBdb8CcuNhl+e+z+WDsat5iw== X-Google-Smtp-Source: ABdhPJwoR0Fkmo9Na2dM1/fOXvJF37GjeGKSSmFizRu+R+7y+/7jIjcFbBQCYikme7Ht5nSy9ZLaWg== X-Received: by 2002:a17:90a:1d43:: with SMTP id u3mr19190689pju.121.1626497804165; Fri, 16 Jul 2021 21:56:44 -0700 (PDT) Received: from shiro.work (p866038-ipngn200510sizuokaden.shizuoka.ocn.ne.jp. [180.9.60.38]) by smtp.googlemail.com with ESMTPSA id w2sm12522885pjf.2.2021.07.16.21.56.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Jul 2021 21:56:43 -0700 (PDT) From: Daniel Palmer To: devicetree@vger.kernel.org, linux-gpio@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linus.walleij@linaro.org, robh@kernel.org, romain.perier@gmail.com, Daniel Palmer Subject: [PATCH 01/10] dt-bindings: gpio: msc313: Add compatible for ssd20xd Date: Sat, 17 Jul 2021 13:56:18 +0900 Message-Id: <20210717045627.1739959-2-daniel@0x0f.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210717045627.1739959-1-daniel@0x0f.com> References: <20210717045627.1739959-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a compatible string for "ssd20xd" for the SigmaStar SSD201 and SSD202D chips. These chips are the same die with different memory bonded so they don't need their own strings. Signed-off-by: Daniel Palmer Acked-by: Rob Herring Reviewed-by: Linus Walleij --- Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml b/Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml index fe1e1c63ffe3..18fe90387b87 100644 --- a/Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml @@ -14,7 +14,9 @@ properties: pattern: "^gpio@[0-9a-f]+$" compatible: - const: mstar,msc313-gpio + enum: + - mstar,msc313-gpio + - sstar,ssd20xd-gpio reg: maxItems: 1 From patchwork Sat Jul 17 04:56:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 479368 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UPPERCASE_50_75, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6DD9C6377B for ; Sat, 17 Jul 2021 04:57:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BB31D613E7 for ; Sat, 17 Jul 2021 04:57:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229379AbhGQFAD (ORCPT ); Sat, 17 Jul 2021 01:00:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37786 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230380AbhGQE7n (ORCPT ); Sat, 17 Jul 2021 00:59:43 -0400 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46DC1C061762 for ; Fri, 16 Jul 2021 21:56:47 -0700 (PDT) Received: by mail-pj1-x1032.google.com with SMTP id me13-20020a17090b17cdb0290173bac8b9c9so10021854pjb.3 for ; Fri, 16 Jul 2021 21:56:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OApFkRKr43qnYe9uO+CssQNA+TR3XmmYu2y9NZ/H4so=; b=QG0tqodzp8dbcGKEw10rITkUq62sflIR9EF3RbHX6Xp/IDJ7zz2qyGjezpSwQQfoSQ q+YhvCktINiuKjxZBmR/cMqwyF1LAQMgMRuduA85VlTURRBBNAc0/kwg3wsbAJHQGJEY c8/LXLloX2EJL0i/jOPcVkdeu6ROidpk1FDMs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OApFkRKr43qnYe9uO+CssQNA+TR3XmmYu2y9NZ/H4so=; b=q9f4W/YDqUHgsH58f9AVUnDEUHtxVFWjxge0yVRJW6JRgDh6a9/4hw7dVpU3c2HiS9 ecOFbx31aGDsgdtrgbpe0y+wb1oTXVh+O6tZjKFT4AhOCdlQCo1tr9ldTYCxGEvhmBni MBlpBnC9zGHjN2Xqho+xWH0xZN6vCc/NfkN8ECKLVtJsmmzizahZ/VR9aLQ/u9WqTmJt lhX2KsGjmbH2vwdx7MMsxl0rCd/tKAfmBqc6izWNHTn0DtJm+e1EgPoiskRdKizVIZOT 87uCn9AqS4dbuMUzkfUq84ZP2uJrvGM6X8PpCV7RV+VA4Pz85dDpwx7fEl3lzrrLoh7w wWEQ== X-Gm-Message-State: AOAM532WsTtxUpdH/Y4Hrk6FNio/vBel6P6+zpaZ0fK7XlgGT7unUsIE HV57OndtbolbhbQABqI9FVzcKlgXgb6SbA== X-Google-Smtp-Source: ABdhPJzQAzLfuyfsmZ3KDCRGKs7De0i2DcinBAkt3kvcyzOFYJZYEaq1l0ayojY5pUgTUuxWG5o1+g== X-Received: by 2002:a17:90b:d82:: with SMTP id bg2mr13097210pjb.28.1626497806633; Fri, 16 Jul 2021 21:56:46 -0700 (PDT) Received: from shiro.work (p866038-ipngn200510sizuokaden.shizuoka.ocn.ne.jp. [180.9.60.38]) by smtp.googlemail.com with ESMTPSA id w2sm12522885pjf.2.2021.07.16.21.56.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Jul 2021 21:56:46 -0700 (PDT) From: Daniel Palmer To: devicetree@vger.kernel.org, linux-gpio@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linus.walleij@linaro.org, robh@kernel.org, romain.perier@gmail.com, Daniel Palmer Subject: [PATCH 02/10] dt-bindings: gpio: msc313: Add offsets for ssd20xd Date: Sat, 17 Jul 2021 13:56:19 +0900 Message-Id: <20210717045627.1739959-3-daniel@0x0f.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210717045627.1739959-1-daniel@0x0f.com> References: <20210717045627.1739959-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the gpio offsets for the SSD201 and SSD202D chips. Signed-off-by: Daniel Palmer Reviewed-by: Linus Walleij --- include/dt-bindings/gpio/msc313-gpio.h | 71 ++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/include/dt-bindings/gpio/msc313-gpio.h b/include/dt-bindings/gpio/msc313-gpio.h index 2dd56683d3c1..5458c6580a02 100644 --- a/include/dt-bindings/gpio/msc313-gpio.h +++ b/include/dt-bindings/gpio/msc313-gpio.h @@ -50,4 +50,75 @@ #define MSC313_GPIO_SPI0_DI (MSC313_GPIO_SPI0 + 2) #define MSC313_GPIO_SPI0_DO (MSC313_GPIO_SPI0 + 3) +/* SSD20x */ +#define SSD20XD_GPIO_FUART 0 +#define SSD20XD_GPIO_FUART_RX (SSD20XD_GPIO_FUART + 0) +#define SSD20XD_GPIO_FUART_TX (SSD20XD_GPIO_FUART + 1) +#define SSD20XD_GPIO_FUART_CTS (SSD20XD_GPIO_FUART + 2) +#define SSD20XD_GPIO_FUART_RTS (SSD20XD_GPIO_FUART + 3) + +#define SSD20XD_GPIO_SD (SSD20XD_GPIO_FUART_RTS + 1) +#define SSD20XD_GPIO_SD_CLK (SSD20XD_GPIO_SD + 0) +#define SSD20XD_GPIO_SD_CMD (SSD20XD_GPIO_SD + 1) +#define SSD20XD_GPIO_SD_D0 (SSD20XD_GPIO_SD + 2) +#define SSD20XD_GPIO_SD_D1 (SSD20XD_GPIO_SD + 3) +#define SSD20XD_GPIO_SD_D2 (SSD20XD_GPIO_SD + 4) +#define SSD20XD_GPIO_SD_D3 (SSD20XD_GPIO_SD + 5) + +#define SSD20XD_GPIO_UART0 (SSD20XD_GPIO_SD_D3 + 1) +#define SSD20XD_GPIO_UART0_RX (SSD20XD_GPIO_UART0 + 0) +#define SSD20XD_GPIO_UART0_TX (SSD20XD_GPIO_UART0 + 1) + +#define SSD20XD_GPIO_UART1 (SSD20XD_GPIO_UART0_TX + 1) +#define SSD20XD_GPIO_UART1_RX (SSD20XD_GPIO_UART1 + 0) +#define SSD20XD_GPIO_UART1_TX (SSD20XD_GPIO_UART1 + 1) + +#define SSD20XD_GPIO_TTL (SSD20XD_GPIO_UART1_TX + 1) +#define SSD20XD_GPIO_TTL0 (SSD20XD_GPIO_TTL + 0) +#define SSD20XD_GPIO_TTL1 (SSD20XD_GPIO_TTL + 1) +#define SSD20XD_GPIO_TTL2 (SSD20XD_GPIO_TTL + 2) +#define SSD20XD_GPIO_TTL3 (SSD20XD_GPIO_TTL + 3) +#define SSD20XD_GPIO_TTL4 (SSD20XD_GPIO_TTL + 4) +#define SSD20XD_GPIO_TTL5 (SSD20XD_GPIO_TTL + 5) +#define SSD20XD_GPIO_TTL6 (SSD20XD_GPIO_TTL + 6) +#define SSD20XD_GPIO_TTL7 (SSD20XD_GPIO_TTL + 7) +#define SSD20XD_GPIO_TTL8 (SSD20XD_GPIO_TTL + 8) +#define SSD20XD_GPIO_TTL9 (SSD20XD_GPIO_TTL + 9) +#define SSD20XD_GPIO_TTL10 (SSD20XD_GPIO_TTL + 10) +#define SSD20XD_GPIO_TTL11 (SSD20XD_GPIO_TTL + 11) +#define SSD20XD_GPIO_TTL12 (SSD20XD_GPIO_TTL + 12) +#define SSD20XD_GPIO_TTL13 (SSD20XD_GPIO_TTL + 13) +#define SSD20XD_GPIO_TTL14 (SSD20XD_GPIO_TTL + 14) +#define SSD20XD_GPIO_TTL15 (SSD20XD_GPIO_TTL + 15) +#define SSD20XD_GPIO_TTL16 (SSD20XD_GPIO_TTL + 16) +#define SSD20XD_GPIO_TTL17 (SSD20XD_GPIO_TTL + 17) +#define SSD20XD_GPIO_TTL18 (SSD20XD_GPIO_TTL + 18) +#define SSD20XD_GPIO_TTL19 (SSD20XD_GPIO_TTL + 19) +#define SSD20XD_GPIO_TTL20 (SSD20XD_GPIO_TTL + 20) +#define SSD20XD_GPIO_TTL21 (SSD20XD_GPIO_TTL + 21) +#define SSD20XD_GPIO_TTL22 (SSD20XD_GPIO_TTL + 22) +#define SSD20XD_GPIO_TTL23 (SSD20XD_GPIO_TTL + 23) +#define SSD20XD_GPIO_TTL24 (SSD20XD_GPIO_TTL + 24) +#define SSD20XD_GPIO_TTL25 (SSD20XD_GPIO_TTL + 25) +#define SSD20XD_GPIO_TTL26 (SSD20XD_GPIO_TTL + 26) +#define SSD20XD_GPIO_TTL27 (SSD20XD_GPIO_TTL + 27) + +#define SSD20XD_GPIO_GPIO (SSD20XD_GPIO_TTL27 + 1) +#define SSD20XD_GPIO_GPIO0 (SSD20XD_GPIO_GPIO + 0) +#define SSD20XD_GPIO_GPIO1 (SSD20XD_GPIO_GPIO + 1) +#define SSD20XD_GPIO_GPIO2 (SSD20XD_GPIO_GPIO + 2) +#define SSD20XD_GPIO_GPIO3 (SSD20XD_GPIO_GPIO + 3) +#define SSD20XD_GPIO_GPIO4 (SSD20XD_GPIO_GPIO + 4) +#define SSD20XD_GPIO_GPIO5 (SSD20XD_GPIO_GPIO + 5) +#define SSD20XD_GPIO_GPIO6 (SSD20XD_GPIO_GPIO + 6) +#define SSD20XD_GPIO_GPIO7 (SSD20XD_GPIO_GPIO + 7) +#define SSD20XD_GPIO_GPIO10 (SSD20XD_GPIO_GPIO + 8) +#define SSD20XD_GPIO_GPIO11 (SSD20XD_GPIO_GPIO + 9) +#define SSD20XD_GPIO_GPIO12 (SSD20XD_GPIO_GPIO + 10) +#define SSD20XD_GPIO_GPIO13 (SSD20XD_GPIO_GPIO + 11) +#define SSD20XD_GPIO_GPIO14 (SSD20XD_GPIO_GPIO + 12) +#define SSD20XD_GPIO_GPIO85 (SSD20XD_GPIO_GPIO + 13) +#define SSD20XD_GPIO_GPIO86 (SSD20XD_GPIO_GPIO + 14) +#define SSD20XD_GPIO_GPIO90 (SSD20XD_GPIO_GPIO + 15) + #endif /* _DT_BINDINGS_MSC313_GPIO_H */ From patchwork Sat Jul 17 04:56:20 2021 Content-Type: text/plain; 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[180.9.60.38]) by smtp.googlemail.com with ESMTPSA id w2sm12522885pjf.2.2021.07.16.21.56.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Jul 2021 21:56:48 -0700 (PDT) From: Daniel Palmer To: devicetree@vger.kernel.org, linux-gpio@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linus.walleij@linaro.org, robh@kernel.org, romain.perier@gmail.com, Daniel Palmer Subject: [PATCH 03/10] gpio: msc313: Code clean ups Date: Sat, 17 Jul 2021 13:56:20 +0900 Message-Id: <20210717045627.1739959-4-daniel@0x0f.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210717045627.1739959-1-daniel@0x0f.com> References: <20210717045627.1739959-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org - Remove the unneeded assignment of ret before returning it. - Remove an unneeded blank line Signed-off-by: Daniel Palmer Reviewed-by: Linus Walleij --- drivers/gpio/gpio-msc313.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpio/gpio-msc313.c b/drivers/gpio/gpio-msc313.c index da31a5ff7a2b..a894bafbd4c3 100644 --- a/drivers/gpio/gpio-msc313.c +++ b/drivers/gpio/gpio-msc313.c @@ -344,7 +344,6 @@ static int msc313_gpio_probe(struct platform_device *pdev) struct irq_domain *parent_domain; struct device_node *parent_node; struct device *dev = &pdev->dev; - int ret; match_data = of_device_get_match_data(dev); if (!match_data) @@ -399,8 +398,7 @@ static int msc313_gpio_probe(struct platform_device *pdev) gpioirqchip->handler = handle_bad_irq; gpioirqchip->default_type = IRQ_TYPE_NONE; - ret = devm_gpiochip_add_data(dev, gpiochip, gpio); - return ret; + return devm_gpiochip_add_data(dev, gpiochip, gpio); } static int msc313_gpio_remove(struct platform_device *pdev) @@ -456,5 +454,4 @@ static struct platform_driver msc313_gpio_driver = { .probe = msc313_gpio_probe, .remove = msc313_gpio_remove, }; - builtin_platform_driver(msc313_gpio_driver); From patchwork Sat Jul 17 04:56:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 479366 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UPPERCASE_50_75, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C645C6377E for ; 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[180.9.60.38]) by smtp.googlemail.com with ESMTPSA id w2sm12522885pjf.2.2021.07.16.21.56.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Jul 2021 21:56:51 -0700 (PDT) From: Daniel Palmer To: devicetree@vger.kernel.org, linux-gpio@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linus.walleij@linaro.org, robh@kernel.org, romain.perier@gmail.com, Daniel Palmer Subject: [PATCH 04/10] gpio: msc313: Add support for SSD201 and SSD202D Date: Sat, 17 Jul 2021 13:56:21 +0900 Message-Id: <20210717045627.1739959-5-daniel@0x0f.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210717045627.1739959-1-daniel@0x0f.com> References: <20210717045627.1739959-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds GPIO support for the SSD201 and SSD202D chips. Signed-off-by: Daniel Palmer Reviewed-by: Linus Walleij --- drivers/gpio/gpio-msc313.c | 261 +++++++++++++++++++++++++++++++++++++ 1 file changed, 261 insertions(+) diff --git a/drivers/gpio/gpio-msc313.c b/drivers/gpio/gpio-msc313.c index a894bafbd4c3..b2c90bdd39d0 100644 --- a/drivers/gpio/gpio-msc313.c +++ b/drivers/gpio/gpio-msc313.c @@ -221,6 +221,263 @@ static const unsigned int msc313_offsets[] = { }; MSC313_GPIO_CHIPDATA(msc313); + +/* + * Unlike the msc313(e) the ssd20xd have a bunch of pins + * that are actually called gpio probably because they + * have no dedicated function. + */ +#define SSD20XD_PINNAME_GPIO0 "gpio0" +#define SSD20XD_PINNAME_GPIO1 "gpio1" +#define SSD20XD_PINNAME_GPIO2 "gpio2" +#define SSD20XD_PINNAME_GPIO3 "gpio3" +#define SSD20XD_PINNAME_GPIO4 "gpio4" +#define SSD20XD_PINNAME_GPIO5 "gpio5" +#define SSD20XD_PINNAME_GPIO6 "gpio6" +#define SSD20XD_PINNAME_GPIO7 "gpio7" +#define SSD20XD_PINNAME_GPIO10 "gpio10" +#define SSD20XD_PINNAME_GPIO11 "gpio11" +#define SSD20XD_PINNAME_GPIO12 "gpio12" +#define SSD20XD_PINNAME_GPIO13 "gpio13" +#define SSD20XD_PINNAME_GPIO14 "gpio14" +#define SSD20XD_PINNAME_GPIO85 "gpio85" +#define SSD20XD_PINNAME_GPIO86 "gpio86" +#define SSD20XD_PINNAME_GPIO90 "gpio90" + +#define SSD20XD_GPIO_NAMES SSD20XD_PINNAME_GPIO0, \ + SSD20XD_PINNAME_GPIO1, \ + SSD20XD_PINNAME_GPIO2, \ + SSD20XD_PINNAME_GPIO3, \ + SSD20XD_PINNAME_GPIO4, \ + SSD20XD_PINNAME_GPIO5, \ + SSD20XD_PINNAME_GPIO6, \ + SSD20XD_PINNAME_GPIO7, \ + SSD20XD_PINNAME_GPIO10, \ + SSD20XD_PINNAME_GPIO11, \ + SSD20XD_PINNAME_GPIO12, \ + SSD20XD_PINNAME_GPIO13, \ + SSD20XD_PINNAME_GPIO14, \ + SSD20XD_PINNAME_GPIO85, \ + SSD20XD_PINNAME_GPIO86, \ + SSD20XD_PINNAME_GPIO90 + +#define SSD20XD_GPIO_OFF_GPIO0 0x0 +#define SSD20XD_GPIO_OFF_GPIO1 0x4 +#define SSD20XD_GPIO_OFF_GPIO2 0x8 +#define SSD20XD_GPIO_OFF_GPIO3 0xc +#define SSD20XD_GPIO_OFF_GPIO4 0x10 +#define SSD20XD_GPIO_OFF_GPIO5 0x14 +#define SSD20XD_GPIO_OFF_GPIO6 0x18 +#define SSD20XD_GPIO_OFF_GPIO7 0x1c +#define SSD20XD_GPIO_OFF_GPIO10 0x28 +#define SSD20XD_GPIO_OFF_GPIO11 0x2c +#define SSD20XD_GPIO_OFF_GPIO12 0x30 +#define SSD20XD_GPIO_OFF_GPIO13 0x34 +#define SSD20XD_GPIO_OFF_GPIO14 0x38 +#define SSD20XD_GPIO_OFF_GPIO85 0x100 +#define SSD20XD_GPIO_OFF_GPIO86 0x104 +#define SSD20XD_GPIO_OFF_GPIO90 0x114 + +#define SSD20XD_GPIO_OFFSETS SSD20XD_GPIO_OFF_GPIO0, \ + SSD20XD_GPIO_OFF_GPIO1, \ + SSD20XD_GPIO_OFF_GPIO2, \ + SSD20XD_GPIO_OFF_GPIO3, \ + SSD20XD_GPIO_OFF_GPIO4, \ + SSD20XD_GPIO_OFF_GPIO5, \ + SSD20XD_GPIO_OFF_GPIO6, \ + SSD20XD_GPIO_OFF_GPIO7, \ + SSD20XD_GPIO_OFF_GPIO10, \ + SSD20XD_GPIO_OFF_GPIO11, \ + SSD20XD_GPIO_OFF_GPIO12, \ + SSD20XD_GPIO_OFF_GPIO13, \ + SSD20XD_GPIO_OFF_GPIO14, \ + SSD20XD_GPIO_OFF_GPIO85, \ + SSD20XD_GPIO_OFF_GPIO86, \ + SSD20XD_GPIO_OFF_GPIO90 + +/* "ttl" pins lcd interface pins */ +#define SSD20XD_PINNAME_TTL0 "ttl0" +#define SSD20XD_PINNAME_TTL1 "ttl1" +#define SSD20XD_PINNAME_TTL2 "ttl2" +#define SSD20XD_PINNAME_TTL3 "ttl3" +#define SSD20XD_PINNAME_TTL4 "ttl4" +#define SSD20XD_PINNAME_TTL5 "ttl5" +#define SSD20XD_PINNAME_TTL6 "ttl6" +#define SSD20XD_PINNAME_TTL7 "ttl7" +#define SSD20XD_PINNAME_TTL8 "ttl8" +#define SSD20XD_PINNAME_TTL9 "ttl9" +#define SSD20XD_PINNAME_TTL10 "ttl10" +#define SSD20XD_PINNAME_TTL11 "ttl11" +#define SSD20XD_PINNAME_TTL12 "ttl12" +#define SSD20XD_PINNAME_TTL13 "ttl13" +#define SSD20XD_PINNAME_TTL14 "ttl14" +#define SSD20XD_PINNAME_TTL15 "ttl15" +#define SSD20XD_PINNAME_TTL16 "ttl16" +#define SSD20XD_PINNAME_TTL17 "ttl17" +#define SSD20XD_PINNAME_TTL18 "ttl18" +#define SSD20XD_PINNAME_TTL19 "ttl19" +#define SSD20XD_PINNAME_TTL20 "ttl20" +#define SSD20XD_PINNAME_TTL21 "ttl21" +#define SSD20XD_PINNAME_TTL22 "ttl22" +#define SSD20XD_PINNAME_TTL23 "ttl23" +#define SSD20XD_PINNAME_TTL24 "ttl24" +#define SSD20XD_PINNAME_TTL25 "ttl25" +#define SSD20XD_PINNAME_TTL26 "ttl26" +#define SSD20XD_PINNAME_TTL27 "ttl27" + +#define SSD20XD_TTL_PINNAMES SSD20XD_PINNAME_TTL0, \ + SSD20XD_PINNAME_TTL1, \ + SSD20XD_PINNAME_TTL2, \ + SSD20XD_PINNAME_TTL3, \ + SSD20XD_PINNAME_TTL4, \ + SSD20XD_PINNAME_TTL5, \ + SSD20XD_PINNAME_TTL6, \ + SSD20XD_PINNAME_TTL7, \ + SSD20XD_PINNAME_TTL8, \ + SSD20XD_PINNAME_TTL9, \ + SSD20XD_PINNAME_TTL10, \ + SSD20XD_PINNAME_TTL11, \ + SSD20XD_PINNAME_TTL12, \ + SSD20XD_PINNAME_TTL13, \ + SSD20XD_PINNAME_TTL14, \ + SSD20XD_PINNAME_TTL15, \ + SSD20XD_PINNAME_TTL16, \ + SSD20XD_PINNAME_TTL17, \ + SSD20XD_PINNAME_TTL18, \ + SSD20XD_PINNAME_TTL19, \ + SSD20XD_PINNAME_TTL20, \ + SSD20XD_PINNAME_TTL21, \ + SSD20XD_PINNAME_TTL22, \ + SSD20XD_PINNAME_TTL23, \ + SSD20XD_PINNAME_TTL24, \ + SSD20XD_PINNAME_TTL25, \ + SSD20XD_PINNAME_TTL26, \ + SSD20XD_PINNAME_TTL27 + +#define SSD20XD_TTL_OFFSET_TTL0 0x80 +#define SSD20XD_TTL_OFFSET_TTL1 0x84 +#define SSD20XD_TTL_OFFSET_TTL2 0x88 +#define SSD20XD_TTL_OFFSET_TTL3 0x8c +#define SSD20XD_TTL_OFFSET_TTL4 0x90 +#define SSD20XD_TTL_OFFSET_TTL5 0x94 +#define SSD20XD_TTL_OFFSET_TTL6 0x98 +#define SSD20XD_TTL_OFFSET_TTL7 0x9c +#define SSD20XD_TTL_OFFSET_TTL8 0xa0 +#define SSD20XD_TTL_OFFSET_TTL9 0xa4 +#define SSD20XD_TTL_OFFSET_TTL10 0xa8 +#define SSD20XD_TTL_OFFSET_TTL11 0xac +#define SSD20XD_TTL_OFFSET_TTL12 0xb0 +#define SSD20XD_TTL_OFFSET_TTL13 0xb4 +#define SSD20XD_TTL_OFFSET_TTL14 0xb8 +#define SSD20XD_TTL_OFFSET_TTL15 0xbc +#define SSD20XD_TTL_OFFSET_TTL16 0xc0 +#define SSD20XD_TTL_OFFSET_TTL17 0xc4 +#define SSD20XD_TTL_OFFSET_TTL18 0xc8 +#define SSD20XD_TTL_OFFSET_TTL19 0xcc +#define SSD20XD_TTL_OFFSET_TTL20 0xd0 +#define SSD20XD_TTL_OFFSET_TTL21 0xd4 +#define SSD20XD_TTL_OFFSET_TTL22 0xd8 +#define SSD20XD_TTL_OFFSET_TTL23 0xdc +#define SSD20XD_TTL_OFFSET_TTL24 0xe0 +#define SSD20XD_TTL_OFFSET_TTL25 0xe4 +#define SSD20XD_TTL_OFFSET_TTL26 0xe8 +#define SSD20XD_TTL_OFFSET_TTL27 0xec + +#define SSD20XD_TTL_OFFSETS SSD20XD_TTL_OFFSET_TTL0, \ + SSD20XD_TTL_OFFSET_TTL1, \ + SSD20XD_TTL_OFFSET_TTL2, \ + SSD20XD_TTL_OFFSET_TTL3, \ + SSD20XD_TTL_OFFSET_TTL4, \ + SSD20XD_TTL_OFFSET_TTL5, \ + SSD20XD_TTL_OFFSET_TTL6, \ + SSD20XD_TTL_OFFSET_TTL7, \ + SSD20XD_TTL_OFFSET_TTL8, \ + SSD20XD_TTL_OFFSET_TTL9, \ + SSD20XD_TTL_OFFSET_TTL10, \ + SSD20XD_TTL_OFFSET_TTL11, \ + SSD20XD_TTL_OFFSET_TTL12, \ + SSD20XD_TTL_OFFSET_TTL13, \ + SSD20XD_TTL_OFFSET_TTL14, \ + SSD20XD_TTL_OFFSET_TTL15, \ + SSD20XD_TTL_OFFSET_TTL16, \ + SSD20XD_TTL_OFFSET_TTL17, \ + SSD20XD_TTL_OFFSET_TTL18, \ + SSD20XD_TTL_OFFSET_TTL19, \ + SSD20XD_TTL_OFFSET_TTL20, \ + SSD20XD_TTL_OFFSET_TTL21, \ + SSD20XD_TTL_OFFSET_TTL22, \ + SSD20XD_TTL_OFFSET_TTL23, \ + SSD20XD_TTL_OFFSET_TTL24, \ + SSD20XD_TTL_OFFSET_TTL25, \ + SSD20XD_TTL_OFFSET_TTL26, \ + SSD20XD_TTL_OFFSET_TTL27 + +/* On the ssd20xd the two normal uarts have dedicated pins */ +#define SSD20XD_PINNAME_UART0_RX "uart0_rx" +#define SSD20XD_PINNAME_UART0_TX "uart0_tx" + +#define SSD20XD_UART0_NAMES \ + SSD20XD_PINNAME_UART0_RX, \ + SSD20XD_PINNAME_UART0_TX + +#define SSD20XD_PINNAME_UART1_RX "uart1_rx" +#define SSD20XD_PINNAME_UART1_TX "uart1_tx" + +#define SSD20XD_UART1_NAMES \ + SSD20XD_PINNAME_UART1_RX, \ + SSD20XD_PINNAME_UART1_TX + +#define SSD20XD_OFF_UART0_RX 0x60 +#define SSD20XD_OFF_UART0_TX 0x64 + +#define SSD20XD_UART0_OFFSETS \ + SSD20XD_OFF_UART0_RX, \ + SSD20XD_OFF_UART0_TX + +#define SSD20XD_OFF_UART1_RX 0x68 +#define SSD20XD_OFF_UART1_TX 0x6c + +#define SSD20XD_UART1_OFFSETS \ + SSD20XD_OFF_UART1_RX, \ + SSD20XD_OFF_UART1_TX + +/* + * ssd20x has the same pin names but different ordering + * of the registers that control the gpio. + */ +#define SSD20XD_OFF_SD_D0 0x140 +#define SSD20XD_OFF_SD_D1 0x144 +#define SSD20XD_OFF_SD_D2 0x148 +#define SSD20XD_OFF_SD_D3 0x14c +#define SSD20XD_OFF_SD_CMD 0x150 +#define SSD20XD_OFF_SD_CLK 0x154 + +#define SSD20XD_SD_OFFSETS SSD20XD_OFF_SD_CLK, \ + SSD20XD_OFF_SD_CMD, \ + SSD20XD_OFF_SD_D0, \ + SSD20XD_OFF_SD_D1, \ + SSD20XD_OFF_SD_D2, \ + SSD20XD_OFF_SD_D3 + +static const char * const ssd20xd_names[] = { + FUART_NAMES, + SD_NAMES, + SSD20XD_UART0_NAMES, + SSD20XD_UART1_NAMES, + SSD20XD_TTL_PINNAMES, + SSD20XD_GPIO_NAMES, +}; + +static const unsigned int ssd20xd_offsets[] = { + FUART_OFFSETS, + SSD20XD_SD_OFFSETS, + SSD20XD_UART0_OFFSETS, + SSD20XD_UART1_OFFSETS, + SSD20XD_TTL_OFFSETS, + SSD20XD_GPIO_OFFSETS, +}; + +MSC313_GPIO_CHIPDATA(ssd20xd); #endif struct msc313_gpio { @@ -412,6 +669,10 @@ static const struct of_device_id msc313_gpio_of_match[] = { .compatible = "mstar,msc313-gpio", .data = &msc313_data, }, + { + .compatible = "sstar,ssd20xd-gpio", + .data = &ssd20xd_data, + }, #endif { } }; From patchwork Sat Jul 17 04:56:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 479367 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, 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[180.9.60.38]) by smtp.googlemail.com with ESMTPSA id w2sm12522885pjf.2.2021.07.16.21.56.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Jul 2021 21:56:53 -0700 (PDT) From: Daniel Palmer To: devicetree@vger.kernel.org, linux-gpio@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linus.walleij@linaro.org, robh@kernel.org, romain.perier@gmail.com, Daniel Palmer Subject: [PATCH 05/10] ARM: dts: mstar: Set gpio compatible for ssd20xd Date: Sat, 17 Jul 2021 13:56:22 +0900 Message-Id: <20210717045627.1739959-6-daniel@0x0f.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210717045627.1739959-1-daniel@0x0f.com> References: <20210717045627.1739959-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Now there is gpio support for ssd20xd set the right compatible in the gpio node. Signed-off-by: Daniel Palmer Reviewed-by: Linus Walleij Reviewed-by: Romain Perier --- arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi index 7a5e28b33f96..6f067da61ba3 100644 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd20xd.dtsi @@ -6,6 +6,11 @@ #include "mstar-infinity2m.dtsi" +&gpio { + compatible = "sstar,ssd20xd-gpio"; + status = "okay"; +}; + &smpctrl { compatible = "sstar,ssd201-smpctrl", "mstar,smpctrl"; status = "okay"; From patchwork Sat Jul 17 04:56:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 479691 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1737C63797 for ; Sat, 17 Jul 2021 04:57:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D9BE1613F2 for ; Sat, 17 Jul 2021 04:57:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231881AbhGQFAF (ORCPT ); Sat, 17 Jul 2021 01:00:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231311AbhGQE7x (ORCPT ); Sat, 17 Jul 2021 00:59:53 -0400 Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE132C061762 for ; Fri, 16 Jul 2021 21:56:56 -0700 (PDT) Received: by mail-pf1-x42b.google.com with SMTP id c1so6784366pfc.13 for ; Fri, 16 Jul 2021 21:56:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CW8+X4ven8LE6a628SvByr7Eb90cm9U9YeyKIDh8Q0I=; b=vxfNy/AVZ2+QtClGwq8aphvCDom0KQ6+D54xbcCEyp10nVFZuz4ofBkxLr2Xx+GH9T QterhwEbaVV7GJtHyyLELiZuvkXDkmmrLVCUTZ+vPddBKWzz5C7DDT0FLkNmJJLxpLnM EhS1rQ/fqr6rmqWzb/71ghhzoe1U9S1ZyVCls= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CW8+X4ven8LE6a628SvByr7Eb90cm9U9YeyKIDh8Q0I=; b=Z0MgsR9+NCBrn7GpZyT2ArwrxYcnqYO7Xb4n04qsFepuqU34KmA6AletqVQvSIcgVX vXSHfjiNT+ofEr9XTnLRKX0ltYtn7kAeZ5UK7bnc6VfE+GSHsrMydk1AOIsvqB8xd6BP rdU26DTWr/+R6XljCet3tGAmr1XR8PaziCVd/rxPWWkmcnyHLKLFR4j7VFFWMxsSTc28 42vsgx7bEjqZjVrh9cu6V3ye+goZJSTliZFP2oD55ueK7krKC3XLHryJjX8xAZ4/q7Lg DAIqYlcMyKQtmzIE+6fEtVl6KwWJLx590gMMtOGOwpunSo/0rbUAT/tjTvGm4Ey9L0Pn 58jA== X-Gm-Message-State: AOAM530JJAZ0jCckPlNYmEqYUk2bhEF9e3Jh0sRl7JQT6SS0R0dQ0qB6 8T/URf73xtQJbSOZP884ME64elOf//GPyQ== X-Google-Smtp-Source: ABdhPJzgkcSKDtEoe0QjGr6QO+9bk6MMOGNJF814v3oQIO5dHPK0v+De5Ul7P+A78cES5+y0x51sIA== X-Received: by 2002:a63:471b:: with SMTP id u27mr13626075pga.301.1626497816200; Fri, 16 Jul 2021 21:56:56 -0700 (PDT) Received: from shiro.work (p866038-ipngn200510sizuokaden.shizuoka.ocn.ne.jp. [180.9.60.38]) by smtp.googlemail.com with ESMTPSA id w2sm12522885pjf.2.2021.07.16.21.56.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Jul 2021 21:56:55 -0700 (PDT) From: Daniel Palmer To: devicetree@vger.kernel.org, linux-gpio@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linus.walleij@linaro.org, robh@kernel.org, romain.perier@gmail.com, Daniel Palmer Subject: [PATCH 06/10] ARM: dts: mstar: unitv2: Wire up LEDs Date: Sat, 17 Jul 2021 13:56:23 +0900 Message-Id: <20210717045627.1739959-7-daniel@0x0f.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210717045627.1739959-1-daniel@0x0f.com> References: <20210717045627.1739959-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the red and white leds present on the unitv2. Signed-off-by: Daniel Palmer --- .../boot/dts/mstar-infinity2m-ssd202d-unitv2.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts index a81684002e45..eb35ce00ae50 100644 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts @@ -7,6 +7,8 @@ /dts-v1/; #include "mstar-infinity2m-ssd202d.dtsi" +#include + / { model = "UnitV2"; compatible = "m5stack,unitv2", "mstar,infinity2m"; @@ -18,6 +20,18 @@ aliases { chosen { stdout-path = "serial0:115200n8"; }; + + leds { + compatible = "gpio-leds"; + white { + gpios = <&gpio SSD20XD_GPIO_GPIO0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "activity"; + }; + red { + gpios = <&gpio SSD20XD_GPIO_GPIO1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; }; &pm_uart { From patchwork Sat Jul 17 04:56:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 479689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1F49C636CB for ; Sat, 17 Jul 2021 04:57:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A9C46613DF for ; Sat, 17 Jul 2021 04:57:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232195AbhGQFAG (ORCPT ); Sat, 17 Jul 2021 01:00:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231387AbhGQE74 (ORCPT ); Sat, 17 Jul 2021 00:59:56 -0400 Received: from mail-pg1-x52f.google.com (mail-pg1-x52f.google.com [IPv6:2607:f8b0:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3285CC061762 for ; Fri, 16 Jul 2021 21:56:59 -0700 (PDT) Received: by mail-pg1-x52f.google.com with SMTP id t9so12053436pgn.4 for ; Fri, 16 Jul 2021 21:56:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SIrdVgz9P1mE1bbJ+kfNCJNaaulCoo7DUfLJr8XjKBo=; b=HO/58JAdAa1iyc4hzq0WIwFcfnVHoRaUS0npx45UKuwfov7YLlcPLPag0Xb11NS/km 0M5/p1WMbr/uIyQtXX5ZOadMgh7jQvoXASYUuuIzzQx6K9m9YXQ24dG0abMQtvZti+Dt 11WbQpOMhxzCjVkEpKR8wTuh6eeiGDaDeIYlc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SIrdVgz9P1mE1bbJ+kfNCJNaaulCoo7DUfLJr8XjKBo=; b=Px41eRNSsa64f/NGu3UVs0mqjMMCEUaEqp9JclUfs31MsBywMGAvE+5D31qiu4mgUZ ro1EZbvQA07+/WXisqpbUdhW+uhH9ICiLq4h0GDX434YTbJ8ekb8D/Qpo5IZTVqX7Kuz WGaDuH+DtDq0db30zDeubUhJFSw3i7e+0mZpuNjUrc21vdsWQbHYHZBpLrtr0O04NgES ehpsTc6w2vPsPp01FMfZkPMWz/AGFP+gpRG9jMzr+0fKGXSAB1uHdzuCylHxNw0zUUle aCZD/ekkBu2Efi5ia9TwMgvq51H/5L+eltQe113yfi8ec2MU2H8kjmgQS+xRroE4D1fH Gp8g== X-Gm-Message-State: AOAM530J6FhITC23hvAKwFOho4fU3Jl5Q6orGbk/YSzrHzBeVrh+VqAy 8R+YZtgbNsn6fiFkJHSJp9csP/vUzLDXNA== X-Google-Smtp-Source: ABdhPJwhoL+9Laz0mhJCLoufLpGxSrkIU6xn/FGH+LSJ2Pqm0A1vzWuWygoUi/8F02eZrG8kex0E0Q== X-Received: by 2002:a65:6909:: with SMTP id s9mr7074493pgq.321.1626497818629; Fri, 16 Jul 2021 21:56:58 -0700 (PDT) Received: from shiro.work (p866038-ipngn200510sizuokaden.shizuoka.ocn.ne.jp. [180.9.60.38]) by smtp.googlemail.com with ESMTPSA id w2sm12522885pjf.2.2021.07.16.21.56.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Jul 2021 21:56:58 -0700 (PDT) From: Daniel Palmer To: devicetree@vger.kernel.org, linux-gpio@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linus.walleij@linaro.org, robh@kernel.org, romain.perier@gmail.com, Daniel Palmer Subject: [PATCH 07/10] ARM: dts: mstar: unitv2: Add core regulator Date: Sat, 17 Jul 2021 13:56:24 +0900 Message-Id: <20210717045627.1739959-8-daniel@0x0f.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210717045627.1739959-1-daniel@0x0f.com> References: <20210717045627.1739959-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a fixed regulator for the "core" (mainly CPU) voltage. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts index eb35ce00ae50..4a22b82afbfd 100644 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts @@ -32,6 +32,14 @@ red { linux,default-trigger = "heartbeat"; }; }; + + vcc_core: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_core"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + }; }; &pm_uart { From patchwork Sat Jul 17 04:56:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 479365 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C860C636C9 for ; Sat, 17 Jul 2021 04:57:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 170A2613DF for ; Sat, 17 Jul 2021 04:57:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231228AbhGQFAH (ORCPT ); Sat, 17 Jul 2021 01:00:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231424AbhGQE76 (ORCPT ); Sat, 17 Jul 2021 00:59:58 -0400 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C368C061762 for ; Fri, 16 Jul 2021 21:57:01 -0700 (PDT) Received: by mail-pf1-x42a.google.com with SMTP id b12so10618619pfv.6 for ; Fri, 16 Jul 2021 21:57:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ui/R1U5l18hTCdlid6Ebs6NC2kv3Eus6s2OeRFbkggQ=; b=M3Job59J4FMxogVCzqxuA9l7bcCRG88yvg7g84YKnqUdBepNOkTn4a6BBNd3iE6gPl AIYATL5ep6ERsyMTBwQ+8/MiSv1qlwDl+XgnifDeB4XweAIosjb3Njc1IgMhTuLwTaX2 DjWwNH8X75Aai0HBj8L4iIW+czdj/qDipUaHk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ui/R1U5l18hTCdlid6Ebs6NC2kv3Eus6s2OeRFbkggQ=; b=dGgZWzhzCTsbYpwGV+d666gDOO0goeGPYupbM7sIgvlMAyePLDExaoGaPlkM0kL/Jn SdEdWu+vBB3KyaAT21b/c3Zeq2BM5i8qliEMPcry9BqCtkrTO0e09T2zM7g/msmWsoVc DBiboJvB5WFDh/xyM6kxD1Gf1aG7N0cx4LRJruetcv55S7Izq1SYAxGHqXQmndumCNSZ oSq/6NuL7ZrTcv5B1aAEvmvKYt8WIFhYeOptQ3DOfQFimFPO6sXijBGGbUVdiJqHikWR F9EJx3ZoUsK5pOYYQHV7wHC5AO93Ta/xGVhHGFYF4JNLV2HP3GeoVA69ZzQVf6jcp9O4 0uIg== X-Gm-Message-State: AOAM5327d0Y4r3/peEj52owWOb44BTNaJvx8Fqu/YUJpdZsAJu1G4Iid pc+fhO7oWzcUiWp6JI5bY7RyjFUetq9ZLw== X-Google-Smtp-Source: ABdhPJygKPBQmyujuMeB5sbOzlu/tuUJQXYPb+lFjw7HhEPaF8ZO+94Mqw/NeeciMC9BVKaKsC6HUQ== X-Received: by 2002:a65:6243:: with SMTP id q3mr13446911pgv.297.1626497821027; Fri, 16 Jul 2021 21:57:01 -0700 (PDT) Received: from shiro.work (p866038-ipngn200510sizuokaden.shizuoka.ocn.ne.jp. [180.9.60.38]) by smtp.googlemail.com with ESMTPSA id w2sm12522885pjf.2.2021.07.16.21.56.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Jul 2021 21:57:00 -0700 (PDT) From: Daniel Palmer To: devicetree@vger.kernel.org, linux-gpio@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linus.walleij@linaro.org, robh@kernel.org, romain.perier@gmail.com, Daniel Palmer Subject: [PATCH 08/10] ARM: dts: mstar: unitv2: Add io regulator Date: Sat, 17 Jul 2021 13:56:25 +0900 Message-Id: <20210717045627.1739959-9-daniel@0x0f.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210717045627.1739959-1-daniel@0x0f.com> References: <20210717045627.1739959-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a fixed regulator for the io voltage. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts index 4a22b82afbfd..314eb37d3be4 100644 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts @@ -40,6 +40,14 @@ vcc_core: regulator@0 { regulator-max-microvolt = <900000>; regulator-boot-on; }; + + vcc_io: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; }; &pm_uart { From patchwork Sat Jul 17 04:56:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 479690 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0EA0C6377A for ; Sat, 17 Jul 2021 04:57:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D11D6613DF for ; Sat, 17 Jul 2021 04:57:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231424AbhGQFAH (ORCPT ); Sat, 17 Jul 2021 01:00:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231555AbhGQFAA (ORCPT ); Sat, 17 Jul 2021 01:00:00 -0400 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0ACD0C061762 for ; Fri, 16 Jul 2021 21:57:04 -0700 (PDT) Received: by mail-pg1-x529.google.com with SMTP id 62so12070828pgf.1 for ; Fri, 16 Jul 2021 21:57:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aku1qg6OU3VkZACTqq4vmZlt3chbHGMWW4QZeLwZZSg=; b=LcLL+C8eYZbYhw3JvlqOoeJEnqeODIylf+XTnwmmiZoBUYvnSsDWXCGLbG0S8ObCJB qfLNtHF2CbsYJ81RQdU8FyMlXysFfOk4C5KC33Mymo8n3gymMXdVbL50yX4WQBYRbcqC lKM1L5C6k3aNQm21Rj45+e4tVfLNCVQcRiFuw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aku1qg6OU3VkZACTqq4vmZlt3chbHGMWW4QZeLwZZSg=; b=idyL/4fcXuSsHN7ksMTD7I3+xl7jneKgAlVsMuoXI9F8x6DzE5NQFrmbROIn4MM1oS mFrit0z3BFS8P7nsDlQCdz9FmofimMUqcjU1BrKuJz85euW9NyueS/hu/v+06N3TpHJo ysZn3IbPwJmT7SqZov+Bs1EjaoHqbIJt2lOe9/u/yuqSOBhITKy2S/z37Ow4a6RWXspC S+Cw5+whNHhb1vhaw6QEeurfYWndyp+LE/Wq6ThiOzJ4hZE7mTU2o5baRrjsmJ/uJphg 6Vtg1Ea4FoVk78rekC9KYlPnwKuAdch4RlKzIhGIfD7eBsJYw51LeiC6n520d+keS7iG JMJQ== X-Gm-Message-State: AOAM532bHmR9kaQLxArqgwJmMSJLXt9FsEow6ivXPiaF7NqPTkHsV/Hs ZpxdR8Hcy9okFuXqkecT+jyWnADlGqJreA== X-Google-Smtp-Source: ABdhPJzLNjYppEScm4RrRKehVCzQIjY8SJ+2kzxPrP/Ozjyy/0VsyL0iMuEFoVBYVGerEj9wOF8R0g== X-Received: by 2002:a63:f64d:: with SMTP id u13mr13502036pgj.156.1626497823375; Fri, 16 Jul 2021 21:57:03 -0700 (PDT) Received: from shiro.work (p866038-ipngn200510sizuokaden.shizuoka.ocn.ne.jp. [180.9.60.38]) by smtp.googlemail.com with ESMTPSA id w2sm12522885pjf.2.2021.07.16.21.57.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Jul 2021 21:57:03 -0700 (PDT) From: Daniel Palmer To: devicetree@vger.kernel.org, linux-gpio@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linus.walleij@linaro.org, robh@kernel.org, romain.perier@gmail.com, Daniel Palmer Subject: [PATCH 09/10] ARM: dts: mstar: unitv2: Add DRAM regulator Date: Sat, 17 Jul 2021 13:56:26 +0900 Message-Id: <20210717045627.1739959-10-daniel@0x0f.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210717045627.1739959-1-daniel@0x0f.com> References: <20210717045627.1739959-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a fixed regulator for the DRAM voltage. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts index 314eb37d3be4..648751a1b27e 100644 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts @@ -48,6 +48,14 @@ vcc_io: regulator@1 { regulator-max-microvolt = <3300000>; regulator-boot-on; }; + + vcc_dram: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vcc_dram"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + }; }; &pm_uart { From patchwork Sat Jul 17 04:56:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 479364 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06C15C636C9 for ; Sat, 17 Jul 2021 04:57:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E5E3E61402 for ; Sat, 17 Jul 2021 04:57:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231657AbhGQFAS (ORCPT ); Sat, 17 Jul 2021 01:00:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37900 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231613AbhGQFAD (ORCPT ); Sat, 17 Jul 2021 01:00:03 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C8A0C061762 for ; Fri, 16 Jul 2021 21:57:06 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id my10so7529796pjb.1 for ; Fri, 16 Jul 2021 21:57:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iH5hOIug88dJD4ivQ2NqJKjZ3aauEwcovfQ35jFjeCY=; b=aXVtX2M6WCascZlHmLoPsu3liAWTk6yKEq2cnbAvh1AHSX5i+9MuCCI9Vz2B2axT2h WycmsN/R3vsh6zQgwhtmAZx8ce1Gno09qvSwNSjSuMfp2+3uiRF7MuwbN0M881Spt1tT 5hDbMgDi/L07LfN0M0VcmsN6YxpgnQvhhENB4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iH5hOIug88dJD4ivQ2NqJKjZ3aauEwcovfQ35jFjeCY=; b=dXDzGbkwcSzD8yI2gN9KUc8TRtVF90q3DAPr7o9zRjZgVAv48vxj///62TFLaWVadD 3zIHzdL1iAjN7BhidWIMrjDz2mMaOD/qqZLwvO88dChzDngB76IJ2up3ULne8M18PNeV k7blNfdcRbUldg1Cayh+a0MStxTFrgEK0hll3yQcIMDpyxQZcxaUXI5HXjzA9+q9sHJf EHYCfGkMC3kfI6enB7ttPsqTkS5c1YO6Iqa8YHCJgvq00farYtW4ftiEGDHc9bVl7g6C RAV6+06hIZJYO5BWJPOttClRf9YxD1wpA0TC3UTa9PKBW+rdLVdr6TWQ4rgLGyURrw2U l3SQ== X-Gm-Message-State: AOAM530l/9v3F9km1nC08w6/M6uZgiA9pcjdRMg6AhfrW2l1POT16ZMv dwGtFL6VHcgNSOC4SVx+B1zm+kWzgGpCJA== X-Google-Smtp-Source: ABdhPJxdUypLTJ2BGFwx4JvhhuK6TYm5Fi8cmR+3/peM5Zh23rIIOV1c6rkmsHihycY3XP2/cRv5Gw== X-Received: by 2002:a17:90a:cd01:: with SMTP id d1mr19035743pju.106.1626497825779; Fri, 16 Jul 2021 21:57:05 -0700 (PDT) Received: from shiro.work (p866038-ipngn200510sizuokaden.shizuoka.ocn.ne.jp. [180.9.60.38]) by smtp.googlemail.com with ESMTPSA id w2sm12522885pjf.2.2021.07.16.21.57.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Jul 2021 21:57:05 -0700 (PDT) From: Daniel Palmer To: devicetree@vger.kernel.org, linux-gpio@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linus.walleij@linaro.org, robh@kernel.org, romain.perier@gmail.com, Daniel Palmer Subject: [PATCH 10/10] ARM: dts: mstar: unitv2: Add wifi switch Date: Sat, 17 Jul 2021 13:56:27 +0900 Message-Id: <20210717045627.1739959-11-daniel@0x0f.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210717045627.1739959-1-daniel@0x0f.com> References: <20210717045627.1739959-1-daniel@0x0f.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a GPIO controlled fixed regulator for the Realtek WiFi connected via USB. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts index 648751a1b27e..525305a3e3ac 100644 --- a/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts +++ b/arch/arm/boot/dts/mstar-infinity2m-ssd202d-unitv2.dts @@ -56,6 +56,14 @@ vcc_dram: regulator@2 { regulator-max-microvolt = <1500000>; regulator-boot-on; }; + + vcc_wifi: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio SSD20XD_GPIO_GPIO14 0>; + }; }; &pm_uart {