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[209.51.188.17]) by mx.google.com with ESMTPS id v12si10259388qto.199.2021.07.17.15.22.37 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 17 Jul 2021 15:22:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=h2eO0gV3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40716 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m4shg-0004Dm-JL for patch@linaro.org; Sat, 17 Jul 2021 18:22:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54964) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m4se9-0006pR-UR for qemu-devel@nongnu.org; Sat, 17 Jul 2021 18:18:58 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:34304) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m4se7-0001yc-C0 for qemu-devel@nongnu.org; Sat, 17 Jul 2021 18:18:57 -0400 Received: by mail-pg1-x530.google.com with SMTP id 62so14574424pgf.1 for ; Sat, 17 Jul 2021 15:18:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ImN2rDIibPWqsxrjnxHa+huo1+KHTGHZlA26Q9cu+A8=; b=h2eO0gV3xligBMjC2kDqMUgnqnmQNHJKhVCc1X534ofr7XVIUMWQHIVRz12ZmGq3C6 z04PWOvASSanJwKBOYLdTXTQWcPuypBDqR5KLGTf+zSLjHe6dldXcoK/k2eseQBSYq6A ErYG0wzH9kWmT/LQQOIuqGvlJ+aSGgIVbCdEPmdnfy9HwopHHJ6VKlFqgvuTDjsk2Ti0 lCJbaRmPa8D/ofxazewakaL2NnmU35RbJhRDjNZNzuVOLz2fYBNQ/UddF1QviQh1zUHu JORDeUWIkxgwi9XVDM/Po+R/ZOcYwEMB9FCyk3zgPKRfYojM9uqeO46T5QRNdnu0IqY0 r5Sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ImN2rDIibPWqsxrjnxHa+huo1+KHTGHZlA26Q9cu+A8=; b=h10dQTollbKN+OQ4UfucJipD5i22xFDBO5KLExFZGrdAnYlWKZEb/vOc7pHp9PGpOV wy1WNKrjNAsZarat/R/SpoFdkAhBbax9V5P67M//3shmC2rMwrOreOUFpX2mHcqznhVH dLOWnd1PcsaFZfVM/xILE+BdJa0kNPDDhagb8kU3bIzMkaOo//viv3ddrN2JRpystqde eu2VWTom7flozoobPMNeLKLv+4aNR3hGFNjmJgyWz08G2KRA1fg995cZlQ3SQfjfjtmd C7nWHoJGHoLqjCMOK+uzNhuRbkD7oSa9kyA4nbTvdIgUP7OnnLFe2ZRKok99YPQzlj1A +bjg== X-Gm-Message-State: AOAM530RVCn4Bm9ayBit42KxGgHqe8WqK/5DkNNwi/bRBUt+qj3chW0Q OATvkZ7MGu7hiyvgIR63N8LTMRoNYgusqg== X-Received: by 2002:a05:6a00:14c4:b029:331:7474:cb4b with SMTP id w4-20020a056a0014c4b02903317474cb4bmr18023776pfu.30.1626560333464; Sat, 17 Jul 2021 15:18:53 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id n14sm2405091pjv.34.2021.07.17.15.18.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Jul 2021 15:18:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 01/13] accel/tcg: Reduce CF_COUNT_MASK to match TCG_MAX_INSNS Date: Sat, 17 Jul 2021 15:18:39 -0700 Message-Id: <20210717221851.2124573-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210717221851.2124573-1-richard.henderson@linaro.org> References: <20210717221851.2124573-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The space reserved for CF_COUNT_MASK was overly large. Reduce to free up cflags bits and eliminate an extra test. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 4 +++- accel/tcg/translate-all.c | 5 ++--- 2 files changed, 5 insertions(+), 4 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 754f4130c9..dfe82ed19c 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -492,7 +492,9 @@ struct TranslationBlock { target_ulong cs_base; /* CS base for this block */ uint32_t flags; /* flags defining in which context the code was generated */ uint32_t cflags; /* compile flags */ -#define CF_COUNT_MASK 0x00007fff + +/* Note that TCG_MAX_INSNS is 512; we validate this match elsewhere. */ +#define CF_COUNT_MASK 0x000001ff #define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ #define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */ #define CF_USE_ICOUNT 0x00020000 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 4df26de858..5cc01d693b 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1428,11 +1428,10 @@ TranslationBlock *tb_gen_code(CPUState *cpu, max_insns = cflags & CF_COUNT_MASK; if (max_insns == 0) { - max_insns = CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { max_insns = TCG_MAX_INSNS; } + QEMU_BUILD_BUG_ON(CF_COUNT_MASK + 1 != TCG_MAX_INSNS); + if (cpu->singlestep_enabled || singlestep) { max_insns = 1; } From patchwork Sat Jul 17 22:18:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 479259 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2745334jao; Sat, 17 Jul 2021 15:23:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz4s9bEPTuIxy8zpZUCj1OHNMyJZ+WEv/tloA3nuKkWgRoHYAColpOw6eUAUHI3psYpKxYW X-Received: by 2002:ac8:7b39:: with SMTP id l25mr10219186qtu.230.1626560592402; Sat, 17 Jul 2021 15:23:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626560592; cv=none; d=google.com; s=arc-20160816; b=TYwhufa/Gr6fE8ABFq7Y48ogeDvN1Et3KFhGgRvJV+Qg7MJjr+CPnF6UEwfBKB1UXG Y0EwSw8v3/J7JabD204JlBB4eQ8nfU4yh/JlwmC2sSadNkMgKjElnHimPOQnOWGrb4J4 wMGtlCyzSRGpcM4xqH/6Ay5fwT1kuXQNPr3xvF/VuSqwz0Pt3O7B07ptzsKPM1bJVbHJ TPnBP7OmZtN8ZhuNK1BKz27gYWY4qiniK1iHPo3IvAa0OmYgCspFbNqtzzLNQ303llfr haCkW86r82yxwZGRDDrffJjEVASs7sJPaviHzglcurTz7RAvCM3X/Q5CG41sz8lWTh39 m8/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=g6WC/1OFwmMEJWjhaux71v3WymnN3hUDPV/lnz7IXaA=; b=JmVjTmstwwptSjDlUWSqkBMTLCjC6bOVXh9GiYkBzQsFFXy5QPKHhPnId3q4vclP5d dX6g+VVxAdXQBDJt7ueW3GoCLHWuJTw13IKzyyVBkFFmZz4GRPyVF3pEKZatT5YmazRw ZgJ1V4qAqF5vgDdu6x8wlcZR85wwXIp8tx02wscrjfmG5mB7wJprv/TkOhqofS/Zc546 ALYmpja1diD90hzhKVYbJ9YmtJoRy2lZO1hrBAx2O053bOYXSD/tmV6A35KFYZk2PMOS pbTuYIwvtv8evazP6j/pIC5Vx3c4h+CVxn6VbpEmYa3PPQmhIadfxWl46wJSsiOUbp9I FsVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yT3ibeQm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f13si12326026qth.69.2021.07.17.15.23.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 17 Jul 2021 15:23:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yT3ibeQm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45432 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m4siF-0007YZ-Fj for patch@linaro.org; Sat, 17 Jul 2021 18:23:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55038) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m4seC-0006sS-3m for qemu-devel@nongnu.org; Sat, 17 Jul 2021 18:19:00 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:39575) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m4se8-0001yz-3T for qemu-devel@nongnu.org; Sat, 17 Jul 2021 18:18:59 -0400 Received: by mail-pj1-x102e.google.com with SMTP id p14-20020a17090ad30eb02901731c776526so11583186pju.4 for ; Sat, 17 Jul 2021 15:18:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=g6WC/1OFwmMEJWjhaux71v3WymnN3hUDPV/lnz7IXaA=; b=yT3ibeQmsaMWNd8m8STIiuyLKvQWRz66pufl9VG6X7+extxDVqGBPc9ik8G8cFIgIB OmIac1BklWmPx3dEvY5yzZ63c5kek2cYQNC9TrSwcGWnF2eGgbO9dodIp/i3w5GFjCxL vfxn4WhC0zn0KAzsojESJ2pmS8/0zBHeNdKXJe4BJ6pDV3nOuz7WLh0wSRs1qctAPOHK Zesbv8jVhk2lFDMj6UT6i+QmLWpKc084piKfYJK6OGNnv4UwNq5MoocC85ZB4ggGS1P/ 7gSYiwUSL2XzuswnfMGHU5EccyQhIVgkOnjIFL2+AGEClQ+Bhb4gtwi8VkeAQx883MRR 2McQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g6WC/1OFwmMEJWjhaux71v3WymnN3hUDPV/lnz7IXaA=; b=MlSG0UDXgs5+mz187hMJ876zddrrYuZ59+Z14nVBeB3wtTqIgZqMPaXdKeUOSiypqJ KxJ0Woo/doUcKjFftSs7GN2kSfBLU1NW3QJEqqLWNH2hMQNcPFwZzgCNYoDsVe4CyxMU ZYr4JW4Azlzs2gh4dp0F9r+cfx0RH4j6Got/JaiJ1h8+H7UF5x8w65o+IYrKHJjkaj3y LWCfhh2Oh5kbfEJ++V6nISH80GnkRapFBYNQ+o0hszJYdyTqyzhW9eHaQjevpQqC//Xm yhrormkTXDJCGDRpWKXvYWNs9ULeMmK6LnFUlMt0choHPLRt/kj8oZOgevDd6R7gah0n Rdiw== X-Gm-Message-State: AOAM532STJ71KbukrhGcbNFruV9Px7i7CwAn92BggLzNrDxNRiU+LufL u7vz5DNMClIfaoHsbFlj69kGDLngZJvorw== X-Received: by 2002:a17:90a:5b0f:: with SMTP id o15mr22919550pji.34.1626560334083; Sat, 17 Jul 2021 15:18:54 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id n14sm2405091pjv.34.2021.07.17.15.18.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Jul 2021 15:18:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 02/13] accel/tcg: Move curr_cflags into cpu-exec.c Date: Sat, 17 Jul 2021 15:18:40 -0700 Message-Id: <20210717221851.2124573-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210717221851.2124573-1-richard.henderson@linaro.org> References: <20210717221851.2124573-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will shortly have more than a simple member read here, with stuff not necessarily exposed to exec/exec-all.h. Reviewed-by: Peter Maydell Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 5 +---- accel/tcg/cpu-exec.c | 5 +++++ 2 files changed, 6 insertions(+), 4 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index dfe82ed19c..ae7603ca75 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -565,10 +565,7 @@ static inline uint32_t tb_cflags(const TranslationBlock *tb) } /* current cflags for hashing/comparison */ -static inline uint32_t curr_cflags(CPUState *cpu) -{ - return cpu->tcg_cflags; -} +uint32_t curr_cflags(CPUState *cpu); /* TranslationBlock invalidate API */ #if defined(CONFIG_USER_ONLY) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index e22bcb99f7..ef4214d893 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -145,6 +145,11 @@ static void init_delay_params(SyncClocks *sc, const CPUState *cpu) } #endif /* CONFIG USER ONLY */ +uint32_t curr_cflags(CPUState *cpu) +{ + return cpu->tcg_cflags; +} + /* Might cause an exception, so have a longjmp destination ready */ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc, target_ulong cs_base, From patchwork Sat Jul 17 22:18:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 479254 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2743785jao; Sat, 17 Jul 2021 15:20:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw3viiKDM3OaAjgq3h3fDamvQzxoN9rN89Uu0R9CdsyT6tXC/HOrI2h97rm9VT9J5WqEBLH X-Received: by 2002:a05:620a:65c:: with SMTP id a28mr3584665qka.77.1626560415766; Sat, 17 Jul 2021 15:20:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626560415; cv=none; d=google.com; s=arc-20160816; b=w1TVOlbDOcn62yaUiT0We0NqMiBUCs4/NoSMPbmwbFhjv57Sc+t0YDDeoxd+QZZnQd 7HyIcVqVUX2KAjTSsLqZPw81UFLtrRGXrOECu0eOyCJWDFrEE8D1x9yh+xUyFvk2nVPO 0pjcC/pI3oUq5mtnV+9zUkBrXgs8qitinOjgkyl5qAXT0m41E5wEVXMQ3i7DsBkohRTH KN0tH1oQGmV4Mfu6sdGOEGMBt9FsIJCE2XyKPv18EK1evlIZaR+pXY4iDxmyiIVGF9vr mznEXPA8zwmdztbcYGA8dV3UWphbea2a64qU4yS0+n6oKgvhwpT1ncsOtogkl2MRqcCu cUhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Yb2TZBaGmBIU6jClQSI4WWkNZXKcd24AJZ/6Z/OuA78=; b=yfJn31rZCcC/PxS9pmFK+j+Qj+LaGvithkMreF8jMm7LSfH/5Vt8o5QamHtzDjwLKR YBHuy+HHVLedzcvgxhSGm7txm97I30vzcda8w7W+tWqQfa2KFt+pqWD8RY7ejnvv/lui Y5onkQHTq1NsVHB1wEjs/amzHLKbc0b05TMf8g3H05sSYbTFWwiLhrI4SOeJbpNbet+t I1OrnJ1UvfxvJjEaf6I9qBdC9RWpa2qpkt46/ASMVtCCo2HAuu1YMxrdnpnZp3+ED3Bp tBJHt2Tnwkxzkn2rncJOURrSwX3UWXHuKjfVXdWsX90+5X6+jC2ackVEyehBOAV/1ydW V9EA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Gji1BlHq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u5si12613389qtc.322.2021.07.17.15.20.15 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 17 Jul 2021 15:20:15 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Gji1BlHq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:32852 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m4sfO-0007Ay-1N for patch@linaro.org; Sat, 17 Jul 2021 18:20:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55040) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m4seC-0006so-7f for qemu-devel@nongnu.org; Sat, 17 Jul 2021 18:19:00 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:38409) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m4se8-0001zK-Ke for qemu-devel@nongnu.org; Sat, 17 Jul 2021 18:18:59 -0400 Received: by mail-pf1-x431.google.com with SMTP id i14so599785pfd.5 for ; Sat, 17 Jul 2021 15:18:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Yb2TZBaGmBIU6jClQSI4WWkNZXKcd24AJZ/6Z/OuA78=; b=Gji1BlHqzmLr0HYhVV9QBysmorVbbjBt6AxnYg4/BNGT+faAJlRRglirSWIroaRSky cPd+2/bqeW0ujzXOuGCcMQu/GZISih/FU4MN+xWMTpDjHo4m4423FUU3VQuFlTWafwoQ qbtL6UrU9U+VTzEhb68GFGqY9KhDReFxyBYrQctW5pcpI6eitgSHg2LJbon0mAmVY7XN iqXVFmbtPjIVjWA88izuuhSNNx9HbNx2qFqFLr0IdGV+5Rx/ziuPmzaQxleC/HuBqRJv gn/U6cIzV0nMLdrv9BWZD4gcaJWCrEq2JatcFsbK1xgB4BI4fR12fMQKrUZDY9o0Xqy6 SgKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Yb2TZBaGmBIU6jClQSI4WWkNZXKcd24AJZ/6Z/OuA78=; b=ULFSvWj/4JBC2LkGrBgagzooHR/v8wKvuQ6YqupI1khS8QvMyeouzYC6T8rEtgjlF5 kBwIYP+OdKmM2WeLrlNlcOZ43FRTvmbsJtIsgOi6bOgWXntmy7bPi1Vnx55lMIhHQpUw 9nuE6vRk1WgCOReKQSvpTsN6Ag2T0Tih/ijgxkNFaAV75OaH12cPU0fM1sPTVh8rGLrj 1KMk8HOwIIqN8ZaXzw5NDMzLetKhBGKBPGnfYI3XytQv7ZYxVw3iZfBuAY96F3yxMtaL pPI5AuHvSz6Dsh2FykwhjRw/bqgnEywYICXrwQx1VSkhgyMPoStFShDjB0WlUJP0lkYq T5Zg== X-Gm-Message-State: AOAM531XZ5K60XPCCcAdqcDpJSUO56IDa68Yh0n8w9VAkKTLd+Xw1W75 4BLTKROz5cya+6s1Iz9Tf8SvI5u6XnXTnw== X-Received: by 2002:a63:5802:: with SMTP id m2mr16907935pgb.171.1626560334699; Sat, 17 Jul 2021 15:18:54 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id n14sm2405091pjv.34.2021.07.17.15.18.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Jul 2021 15:18:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 03/13] accel/tcg: Add CF_NO_GOTO_TB and CF_NO_GOTO_PTR Date: Sat, 17 Jul 2021 15:18:41 -0700 Message-Id: <20210717221851.2124573-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210717221851.2124573-1-richard.henderson@linaro.org> References: <20210717221851.2124573-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the -d nochain check to bits on tb->cflags. These will be used for more than -d nochain shortly. Set bits during curr_cflags, test them in translator_use_goto_tb, assert we're not doing anything odd in tcg_gen_goto_tb. The test in tcg_gen_exit_tb is redundant with the assert for goto_tb_issue_mask. Reviewed-by: Alex Bennée Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 16 +++++++++------- accel/tcg/cpu-exec.c | 8 +++++++- accel/tcg/translator.c | 5 +++++ tcg/tcg-op.c | 28 ++++++++++++---------------- 4 files changed, 33 insertions(+), 24 deletions(-) -- 2.25.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index ae7603ca75..6873cce8df 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -494,13 +494,15 @@ struct TranslationBlock { uint32_t cflags; /* compile flags */ /* Note that TCG_MAX_INSNS is 512; we validate this match elsewhere. */ -#define CF_COUNT_MASK 0x000001ff -#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ -#define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */ -#define CF_USE_ICOUNT 0x00020000 -#define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock held */ -#define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */ -#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ +#define CF_COUNT_MASK 0x000001ff +#define CF_NO_GOTO_TB 0x00000200 /* Do not chain with goto_tb */ +#define CF_NO_GOTO_PTR 0x00000400 /* Do not chain with goto_ptr */ +#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ +#define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */ +#define CF_USE_ICOUNT 0x00020000 +#define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock held */ +#define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */ +#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ #define CF_CLUSTER_SHIFT 24 /* Per-vCPU dynamic tracing state used to generate this TB */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index ef4214d893..d3232d5764 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -147,7 +147,13 @@ static void init_delay_params(SyncClocks *sc, const CPUState *cpu) uint32_t curr_cflags(CPUState *cpu) { - return cpu->tcg_cflags; + uint32_t cflags = cpu->tcg_cflags; + + if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { + cflags |= CF_NO_GOTO_TB | CF_NO_GOTO_PTR; + } + + return cflags; } /* Might cause an exception, so have a longjmp destination ready */ diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 59804af37b..2ea5a74f30 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -33,6 +33,11 @@ void translator_loop_temp_check(DisasContextBase *db) bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest) { + /* Suppress goto_tb if requested. */ + if (tb_cflags(db->tb) & CF_NO_GOTO_TB) { + return false; + } + /* Suppress goto_tb in the case of single-steping. */ if (db->singlestep_enabled || singlestep) { return false; diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 0c561fb253..e0d54d537f 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2723,10 +2723,6 @@ void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx) seen this numbered exit before, via tcg_gen_goto_tb. */ tcg_debug_assert(tcg_ctx->goto_tb_issue_mask & (1 << idx)); #endif - /* When not chaining, exit without indicating a link. */ - if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { - val = 0; - } } else { /* This is an exit via the exitreq label. */ tcg_debug_assert(idx == TB_EXIT_REQUESTED); @@ -2738,6 +2734,8 @@ void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx) void tcg_gen_goto_tb(unsigned idx) { + /* We tested CF_NO_GOTO_TB in translator_use_goto_tb. */ + tcg_debug_assert(!(tcg_ctx->tb_cflags & CF_NO_GOTO_TB)); /* We only support two chained exits. */ tcg_debug_assert(idx <= TB_EXIT_IDXMAX); #ifdef CONFIG_DEBUG_TCG @@ -2746,25 +2744,23 @@ void tcg_gen_goto_tb(unsigned idx) tcg_ctx->goto_tb_issue_mask |= 1 << idx; #endif plugin_gen_disable_mem_helpers(); - /* When not chaining, we simply fall through to the "fallback" exit. */ - if (!qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { - tcg_gen_op1i(INDEX_op_goto_tb, idx); - } + tcg_gen_op1i(INDEX_op_goto_tb, idx); } void tcg_gen_lookup_and_goto_ptr(void) { - if (!qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { - TCGv_ptr ptr; + TCGv_ptr ptr; - plugin_gen_disable_mem_helpers(); - ptr = tcg_temp_new_ptr(); - gen_helper_lookup_tb_ptr(ptr, cpu_env); - tcg_gen_op1i(INDEX_op_goto_ptr, tcgv_ptr_arg(ptr)); - tcg_temp_free_ptr(ptr); - } else { + if (tcg_ctx->tb_cflags & CF_NO_GOTO_PTR) { tcg_gen_exit_tb(NULL, 0); + return; } + + plugin_gen_disable_mem_helpers(); + ptr = tcg_temp_new_ptr(); + gen_helper_lookup_tb_ptr(ptr, cpu_env); + tcg_gen_op1i(INDEX_op_goto_ptr, tcgv_ptr_arg(ptr)); + tcg_temp_free_ptr(ptr); } static inline MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st) From patchwork Sat Jul 17 22:18:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 479255 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2744124jao; 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But we now include -d cpu logging in helper_lookup_tb_ptr so there is no need to exclude goto_ptr. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index d3232d5764..70ea3c7d68 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -150,7 +150,7 @@ uint32_t curr_cflags(CPUState *cpu) uint32_t cflags = cpu->tcg_cflags; if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { - cflags |= CF_NO_GOTO_TB | CF_NO_GOTO_PTR; + cflags |= CF_NO_GOTO_TB; } return cflags; From patchwork Sat Jul 17 22:18:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 479260 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2746255jao; Sat, 17 Jul 2021 15:24:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw4bIGaY2coVap3bmIp7WsEm9K0QaxFcvqOSq4Bh/zjH39ZrZQ+cthF3aoMWzYsIYmnWpMa X-Received: by 2002:a92:c989:: with SMTP id y9mr6672901iln.183.1626560694790; Sat, 17 Jul 2021 15:24:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626560694; cv=none; d=google.com; s=arc-20160816; b=hZVWxdAXqo75fPX66nQU9TJBmncdkIIfywyVhyEHDuDrzKqa1fBvzG4ORjER6UpTRX 6Jnmez6RGooTZFmAjyWGZBcIJby5cedtI8yRXc4y3ah0CL5BRwG7C9U+2a1qnbQBvqIm lx/79RqFs+CsaPS2hFNwLzzyeeyFYGM42Z0t0o/WXQiiw/z7ME7QRkQs/0BkyLu+5eYD ZtwZ+1/CxhlSghE9ZRidgKx2u/L+H1xriZZbqPuk/DFy9XI1NRrgFo68MiXEYszOVzoS y8n04px7sEG6yhUNz/dswIxelaZhiXSJ1cHJ5nlcbxgmX0fqxhEYb+63YRwrHlGQHtaf 45Iw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ZOLiMEmN0a3chiS5zK6wK/UK5sFKrMRuxK04aSAiGGo=; b=h2H1i8EQZcueMTq9pplvtyyEko4RXdoEYs3OnapqSaCrU4HL0KHFYz4NBhDusq5/vH +NllVqQGIOHQ7Die/ufCKCtAkubacoR0/Jw3aqgF9dZ5FxgOp3NnuDi4E7BLaBtwoac0 TlpisDOvyrdtAltkEMEPQyiwpOiBsrkjeu/5X3oQmkzOtztkNzJNGuQyle26PilqTh/X Bft7Q+7SAiH1++m8IgyLqJ403kCVzLx/kQJePRpdd9ggSKu/Dokn1ZKxx/dtF6xUuT3o +27SaJeMEjsavk6nXFLpKNW5AYQeZtil/gX3SJ/su40YTLB3odhxuzrRo5+YE4p0XYmF HYwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hvtLbmo0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y13si7945371ilu.34.2021.07.17.15.24.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 17 Jul 2021 15:24:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hvtLbmo0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49278 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m4sjs-0001gc-70 for patch@linaro.org; Sat, 17 Jul 2021 18:24:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55052) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m4seC-0006tZ-GG for qemu-devel@nongnu.org; Sat, 17 Jul 2021 18:19:00 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:38844) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m4seA-0001zS-EY for qemu-devel@nongnu.org; Sat, 17 Jul 2021 18:19:00 -0400 Received: by mail-pj1-x1035.google.com with SMTP id me13-20020a17090b17cdb0290173bac8b9c9so11571909pjb.3 for ; Sat, 17 Jul 2021 15:18:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZOLiMEmN0a3chiS5zK6wK/UK5sFKrMRuxK04aSAiGGo=; b=hvtLbmo0JqQJRwVE3/R8/tB9fK/D+5mU1FdDgwGTIBfLkARVJLLdfS5pmU2LSoLx8J veNdRS7DNusqZFRFH7KvnhVIhgp3aL1qgo2epcBifeiJuzqLFt390INVUoKDMFv4Zjbk 7V1wg3tNKtBu2ea9h6869hg8U6oOtqkseztcxHNrEVKeQ3YULYDrILCZv9RBy9CJIaaR +s5emQ13KNC45EUVgiAOqxc/5GVkEUqGEkON68VFs8ay8PBwuUZXnlIKnGGLkogeGGci A+MCQeq/zLZG2jw/0zPQIXBxTq5yT5a1MxGpikRFxAFJ4w8MQuSxYdZtODzt94vN2fU/ yKkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZOLiMEmN0a3chiS5zK6wK/UK5sFKrMRuxK04aSAiGGo=; b=etBzU5BUUHTtL9fgPqWGhF2iVMtoJ1JkSzqN3RkyAKOmRcAzfXJVvyOgjw3Nv0s1gu A/rcHcL7pwjaQRew+OSJBuhSviikaq+axlqMux3qVjGRxJMGRpDNgzAmiQgwKJSaiT/w r0uE+c1VcDj8z9OJDlyU+PyqtibQusV9dHsW2APaLaY0YQK8jVGZINgrLEWtH99RVepg vxyzG3RyDjTTQM5MkVt5EOIaFVe+3c8Ws3X+x3qfwh1Kb+BuUqnObNbz0vaUMWOxxjNM s/oXbsL3I5TDO5QpSKnelDZEN2LX9w+StzcrpjZDEnvchrIhwVXMGlC5l70xRzSbgwhA aqdQ== X-Gm-Message-State: AOAM533zjbhSqVtPezoOLmXuPYi9TqoFRwwEEhQY1tpvoCDE6jN9lgC9 q4kq9L1BTNwvgKod8laPYjDLeIzzyEr7Iw== X-Received: by 2002:a17:90a:86c6:: with SMTP id y6mr16353533pjv.16.1626560335840; Sat, 17 Jul 2021 15:18:55 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id n14sm2405091pjv.34.2021.07.17.15.18.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Jul 2021 15:18:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 05/13] accel/tcg: Handle -singlestep in curr_cflags Date: Sat, 17 Jul 2021 15:18:43 -0700 Message-Id: <20210717221851.2124573-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210717221851.2124573-1-richard.henderson@linaro.org> References: <20210717221851.2124573-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Exchange the test in translator_use_goto_tb for CF_NO_GOTO_TB, and the test in tb_gen_code for setting CF_COUNT_MASK to 1. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 8 +++++++- accel/tcg/translate-all.c | 2 +- accel/tcg/translator.c | 2 +- 3 files changed, 9 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 70ea3c7d68..2206c463f5 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -149,7 +149,13 @@ uint32_t curr_cflags(CPUState *cpu) { uint32_t cflags = cpu->tcg_cflags; - if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { + /* + * For singlestep and -d nochain, suppress goto_tb so that + * we can log -d cpu,exec after every TB. + */ + if (singlestep) { + cflags |= CF_NO_GOTO_TB | 1; + } else if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { cflags |= CF_NO_GOTO_TB; } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 5cc01d693b..bf82c15aab 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1432,7 +1432,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } QEMU_BUILD_BUG_ON(CF_COUNT_MASK + 1 != TCG_MAX_INSNS); - if (cpu->singlestep_enabled || singlestep) { + if (cpu->singlestep_enabled) { max_insns = 1; } diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 2ea5a74f30..a59eb7c11b 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -39,7 +39,7 @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest) } /* Suppress goto_tb in the case of single-steping. */ - if (db->singlestep_enabled || singlestep) { + if (db->singlestep_enabled) { return false; } From patchwork Sat Jul 17 22:18:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 479261 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2746430jao; Sat, 17 Jul 2021 15:25:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwMotkuTAr1ycvcJAlufz0zPvcr6Od323GMhDUFUIRABGb+LbO3RJY+9W6JjVz57DhZLaee X-Received: by 2002:a5d:914a:: with SMTP id y10mr12883454ioq.140.1626560713858; Sat, 17 Jul 2021 15:25:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626560713; cv=none; d=google.com; s=arc-20160816; b=UbW301xaDnkc+aJxU/pgAR0AjlauFjKDUMtaZU0y6FDi4TUwRuWxs6pZkKs5dOR7ua 1biTWaQ0mhK6ZRJDbl1rBC2nvnVNov195V2VP1oL4vIbSsWttb56q3vAAWRDBBvcvLQf 4hP8KxQC1c2OLYjAeuQ0boiLe1FdQPvXEQPPfeFls26QFRsYjOgK8KuJeNVb5l5rbzS1 0yGTu2Ap1guYvlCFPV2dLRRl8ph+1jXtRK3u0YFajLr80upbOy9ktj9z0ldyzS3VWVao awOuJyrlZO4skPKGSr1AXzOhaUvSlwDx+YqjJw0lxmIIV0tJjr5RtNiAFcZ/QzZMG8xc qCiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8YnkwL2N7MCyAYblTwdwFeZAAt2ZW8w1UlaHPMDWJNk=; b=IXBdb0vtwa/VsrUy8Cw3GDe0zaJ+7U191zTVIYh0E3JGV9m9Z1Zy4fn1Hn7pD9ZIsk OWLtcGfgsePnFn805ihIbkOdAoYKE7Ru2EL7jfk5WoXnkx8uJLh40K638IERJPojVALz 6yHXC3llZ/u3+O4SArXSCpApkMotF60vSX6h03iJ1ZMMaFSwEbdeWBSSMQeK2acRgb6R 72LdgD68Hw1DV6FQ7F2yDEeW1YJWC4ZoNwYa9bwKBKlUNzKUQnZ93doHFN6x9of2qXB3 +zOtDbEy3ZKROXjqUT/XsZTm7fvEBM6z6Ukk2BC1ekMks65kcZIfKUGzgyy1KxKjLnSu uc2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SAUvc8JL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t7si15046839jam.62.2021.07.17.15.25.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 17 Jul 2021 15:25:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SAUvc8JL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53694 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m4skD-0004Zo-AC for patch@linaro.org; Sat, 17 Jul 2021 18:25:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55056) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m4seC-0006u1-Jv for qemu-devel@nongnu.org; Sat, 17 Jul 2021 18:19:00 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:37590) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m4seB-0001zY-0E for qemu-devel@nongnu.org; Sat, 17 Jul 2021 18:19:00 -0400 Received: by mail-pg1-x532.google.com with SMTP id t9so14558429pgn.4 for ; Sat, 17 Jul 2021 15:18:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8YnkwL2N7MCyAYblTwdwFeZAAt2ZW8w1UlaHPMDWJNk=; b=SAUvc8JL8Xrg4kgvWXQGioO8ay6EbZW7CdIBHNtFtZ7AvOelmyFOih9Q6FeAPth5GI LSV7hiIOd3agDeV9KvcYn9B3Eb+0M3RGXEZG7EWNOAWZYMk7g5j1KD3EWa8/hXI759L1 9PhWqUKsRuMVtbv1SriQQkyKoMw+DwpRj4qtL7R4y5FntCqcNgPd/CmhfgcxbEGT8+mc yxe0nLtXJNfNHWNp8alPSzK5rQr/S9YzIzjh/rhO0/+W8zSMteHLlWMii+ZY0QtDbyER Slll1DQMOs1EzBWZIZBk5uZy1r7jG5q+xZGJdo/O/G5qfzZ/WeFI1aKQ4cSAl7Axj+Yj YmxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8YnkwL2N7MCyAYblTwdwFeZAAt2ZW8w1UlaHPMDWJNk=; b=h4D29AnBZLoHorRZYogjWDKvfLShsIut+mgmQQ16cTp6ytpNGhEAI+HQqtXHnhNeYj kClNrEq1se1kFkxH3hXecufQguWznTou+HduSXhj0dtfNNzko62TSiyuA+5CxrRROmhI YHq9eykB7ZB6IkZJ2zg6EnSSVaH91tpEvKPveNyCXCPlz9Tg0R+Lh4kSA7iCc5rdebNF KZeHckTp8b24l64pTDGaYl1MDncPKT5c7pXrvNBjjl9Ee6WEctPTcUiCdtLvr82ttBts EcJVmd6USZZQeft1i8oMlA6HKNIY2EMe0hcRHQfAHeMMmFZlEVfb+El86fWter84ii9m s+nQ== X-Gm-Message-State: AOAM530strhOv6k7UOudAb94QF3vlV+YkqNqVLiPMoE4fFmj8u8ScUzf j+uWSIhEHT+tgRlanmfjV892YFqspHmHAw== X-Received: by 2002:a65:6191:: with SMTP id c17mr16991607pgv.153.1626560336548; Sat, 17 Jul 2021 15:18:56 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id n14sm2405091pjv.34.2021.07.17.15.18.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Jul 2021 15:18:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 06/13] accel/tcg: Use CF_NO_GOTO_{TB, PTR} in cpu_exec_step_atomic Date: Sat, 17 Jul 2021 15:18:44 -0700 Message-Id: <20210717221851.2124573-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210717221851.2124573-1-richard.henderson@linaro.org> References: <20210717221851.2124573-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Request that the one TB returns immediately, so that we release the exclusive lock as soon as possible. Reviewed-by: Peter Maydell Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 2206c463f5..5bb099174f 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -330,8 +330,7 @@ void cpu_exec_step_atomic(CPUState *cpu) CPUArchState *env = (CPUArchState *)cpu->env_ptr; TranslationBlock *tb; target_ulong cs_base, pc; - uint32_t flags; - uint32_t cflags = (curr_cflags(cpu) & ~CF_PARALLEL) | 1; + uint32_t flags, cflags; int tb_exit; if (sigsetjmp(cpu->jmp_env, 0) == 0) { @@ -341,8 +340,14 @@ void cpu_exec_step_atomic(CPUState *cpu) cpu->running = true; cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - tb = tb_lookup(cpu, pc, cs_base, flags, cflags); + cflags = curr_cflags(cpu); + /* Execute in a serial context. */ + cflags &= ~CF_PARALLEL; + /* After 1 insn, return and release the exclusive lock. */ + cflags |= CF_NO_GOTO_TB | CF_NO_GOTO_PTR | 1; + + tb = tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb == NULL) { mmap_lock(); tb = tb_gen_code(cpu, pc, cs_base, flags, cflags); From patchwork Sat Jul 17 22:18:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 479253 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2743285jao; Sat, 17 Jul 2021 15:19:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwP+OTfAIwmWqNYqwV7TAUtVW2WAEx63EhwMTLoRE3X0q4YEvgAnsW6FGFrFkbebPmzfcp3 X-Received: by 2002:ad4:5bee:: with SMTP id k14mr17483001qvc.10.1626560358248; Sat, 17 Jul 2021 15:19:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626560358; cv=none; d=google.com; s=arc-20160816; b=CmIcttxj9zoMjMq43XUdXcS5jgbUacgGqkpIbSez2JdNv207FwAFuqXM1QR3JbECOe wHqJ92r3ydcehfwVknOw9QuZ5TEraxVrJDHdohLOg5g667ueratF75pcw4TWFVveUNp5 EpFRNf+ioBkqDA7vulKEvp5SXVbrxZp4z4MVPvSWiIate/pcYVqufleKmhU+dGDQQsxF lYVvIAXDtuCmys206FqNDtEhEJHeoPah4lMqss0hNOHIQ053YORVbH4cTdenWsgepYE6 ffWCfMRO8yx2hQTRSsAwEQLGzFNTm+F8sQPYR0XUDuP7RblTjqcQkG0F4hHYehihsIOi MZ8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fTNV1A4k/Xn3P/CnpnqSKcH5ZtAfJBxZRFThgdFD0A8=; b=01A/di43cu5mHsNaTDTEoZpQqBCQP5tfK8vWfwLMkOp/KocW/M0VVllzSm+PU4vyl+ jVGtTnaEopq7DpwR+htOReoZmGyKpv2w2NZdikxU5pMNIKuMhJ4EUsnpF7sVAYxlp2Zd Bhcjb/Ei5sGtz8y7CxsGuXK92nFqld1bXtDIOq93Zx1zEQIHAIj74JBXrgTWkNsWBDSq zqyW8nRreiOo5S5kEm4hqlVufdu7ztF8LHwRcUSpyrEuY3T4LiC1T34uE+SFesgAKj6V oacW7HY8tuwMshHvEjvXd3EkJUk9roKv41XghCE0aYjKMmsL710D+h+sIuUPpzzEBg3v shsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="DzGiB+r/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) -- 2.25.1 Reviewed-by: Alex Bennée diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 5bb099174f..4d043a11aa 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -502,15 +502,29 @@ static inline void tb_add_jump(TranslationBlock *tb, int n, static inline TranslationBlock *tb_find(CPUState *cpu, TranslationBlock *last_tb, - int tb_exit, uint32_t cflags) + int tb_exit) { CPUArchState *env = (CPUArchState *)cpu->env_ptr; TranslationBlock *tb; target_ulong cs_base, pc; - uint32_t flags; + uint32_t flags, cflags; cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); + /* + * When requested, use an exact setting for cflags for the next + * execution. This is used for icount, precise smc, and stop- + * after-access watchpoints. Since this request should never + * have CF_INVALID set, -1 is a convenient invalid value that + * does not require tcg headers for cpu_common_reset. + */ + cflags = cpu->cflags_next_tb; + if (cflags == -1) { + cflags = curr_cflags(cpu); + } else { + cpu->cflags_next_tb = -1; + } + tb = tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb == NULL) { mmap_lock(); @@ -868,21 +882,7 @@ int cpu_exec(CPUState *cpu) int tb_exit = 0; while (!cpu_handle_interrupt(cpu, &last_tb)) { - uint32_t cflags = cpu->cflags_next_tb; - TranslationBlock *tb; - - /* When requested, use an exact setting for cflags for the next - execution. This is used for icount, precise smc, and stop- - after-access watchpoints. Since this request should never - have CF_INVALID set, -1 is a convenient invalid value that - does not require tcg headers for cpu_common_reset. */ - if (cflags == -1) { - cflags = curr_cflags(cpu); - } else { - cpu->cflags_next_tb = -1; - } - - tb = tb_find(cpu, last_tb, tb_exit, cflags); + TranslationBlock *tb = tb_find(cpu, last_tb, tb_exit); cpu_loop_exec_tb(cpu, tb, &last_tb, &tb_exit); /* Try to align the host and virtual clocks if the guest is in advance */ From patchwork Sat Jul 17 22:18:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 479265 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2748945jao; Sat, 17 Jul 2021 15:29:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyrbFrTj1J3qfPJBtJ0uoWjZceyjNM7MrZA8Ez/QMaDXFlt0TArmxRwJDLCocYozgIF3Po8 X-Received: by 2002:a0c:eece:: with SMTP id h14mr17724157qvs.12.1626560968145; Sat, 17 Jul 2021 15:29:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626560968; cv=none; d=google.com; s=arc-20160816; b=kNEsX8VcefcBhEB+Sva4oufX4Ftkg2noCZwR6DKlszldaZMQNAcv4dvxdqv9D84vzz ysfX8yB+hZYrYygp8xQ7C7HwM0NonuZd1laGQHCeYT/JyZAmgYSWVkbP0P6VyCOSqL0E ZSB3q8YpWG9PdKRfWWyMhO4IcL0FMBThPvTYWGm3GhV3wcmijPdxsmGwEwyXv95YB/yN ule/t/JP4Lnj+ADCoqBFgIM90j/nHNQv/nQbO2WeMigcdf8qoqV53Kno2osgjlMy7FDp 66asPfTN45vJE9uQu2hACYKoo8XKOpLAIgQeYGybiqlmnchFJgKIL4PLAjNKjzKVTgWl DCQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mOMfbSr7dP2LtForXHD7QhzKF/cyMbvAW5OerGJ5K/M=; b=VEh9QWq94OTkI3TOlJqut2Yj+7DDOsqQ3Yyhc7J5VwkNFK+bSz64Be4vXiazm20hvp /7qzKUmqdoMekEQhl1d4Qfmi3vXcIWY0B+M/NSqxCdLrq8Qy2Jt5KS0JTbJ2+r6s/b9+ j/iOKW1oHDORF9qHBI5pp2suS/Ge4Rmyrk+UBW6W/vlZq6oXqVEx94P6xONbBgm8QIMO FQ+L3I2mgNHpy6VRYjwvdNC42jQDYI7C0h2FcM1n0CNe4Kp9JqvqPE+/IHdBjfuQpKNu SlIHl+OfIVTqu6imB9tTkMBn+cWALgDD5u+2IpJ4gZHpUk46a55ShPYoDoJnpRZVUCN6 3ERg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bfcl9CDi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Advance pc so that the breakpoint covers the insn at the bp. Signed-off-by: Richard Henderson --- target/avr/translate.c | 1 + 1 file changed, 1 insertion(+) -- 2.25.1 Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/avr/translate.c b/target/avr/translate.c index 8237a03c23..d768063d65 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -2950,6 +2950,7 @@ static bool avr_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, DisasContext *ctx = container_of(dcbase, DisasContext, base); gen_breakpoint(ctx); + ctx->base.pc_next += 2; /* advance by minimum insn len so tb->size != 0 */ return true; } From patchwork Sat Jul 17 22:18:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 479263 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2747788jao; Sat, 17 Jul 2021 15:27:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzwPFKx5n8VvxD/iQYv6j1/cjAKt1pRGWJrKiK8VdbxIjWUl2lPYfWZgJLLSbEsOWWtUisL X-Received: by 2002:a05:622a:1051:: with SMTP id f17mr15949883qte.226.1626560834970; Sat, 17 Jul 2021 15:27:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626560834; cv=none; d=google.com; s=arc-20160816; b=aWsXbGmAa7i68ObRtmCsmISSW70ROBnCAosY8CNZa3KA4Er4oEHgZpmIuY6rSQrbyg NKc/0ZflKBXt/yTw42HOc3R1JowrO5lojBN3doWkBH2ksDhQrOmlQ/JpN2VgG5ajWCd1 vM4LukrM2+CssX9NvQs6MXzg/teP1vlwI505GWmxj0qPskDrUcEMceJhYhpzXOuaEqjv rjFHWisxDO+Wqut2lU+oHqyronAA0p9qDWrknWrGGOT3AyWScdtwG5aAQ9HYd10YaXG8 9WK9ZzIzdeex+2zbOtr3O/CfHKtL6aYXF+6gIFjbDoRcJ5rhxM8megRQD/dCenBPOK8o RBwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4rIxiJifn9NWIyljY9ef9dZx7dheact/TSBWFFk89i0=; b=PaVchGhl/IaDXQKzjzlQR416BQqbkC/3VhOiB//ZD53YHgAGEoMYbxRq0fPbDALtAa qDmQgyHzTs/GaED6MgTlVb1s5q7YiH6L1+mlE474+XiGt6CQRqtG97TNBDV7reQ1fOdj 2qjtifgZXZP9YKaC7lMltN/qnvPZeYE9aO/eC/G8/2yxVZTQ1TETQ8LpMGPDFKzHxX7u FP7RzLi9xLsrqdDw1wqffwisYxZIfeHMXFsQmMHD5kzSPHsl7JoSuUXqWlWRFP6Zn0he 0GHZi5sfzKDi6CbGfpxREvGF6TDmq5b88LH8zcj7/IbdEO5/S/RBoEcATYd7tiwd30Pa kqCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=enfnnCQ4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e18si4804435qkm.68.2021.07.17.15.27.14 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 17 Jul 2021 15:27:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=enfnnCQ4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:59498 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m4smA-0008US-Ap for patch@linaro.org; Sat, 17 Jul 2021 18:27:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55084) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m4seD-0006wn-JQ for qemu-devel@nongnu.org; Sat, 17 Jul 2021 18:19:01 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:35617) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m4seB-000215-R1 for qemu-devel@nongnu.org; Sat, 17 Jul 2021 18:19:01 -0400 Received: by mail-pf1-x430.google.com with SMTP id d12so12638637pfj.2 for ; Sat, 17 Jul 2021 15:18:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4rIxiJifn9NWIyljY9ef9dZx7dheact/TSBWFFk89i0=; b=enfnnCQ4TTZh+RdkoRMsuDmhXjofSvfY6UiF9toAj7kCUjXzycufrQxAAjrm0IxuKl zy4C6gdfZNxBcl/SGtdUlG1TpDCaqmOmwCSBpzGkoBeMS2bpnOGEb2BumhzpsKr0E/t9 8BVxle5l8NvtwU2hY5dVqgs8S5KvNmYo4TGGCyR+txrShd61Ph2hOaWjkehaxzMvHGjj cV8l7BWIZ0QdHKNEENugvpPlXNSCx+3K1mwqCWHbsAEtCgtqOLgPqE6MHQhNsBiv3x6N efoa6hbQCPaI+a/C+6S9G3wwBb/iZaqzY14d2lEKiKVMkIcEtJ7sDMbYSbqAGtdKtnhB CGtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4rIxiJifn9NWIyljY9ef9dZx7dheact/TSBWFFk89i0=; b=O30lNO2MATdQrXBf/RiGZKBQd3kWRKZJnkkbWNmFPMUNsR4gjaf7UTtDm/7OQWLeTS NySaQWZHfBmFi+nuI9p+wy8CqYcrxMy2oa3Ia1gGSmst4DA3CiVygvJeMQCNrWn6LpOm sXPRorejODo+lA8RML51yHEOR3TwUKbMMpIqhIr+pRtRun7zDLQWL5rK/atUHsaCX4sM fVnl+cjrB3iPNXjnYpPY8lLBctDJxpfQ4ZaFVUfiL404eLxClEbItsCTOFywuw6RxZXB uJ+dO3w4cQGfTuvHsox6fU9p7PrTTjJJ+LKIaiVsa1WUryQmKKGLCPzx/6fzCzgJ/hcR FjwQ== X-Gm-Message-State: AOAM530XlrALFURa2SQl182c5O9VCbg9LuzLu+ZZ7UoWgtoBr/zdOrsT 8M6eSai0yHifzoGr3d1zKoZI/hA0gK3vsQ== X-Received: by 2002:a05:6a00:170b:b029:32a:3950:f51b with SMTP id h11-20020a056a00170bb029032a3950f51bmr17572277pfc.64.1626560338377; Sat, 17 Jul 2021 15:18:58 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id n14sm2405091pjv.34.2021.07.17.15.18.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Jul 2021 15:18:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 09/13] target/mips: Reduce mips_tr_breakpoint_check pc advance to 2 Date: Sat, 17 Jul 2021 15:18:47 -0700 Message-Id: <20210717221851.2124573-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210717221851.2124573-1-richard.henderson@linaro.org> References: <20210717221851.2124573-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The actual number of bytes advanced need not be 100% exact, but we should not cross a page when the insn would not. If mips16 or mips32e are enabled, the minimum insn size is 2. Signed-off-by: Richard Henderson --- target/mips/tcg/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index fd980ea966..ef00fbd2ac 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -16192,7 +16192,7 @@ static bool mips_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, * properly cleared -- thus we increment the PC here so that * the logic setting tb->size below does the right thing. */ - ctx->base.pc_next += 4; + ctx->base.pc_next += 2; return true; } From patchwork Sat Jul 17 22:18:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 479264 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2748561jao; Sat, 17 Jul 2021 15:28:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwtzT2RxP1lnEtP45IznOi0YlSw5r4Pi89BaS8u7G45d1OdSKLXyAStinM5uqbPrRRXsCRI X-Received: by 2002:a05:620a:2991:: with SMTP id r17mr16740436qkp.252.1626560920606; Sat, 17 Jul 2021 15:28:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626560920; cv=none; d=google.com; s=arc-20160816; b=LvJ6P6220WYocuEevmmBNUn7bs+dng6sib1WRgyaujPCznUnMkgobsuAFcXvuvGXiV r+dx8VMYgyAm/nkU3vkRGr0saQfknnkkcBbWIqZcmHeY1VGm0BM5j5HJ2zgcoqHK+TTh DJRPDQeVDiwKft0Ma4ODku/1NUonOCAzMhoxeZP1mYKaGQNUKjnNw5Xj/JKIRtGiy+20 10+vRgIxHnrHViGWckBbFvdM9veFcxlTpy/rcKFAx7p9wkuf8hxU7yd8sVKfRWRk2/l7 gNVVsqlqIxXOMM5yRxL+c3wVVMY446FqC8a2xw2j5F8pLU1AvEmO5eQMSZyaAcIIwv15 rl0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=4vJFTwgrLYV+L/7QAHTqeXEOD1JYdbKVZbtwn9ca/8k=; b=mD8OJeiD5rx2i0yoGf9v0okc7GZEwSRGTRNSprV9uygN5JbMNOCRNsS+IyXfoAncFd 9M1FpuqnYRoU/1+zq8o1be5lVNOTaETGSe/BoMTRqPFUhjtkCQR+BGy1RofHAYRGQBjT B12YFYaPzuPHeW6d4MV9lT63xD4VPUpyZRzoQ/giyk9CWbfLVK/1M8/QR3ROnzmPiGHU 8+MJ440TKtDyqsqGzIu+UlR0tGi6jpf1ynjRnMd/dwjrc2ioEhKgSQ9E/9O9SRVk08uu yeR/oVOJtwHv/mJ++XcBVH2OGnOT+T28g2pbgVw91B0tpr2T/scwHaFurumW9sz+lwXP jw6A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bEdI9q8n; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id dv3si12068937qvb.199.2021.07.17.15.28.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 17 Jul 2021 15:28:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=bEdI9q8n; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34432 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m4snY-0002Cj-2X for patch@linaro.org; Sat, 17 Jul 2021 18:28:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55090) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m4seD-0006xI-Nb for qemu-devel@nongnu.org; Sat, 17 Jul 2021 18:19:01 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:33469) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m4seC-00021I-7X for qemu-devel@nongnu.org; Sat, 17 Jul 2021 18:19:01 -0400 Received: by mail-pf1-x433.google.com with SMTP id m83so12650949pfd.0 for ; Sat, 17 Jul 2021 15:18:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4vJFTwgrLYV+L/7QAHTqeXEOD1JYdbKVZbtwn9ca/8k=; b=bEdI9q8n47BduQgIUqtwsZKqDjwEvmJ71M0zy4w6Loh9szTjokvoFekdoLzn/257Rj qrNcQk+bvHi0DflfAP+IcNYVlYVW9S3ARcgCwlMpSvC3722Le+s431zDoeIybXSG4I0T oCfDjUjoS2F6s834ncYV42efNvaFgHRWySfRfoJQw71a9sbteprchfIsaazF2dNAi/A+ owzHfq6oWfpLB6eNu0JX/dzYNMP4bNhvbo/f18q4iuJN2WRlUgPbTrkxP+S1Ol3USjTe AvJMJTYbScjP0Mj6J8999Vu7ZdTtz2tCb49axMAf8AMo8ZwbM5g7miNR+qu6VqoaRM0b WhWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4vJFTwgrLYV+L/7QAHTqeXEOD1JYdbKVZbtwn9ca/8k=; b=MVatzp7CVogJRWDDuWFmwUAYk8BgQdB8nDdZewrnrx5bk4Fy723hBJCB0hPx4yeSOE 7p2IBU3q8Q5BGfM4/8/WdywOMtUYgDKaq6g6jUxQsRd99JkXxszHJYtltqTk9oQzrjRZ zegsAjL3Gy1hQ2cLM6QQOFx4fXQmg52/8w8Kbjzp8L7om9GrjwPsIk5U6sN/mndUj5Od yiMMHrSKHGuPlAFrE9cQTIltOL8GzVwFvw1peh2CVqEO2YzPYmzdeb8Iuv0NknkH0z2q KqUvNB3g4OX415WJRrLYrL4wquxX2eFJUrrkWTMYT20h1DP9l3BfDbXbXfUspyg5ZZPX xYIQ== X-Gm-Message-State: AOAM530yqbQAhN/t7JSkE/QjB6mCoyKbODxxhb4zjhfYgowh76pM8juT si7YL9Zjr+MerZoH79sSqdoixtZWxONihw== X-Received: by 2002:a05:6a00:2ac:b029:331:690d:7f26 with SMTP id q12-20020a056a0002acb0290331690d7f26mr17387355pfs.78.1626560338979; Sat, 17 Jul 2021 15:18:58 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id n14sm2405091pjv.34.2021.07.17.15.18.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Jul 2021 15:18:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 10/13] target/riscv: Reduce riscv_tr_breakpoint_check pc advance to 2 Date: Sat, 17 Jul 2021 15:18:48 -0700 Message-Id: <20210717221851.2124573-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210717221851.2124573-1-richard.henderson@linaro.org> References: <20210717221851.2124573-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The actual number of bytes advanced need not be 100% exact, but we should not cross a page when the insn would not. If rvc is enabled, the minimum insn size is 2. Signed-off-by: Richard Henderson --- target/riscv/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/target/riscv/translate.c b/target/riscv/translate.c index deda0c8a44..5527f37ada 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -973,7 +973,7 @@ static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting tb->size below does the right thing. */ - ctx->base.pc_next += 4; + ctx->base.pc_next += 2; return true; } From patchwork Sat Jul 17 22:18:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 479256 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2744816jao; Sat, 17 Jul 2021 15:22:12 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwbb/D1Q9d9t3bEDzl0RLdI2lKCIyAKI49j8vM/gMj5taGmBl31F8cKTHw7LXgrd7Bl5FBf X-Received: by 2002:a37:65ca:: with SMTP id z193mr16702587qkb.174.1626560532646; Sat, 17 Jul 2021 15:22:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626560532; cv=none; d=google.com; s=arc-20160816; b=bxGVF7vwEn5ev/Z6qrgGCf1019Vb9ECylPmc/DDwCEwcQmhG0Runc6vgGKEIUl2dIF Fa9deeigop0eQ4vMiY97CYnS8hiEK560WUmIZuUL4FprG6Q9M1QFHCrIn70QRF+f1+24 zKFeR++aqhjEcm7ZZFIPy22OYTM33nbF/D7Z1nj6giDFJCvg5mnZgvSLYV5wOlO7lQUW iHDZvapJAi9rkWUKeOyp4YcDNJK9yR3sCy1FL/dY9rfnAdibq+PXDoT1c3BSw84QyArN cIcjJAE+I9R4rjem7YZ83JfShY7zn6N4je7LevBOJj9ViJdlhjGlVgKQl+va3qM/eJAv QJWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+gQ4zGiHBMFOTepkFnDJmbuO8GBFl4Paf2oogztjk/Y=; b=hcoyTcrNmonFCbMqvniOrraqRBKEJl34HlqZB7F8V1CIa6H9g6ttpcwjzB7vNDeH48 3qAk3N/G1+YUr7qfZ8LW3+U015G4qMMZA84v50rEOZvJivsFyvNubWToeO5nZMDAzRW7 fNT+zbM++KN2eotzy0V6d/lXzBHv+Uf1VlqD5Bky7d5f3F5aDOQvP+tEOQP8mG03zORs pvNXcy950EbzEC3mnMRqn66XF9QVFF5SaH+W6WQvEO8xENK9cS3kiOseCmOnVvKAsk78 4QqXompkvU/4TGZwX4/gXawaY4ha+r6YqJWWONICa/mRCU2Vu1F+bQcQ0fQW+YPWAtml yYUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=zgI3FYbU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Return the instruction length to consolidate the adjustment of db->pc_next. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/translator.h | 17 +++++++++------ accel/tcg/translator.c | 40 ++++++++++++++++++++++++----------- target/alpha/translate.c | 12 +++-------- target/arm/translate-a64.c | 14 ++++-------- target/arm/translate.c | 20 +++++++----------- target/avr/translate.c | 7 +++--- target/cris/translate.c | 14 ++++-------- target/hexagon/translate.c | 13 +++--------- target/hppa/translate.c | 7 +++--- target/i386/tcg/translate.c | 15 ++++--------- target/m68k/translate.c | 14 +++--------- target/microblaze/translate.c | 14 +++--------- target/mips/tcg/translate.c | 14 ++++-------- target/nios2/translate.c | 13 +++--------- target/openrisc/translate.c | 11 +++------- target/ppc/translate.c | 13 +++--------- target/riscv/translate.c | 11 +++------- target/rx/translate.c | 8 +++---- target/s390x/tcg/translate.c | 12 ++++------- target/sh4/translate.c | 12 ++++------- target/sparc/translate.c | 9 ++++---- target/tricore/translate.c | 13 +++--------- target/xtensa/translate.c | 12 ++++------- 23 files changed, 115 insertions(+), 200 deletions(-) -- 2.25.1 diff --git a/include/exec/translator.h b/include/exec/translator.h index dd9c06d40d..433b753c5c 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -92,11 +92,15 @@ typedef struct DisasContextBase { * @breakpoint_check: * When called, the breakpoint has already been checked to match the PC, * but the target may decide the breakpoint missed the address - * (e.g., due to conditions encoded in their flags). Return true to - * indicate that the breakpoint did hit, in which case no more breakpoints - * are checked. If the breakpoint did hit, emit any code required to - * signal the exception, and set db->is_jmp as necessary to terminate - * the main loop. + * (e.g., due to conditions encoded in their flags), in which case + * db->is_jmp may be left as DISAS_NEXT or DISAS_TOO_MANY to indicate + * that the insn should be translated. Anything other than those two + * will be taken to indicate an exception has been raised, but in most + * cases db->is_jmp should be set to DISAS_NORETURN. + * + * Return the minimum instruction size that should be applied to the TB. + * The size of any TB cannot be zero, as that breaks the math used to + * invalidate TBs. * * @translate_insn: * Disassemble one instruction and set db->pc_next for the start @@ -113,8 +117,7 @@ typedef struct TranslatorOps { void (*init_disas_context)(DisasContextBase *db, CPUState *cpu); void (*tb_start)(DisasContextBase *db, CPUState *cpu); void (*insn_start)(DisasContextBase *db, CPUState *cpu); - bool (*breakpoint_check)(DisasContextBase *db, CPUState *cpu, - const CPUBreakpoint *bp); + int (*breakpoint_check)(DisasContextBase *db, CPUState *cpu, int flags); void (*translate_insn)(DisasContextBase *db, CPUState *cpu); void (*tb_stop)(DisasContextBase *db, CPUState *cpu); void (*disas_log)(const DisasContextBase *db, CPUState *cpu); diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index a59eb7c11b..1c44d096d8 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -50,7 +50,6 @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest) void translator_loop(const TranslatorOps *ops, DisasContextBase *db, CPUState *cpu, TranslationBlock *tb, int max_insns) { - int bp_insn = 0; bool plugin_enabled; /* Initialize DisasContext */ @@ -91,19 +90,35 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db, CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { if (bp->pc == db->pc_next) { - if (ops->breakpoint_check(db, cpu, bp)) { - bp_insn = 1; - break; + int len = ops->breakpoint_check(db, cpu, bp->flags); + + /* + * The breakpoint_check hook may use DISAS_TOO_MANY + * to indicate that only one more instruction is to + * be executed. Otherwise it should use DISAS_NORETURN + * when generating an exception, but may use a + * DISAS_TARGET_* value for Something Else. + */ + if (db->is_jmp > DISAS_TOO_MANY) { + /* + * The address covered by the breakpoint must be + * included in [tb->pc, tb->pc + tb->size) in order + * to for it to be properly cleared. Thus we + * increment the PC here so that the logic setting + * tb->size below does the right thing. + */ + tcg_debug_assert(len > 0); + db->pc_next += len; + + /* + * The breakpoint definitely hit, so decrement the + * number of instructions completed for icount. + */ + db->num_insns--; + goto done; } } } - /* The breakpoint_check hook may use DISAS_TOO_MANY to indicate - that only one more instruction is to be executed. Otherwise - it should use DISAS_NORETURN when generating an exception, - but may use a DISAS_TARGET_* value for Something Else. */ - if (db->is_jmp > DISAS_TOO_MANY) { - break; - } } /* Disassemble one instruction. The translate_insn hook should @@ -142,9 +157,10 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db, } } + done: /* Emit code to exit the TB, as indicated by db->is_jmp. */ ops->tb_stop(db, cpu); - gen_tb_end(db->tb, db->num_insns - bp_insn); + gen_tb_end(db->tb, db->num_insns); if (plugin_enabled) { plugin_gen_tb_end(cpu); diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 103c6326a2..b3e4777dc3 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2978,19 +2978,13 @@ static void alpha_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) tcg_gen_insn_start(dcbase->pc_next); } -static bool alpha_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, - const CPUBreakpoint *bp) +static int alpha_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, + int bp_flags) { DisasContext *ctx = container_of(dcbase, DisasContext, base); ctx->base.is_jmp = gen_excp(ctx, EXCP_DEBUG, 0); - - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - ctx->base.pc_next += 4; - return true; + return 4; /* minimum instruction length */ } static void alpha_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ca11a5fecd..4efd4e95d6 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14844,28 +14844,22 @@ static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) dc->insn_start = tcg_last_op(); } -static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, - const CPUBreakpoint *bp) +static int aarch64_tr_breakpoint_check(DisasContextBase *dcbase, + CPUState *cpu, int bp_flags) { DisasContext *dc = container_of(dcbase, DisasContext, base); - if (bp->flags & BP_CPU) { + if (bp_flags & BP_CPU) { gen_a64_set_pc_im(dc->base.pc_next); gen_helper_check_breakpoints(cpu_env); /* End the TB early; it likely won't be executed */ dc->base.is_jmp = DISAS_TOO_MANY; } else { gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - tb->size below does the right thing. */ - dc->base.pc_next += 4; dc->base.is_jmp = DISAS_NORETURN; } - return true; + return 4; /* minimum instruction length */ } static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) diff --git a/target/arm/translate.c b/target/arm/translate.c index e1a8152598..ebac31c3ac 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9438,12 +9438,12 @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) dc->insn_start = tcg_last_op(); } -static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, - const CPUBreakpoint *bp) +static int arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, + int bp_flags) { DisasContext *dc = container_of(dcbase, DisasContext, base); - if (bp->flags & BP_CPU) { + if (bp_flags & BP_CPU) { gen_set_condexec(dc); gen_set_pc_im(dc, dc->base.pc_next); gen_helper_check_breakpoints(cpu_env); @@ -9451,18 +9451,14 @@ static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, dc->base.is_jmp = DISAS_TOO_MANY; } else { gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - tb->size below does the right thing. */ - /* TODO: Advance PC by correct instruction length to - * avoid disassembler error messages */ - dc->base.pc_next += 2; dc->base.is_jmp = DISAS_NORETURN; } - return true; + /* + * TODO: Advance PC by correct instruction length to avoid disassembler + * error messages. In the meantime, minimum instruction length. + */ + return 2; } static bool arm_pre_translate_insn(DisasContext *dc) diff --git a/target/avr/translate.c b/target/avr/translate.c index d768063d65..73ff467926 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -2944,14 +2944,13 @@ static void avr_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) tcg_gen_insn_start(ctx->npc); } -static bool avr_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, - const CPUBreakpoint *bp) +static int avr_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, + int bp_flags) { DisasContext *ctx = container_of(dcbase, DisasContext, base); gen_breakpoint(ctx); - ctx->base.pc_next += 2; /* advance by minimum insn len so tb->size != 0 */ - return true; + return 2; /* minimum instruction length */ } static void avr_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/cris/translate.c b/target/cris/translate.c index 9258c13e9f..b590e79433 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3118,8 +3118,8 @@ static void cris_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) tcg_gen_insn_start(dc->delayed_branch == 1 ? dc->ppc | 1 : dc->pc); } -static bool cris_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, - const CPUBreakpoint *bp) +static int cris_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, + int bp_flags) { DisasContext *dc = container_of(dcbase, DisasContext, base); @@ -3127,14 +3127,8 @@ static bool cris_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, tcg_gen_movi_tl(env_pc, dc->pc); t_gen_raise_exception(EXCP_DEBUG); dc->base.is_jmp = DISAS_NORETURN; - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - dc->pc += 2; - return true; + + return 2; /* minimum instruction length */ } static void cris_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index b23d36adf5..75c0d40a13 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -540,20 +540,13 @@ static void hexagon_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) tcg_gen_insn_start(ctx->base.pc_next); } -static bool hexagon_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, - const CPUBreakpoint *bp) +static int hexagon_tr_breakpoint_check(DisasContextBase *dcbase, + CPUState *cpu, int bp_flags) { DisasContext *ctx = container_of(dcbase, DisasContext, base); gen_exception_end_tb(ctx, EXCP_DEBUG); - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - ctx->base.pc_next += 4; - return true; + return 4; /* minimum packet length */ } static bool pkt_crosses_page(CPUHexagonState *env, DisasContext *ctx) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 2552747138..87c08948c1 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4159,14 +4159,13 @@ static void hppa_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b); } -static bool hppa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, - const CPUBreakpoint *bp) +static int hppa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, + int bp_flags) { DisasContext *ctx = container_of(dcbase, DisasContext, base); gen_excp(ctx, EXCP_DEBUG); - ctx->base.pc_next += 4; - return true; + return 4; /* minimum instruction length */ } static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 8520d5a1e2..3645fdfe09 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -8635,23 +8635,16 @@ static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); } -static bool i386_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, - const CPUBreakpoint *bp) +static int i386_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, + int bp_flags) { DisasContext *dc = container_of(dcbase, DisasContext, base); /* If RF is set, suppress an internally generated breakpoint. */ int flags = dc->base.tb->flags & HF_RF_MASK ? BP_GDB : BP_ANY; - if (bp->flags & flags) { + if (bp_flags & flags) { gen_debug(dc); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the generic logic setting tb->size later does the right thing. */ - dc->base.pc_next += 1; - return true; - } else { - return false; } + return 1; /* minimum instruction length */ } static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 1fee04b8dd..79c1847d54 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -6208,21 +6208,13 @@ static void m68k_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); } -static bool m68k_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, - const CPUBreakpoint *bp) +static int m68k_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, + int bp_flags) { DisasContext *dc = container_of(dcbase, DisasContext, base); gen_exception(dc, dc->base.pc_next, EXCP_DEBUG); - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - dc->base.pc_next += 2; - - return true; + return 2; /* minimum instruction length */ } static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index c68a84a219..09a364cceb 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1673,21 +1673,13 @@ static void mb_tr_insn_start(DisasContextBase *dcb, CPUState *cs) dc->insn_start = tcg_last_op(); } -static bool mb_tr_breakpoint_check(DisasContextBase *dcb, CPUState *cs, - const CPUBreakpoint *bp) +static int mb_tr_breakpoint_check(DisasContextBase *dcb, CPUState *cs, + int bp_flags) { DisasContext *dc = container_of(dcb, DisasContext, base); gen_raise_exception_sync(dc, EXCP_DEBUG); - - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - dc->base.pc_next += 4; - return true; + return 4; /* minimum instruction length */ } static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index ef00fbd2ac..175bddd4d4 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -16178,22 +16178,16 @@ static void mips_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) ctx->btarget); } -static bool mips_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, - const CPUBreakpoint *bp) +static int mips_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, + int bp_flags) { DisasContext *ctx = container_of(dcbase, DisasContext, base); save_cpu_state(ctx, 1); ctx->base.is_jmp = DISAS_NORETURN; gen_helper_raise_exception_debug(cpu_env); - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - ctx->base.pc_next += 2; - return true; + + return 2; /* minimum instruction length */ } static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 17742cebc7..1d1c66b88f 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -777,20 +777,13 @@ static void nios2_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) tcg_gen_insn_start(dcbase->pc_next); } -static bool nios2_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, - const CPUBreakpoint *bp) +static int nios2_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, + int bp_flags) { DisasContext *dc = container_of(dcbase, DisasContext, base); gen_exception(dc, EXCP_DEBUG); - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - dc->base.pc_next += 4; - return true; + return 4; /* minimum instruction length */ } static void nios2_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 059da48475..8b66a4a077 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1609,20 +1609,15 @@ static void openrisc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) | (dc->base.num_insns > 1 ? 2 : 0)); } -static bool openrisc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, - const CPUBreakpoint *bp) +static int openrisc_tr_breakpoint_check(DisasContextBase *dcbase, + CPUState *cs, int bp_flags) { DisasContext *dc = container_of(dcbase, DisasContext, base); tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); gen_exception(dc, EXCP_DEBUG); dc->base.is_jmp = DISAS_NORETURN; - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - dc->base.pc_next += 4; - return true; + return 4; /* minimum instruction length */ } static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 0a55cb7181..5093be0694 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -8565,21 +8565,14 @@ static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) tcg_gen_insn_start(dcbase->pc_next); } -static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, - const CPUBreakpoint *bp) +static int ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, + int bp_flags) { DisasContext *ctx = container_of(dcbase, DisasContext, base); gen_update_nip(ctx, ctx->base.pc_next); gen_debug_exception(ctx); - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be properly - * cleared -- thus we increment the PC here so that the logic - * setting tb->size below does the right thing. - */ - ctx->base.pc_next += 4; - return true; + return 4; /* minimum instruction length */ } static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5527f37ada..8a6bc58572 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -961,20 +961,15 @@ static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) tcg_gen_insn_start(ctx->base.pc_next); } -static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, - const CPUBreakpoint *bp) +static int riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, + int bp_flags) { DisasContext *ctx = container_of(dcbase, DisasContext, base); tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); ctx->base.is_jmp = DISAS_NORETURN; gen_exception_debug(); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - ctx->base.pc_next += 2; - return true; + return 2; /* minimum instruction length */ } static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) diff --git a/target/rx/translate.c b/target/rx/translate.c index 23a626438a..5e9950f3ac 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -2309,8 +2309,8 @@ static void rx_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) tcg_gen_insn_start(ctx->base.pc_next); } -static bool rx_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, - const CPUBreakpoint *bp) +static int rx_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, + int bp_flags) { DisasContext *ctx = container_of(dcbase, DisasContext, base); @@ -2318,8 +2318,8 @@ static bool rx_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); gen_helper_debug(cpu_env); ctx->base.is_jmp = DISAS_NORETURN; - ctx->base.pc_next += 1; - return true; + + return 1; /* minimum instruction length */ } static void rx_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 92fa7656c2..5aba4ba941 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -6552,8 +6552,8 @@ static void s390x_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) { } -static bool s390x_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, - const CPUBreakpoint *bp) +static int s390x_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, + int bp_flags) { DisasContext *dc = container_of(dcbase, DisasContext, base); @@ -6567,12 +6567,8 @@ static bool s390x_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, dc->base.is_jmp = DISAS_PC_STALE; dc->do_debug = true; - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size does the right thing. */ - dc->base.pc_next += 2; - return true; + + return 2; /* minimum instruction length */ } static void s390x_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 40898e2393..b1e19bf976 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -2289,8 +2289,8 @@ static void sh4_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags); } -static bool sh4_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, - const CPUBreakpoint *bp) +static int sh4_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, + int bp_flags) { DisasContext *ctx = container_of(dcbase, DisasContext, base); @@ -2298,12 +2298,8 @@ static bool sh4_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, gen_save_cpu_state(ctx, true); gen_helper_debug(cpu_env); ctx->base.is_jmp = DISAS_NORETURN; - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - ctx->base.pc_next += 2; - return true; + + return 2; /* minimum instruction length */ } static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index e530cb4aa8..d6b554cefe 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5854,8 +5854,8 @@ static void sparc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) } } -static bool sparc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, - const CPUBreakpoint *bp) +static int sparc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, + int bp_flags) { DisasContext *dc = container_of(dcbase, DisasContext, base); @@ -5865,9 +5865,8 @@ static bool sparc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, gen_helper_debug(cpu_env); tcg_gen_exit_tb(NULL, 0); dc->base.is_jmp = DISAS_NORETURN; - /* update pc_next so that the current instruction is included in tb->size */ - dc->base.pc_next += 4; - return true; + + return 4; /* minimum instruction length */ } static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 865020754d..8c39134d52 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8810,19 +8810,12 @@ static void tricore_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) tcg_gen_insn_start(ctx->base.pc_next); } -static bool tricore_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, - const CPUBreakpoint *bp) +static int tricore_tr_breakpoint_check(DisasContextBase *dcbase, + CPUState *cpu, int bp_flags) { DisasContext *ctx = container_of(dcbase, DisasContext, base); generate_qemu_excp(ctx, EXCP_DEBUG); - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - ctx->base.pc_next += 4; - return true; + return 4; /* minimum instruction length */ } static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 7094cfcf1d..6e7ad266f4 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1232,20 +1232,16 @@ static void xtensa_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) tcg_gen_insn_start(dcbase->pc_next); } -static bool xtensa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, - const CPUBreakpoint *bp) +static int xtensa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, + int bp_flags) { DisasContext *dc = container_of(dcbase, DisasContext, base); tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); gen_exception(dc, EXCP_DEBUG); dc->base.is_jmp = DISAS_NORETURN; - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - dc->base.pc_next += 2; - return true; + + return 2; /* minimum instruction length */ } static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) From patchwork Sat Jul 17 22:18:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 479258 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2745172jao; Sat, 17 Jul 2021 15:22:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwSuUhp3fSDdr19gTSzxdbIYrLzY+AhIQ0vkesWa300yWETtQxgpPk3cs+kVXsMB+klZPZ9 X-Received: by 2002:ac8:4cc8:: with SMTP id l8mr16120964qtv.336.1626560575169; Sat, 17 Jul 2021 15:22:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626560575; cv=none; d=google.com; s=arc-20160816; b=ozWay2Wu+k9zAEYMS9cqo0TiqZOUY029C+5c1EqcT4hSAWRtJJf1mZGJyUSKDc/2ir 3/E+U2t+gEGMYBMMqoJgD8Mm16EY0oY87WvMO3q6BAsy4/qGlYj4Fn+o6Wb7kA9USMZw DIKcdHgbVx5v0YClwvz/ycmA+kjptyhXCR6sDcKSeGOKw49bCSieGSyo0yXnSWZHLHV6 S7hM2Ddi3H8FE2HAAXq2vUY0LDKdhDtMY8wGOrBXHINNGx/ITOkyz2oeKT0CdowAOO7w QfL+VHtKq3kSmxBmOMrBJ2XE9p7BSi5bD3169wdq8HZzrvGPyOP1foO81axgt/XWSkhC 5CDw== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id i15si10730345qkl.197.2021.07.17.15.22.55 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 17 Jul 2021 15:22:55 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=e32ma5Z3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41246 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m4shy-0004ZQ-JK for patch@linaro.org; Sat, 17 Jul 2021 18:22:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55112) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m4seF-00072u-JB for qemu-devel@nongnu.org; Sat, 17 Jul 2021 18:19:03 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:38595) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m4seD-00023X-Vx for qemu-devel@nongnu.org; Sat, 17 Jul 2021 18:19:03 -0400 Received: by mail-pg1-x535.google.com with SMTP id h4so14538273pgp.5 for ; Sat, 17 Jul 2021 15:19:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P6wdHlO6cHzs3gBckJx4V6EWh6TuoOxJ0Z4U1Y1q9Fw=; b=e32ma5Z3xM+TahQ79kY4E7Yq7pcnxIT1+KHbZsVAze4gWRs9PJ1AqAj4FgXCM1uJFN Rlw/UqDGSt1ru4+B3CIOJ2kSFq/T+H9ftDQrcoeRmpA9nEZG/CA5j9pvaSe/jFEgvhYI 1g9YvLyiC5B1qfUNQE9mBSYfPVYodPgJodpuBGKgV6G1+1J8jJ7ZEDusOt/ONHCbB13E 6fD23uoIcPVwuAmsmvsZM21x/5gznSGiSTAfgfYYvFVaFfl02+q5+MA/Y5NtmU35pLnQ +yjqJrjVDBDxstlfLLlxWh/7hIvVOSb6KGq96Pp9ha44N4opLl85mXaZFQvfbOWv1pAm E0cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P6wdHlO6cHzs3gBckJx4V6EWh6TuoOxJ0Z4U1Y1q9Fw=; b=PU49llL2QzjjnVdfVYPj9bO2t7w3Fr75ze6TxqaYPs1S3MB0vibsTqLV+CftmoV2FZ EmfLiasbzyNs53jBRiHgZ1dZOSqzkbdbdngeTDCdAz+6kTk61FDCemFVTMDZfnMGB+dg zlT+/yI+5kGWa3LjvigZ2ePfIf5JUDGflOZTEKSKeqaxxB38liS9ECaS2ZEkPeODvxrn Vk+K6DnspLwDhYtVgreOoHXItieo5UWPT1t5r2MUwi01VVLejqSV9KIbdXZVQIQN8BPH 0QC3HvwUd0MG18MYi1jDaYfJck6musPSNCsV5cxERSqAEWQgjLVTfhQ2AFAOi6MzjEQW +I5g== X-Gm-Message-State: AOAM533WyixL3ke2G5Uq5B4LKUFv8J3iNYKkH5DbQvmMzZbzRAaa0Rt1 JeenIA6VjhQnrd/dt0xJznkLwazYxIcGzw== X-Received: by 2002:a62:1743:0:b029:32c:d286:edd8 with SMTP id 64-20020a6217430000b029032cd286edd8mr17344415pfx.77.1626560340443; Sat, 17 Jul 2021 15:19:00 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id n14sm2405091pjv.34.2021.07.17.15.19.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Jul 2021 15:19:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 12/13] accel/tcg: Hoist tb_cflags to a local in translator_loop Date: Sat, 17 Jul 2021 15:18:50 -0700 Message-Id: <20210717221851.2124573-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210717221851.2124573-1-richard.henderson@linaro.org> References: <20210717221851.2124573-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The access internal to tb_cflags() is atomic. Avoid re-reading it as such for the multiple uses. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- accel/tcg/translator.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 1c44d096d8..449159a27c 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -50,6 +50,7 @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest) void translator_loop(const TranslatorOps *ops, DisasContextBase *db, CPUState *cpu, TranslationBlock *tb, int max_insns) { + uint32_t cflags = tb_cflags(tb); bool plugin_enabled; /* Initialize DisasContext */ @@ -72,8 +73,7 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db, ops->tb_start(db, cpu); tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */ - plugin_enabled = plugin_gen_tb_start(cpu, tb, - tb_cflags(db->tb) & CF_MEMI_ONLY); + plugin_enabled = plugin_gen_tb_start(cpu, tb, cflags & CF_MEMI_ONLY); while (true) { db->num_insns++; @@ -125,14 +125,13 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db, update db->pc_next and db->is_jmp to indicate what should be done next -- either exiting this loop or locate the start of the next instruction. */ - if (db->num_insns == db->max_insns - && (tb_cflags(db->tb) & CF_LAST_IO)) { + if (db->num_insns == db->max_insns && (cflags & CF_LAST_IO)) { /* Accept I/O on the last instruction. */ gen_io_start(); ops->translate_insn(db, cpu); } else { /* we should only see CF_MEMI_ONLY for io_recompile */ - tcg_debug_assert(!(tb_cflags(db->tb) & CF_MEMI_ONLY)); + tcg_debug_assert(!(cflags & CF_MEMI_ONLY)); ops->translate_insn(db, cpu); } From patchwork Sat Jul 17 22:18:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 479262 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp2747281jao; Sat, 17 Jul 2021 15:26:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwg/IsoNyjAB9CogRejEPTHWP8KiYEp01pr3mDVpwqtYMAbdjF0y3/bitmpypNcjjBv4cIA X-Received: by 2002:a5e:9309:: with SMTP id k9mr12338338iom.207.1626560788644; Sat, 17 Jul 2021 15:26:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626560788; cv=none; d=google.com; s=arc-20160816; b=zp1V2iEevjk8lSteMgB8LA1l1L64mmtRQ4BAB7L/6vKloYTxGSblwYgbh+PMWTEJvD ketSxwFA0D5qiIsS5B3V5gxxVLhPzxpB+wBR30a3BsKbZaBmeZUCDPS91/59OVCWoN7v qgiSzmXm/K7lpq6FMq7S++PFFgXLNnrYW+xYSSM/Srzrp+PcuMIigJCfddzd7te2WdOF tkfRdLQc8u+hyExu9ZBISlS2N/esM072RfdWyxPY6OO9lJddrqKratUaIzxtT24pfULs L5m1GXfeaPGgd2EyjTeyUNnejGn2M7aRaFjgH/L3boq6nEE5l9JtdOPKhPmmsXKQQ/jo 5oLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9vx86PgWMxoiJSSmKkLu6qGQtya4TR0bsIaSqpq0o3I=; b=RHesfS1yqwA4Qh9snUy1gme6aCsbqddBsgmp1KWbtOrfFH0EAMjT5fHXbKqbJ4ncsG G6AP7z6brqJLhzaBcHu0fn63aq7/Ph/bbxLHiqQUsweGl1ocSYia+Dj62TIzCitkM8C+ zvjj2Cr74neqvkundbwIVhniTRLajJky6M+7GcurbnK8O6WC6elURMesiETsS6iexNW6 sbcu3sy0xkcjNvpSyCR1GW8AY1nIgP+YeUHQZf8E4AgwD65KUA+RAQl5QH856gltB+y5 hZu1Kb+e1MK2C1soNCfW/3zDXGEPHfr7vVdl6HfJcddfTrRNRnedFN3JqLhrzpt6MvMt 657Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="Ql/2bzHb"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e20si5608363iow.6.2021.07.17.15.26.28 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 17 Jul 2021 15:26:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="Ql/2bzHb"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:56588 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m4slQ-0006Ue-2E for patch@linaro.org; Sat, 17 Jul 2021 18:26:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55128) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m4seG-00076d-LA for qemu-devel@nongnu.org; Sat, 17 Jul 2021 18:19:04 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:43745) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m4seE-00023q-EV for qemu-devel@nongnu.org; Sat, 17 Jul 2021 18:19:04 -0400 Received: by mail-pf1-x431.google.com with SMTP id a127so12597365pfa.10 for ; Sat, 17 Jul 2021 15:19:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9vx86PgWMxoiJSSmKkLu6qGQtya4TR0bsIaSqpq0o3I=; b=Ql/2bzHb1N+7IZInIbM5XZz7O5oAkEhRBzd18PnZScJaHKtLkN/4a506CluuBKNKsw t3ilI+jOZ5gc8YdsIu9vf5TcdyuVsOirQqdcQDCjYaLvYxcPmqq/jLir0THCdajPKQE/ C9yS5Ce4dwEJeL0sEZed91p9aEHQ3j1odjXFXoSZxhlzB1ko8uO9Mp3MtxEpFgLaUnHB 0VxbG9mhSFD5Wp7Yw4NqCYnVanf23RjDfFzzbHJGEgl3ewSExKUwUpIUBUDECHUhDre3 ngIJuIvsBulqQqjJAITHvF+HmCLIZfPIumRGN/9nhJ3wPh027j5GtMYjdifdZ3jyvWof mGVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9vx86PgWMxoiJSSmKkLu6qGQtya4TR0bsIaSqpq0o3I=; b=kthylgjC4I1C9CjHRCcF5QM6FCZn4LKHVhMdYmpEoqhHRVVvUpgXXrzosoFTp2FVoJ UpBfT4CUMXXPRtOyp1Q95SDJ/q/RZ6Xy5fFQxK+l7Ov/xE3KpAG0JRqBwsjDM3+EIn1I mLE6vUK0D82fFmU2aWpy96QjUnnDu4UzjTkoPOVBmg/hKbHDAH6bfnGVxDt0B7j0rAxT txklJYUrHH4BKqDdPCVxJj5bjXnHoRyQsstbJW14pDq3nnG7a4A9NgftJXb75fbc76Hh BZzINrKXuWSO5d+9NYMG2gjukMsNpXEEJ4AZ9l8+kuiRsdBEUs27t1JwMa4SthvBmH7l BOlg== X-Gm-Message-State: AOAM530ZUfQ8XAQVna9DaS++RHouRdk/0f4v5ddYAfpdqqbV1Ih2d6o0 ZZpygk5VqgesfKlRL6231dFSpPEnvRnDfw== X-Received: by 2002:aa7:96b5:0:b029:337:1507:a188 with SMTP id g21-20020aa796b50000b02903371507a188mr8823881pfk.32.1626560341074; Sat, 17 Jul 2021 15:19:01 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id n14sm2405091pjv.34.2021.07.17.15.19.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Jul 2021 15:19:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 13/13] accel/tcg: Encode breakpoint info into tb->cflags Date: Sat, 17 Jul 2021 15:18:51 -0700 Message-Id: <20210717221851.2124573-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210717221851.2124573-1-richard.henderson@linaro.org> References: <20210717221851.2124573-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Having this data in cflags means that hashing takes care of selecting a TB with or without exceptions built in. Which means that we no longer need to flush all TBs. This does require that we single-step while we're within a page that contains a breakpoint, so it's not yet ideal, but should be an improvement over some corner-case slowdowns. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/404 Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 7 ++++ accel/tcg/cpu-exec.c | 68 ++++++++++++++++++++++++++++++- accel/tcg/translate-all.c | 4 -- accel/tcg/translator.c | 85 +++++++++++++++++++++------------------ cpu.c | 24 ----------- 5 files changed, 119 insertions(+), 69 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 6873cce8df..7ab2578f71 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -502,9 +502,16 @@ struct TranslationBlock { #define CF_USE_ICOUNT 0x00020000 #define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock held */ #define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */ +#define CF_BP_MASK 0x00300000 /* See below */ +#define CF_BP_SHIFT 20 #define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ #define CF_CLUSTER_SHIFT 24 +#define CF_BP_NONE (0 << CF_BP_SHIFT) /* TB does not interact with BPs */ +#define CF_BP_SSTEP (1 << CF_BP_SHIFT) /* gdbstub single-step in effect */ +#define CF_BP_GDB (2 << CF_BP_SHIFT) /* gdbstub breakpoint at tb->pc */ +#define CF_BP_CPU (3 << CF_BP_SHIFT) /* arch breakpoint at tb->pc */ + /* Per-vCPU dynamic tracing state used to generate this TB */ uint32_t trace_vcpu_dstate; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 4d043a11aa..179a425ece 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -222,6 +222,65 @@ static inline void log_cpu_exec(target_ulong pc, CPUState *cpu, } } +static uint32_t cflags_for_breakpoints(CPUState *cpu, target_ulong pc, + uint32_t cflags) +{ + uint32_t bflags = 0; + + if (unlikely(cpu->singlestep_enabled)) { + bflags = CF_BP_SSTEP; + } else { + bool match_page = false; + CPUBreakpoint *bp; + + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { + /* Note exact pc matches */ + if (pc == bp->pc) { + if (bp->flags & BP_GDB) { + bflags = CF_BP_GDB; + break; + } + if (bp->flags & BP_CPU) { + bflags = CF_BP_CPU; + break; + } + } + /* Note page matches */ + if (((pc ^ bp->pc) & TARGET_PAGE_MASK) == 0) { + match_page = true; + } + } + + if (likely(!bflags)) { + if (likely(!match_page)) { + return cflags; + } + + /* + * Within the same page as a breakpoint, single-step, + * returning to helper_lookup_tb_ptr after each looking + * for the actual breakpoint. + * + * TODO: Perhaps better to record all of the TBs associated + * with a given virtual page that contains a breakpoint, and + * then invalidate them when a new overlapping breakpoint is + * set on the page. Non-overlapping TBs would not be + * invalidated, nor would any TB need to be invalidated as + * breakpoints are removed. + */ + bflags = CF_NO_GOTO_TB; + } + } + + /* + * Reduce the TB to one insn. + * In the case of a BP hit, we will be raising an exception anyway. + * In the case of a page hit, return to helper_lookup_tb_ptr after + * every insn to look for the breakpoint. + */ + return (cflags & ~CF_COUNT_MASK) | 1 | bflags; +} + /** * helper_lookup_tb_ptr: quick check for next tb * @env: current cpu state @@ -235,11 +294,13 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) CPUState *cpu = env_cpu(env); TranslationBlock *tb; target_ulong cs_base, pc; - uint32_t flags; + uint32_t flags, cflags; cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - tb = tb_lookup(cpu, pc, cs_base, flags, curr_cflags(cpu)); + cflags = cflags_for_breakpoints(cpu, pc, curr_cflags(cpu)); + + tb = tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb == NULL) { return tcg_code_gen_epilogue; } @@ -346,6 +407,8 @@ void cpu_exec_step_atomic(CPUState *cpu) cflags &= ~CF_PARALLEL; /* After 1 insn, return and release the exclusive lock. */ cflags |= CF_NO_GOTO_TB | CF_NO_GOTO_PTR | 1; + /* Raise any post-instruction debug exceptions. */ + cflags = cflags_for_breakpoints(cpu, pc, cflags); tb = tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb == NULL) { @@ -524,6 +587,7 @@ static inline TranslationBlock *tb_find(CPUState *cpu, } else { cpu->cflags_next_tb = -1; } + cflags = cflags_for_breakpoints(cpu, pc, cflags); tb = tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb == NULL) { diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index bf82c15aab..bbfcfb698c 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1432,10 +1432,6 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } QEMU_BUILD_BUG_ON(CF_COUNT_MASK + 1 != TCG_MAX_INSNS); - if (cpu->singlestep_enabled) { - max_insns = 1; - } - buffer_overflow: tb = tcg_tb_alloc(tcg_ctx); if (unlikely(!tb)) { diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 449159a27c..01b48137da 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -33,13 +33,8 @@ void translator_loop_temp_check(DisasContextBase *db) bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest) { - /* Suppress goto_tb if requested. */ - if (tb_cflags(db->tb) & CF_NO_GOTO_TB) { - return false; - } - - /* Suppress goto_tb in the case of single-steping. */ - if (db->singlestep_enabled) { + /* Suppress goto_tb if requested, or required by breakpoints. */ + if (tb_cflags(db->tb) & (CF_NO_GOTO_TB | CF_BP_MASK)) { return false; } @@ -51,6 +46,7 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db, CPUState *cpu, TranslationBlock *tb, int max_insns) { uint32_t cflags = tb_cflags(tb); + int bp_flags = 0; bool plugin_enabled; /* Initialize DisasContext */ @@ -60,7 +56,23 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db, db->is_jmp = DISAS_NEXT; db->num_insns = 0; db->max_insns = max_insns; - db->singlestep_enabled = cpu->singlestep_enabled; + db->singlestep_enabled = false; + + switch (cflags & CF_BP_MASK) { + case CF_BP_NONE: + break; + case CF_BP_SSTEP: + db->singlestep_enabled = true; + break; + case CF_BP_GDB: + bp_flags = BP_GDB; + break; + case CF_BP_CPU: + bp_flags = BP_CPU; + break; + default: + g_assert_not_reached(); + } ops->init_disas_context(db, cpu); tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */ @@ -85,39 +97,34 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db, } /* Pass breakpoint hits to target for further processing */ - if (!db->singlestep_enabled - && unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - if (bp->pc == db->pc_next) { - int len = ops->breakpoint_check(db, cpu, bp->flags); + if (unlikely(bp_flags)) { + int len = ops->breakpoint_check(db, cpu, bp_flags); - /* - * The breakpoint_check hook may use DISAS_TOO_MANY - * to indicate that only one more instruction is to - * be executed. Otherwise it should use DISAS_NORETURN - * when generating an exception, but may use a - * DISAS_TARGET_* value for Something Else. - */ - if (db->is_jmp > DISAS_TOO_MANY) { - /* - * The address covered by the breakpoint must be - * included in [tb->pc, tb->pc + tb->size) in order - * to for it to be properly cleared. Thus we - * increment the PC here so that the logic setting - * tb->size below does the right thing. - */ - tcg_debug_assert(len > 0); - db->pc_next += len; + /* + * When there is a bp hit, we're going to execute a maximum + * of one instruction. The breakpoint_check hook may use + * DISAS_NEXT or DISAS_TOO_MANY to indicate that the current + * instruction should be translated. Anything else is taken + * to mean that an exception has been raised and that zero + * instructions will be executed. + */ + if (db->is_jmp > DISAS_TOO_MANY) { + /* + * The address covered by the breakpoint must be + * included in [tb->pc, tb->pc + tb->size) in order + * to for it to be properly cleared. Thus we + * increment the PC here so that the logic setting + * tb->size below does the right thing. + */ + tcg_debug_assert(len > 0); + db->pc_next += len; - /* - * The breakpoint definitely hit, so decrement the - * number of instructions completed for icount. - */ - db->num_insns--; - goto done; - } - } + /* + * The breakpoint definitely hit, so decrement the + * number of instructions completed for icount. + */ + db->num_insns--; + goto done; } } diff --git a/cpu.c b/cpu.c index 83059537d7..addcb5db9c 100644 --- a/cpu.c +++ b/cpu.c @@ -225,11 +225,6 @@ void tb_invalidate_phys_addr(target_ulong addr) tb_invalidate_phys_page_range(addr, addr + 1); mmap_unlock(); } - -static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) -{ - tb_invalidate_phys_addr(pc); -} #else void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs) { @@ -250,17 +245,6 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs) ram_addr = memory_region_get_ram_addr(mr) + addr; tb_invalidate_phys_page_range(ram_addr, ram_addr + 1); } - -static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) -{ - /* - * There may not be a virtual to physical translation for the pc - * right now, but there may exist cached TB for this pc. - * Flush the whole TB cache to force re-translation of such TBs. - * This is heavyweight, but we're debugging anyway. - */ - tb_flush(cpu); -} #endif /* Add a breakpoint. */ @@ -281,8 +265,6 @@ int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry); } - breakpoint_invalidate(cpu, pc); - if (breakpoint) { *breakpoint = bp; } @@ -310,8 +292,6 @@ void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *bp) { QTAILQ_REMOVE(&cpu->breakpoints, bp, entry); - breakpoint_invalidate(cpu, bp->pc); - trace_breakpoint_remove(cpu->cpu_index, bp->pc, bp->flags); g_free(bp); } @@ -336,10 +316,6 @@ void cpu_single_step(CPUState *cpu, int enabled) cpu->singlestep_enabled = enabled; if (kvm_enabled()) { kvm_update_guest_debug(cpu, 0); - } else { - /* must flush all the translated code to avoid inconsistencies */ - /* XXX: only flush what is necessary */ - tb_flush(cpu); } trace_breakpoint_singlestep(cpu->cpu_index, enabled); }