From patchwork Thu Aug 30 08:21:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 145524 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp536435ljw; Thu, 30 Aug 2018 01:22:07 -0700 (PDT) X-Google-Smtp-Source: ANB0VdagCLCeowhUQHfcATYk4NYVWg7Bhr+Uj9RWzRzpvUQNmsKmxSCHSFDjgan9DgWzAsCmJsd0 X-Received: by 2002:a62:ed5:: with SMTP id 82-v6mr9353363pfo.198.1535617327815; Thu, 30 Aug 2018 01:22:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535617327; cv=none; d=google.com; s=arc-20160816; b=U9sidYSlQXtQlQ0npLeroWNBcUzP0cAkVgC6BXGMXZh9U9cEiB/bVqTPslOKX08/sK hg9a8t2HlgrYBfEH4gvmeYxp3H+S0wRwtlPeEl6xKBzAQL9AvLIlfCRxVMaGNh5AK06H HMqJhcvYsXEtepBz1dkV4RweaWeVSu6yQJv0v42sZL0qcS7jQl+OL70KBX5dv/DbDGx9 cKK4G3XUqSry7wF5anrMJ8/BR9m4LEi8vJ64/1y5jh9Gklix0N6D0zggFdP1NV8eO16D GXvKvFN6UgLprmEirn2eHkBWiYffH+B1iq7g/22MQ6bQPBFPij5BKZL6NRY+lMDsRqMC 96FQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=wnkKMmT7/ywpaLhHSygUL9Mw6DLIQeVe394xHakWOIg=; b=qrizYFuhwYE1riwUZxnkJCkRcYXd6VZITy4nIENyjEEmnOVkO2fB+2yHIVN2/yzE5V jWZEBWhUPQcr6JhIk1MvepnJo55H5NNNnPbLh0pazlNJgeEyAlLS5Hqos9k6fV+e01V0 ODQAy7nvg/a3BJB+DRM6aXRMVdoD6qVor7Dd6clCe6EKUjWWKzPtoTlpmpKbs4PYOcok MVRAQujXj4XAPWVvCeGOrAVADelBuMeoyfzNHVwivH88oXi/+m5ftQ2gLOYQ8bqzmhyd riGcUhAS9fUFdugk38M0noZ2SvUAI84r9Qm1RzIFUmqJ3Ayf0w7++ugtCEJHrVzvS692 KUVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=d7VvPGC+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q23-v6si6322167pgq.483.2018.08.30.01.22.07; Thu, 30 Aug 2018 01:22:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=d7VvPGC+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727965AbeH3MXA (ORCPT + 32 others); Thu, 30 Aug 2018 08:23:00 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:45125 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727863AbeH3MW7 (ORCPT ); Thu, 30 Aug 2018 08:22:59 -0400 Received: by mail-pg1-f196.google.com with SMTP id m4-v6so3551701pgv.12 for ; Thu, 30 Aug 2018 01:22:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wnkKMmT7/ywpaLhHSygUL9Mw6DLIQeVe394xHakWOIg=; b=d7VvPGC+1/HFqHyXuQoPiiW4fbwXzmA9LJvbwgHtrqQ8Km2dkiskXqyIxGTQm3HvvG F1x7ra2bE2P5ghqL+fb4c6IjrH6uznBqc6GDRvoUQMC+LjFCpZB8667VUCVdGRa4nlIs EV4Vo1iM5oWZYMzPqEBhGDFaXTYbR0DJ4iLhA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wnkKMmT7/ywpaLhHSygUL9Mw6DLIQeVe394xHakWOIg=; b=pkZhuv3nB4Rucj9rTM7NBwAoEHdM/EUYDDh1ybeD+vnmc8Ri6sD8FKIUI7N2bMOFqn 73kg4VX29nluElTaN+XOnbHfI60/BtT6H+9VnZluhHkkLmLEGDCr3yKXQbXBDD9Pky4n UL27qly4X7CcGsylgiQ/PXRvMw8bgQYQeXucdXJ0bwRNR3aVb+6DTnYg7AcNk/azvxJx lha2LSjz3iw15mXh68o/f6SzTWNHHOPA0u9zq+6hj8re2dmc9PrKDYK/U20gkEUGprwq GxBfmQJCzqTZxKzPDqsA8h0dvYQQec+u6xkzxfe5Z4mirR/tGs0UdPW5Wyd0Q9GUDhNE MH7w== X-Gm-Message-State: APzg51CmdcTjNPmNw9AvU+NENjlAf0UZ+iC+M3k9fi78q3C8YBqbn4Xn CeFe+6J6D7DTq18h6w6gSLsttg== X-Received: by 2002:a63:5815:: with SMTP id m21-v6mr8742255pgb.78.1535617321554; Thu, 30 Aug 2018 01:22:01 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id j22-v6sm8224885pfh.45.2018.08.30.01.21.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 30 Aug 2018 01:22:00 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter , Rob Herring Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V8 1/9] mmc: sdhci: Add version V4 definition Date: Thu, 30 Aug 2018 16:21:37 +0800 Message-Id: <1535617305-16952-2-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535617305-16952-1-git-send-email-zhang.chunyan@linaro.org> References: <1535617305-16952-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Added definitions for v400, v410, v420. Signed-off-by: Chunyan Zhang Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 2 +- drivers/mmc/host/sdhci.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 97e4efa..01bf88c 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3508,7 +3508,7 @@ int sdhci_setup_host(struct sdhci_host *host) override_timeout_clk = host->timeout_clk; - if (host->version > SDHCI_SPEC_300) { + if (host->version > SDHCI_SPEC_420) { pr_err("%s: Unknown controller version (%d). You may experience problems.\n", mmc_hostname(mmc), host->version); } diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 732d82f..dbd48a8 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -270,6 +270,9 @@ #define SDHCI_SPEC_100 0 #define SDHCI_SPEC_200 1 #define SDHCI_SPEC_300 2 +#define SDHCI_SPEC_400 3 +#define SDHCI_SPEC_410 4 +#define SDHCI_SPEC_420 5 /* * End of controller registers. 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[209.132.180.67]) by mx.google.com with ESMTP id p1-v6si5971858plk.294.2018.08.30.01.22.10; Thu, 30 Aug 2018 01:22:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gUmkOhig; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728003AbeH3MXF (ORCPT + 32 others); Thu, 30 Aug 2018 08:23:05 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:34033 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727863AbeH3MXE (ORCPT ); Thu, 30 Aug 2018 08:23:04 -0400 Received: by mail-pg1-f194.google.com with SMTP id d19-v6so3573746pgv.1 for ; Thu, 30 Aug 2018 01:22:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ergCaURol2Se4ESlok/cft+LAqO2WAQPcTbIx100RWc=; b=gUmkOhigOe2/KEpL5p6vHHpnCyfHlBwsNXrnY0EKBwAXD3TIIKF7RHDde5ALJapTsV Sj5cylNIoGJgrz6V0+zLPaxK2VKvcKnzhTDk7xjVIbdNsFt2ub6d4KmmCYFH8uFMjAxZ gRygHLiV/nwso6zawriYP/ykSHnmt5ehvZv/k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ergCaURol2Se4ESlok/cft+LAqO2WAQPcTbIx100RWc=; b=GKzaYPWjsrAHCTdSLwRSKFKu9CdyMMFiHiY3G1a9vnzi3pES4l/ojYxLOhGFguyd/N Lukcl4KgGMcvOfznJh4sqDmZMLBuSnCkI1pCNYlDtEO5YEO6INtU8paZtNb1jK2xHOQU mRRdN9GnVeouovTNuTfKlzfRaeVQtoQqoOBaIIf9llP9rqhNE8oFQkAVbvfO263NvZhC 6P3fhLpITbc3tg7u9ZWYv2jk0yMV3H6yByFXFczCvXmjv4sadcCQsiuuM2Sy9p6Z3Vk8 H5YOXfaTTErziNgCFJmDp9kv0mngNCSS6VcdSN2oNMsTTQkKQ2aqt9cA0HvSKDwH/aE4 scVw== X-Gm-Message-State: APzg51DkKrkGQ7/uAMnpxbtCXboB369ISYZ3jJzFc95WZM/Id40JkHlO JxAOhkfBCqYPSP8fCqilDHhsbA== X-Received: by 2002:a63:4306:: with SMTP id q6-v6mr7371908pga.181.1535617326234; Thu, 30 Aug 2018 01:22:06 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id j22-v6sm8224885pfh.45.2018.08.30.01.22.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 30 Aug 2018 01:22:05 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter , Rob Herring Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V8 2/9] mmc: sdhci: Add sd host v4 mode Date: Thu, 30 Aug 2018 16:21:38 +0800 Message-Id: <1535617305-16952-3-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535617305-16952-1-git-send-email-zhang.chunyan@linaro.org> References: <1535617305-16952-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For SD host controller version 4.00 or later ones, there're two modes of implementation - Version 3.00 compatible mode or Version 4 mode. This patch introduced an interface to enable v4 mode. Signed-off-by: Chunyan Zhang Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 29 +++++++++++++++++++++++++++++ drivers/mmc/host/sdhci.h | 3 +++ 2 files changed, 32 insertions(+) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 01bf88c..0c61105 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -123,6 +123,29 @@ EXPORT_SYMBOL_GPL(sdhci_dumpregs); * * \*****************************************************************************/ +static void sdhci_do_enable_v4_mode(struct sdhci_host *host) +{ + u16 ctrl2; + + ctrl2 = sdhci_readb(host, SDHCI_HOST_CONTROL2); + if (ctrl2 & SDHCI_CTRL_V4_MODE) + return; + + ctrl2 |= SDHCI_CTRL_V4_MODE; + sdhci_writeb(host, ctrl2, SDHCI_HOST_CONTROL); +} + +/* + * This can be called before sdhci_add_host() by Vendor's host controller + * driver to enable v4 mode if supported. + */ +void sdhci_enable_v4_mode(struct sdhci_host *host) +{ + host->v4_mode = true; + sdhci_do_enable_v4_mode(host); +} +EXPORT_SYMBOL_GPL(sdhci_enable_v4_mode); + static inline bool sdhci_data_line_cmd(struct mmc_command *cmd) { return cmd->data || cmd->flags & MMC_RSP_BUSY; @@ -252,6 +275,9 @@ static void sdhci_init(struct sdhci_host *host, int soft) else sdhci_do_reset(host, SDHCI_RESET_ALL); + if (host->v4_mode) + sdhci_do_enable_v4_mode(host); + sdhci_set_default_irqs(host); host->cqe_on = false; @@ -3378,6 +3404,9 @@ void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1) sdhci_do_reset(host, SDHCI_RESET_ALL); + if (host->v4_mode) + sdhci_do_enable_v4_mode(host); + of_property_read_u64(mmc_dev(host->mmc)->of_node, "sdhci-caps-mask", &dt_caps_mask); of_property_read_u64(mmc_dev(host->mmc)->of_node, diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index dbd48a8..61611e3 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -184,6 +184,7 @@ #define SDHCI_CTRL_DRV_TYPE_D 0x0030 #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CTRL_V4_MODE 0x1000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 #define SDHCI_CAPABILITIES 0x40 @@ -504,6 +505,7 @@ struct sdhci_host { bool preset_enabled; /* Preset is enabled */ bool pending_reset; /* Cmd/data reset is pending */ bool irq_wake_enabled; /* IRQ wakeup is enabled */ + bool v4_mode; /* Host Version 4 Enable */ struct mmc_request *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */ struct mmc_command *cmd; /* Current command */ @@ -752,6 +754,7 @@ bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error, int *data_error); void sdhci_dumpregs(struct sdhci_host *host); +void sdhci_enable_v4_mode(struct sdhci_host *host); void sdhci_start_tuning(struct sdhci_host *host); void sdhci_end_tuning(struct sdhci_host *host); From patchwork Thu Aug 30 08:21:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 145527 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp536600ljw; Thu, 30 Aug 2018 01:22:19 -0700 (PDT) X-Google-Smtp-Source: ANB0VdYpEp8T4W9sSHyUy+gzUMDGb7/nAgWDYGUpBhUbbvcZG7M3xL5Yps5bCCP2AeBFn6diN9Wc X-Received: by 2002:a17:902:b78a:: with SMTP id e10-v6mr9337214pls.79.1535617339061; Thu, 30 Aug 2018 01:22:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535617339; cv=none; d=google.com; s=arc-20160816; b=FjNv3kn/pimy4vNSlXA99YbiF640EgEnspoqukapok6220pM8VY3Kc23WEoK63pu/A zRgFzg7dlHIcD2x+gr8CMRhou2hE1sXIWsQAY8L+n8umEHzDN7LePmuYSSLLaRiArZF4 yK0tPbjYucnZ0DO9dnHul+ilSE6gPGATnOO+astGLmYSE97gQrgDTnOE1/mXgNgOuzAw HPGQkC8XxakwFiHT4xEQWeHTVlzCTAbQlaHVjl7ZQpLbGxIOrdMLw4ZQEqQPTbLPiIta pAgh0ndjBvAYB4+qhCA4gorUtmaxtnf28EL25a6aBWDjNyfAxups0YcDEzxnUdeBu31H BUpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=A+NKJyWIAuCP+cRhS5RHzcAWBSzMQjHaPTkiXZajSsU=; b=tcpMu0xMqFyh0+QCcQaclu2ESmyIbRXnsE1e3yaUx5wgQW/FqsMtZLvOGYZh0qbgYC mJ/Gov/SsJwnP7Q4PkY0XStRLvnFVXcjSjVlPOHdkFjM4HBo/wbMMkjQGXuMJR5/fGPq wgvUK8xLvrk1+y6V9VGjNhdLrArHPKLiWiTka1fueC9QfcmY129Et/bxM2BW+m9fRsRm OZ6YmfJ0aybeMKrBX6x1Xy2FGMgp98tysGNySAWrWC/gm+S9PZ9HUUWNFWXns+9Jqha6 mMrf0pMBxGlvF2nj9lsWji8MkTOdSRnyEGL6jUdnjDTY22FC3KCfmS9Dc3mWsEIlThe6 rRVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=erG8ml1N; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 92-v6si6188682pli.518.2018.08.30.01.22.18; Thu, 30 Aug 2018 01:22:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=erG8ml1N; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728046AbeH3MXO (ORCPT + 32 others); Thu, 30 Aug 2018 08:23:14 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:36379 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728007AbeH3MXN (ORCPT ); Thu, 30 Aug 2018 08:23:13 -0400 Received: by mail-pf1-f195.google.com with SMTP id b11-v6so3565200pfo.3 for ; Thu, 30 Aug 2018 01:22:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=A+NKJyWIAuCP+cRhS5RHzcAWBSzMQjHaPTkiXZajSsU=; b=erG8ml1NfIFcTgKHagMT8IlB29/NqmBs6Xh7xejZyUwmUNZZhjol5DTtWSITl3pg+l IojgaAK8HwnpleXeh+W9mDZGfejysoCKQ6FBNCHjN4b2EX/k7uhO/0lGdD+iAQGVZVSG ytg3G9encNge1RDO5hLFf148r8z0cbEWKKiZo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=A+NKJyWIAuCP+cRhS5RHzcAWBSzMQjHaPTkiXZajSsU=; b=T/JuqbKgEScc8AOkOKuXfyJgkzMkaaf9AAr+iVyevc82s3MInU8PK2gq202oKBw+eI oOccBcUjyYUJS2SWFQSCZBiQOHCmtIdT2XJagjSstS/L1WAPt9SOj2oR7PWvup2Tifbn BI4cfKXXOI2NhmJSkR1UG0Jl3f3oXOR+85Ho1eMkDkaEyMTTm2mo+M9otyLa7PFyDGTr 08GuiY1avQDrPhFinjcmiqb5VvQkpvBeNTNQB7FCT+RPsDZhHzbkQ52gm8jUiC3rx6b9 Ggy0k+sSFMpcLvCrZZec5ZpgrCEA9uHmawTm10sZMcKwtb2dvl3A6yR2HfyDXPEHHVxC JV6Q== X-Gm-Message-State: APzg51CYnn3WJOpINnNNMfTVX83kOPFjvwC07LdZuZ86VkmJ4WvZ11dB qEp4BMyHmDRLfX2F7NKQzUMOug== X-Received: by 2002:a63:6183:: with SMTP id v125-v6mr8964116pgb.242.1535617335287; Thu, 30 Aug 2018 01:22:15 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id j22-v6sm8224885pfh.45.2018.08.30.01.22.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 30 Aug 2018 01:22:14 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter , Rob Herring Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V8 4/9] mmc: sdhci: Add ADMA2 64-bit addressing support for V4 mode Date: Thu, 30 Aug 2018 16:21:40 +0800 Message-Id: <1535617305-16952-5-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535617305-16952-1-git-send-email-zhang.chunyan@linaro.org> References: <1535617305-16952-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ADMA2 64-bit addressing support is divided into V3 mode and V4 mode. So there are two kinds of descriptors for ADMA2 64-bit addressing i.e. 96-bit Descriptor for V3 mode, and 128-bit Descriptor for V4 mode. 128-bit Descriptor is aligned to 8-byte. For V4 mode, ADMA2 64-bit addressing is enabled via Host Control 2 register. Signed-off-by: Chunyan Zhang Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 92 +++++++++++++++++++++++++++++++++++------------- drivers/mmc/host/sdhci.h | 12 +++++-- 2 files changed, 78 insertions(+), 26 deletions(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 6fb70da..17345b6 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -266,6 +266,52 @@ static void sdhci_set_default_irqs(struct sdhci_host *host) sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); } +static void sdhci_config_dma(struct sdhci_host *host) +{ + u8 ctrl; + u16 ctrl2; + + if (host->version < SDHCI_SPEC_200) + return; + + ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); + + /* + * Always adjust the DMA selection as some controllers + * (e.g. JMicron) can't do PIO properly when the selection + * is ADMA. + */ + ctrl &= ~SDHCI_CTRL_DMA_MASK; + if (!(host->flags & SDHCI_REQ_USE_DMA)) + goto out; + + /* Note if DMA Select is zero then SDMA is selected */ + if (host->flags & SDHCI_USE_ADMA) + ctrl |= SDHCI_CTRL_ADMA32; + + if (host->flags & SDHCI_USE_64_BIT_DMA) { + /* + * If v4 mode, all supported DMA can be 64-bit addressing if + * controller supports 64-bit system address, otherwise only + * ADMA can support 64-bit addressing. + */ + if (host->v4_mode) { + ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + ctrl2 |= SDHCI_CTRL_64BIT_ADDR; + sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); + } else if (host->flags & SDHCI_USE_ADMA) { + /* + * Don't need to undo SDHCI_CTRL_ADMA32 in order to + * set SDHCI_CTRL_ADMA64. + */ + ctrl |= SDHCI_CTRL_ADMA64; + } + } + +out: + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); +} + static void sdhci_init(struct sdhci_host *host, int soft) { struct mmc_host *mmc = host->mmc; @@ -913,7 +959,6 @@ static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) { - u8 ctrl; struct mmc_data *data = cmd->data; host->data_timeout = 0; @@ -1009,25 +1054,7 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) } } - /* - * Always adjust the DMA selection as some controllers - * (e.g. JMicron) can't do PIO properly when the selection - * is ADMA. - */ - if (host->version >= SDHCI_SPEC_200) { - ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); - ctrl &= ~SDHCI_CTRL_DMA_MASK; - if ((host->flags & SDHCI_REQ_USE_DMA) && - (host->flags & SDHCI_USE_ADMA)) { - if (host->flags & SDHCI_USE_64_BIT_DMA) - ctrl |= SDHCI_CTRL_ADMA64; - else - ctrl |= SDHCI_CTRL_ADMA32; - } else { - ctrl |= SDHCI_CTRL_SDMA; - } - sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); - } + sdhci_config_dma(host); if (!(host->flags & SDHCI_REQ_USE_DMA)) { int flags; @@ -3511,6 +3538,19 @@ static int sdhci_allocate_bounce_buffer(struct sdhci_host *host) return 0; } +static inline bool sdhci_can_64bit_dma(struct sdhci_host *host) +{ + /* + * According to SD Host Controller spec v4.10, bit[27] added from + * version 4.10 in Capabilities Register is used as 64-bit System + * Address support for V4 mode. + */ + if (host->version >= SDHCI_SPEC_410 && host->v4_mode) + return host->caps & SDHCI_CAN_64BIT_V4; + + return host->caps & SDHCI_CAN_64BIT; +} + int sdhci_setup_host(struct sdhci_host *host) { struct mmc_host *mmc; @@ -3582,7 +3622,7 @@ int sdhci_setup_host(struct sdhci_host *host) * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to * implement. */ - if (host->caps & SDHCI_CAN_64BIT) + if (sdhci_can_64bit_dma(host)) host->flags |= SDHCI_USE_64_BIT_DMA; if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { @@ -3616,8 +3656,8 @@ int sdhci_setup_host(struct sdhci_host *host) */ if (host->flags & SDHCI_USE_64_BIT_DMA) { host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * - SDHCI_ADMA2_64_DESC_SZ; - host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; + SDHCI_ADMA2_64_DESC_SZ(host); + host->desc_sz = SDHCI_ADMA2_64_DESC_SZ(host); } else { host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * SDHCI_ADMA2_32_DESC_SZ; @@ -3625,7 +3665,11 @@ int sdhci_setup_host(struct sdhci_host *host) } host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; - buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz + + /* + * Use zalloc to zero the reserved high 32-bits of 128-bit + * descriptors so that they never need to be written. + */ + buf = dma_zalloc_coherent(mmc_dev(mmc), host->align_buffer_sz + host->adma_table_sz, &dma, GFP_KERNEL); if (!buf) { pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 61611e3..c5cc513 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -185,6 +185,7 @@ #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 #define SDHCI_CTRL_V4_MODE 0x1000 +#define SDHCI_CTRL_64BIT_ADDR 0x2000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 #define SDHCI_CAPABILITIES 0x40 @@ -205,6 +206,7 @@ #define SDHCI_CAN_VDD_330 0x01000000 #define SDHCI_CAN_VDD_300 0x02000000 #define SDHCI_CAN_VDD_180 0x04000000 +#define SDHCI_CAN_64BIT_V4 0x08000000 #define SDHCI_CAN_64BIT 0x10000000 #define SDHCI_SUPPORT_SDR50 0x00000001 @@ -309,8 +311,14 @@ struct sdhci_adma2_32_desc { */ #define SDHCI_ADMA2_DESC_ALIGN 8 -/* ADMA2 64-bit DMA descriptor size */ -#define SDHCI_ADMA2_64_DESC_SZ 12 +/* + * ADMA2 64-bit DMA descriptor size + * According to SD Host Controller spec v4.10, there are two kinds of + * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit + * Descriptor, if Host Version 4 Enable is set in the Host Control 2 + * register, 128-bit Descriptor will be selected. + */ +#define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) /* * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte From patchwork Thu Aug 30 08:21:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 145528 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp536647ljw; Thu, 30 Aug 2018 01:22:23 -0700 (PDT) X-Google-Smtp-Source: ANB0VdY+3T0/hqShevlQIk6kzgh6X1SVMjd5bHebik7K+MjD8VvyPb//1WtcfoqKj2GR9qCp5hhZ X-Received: by 2002:a62:1bc2:: with SMTP id b185-v6mr9551641pfb.170.1535617343081; Thu, 30 Aug 2018 01:22:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535617343; cv=none; d=google.com; s=arc-20160816; b=VQzGkuZUE6t/hi1Vd67QU6D/MIpTrv92QKkyf0Re/HT8Aa0+ITgOXeIQVk5U1r4ewd t9sk9oIU1uDPHKdSV1wB9wAxGQh71bqTkAI1iTqCBUiEfpXL9ztyGskARnwKk/viUeCO fk42YEWtfzKd1OApCLr/dcWqAePb45uCrJGn/5rsHpPtvzcC4sYLoKSlufTsKWjlO+bd ww4DGnmfK+msZA3BPXHoIWihG3FHq8mTibhXlMviTmR9uRSRG3FVvCI4EpWFHn27p8e4 Wj2+QGwVTshnsATDhIZXyFebNB68KJzd53oI6z/pjPut3oA9EvItPCuM63iqvOu2O59s ND+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=3ML8nLjCbNbISUG+Te8iXuKkkqfqMMtZy3g4F+HUTCY=; b=aiVutlJ7aqahynWDVC5biR6rR6dQm8HioxsgA9FCJdCPDQ1Ckz2YULsqE8918fucfV 5En1ZOSGT6+dG6Cg12yo4T+bNjBAfD3rAM4TSxDmlirmMDl1yPap/kMPTlSP9FG1jzdM 6pzmzRuO11wqTbBkIlfesy8rnwpbZbx6yNwxL6TRRponMYotdjtej9XiCe4gQKb1xVIo /3MdcyODFHtwpbD9WsKbjxF9Ua2QXZUWgqMLvH6KcQPJPSG+UwqqpVukQXzFVJluxEJO 7hfrKTMfk1gUlHxSj4Ck8e8qTqeAt1NeN3ER6klgfCH5+HITCF354zJaqnXYCCrFCbeK U8Dw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=W6ReI4x1; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 92-v6si6188682pli.518.2018.08.30.01.22.22; Thu, 30 Aug 2018 01:22:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=W6ReI4x1; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728066AbeH3MXT (ORCPT + 32 others); Thu, 30 Aug 2018 08:23:19 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:36634 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728007AbeH3MXT (ORCPT ); Thu, 30 Aug 2018 08:23:19 -0400 Received: by mail-pg1-f193.google.com with SMTP id d1-v6so3567739pgo.3 for ; Thu, 30 Aug 2018 01:22:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3ML8nLjCbNbISUG+Te8iXuKkkqfqMMtZy3g4F+HUTCY=; b=W6ReI4x1Bc/JmVCF489DBl573vArOUp3cJURvJx9EXcspdw1VS15ynJVuAHRR1exLj x1PjZQ87eAHftm6Wv/LTZk1KuUzvimrJ4PNbshzliEbuMSZg9ESuN57vAAc7G3iLJ4Jz CYvAr9lGj8h1xuaJO2bIJ1CHUu9Cr1+Jp9WkU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3ML8nLjCbNbISUG+Te8iXuKkkqfqMMtZy3g4F+HUTCY=; b=NKSCvXiHu6tHve35jkAKNz55zc+ICDMDqsSFpv+9rzY2NOa1LHdXEj+BYa9ZMi7D6q IJCEaBDKJVvIwPrg+ivpUj7gE02yP6bCpkN8i1bB3xN61QYsQP4acPm/+Joi3+24LhcW Fkr8Yizm0cIjjxzjOCm0AlbqlEUWqsO7dMO6bVYXxQ2eaZilPjWimsgq5oIi3ii2wdjV bqld1LyJkPahSwA5ZQiLj3au9vPlM+lIlvZyeWDEmB0TLPs2rWPhmsab9XKkismrGd62 qXnhCuV+bWo4TcgNqhditCkK571xkybcTXVHsK6RDmRKZ3NW9vtUPbK6dOIb0DbrfFek TDuA== X-Gm-Message-State: APzg51AxpZbJzN6Vg48kyet2STLITZC2pYobJsDTYDI7vuQNE2K7Qs04 hDNdrpla4y1HWE/+sWRMK3s8ig== X-Received: by 2002:a62:9541:: with SMTP id p62-v6mr9585423pfd.194.1535617340445; Thu, 30 Aug 2018 01:22:20 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id j22-v6sm8224885pfh.45.2018.08.30.01.22.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 30 Aug 2018 01:22:19 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter , Rob Herring Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V8 5/9] mmc: sdhci: Add 32-bit block count support for v4 mode Date: Thu, 30 Aug 2018 16:21:41 +0800 Message-Id: <1535617305-16952-6-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535617305-16952-1-git-send-email-zhang.chunyan@linaro.org> References: <1535617305-16952-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Host Controller Version 4.10 re-defines SDMA System Address register as 32-bit Block Count for v4 mode, and SDMA uses ADMA System Address register (05Fh-058h) instead if v4 mode is enabled. Also when using 32-bit block count, 16-bit block count register need to be set to zero. Since using 32-bit Block Count would cause problems for auto-cmd23, it can be chosen via host->quirk2. Signed-off-by: Chunyan Zhang Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 14 +++++++++++++- drivers/mmc/host/sdhci.h | 8 ++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 17345b6..604bf4c 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1073,7 +1073,19 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) /* Set the DMA boundary value and block size */ sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz), SDHCI_BLOCK_SIZE); - sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + + /* + * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count + * can be supported, in that case 16-bit block count register must be 0. + */ + if (host->version >= SDHCI_SPEC_410 && host->v4_mode && + (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) { + if (sdhci_readw(host, SDHCI_BLOCK_COUNT)) + sdhci_writew(host, 0, SDHCI_BLOCK_COUNT); + sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT); + } else { + sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + } } static inline bool sdhci_auto_cmd12(struct sdhci_host *host, diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index c5cc513..f7a1079 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -28,6 +28,7 @@ #define SDHCI_DMA_ADDRESS 0x00 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS +#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS #define SDHCI_BLOCK_SIZE 0x04 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) @@ -462,6 +463,13 @@ struct sdhci_host { * obtainable timeout. */ #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17) +/* + * 32-bit block count may not support eMMC where upper bits of CMD23 are used + * for other purposes. Consequently we support 16-bit block count by default. + * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit + * block count. + */ +#define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */ From patchwork Thu Aug 30 08:21:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 145529 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp536708ljw; Thu, 30 Aug 2018 01:22:27 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZfAwlinglygtrWeGyfVgNv+CUquXAt3rzNMkTrYj1W4FoEeUNUiQl/1sMY8+LqE+UPERf3 X-Received: by 2002:a65:608b:: with SMTP id t11-v6mr8941033pgu.259.1535617347370; Thu, 30 Aug 2018 01:22:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535617347; cv=none; d=google.com; s=arc-20160816; b=WnVeS/7mdN9Ch7KT1HXyQ45CFReVYT5IxVyLUeoe3p5whyax8IDOXP4O/i1DnQnlIj ngXMM+Bb0d44Mk4/BLcKLnbeeByoxF7QaZTwuuouhQTXM29cMDy7+iO90zSlo5rQ+Q9m J8G3VHu3MC2M3Lfu80PG8hoxQWn+3UUQ/shNBbitNBdIlAlS1DP8PhSersbON/j5aYa1 BPqL5tPINmpiDR4CBBqQI7qYD1LOsEHVu0bQXF4DEkQ5cKirEVxhgpbo3Z1kLYWf4Tcp 9yXDmrDuV8zQkPLhW/9UsxxN6F6e4vEK3Xf2gaAn4X3Sazeu0IgjqocSSI5w47chCFoO O2LA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=wEk8L8aXukkJv1K6t9rubtGOMku4W8yH0JTNZ/Ehvmg=; b=LO4pGmTnvyKbfxqdfyUiYCBpqfz+z2htSZufZNjuuVZ0HHiSY+gPeuDHAUGbAtAUmH 2K0mwxujYltGC1NjLNXvhTwNHOmkWAYkcN5HAx8xGDxFwexcO/6E9IGjrrAkXv1Rqen0 jD6oHcrWEOikuXNM4+kUJ01QtQl6aTac6pLw8hJG67U7nbe0EiRyCAMfO58nkcWIie9e xC7Avgt+f/ZwWETD9c5iHSK7Kj+ZvQgp5Ts2VX4iVlzlA0bvTc3TpoDNMLR2PWdODYty OiGyrFk4v1lSjAyIxQsEC7yhTy7x9ffAVXFWfO7D3tyLcaInLdWjfLTaMED78v+18W2r qmTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LR3hnZwZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a24-v6si4848191pgi.515.2018.08.30.01.22.27; Thu, 30 Aug 2018 01:22:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LR3hnZwZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728085AbeH3MXX (ORCPT + 32 others); Thu, 30 Aug 2018 08:23:23 -0400 Received: from mail-pl1-f194.google.com ([209.85.214.194]:45459 "EHLO mail-pl1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728068AbeH3MXW (ORCPT ); Thu, 30 Aug 2018 08:23:22 -0400 Received: by mail-pl1-f194.google.com with SMTP id j8-v6so3505420pll.12 for ; Thu, 30 Aug 2018 01:22:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wEk8L8aXukkJv1K6t9rubtGOMku4W8yH0JTNZ/Ehvmg=; b=LR3hnZwZZEkZzI5hV1ypiw2l3mKEZ19A/ZP0BkAhK6W2995DsTGuLCGpLfACwJFIMp QC1HT2cRxZjjRYzl9EDTMowmO34FS1mKPb5nNM4+Duc5hVJSaWIbR0P4mC+6MtVVg3UU VQXO4qaMd4H1WK9FPwCGYj0R0JTfMbwQ3crMU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wEk8L8aXukkJv1K6t9rubtGOMku4W8yH0JTNZ/Ehvmg=; b=aWdrXAVWFtj9DMpP+aoQrXjLcCgEihDK2j/zxVfNL/YeuHTPF95fybtregVgA4AsN3 Kmqdd2d5NnmrtvqPzZbvjFYHHBIVKoCAsg4OBQyaIQvaBDhbJ+v4gHpKCxIrI762Wqxx wx/M7dH8ztQRVzfFH7we8cGo0bkRyBOmZPiWbDhOiPwyPyY2aJvj/oLqLLrth67Kurx3 iEF7p9hwZX1RSs9O6IgziAURV5kPYYVh1L0jU5pKF73GGZhwJTJRq/oXG96Xm8Tsmn1l IjEpwyM9Wo50rfNWn/L8973v4YrIAvyL+CamHGAWRJN1UsEZQeX9A0g4xiJYVw9XiZv2 m8Ag== X-Gm-Message-State: APzg51D+XzpcaEw4K2nUZflvHm8O0/Nz/KlwSgioVFWhhrAbCRDxJFGd Y+vDMTgcopHitXgZjDqiwS1Onw== X-Received: by 2002:a17:902:722:: with SMTP id 31-v6mr9137959pli.207.1535617344557; Thu, 30 Aug 2018 01:22:24 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id j22-v6sm8224885pfh.45.2018.08.30.01.22.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 30 Aug 2018 01:22:23 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter , Rob Herring Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V8 6/9] mmc: sdhci: Add Auto CMD Auto Select support Date: Thu, 30 Aug 2018 16:21:42 +0800 Message-Id: <1535617305-16952-7-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535617305-16952-1-git-send-email-zhang.chunyan@linaro.org> References: <1535617305-16952-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As SD Host Controller Specification v4.10 documents: Host Controller Version 4.10 defines this "Auto CMD Auto Select" mode. Selection of Auto CMD depends on setting of CMD23 Enable in the Host Control 2 register which indicates whether card supports CMD23. If CMD23 Enable =1, Auto CMD23 is used and if CMD23 Enable =0, Auto CMD12 is used. In case of Version 4.10 or later, use of Auto CMD Auto Select is recommended rather than use of Auto CMD12 Enable or Auto CMD23 Enable. This patch add this new mode support. Signed-off-by: Chunyan Zhang Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 49 ++++++++++++++++++++++++++++++++++++++---------- drivers/mmc/host/sdhci.h | 2 ++ 2 files changed, 41 insertions(+), 10 deletions(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 604bf4c..62d843ac90 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1095,6 +1095,43 @@ static inline bool sdhci_auto_cmd12(struct sdhci_host *host, !mrq->cap_cmd_during_tfr; } +static inline void sdhci_auto_cmd_select(struct sdhci_host *host, + struct mmc_command *cmd, + u16 *mode) +{ + bool use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) && + (cmd->opcode != SD_IO_RW_EXTENDED); + bool use_cmd23 = cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23); + u16 ctrl2; + + /* + * In case of Version 4.10 or later, use of 'Auto CMD Auto + * Select' is recommended rather than use of 'Auto CMD12 + * Enable' or 'Auto CMD23 Enable'. + */ + if (host->version >= SDHCI_SPEC_410 && (use_cmd12 || use_cmd23)) { + *mode |= SDHCI_TRNS_AUTO_SEL; + + ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + if (use_cmd23) + ctrl2 |= SDHCI_CMD23_ENABLE; + else + ctrl2 &= ~SDHCI_CMD23_ENABLE; + sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); + + return; + } + + /* + * If we are sending CMD23, CMD12 never gets sent + * on successful completion (so no Auto-CMD12). + */ + if (use_cmd12) + *mode |= SDHCI_TRNS_AUTO_CMD12; + else if (use_cmd23) + *mode |= SDHCI_TRNS_AUTO_CMD23; +} + static void sdhci_set_transfer_mode(struct sdhci_host *host, struct mmc_command *cmd) { @@ -1123,17 +1160,9 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host, if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI; - /* - * If we are sending CMD23, CMD12 never gets sent - * on successful completion (so no Auto-CMD12). - */ - if (sdhci_auto_cmd12(host, cmd->mrq) && - (cmd->opcode != SD_IO_RW_EXTENDED)) - mode |= SDHCI_TRNS_AUTO_CMD12; - else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { - mode |= SDHCI_TRNS_AUTO_CMD23; + sdhci_auto_cmd_select(host, cmd, &mode); + if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2); - } } if (data->flags & MMC_DATA_READ) diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index f7a1079..4a19ff8 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -42,6 +42,7 @@ #define SDHCI_TRNS_BLK_CNT_EN 0x02 #define SDHCI_TRNS_AUTO_CMD12 0x04 #define SDHCI_TRNS_AUTO_CMD23 0x08 +#define SDHCI_TRNS_AUTO_SEL 0x0C #define SDHCI_TRNS_READ 0x10 #define SDHCI_TRNS_MULTI 0x20 @@ -185,6 +186,7 @@ #define SDHCI_CTRL_DRV_TYPE_D 0x0030 #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CMD23_ENABLE 0x0800 #define SDHCI_CTRL_V4_MODE 0x1000 #define SDHCI_CTRL_64BIT_ADDR 0x2000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 From patchwork Thu Aug 30 08:21:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 145530 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp536775ljw; Thu, 30 Aug 2018 01:22:32 -0700 (PDT) X-Google-Smtp-Source: ANB0VdZW8PPXfPSY1pcfbATi/lzxsvCwYW+/vWIkbzkLrzv6NzVeo9JACaK21xfRG576J7eCxmhP X-Received: by 2002:a62:760a:: with SMTP id r10-v6mr9492924pfc.207.1535617352335; Thu, 30 Aug 2018 01:22:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535617352; cv=none; d=google.com; s=arc-20160816; b=WTrdQI46SIOKa9k+PpfZawgJjXslz/tvtWrzPnuvO7qzhN75xjDmHEJ4Raa42bsHL0 LdmrX1fG+z4Q5J6Pid+sUL+nhc+g6rKXB5zFNI1UxHXHuwurtyWlzYinKWeZFTvXuvt5 EHPxhXohAXJ8N9p6qR0JzRUwoHIgrgwI0YpDkiQ+iRVlGFXicx2w2fdHQeAMul+sEb6l HUT2p2VyT6aLPiLBuTETzLDQAgstI2Rx20WdW/pJRBVPCwYMQ7B51g5ypjXFDWdm4dTd J6l33IM988H9F00+oX1JazsfK85kmqIBNHT6H0qYRk6KavtNw0mqgCgol+qNo3KdB3ra DMUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Ah8c1s4NQMeDLK8VDxuLb0Way+MTHYiFrnLMxjLrOic=; b=1J9pn7xdteb7KU+R6rJDunyPVVD/4rckKLmdpi/6wbZCGHy1X/4mUVuM1fTdaPRztB M93o5JDz0+WVl0cLjR1MuwGbulREe7AuIwpgdqs7jrjdvXIQRUXZVr0Alj0etabvQ0SG Sy5Hj2Pyr70Sxy1K7pVKEMxyvTCr/8wd4fLJPCEYXzlpAlzxGJeSWxKf1hg1eVyEuwq7 QyL3CwTnMITXkvHXXXf3dCpSNiHninl6dTkhYA5HvfBtIzgQJpyzEWPgKNJvIcreBmHc SINFSzJC7XUbrWHIfIVeagRc8pC76ynxWF73eKHYnE0RpVMLVswLy4uET9SnxOOY7eFB iwFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ci2esfNn; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a24-v6si4848191pgi.515.2018.08.30.01.22.32; Thu, 30 Aug 2018 01:22:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ci2esfNn; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728109AbeH3MX2 (ORCPT + 32 others); Thu, 30 Aug 2018 08:23:28 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:38981 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728068AbeH3MX1 (ORCPT ); Thu, 30 Aug 2018 08:23:27 -0400 Received: by mail-pg1-f193.google.com with SMTP id g20-v6so3565829pgv.6 for ; Thu, 30 Aug 2018 01:22:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ah8c1s4NQMeDLK8VDxuLb0Way+MTHYiFrnLMxjLrOic=; b=Ci2esfNnkrultBR2JC8oOpP8798ra5xy2lQVamINyr0vxNV8Va0QyFMobOXx5BrTzh 6AYTQroAWBjY4/dEK9n5xbBTh1ejAtr+e3CihREeL95NRivmUT87sZVVp+HWAHO8tLJb gQM80n7RDnruyd9l43yPB0goqCGQYGKbd3n5M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ah8c1s4NQMeDLK8VDxuLb0Way+MTHYiFrnLMxjLrOic=; b=liml2WMh12h40TF8sjpuPpoTFNwCjsIRoP2OHsyqDUq5wO7Y2MuZYLKT/4o9U2cZDH stESk/krcJyeUE36qLbh4iDkvKMBEFIlHG2gRI+ztaTsg12bBh4/bdHd0Ot3+9ikIgob rZinNp64dkU0UMaLMfEayqILP56bX0Do2VIZ6t8VeCScNI6TXPHePv91wA+dnF5LAc9h OF4kyG6ODn9MMDy/jzTTJUx2+wk9gBS29QJVSaOkRLzqFW0RGJwL06bo6ZTbsYDmSpKu HvFlkHv6iAj+2AjubpgIEyxw1gweUkvvwHTmCoWuSiXycYtqJSBfpKZadse6BP9313jx qgKQ== X-Gm-Message-State: APzg51C2bcczmlcGMHFSmYnEMwQ6YRbkaE4OFY2vAKT1YXNi20wUKgjy blHuaPvPsJjQlx9RVbzcvK1s/A== X-Received: by 2002:aa7:88d3:: with SMTP id p19-v6mr9499481pfo.160.1535617349542; Thu, 30 Aug 2018 01:22:29 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id j22-v6sm8224885pfh.45.2018.08.30.01.22.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 30 Aug 2018 01:22:28 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter , Rob Herring Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V8 7/9] mmc: sdhci: SDMA may use Auto-CMD23 in v4 mode Date: Thu, 30 Aug 2018 16:21:43 +0800 Message-Id: <1535617305-16952-8-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535617305-16952-1-git-send-email-zhang.chunyan@linaro.org> References: <1535617305-16952-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When Host Version 4 Enable is set to 1, SDMA uses ADMA System Address register (05Fh-058h) instead of using register (000h-004h) to indicate its system address of data location. The register (000h-004h) is re-assigned to 32-bit Block Count and Auto CMD23 argument, so then SDMA may use Auto CMD23. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 62d843ac90..606d331 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3834,10 +3834,13 @@ int sdhci_setup_host(struct sdhci_host *host) if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) host->flags |= SDHCI_AUTO_CMD12; - /* Auto-CMD23 stuff only works in ADMA or PIO. */ + /* + * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO. + * For v4 mode, SDMA may use Auto-CMD23 as well. + */ if ((host->version >= SDHCI_SPEC_300) && ((host->flags & SDHCI_USE_ADMA) || - !(host->flags & SDHCI_USE_SDMA)) && + !(host->flags & SDHCI_USE_SDMA) || host->v4_mode) && !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) { host->flags |= SDHCI_AUTO_CMD23; DBG("Auto-CMD23 available\n"); From patchwork Thu Aug 30 08:21:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 145531 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp536848ljw; Thu, 30 Aug 2018 01:22:39 -0700 (PDT) X-Google-Smtp-Source: ANB0VdbHuuw6c4mry2R2NZl09aOVFLOElwvTWyhs7fDpTd24InZplXY4fF/eixvhoAUHtdS37TkV X-Received: by 2002:a62:50c3:: with SMTP id g64-v6mr9363458pfj.244.1535617358940; Thu, 30 Aug 2018 01:22:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535617358; cv=none; d=google.com; s=arc-20160816; b=sWnl6lJgR84xPZz9ZEWiigyKRzZ2JXBLmfEGjlFeX7Ia3Z54fqz3eqd/nvKqLiqu1o Efh3ihZSYOhGSV5N9y67Ykon9/5vH/9lVGFGkYQiafhqieelqCHjBlfIZaYC24XWeYHL QMq/Xe4/Ma2WjSpL2fagOrH/DxFup7sXlVNf2pmhC4NwerKA6aVH6hHsFEYU9Hjd4kmd 9ZlVYbISQqmzLZUAJ4duGnJUjZIkzytnlxnC/lvFru1uV5+b7IvUe1QTv0X+HKFo+0q4 w2dAn7kBAImjPSCNWgz7hj4gHUWj1z0puhkUZRVi5Ugqh4DWwguJQ/lKX3R7rmuOn9B7 lazA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=lbl2Ol4tvWCqEUXMHrsdzYUUWBHhSaEGpsPmSSMCa9U=; b=f46099nAwpURIVIR+fsQmi7jJKaElX30buPlWLQah8n8O2itLC5xSC7+2e/u7g0OBe 8FTPsSMGnNH7gGSj41LpAnDlrUKBN0/WaB8ysJYEFGIlz4oO69vdry1zA2mJe66y3JEz iMJqfRSJnRp2ppXbjCiakz+fDQjeUFbiDKNGQeyHvwXYeUb5FKEmihsc+7sB0yzj0JxA eK/E+PfyCxnKKa5LUty0HDnk/dfnmzywSYf9dR7/QMiywX5wtYzMnvZxrc2E3gsCKHGb BJMSnVPVgmO1S93jNfval4tB245Ei0qgSKx+YqirfdEkCZnS1lM/WJbdxEdVJxbqSDUV yFVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=U5e6xLKl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a6-v6si5707520plz.227.2018.08.30.01.22.38; Thu, 30 Aug 2018 01:22:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=U5e6xLKl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728130AbeH3MXe (ORCPT + 32 others); Thu, 30 Aug 2018 08:23:34 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:45173 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728112AbeH3MXd (ORCPT ); Thu, 30 Aug 2018 08:23:33 -0400 Received: by mail-pf1-f195.google.com with SMTP id i26-v6so3537443pfo.12 for ; Thu, 30 Aug 2018 01:22:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lbl2Ol4tvWCqEUXMHrsdzYUUWBHhSaEGpsPmSSMCa9U=; b=U5e6xLKlsyUqFLXzooBRE+GxRzP0erC+T24dMQYq8N6UT5UfCFqDpL3b2wPFGCMY+M p1qcrcZd70H8ODoftcMjrf+9KQ+u3M1T2cf9N0be60nlN3Jj0DqNFrOH+fePVUMQgMq3 kLBXAxujopIyTZZmjsHzHzgADA5cSOaa3qCQc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lbl2Ol4tvWCqEUXMHrsdzYUUWBHhSaEGpsPmSSMCa9U=; b=otTQ6TgmtBt1PyzHK0cOUAH1GmNBOkCECEOu13+nKvBBza6Tq+q582B4atbhA48+Of ZqRUKIm0itC5WuJBar4GOCJM02mVn423i2wKpI4xABdpdeQ3rc4s7DqJE4TzFoq8PDKf nBvhIek0T1j863vfQfS+AV6gWogtaekKAMUlfH/P2cUpM9/fJEszVBYmDP+JSrJ61FaS pN1Eft85VWm5ReVbatWfl1mkmRwewUngzCXAYJ3MCLhBlKGBHROYteXQW7lDdj8xuxX9 ywFSynEUqkrlZUVZF+HaZ2N4vTz++xtO4aT5VVH5jPRoTyhv0BmT5uXqDGSgs2Fpo3ln NnaA== X-Gm-Message-State: APzg51D3A/1J2mH4GYaymgGB8/iU2LxUY+Sd7E0YGLDN/ZqCxYyTL6Uw H1+ahLa8KJkNIIIBjQiINQxSag== X-Received: by 2002:a63:5964:: with SMTP id j36-v6mr8777160pgm.222.1535617354811; Thu, 30 Aug 2018 01:22:34 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id j22-v6sm8224885pfh.45.2018.08.30.01.22.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 30 Aug 2018 01:22:33 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter , Rob Herring Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V8 8/9] mmc: sdhci-sprd: Add Spreadtrum's initial host controller Date: Thu, 30 Aug 2018 16:21:44 +0800 Message-Id: <1535617305-16952-9-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535617305-16952-1-git-send-email-zhang.chunyan@linaro.org> References: <1535617305-16952-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chunyan Zhang This patch adds the initial support of Secure Digital Host Controller Interface compliant controller found in some latest Spreadtrum chipsets. This patch has been tested on the version of SPRD-R11 controller. R11 is a variant based on SD v4.0 specification. With this driver, R11 mmc can be initialized, can be mounted, read and written. Original-by: Billows Wu Signed-off-by: Chunyan Zhang --- drivers/mmc/host/Kconfig | 13 ++ drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-sprd.c | 498 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 512 insertions(+) create mode 100644 drivers/mmc/host/sdhci-sprd.c -- 2.7.4 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index d09feb6..cf984f0 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -593,6 +593,19 @@ config MMC_SDRICOH_CS To compile this driver as a module, choose M here: the module will be called sdricoh_cs. +config MMC_SDHCI_SPRD + tristate "Spreadtrum SDIO host Controller" + depends on ARCH_SPRD + depends on MMC_SDHCI_PLTFM + select MMC_SDHCI_IO_ACCESSORS + help + This selects the SDIO Host Controller in Spreadtrum + SoCs, this driver supports R11(IP version: R11P0). + + If you have a controller with this interface, say Y or M here. + + If unsure, say N. + config MMC_TMIO_CORE tristate diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index a835d1a..5363d06 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -92,6 +92,7 @@ obj-$(CONFIG_MMC_SDHCI_ST) += sdhci-st.o obj-$(CONFIG_MMC_SDHCI_MICROCHIP_PIC32) += sdhci-pic32.o obj-$(CONFIG_MMC_SDHCI_BRCMSTB) += sdhci-brcmstb.o obj-$(CONFIG_MMC_SDHCI_OMAP) += sdhci-omap.o +obj-$(CONFIG_MMC_SDHCI_SPRD) += sdhci-sprd.o obj-$(CONFIG_MMC_CQHCI) += cqhci.o ifeq ($(CONFIG_CB710_DEBUG),y) diff --git a/drivers/mmc/host/sdhci-sprd.c b/drivers/mmc/host/sdhci-sprd.c new file mode 100644 index 0000000..3d5128e --- /dev/null +++ b/drivers/mmc/host/sdhci-sprd.c @@ -0,0 +1,498 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Secure Digital Host Controller +// +// Copyright (C) 2018 Spreadtrum, Inc. +// Author: Chunyan Zhang + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sdhci-pltfm.h" + +/* SDHCI_ARGUMENT2 register high 16bit */ +#define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16) + +#define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 +#define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) +#define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) +#define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21) +#define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29) + +#define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 +#define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25) +#define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24) + +#define SDHCI_SPRD_REG_DEBOUNCE 0x28C +#define SDHCI_SPRD_BIT_DLL_BAK BIT(0) +#define SDHCI_SPRD_BIT_DLL_VAL BIT(1) + +#define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B + +/* SDHCI_HOST_CONTROL2 */ +#define SDHCI_SPRD_CTRL_HS200 0x0005 +#define SDHCI_SPRD_CTRL_HS400 0x0006 + +/* + * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is + * reserved, and only used on Spreadtrum's design, the hardware cannot work + * if this bit is cleared. + * 1 : normal work + * 0 : hardware reset + */ +#define SDHCI_HW_RESET_CARD BIT(3) + +#define SDHCI_SPRD_MAX_CUR 0xFFFFFF +#define SDHCI_SPRD_CLK_MAX_DIV 1023 + +#define SDHCI_SPRD_CLK_DEF_RATE 26000000 + +struct sdhci_sprd_host { + u32 version; + struct clk *clk_sdio; + struct clk *clk_enable; + u32 base_rate; + int flags; /* backup of host attribute */ +}; + +#define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) + +static void sdhci_sprd_init_config(struct sdhci_host *host) +{ + u16 val; + + /* set dll backup mode */ + val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); + val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; + sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); +} + +static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) +{ + if (unlikely(reg == SDHCI_MAX_CURRENT)) + return SDHCI_SPRD_MAX_CUR; + + return readl_relaxed(host->ioaddr + reg); +} + +static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) +{ + /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ + if (unlikely(reg == SDHCI_MAX_CURRENT)) + return; + + if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) + val = val & SDHCI_SPRD_INT_SIGNAL_MASK; + + writel_relaxed(val, host->ioaddr + reg); +} + +static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg) +{ + /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */ + if (unlikely(reg == SDHCI_BLOCK_COUNT)) + return; + + writew_relaxed(val, host->ioaddr + reg); +} + +static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) +{ + /* + * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the + * standard specification, sdhci_reset() write this register directly + * without checking other reserved bits, that will clear BIT(3) which + * is defined as hardware reset on Spreadtrum's platform and clearing + * it by mistake will lead the card not work. So here we need to work + * around it. + */ + if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { + if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) + val |= SDHCI_HW_RESET_CARD; + } + + writeb_relaxed(val, host->ioaddr + reg); +} + +static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) +{ + u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + + ctrl &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); +} + +static inline void +sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) +{ + u32 dll_dly_offset; + + dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); + if (en) + dll_dly_offset |= mask; + else + dll_dly_offset &= ~mask; + sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); +} + +static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) +{ + u32 div; + + /* select 2x clock source */ + if (base_clk <= clk * 2) + return 0; + + div = (u32) (base_clk / (clk * 2)); + + if ((base_clk / div) > (clk * 2)) + div++; + + if (div > SDHCI_SPRD_CLK_MAX_DIV) + div = SDHCI_SPRD_CLK_MAX_DIV; + + if (div % 2) + div = (div + 1) / 2; + else + div = div / 2; + + return div; +} + +static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, + unsigned int clk) +{ + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + u32 div, val, mask; + + div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); + + clk |= ((div & 0x300) >> 2) | ((div & 0xFF) << 8); + sdhci_enable_clk(host, clk); + + /* enable auto gate sdhc_enable_auto_gate */ + val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); + mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | + SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; + if (mask != (val & mask)) { + val |= mask; + sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); + } +} + +static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) +{ + bool en = false; + + if (clock == 0) { + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + } else if (clock != host->clock) { + sdhci_sprd_sd_clk_off(host); + _sdhci_sprd_set_clock(host, clock); + + if (clock <= 400000) + en = true; + sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | + SDHCI_SPRD_BIT_POSRD_DLY_INV, en); + } else { + _sdhci_sprd_set_clock(host, clock); + } +} + +static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) +{ + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + + return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); +} + +static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) +{ + return 400000; +} + +static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, + unsigned int timing) +{ + u16 ctrl_2; + + if (timing == host->timing) + return; + + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + /* Select Bus Speed Mode for host */ + ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; + switch (timing) { + case MMC_TIMING_UHS_SDR12: + ctrl_2 |= SDHCI_CTRL_UHS_SDR12; + break; + case MMC_TIMING_MMC_HS: + case MMC_TIMING_SD_HS: + case MMC_TIMING_UHS_SDR25: + ctrl_2 |= SDHCI_CTRL_UHS_SDR25; + break; + case MMC_TIMING_UHS_SDR50: + ctrl_2 |= SDHCI_CTRL_UHS_SDR50; + break; + case MMC_TIMING_UHS_SDR104: + ctrl_2 |= SDHCI_CTRL_UHS_SDR104; + break; + case MMC_TIMING_UHS_DDR50: + case MMC_TIMING_MMC_DDR52: + ctrl_2 |= SDHCI_CTRL_UHS_DDR50; + break; + case MMC_TIMING_MMC_HS200: + ctrl_2 |= SDHCI_SPRD_CTRL_HS200; + break; + case MMC_TIMING_MMC_HS400: + ctrl_2 |= SDHCI_SPRD_CTRL_HS400; + break; + default: + break; + } + + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); +} + +static void sdhci_sprd_hw_reset(struct sdhci_host *host) +{ + int val; + + /* + * Note: don't use sdhci_writeb() API here since it is redirected to + * sdhci_sprd_writeb() in which we have a workaround for + * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can + * not be cleared. + */ + val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); + val &= ~SDHCI_HW_RESET_CARD; + writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); + /* wait for 10 us */ + usleep_range(10, 20); + + val |= SDHCI_HW_RESET_CARD; + writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); + usleep_range(300, 500); +} + +static struct sdhci_ops sdhci_sprd_ops = { + .read_l = sdhci_sprd_readl, + .write_l = sdhci_sprd_writel, + .write_b = sdhci_sprd_writeb, + .set_clock = sdhci_sprd_set_clock, + .get_max_clock = sdhci_sprd_get_max_clock, + .get_min_clock = sdhci_sprd_get_min_clock, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, + .hw_reset = sdhci_sprd_hw_reset, +}; + +static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq) +{ + struct sdhci_host *host = mmc_priv(mmc); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + + host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23; + + /* + * From version 4.10 onward, ARGUMENT2 register is also as 32-bit + * block count register which doesn't support stuff bits of + * CMD23 argument on Spreadtrum's sd host controller. + */ + if (host->version >= SDHCI_SPEC_410 && + mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) && + (host->flags & SDHCI_AUTO_CMD23)) + host->flags &= ~SDHCI_AUTO_CMD23; + + sdhci_request(mmc, mrq); +} + +static const struct sdhci_pltfm_data sdhci_sprd_pdata = { + .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, + .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | + SDHCI_QUIRK2_USE_32BIT_BLK_CNT, + .ops = &sdhci_sprd_ops, +}; + +static int sdhci_sprd_probe(struct platform_device *pdev) +{ + struct sdhci_host *host; + struct sdhci_sprd_host *sprd_host; + struct clk *clk; + int ret = 0; + + host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); + if (IS_ERR(host)) + return PTR_ERR(host); + + host->dma_mask = DMA_BIT_MASK(64); + pdev->dev.dma_mask = &host->dma_mask; + host->mmc_host_ops.request = sdhci_sprd_request; + + host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | + MMC_CAP_ERASE | MMC_CAP_CMD23; + ret = mmc_of_parse(host->mmc); + if (ret) + goto pltfm_free; + + sprd_host = TO_SPRD_HOST(host); + + clk = devm_clk_get(&pdev->dev, "sdio"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + goto pltfm_free; + } + sprd_host->clk_sdio = clk; + sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); + if (!sprd_host->base_rate) + sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; + + clk = devm_clk_get(&pdev->dev, "enable"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + goto pltfm_free; + } + sprd_host->clk_enable = clk; + + ret = clk_prepare_enable(sprd_host->clk_sdio); + if (ret) + goto pltfm_free; + + clk_prepare_enable(sprd_host->clk_enable); + if (ret) + goto clk_disable; + + sdhci_sprd_init_config(host); + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> + SDHCI_VENDOR_VER_SHIFT); + + pm_runtime_get_noresume(&pdev->dev); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + pm_runtime_set_autosuspend_delay(&pdev->dev, 50); + pm_runtime_use_autosuspend(&pdev->dev); + pm_suspend_ignore_children(&pdev->dev, 1); + + sdhci_enable_v4_mode(host); + + ret = sdhci_setup_host(host); + if (ret) + goto pm_runtime_disable; + + sprd_host->flags = host->flags; + + ret = __sdhci_add_host(host); + if (ret) + goto err_cleanup_host; + + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_put_autosuspend(&pdev->dev); + + return 0; + +err_cleanup_host: + sdhci_cleanup_host(host); + +pm_runtime_disable: + pm_runtime_disable(&pdev->dev); + pm_runtime_set_suspended(&pdev->dev); + + clk_disable_unprepare(sprd_host->clk_enable); + +clk_disable: + clk_disable_unprepare(sprd_host->clk_sdio); + +pltfm_free: + sdhci_pltfm_free(pdev); + return ret; +} + +static int sdhci_sprd_remove(struct platform_device *pdev) +{ + struct sdhci_host *host = platform_get_drvdata(pdev); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + struct mmc_host *mmc = host->mmc; + + mmc_remove_host(mmc); + clk_disable_unprepare(sprd_host->clk_sdio); + clk_disable_unprepare(sprd_host->clk_enable); + + mmc_free_host(mmc); + + return 0; +} + +static const struct of_device_id sdhci_sprd_of_match[] = { + { .compatible = "sprd,sdhci-r11", }, + { } +}; +MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); + +#ifdef CONFIG_PM +static int sdhci_sprd_runtime_suspend(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + + sdhci_runtime_suspend_host(host); + + clk_disable_unprepare(sprd_host->clk_sdio); + clk_disable_unprepare(sprd_host->clk_enable); + + return 0; +} + +static int sdhci_sprd_runtime_resume(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + int ret; + + ret = clk_prepare_enable(sprd_host->clk_enable); + if (ret) + return ret; + + ret = clk_prepare_enable(sprd_host->clk_sdio); + if (ret) { + clk_disable_unprepare(sprd_host->clk_enable); + return ret; + } + + sdhci_runtime_resume_host(host); + + return 0; +} +#endif + +static const struct dev_pm_ops sdhci_sprd_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) + SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, + sdhci_sprd_runtime_resume, NULL) +}; + +static struct platform_driver sdhci_sprd_driver = { + .probe = sdhci_sprd_probe, + .remove = sdhci_sprd_remove, + .driver = { + .name = "sdhci_sprd_r11", + .of_match_table = of_match_ptr(sdhci_sprd_of_match), + .pm = &sdhci_sprd_pm_ops, + }, +}; +module_platform_driver(sdhci_sprd_driver); + +MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:sdhci-sprd-r11");