From patchwork Wed Aug 29 06:04:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "\(Exiting\) Baolin Wang" X-Patchwork-Id: 145377 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp296793ljw; Tue, 28 Aug 2018 23:04:29 -0700 (PDT) X-Google-Smtp-Source: ANB0VdYhAVeh9jsXdckGM0DWH+Wct047HVJA1cd5Q/ElI9zaepjYdHCc4a3BFIa9I05VPNBd1XnH X-Received: by 2002:a63:4c54:: with SMTP id m20-v6mr4417054pgl.292.1535522669621; Tue, 28 Aug 2018 23:04:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535522669; cv=none; d=google.com; s=arc-20160816; b=l6S0hlP+2ZVWrFHwzifJRKLtPcaObo0yg4Un0MqsdHklalZVgYtADZQRFIge82Yjc0 UjmaH2R1Q1eFbvndPj5KWhz38PKklZdXzSkEinzz7EH9a5oRmJSyWt55oo0VWHOUVbJY IR4XLVdhBF3CuMwAwVAPJ36w5DhAJnMOLrk+PxGN0Fx+mhd1wkqNbel2X5HZG/okZRJd chgC7Tcv3qm2+HZKPBX2CkKGscgi1MTCHtcvChfgP/HUpGF4wI3qD/EoaJm77mCkZkib gWHbuZY1ON4RKAGn07Tzs0MLKclHh21pmbm+LzPd86WFC1XKe9WYfgDfSi12xYCI12Z5 hQ8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=QYs/+wtywkNmEn4RKbGv+95uUTJD4f+z+ToiDyC70jw=; b=YboxBvMIlJMjtmRd9wRBn7G48aVPAvbCZ9gwg9BQ5UbKC/bSTqlfmJjfe8sOuWDYgP J2W+yO1abAWOrsE4kJUJsU+sAR1L2G8pTUsZR5kw78q4+BQPQZaAcxanqnDsrALfcgLp V+/ZIb5PEzjQecE2uL2cdInpnbq8T9vVpuwcnRT0rY68xWqsHIOvzLnsNHz/QwYaLqYW Y2fizGH8+QD/HgvR01oaI+ubbtAsRpsQnO67O/M36dBXFWwPrvTBAXpszQKmKIpvahim /oJxOcrIRtDDuoQZXIWQdntRAOiP5v5BSxMqqHCEwYzPVx3x8zcMutgn2qcqxpVHRHZr YLOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KJ9gNWIr; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h14-v6si2985515pgg.540.2018.08.28.23.04.29; Tue, 28 Aug 2018 23:04:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KJ9gNWIr; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727324AbeH2J7h (ORCPT + 6 others); Wed, 29 Aug 2018 05:59:37 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:43151 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727316AbeH2J7h (ORCPT ); Wed, 29 Aug 2018 05:59:37 -0400 Received: by mail-pf1-f196.google.com with SMTP id j26-v6so1778137pfi.10 for ; Tue, 28 Aug 2018 23:04:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=QYs/+wtywkNmEn4RKbGv+95uUTJD4f+z+ToiDyC70jw=; b=KJ9gNWIrTIbnMM84F7GPQrOdUeQ5Vd7OUPBeDIOV1lnn5zgJO5OQkXcaED86nWEQYh uMhDaq8MLcLSyDZ2Vjfok8mT579dEtFIwIjJFrVY55vxtKmgc9/nzU+yuLL4Ct1WCbgY agnZQE2Sx91wEhIw4iyvkdIzInWgKDYuW77ms= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=QYs/+wtywkNmEn4RKbGv+95uUTJD4f+z+ToiDyC70jw=; b=kGPN2+PHE+y8MLv4qhJKM/P06aILeXBivpdiPuB9U0WPRfXWWk9m2nArEIWGMGikos 2gB6TtQg/78k6dGD1TRZvoU52B46Ef6+x4oBpkv22L/OsGZeEQWHde+Sm6cFBm9ivlSK 02vrlnYuu+I24bI+3aD7ETkfSjm1ZKdwqvfSROeLYhROwGf47iSIqSCnYV7T1dXR+dDY xHntTCWwMJ2Mu6g7GSblq+uZmLs83wHBOQWnUdmRJ9HaEJRF3AVAIwpe0y+IgA6i+ZO1 6ezub8dcHA48s1Rj/yIyAnTveMOcSDfCToT9iohpfKZ2wzlDoo9nRYHDETcUcqWNWyPh Glkg== X-Gm-Message-State: APzg51BOrZxaplf1kBGWtx9eJJnfcDTysqFAwl8NZD2Z82NBlTxD/XDV 1WZbJ5EsvZWQ1Tm76KaHnaTzww== X-Received: by 2002:a63:1618:: with SMTP id w24-v6mr4489155pgl.43.1535522663479; Tue, 28 Aug 2018 23:04:23 -0700 (PDT) Received: from baolinwangubtpc.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id c85-v6sm5188729pfd.110.2018.08.28.23.04.19 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 28 Aug 2018 23:04:23 -0700 (PDT) From: Baolin Wang To: jic23@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com Cc: knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net, freeman.liu@spreadtrum.com, broonie@kernel.org, baolin.wang@linaro.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/2] iio: adc: sc27xx: Add ADC scale calibration Date: Wed, 29 Aug 2018 14:04:05 +0800 Message-Id: <61cad47d5d10c771d3cc371744533e87d192ee96.1535434262.git.baolin.wang@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <0adef2f9eafa913eb9f4bc1ed3dc643d09bf02a2.1535434262.git.baolin.wang@linaro.org> References: <0adef2f9eafa913eb9f4bc1ed3dc643d09bf02a2.1535434262.git.baolin.wang@linaro.org> In-Reply-To: <0adef2f9eafa913eb9f4bc1ed3dc643d09bf02a2.1535434262.git.baolin.wang@linaro.org> References: <0adef2f9eafa913eb9f4bc1ed3dc643d09bf02a2.1535434262.git.baolin.wang@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds support to read calibration values from the eFuse controller to calibrate the ADC channel scales, which can make ADC sample data more accurate. Signed-off-by: Baolin Wang --- Changes from v1: - Use nvmem_cell_read() instead of nvmem_cell_read_u32(). --- .../bindings/iio/adc/sprd,sc27xx-adc.txt | 4 ++ drivers/iio/adc/sc27xx_adc.c | 74 +++++++++++++++++++- 2 files changed, 75 insertions(+), 3 deletions(-) -- 1.7.9.5 diff --git a/Documentation/devicetree/bindings/iio/adc/sprd,sc27xx-adc.txt b/Documentation/devicetree/bindings/iio/adc/sprd,sc27xx-adc.txt index 8aad960..b4daa15 100644 --- a/Documentation/devicetree/bindings/iio/adc/sprd,sc27xx-adc.txt +++ b/Documentation/devicetree/bindings/iio/adc/sprd,sc27xx-adc.txt @@ -12,6 +12,8 @@ Required properties: - interrupts: The interrupt number for the ADC device. - #io-channel-cells: Number of cells in an IIO specifier. - hwlocks: Reference to a phandle of a hwlock provider node. +- nvmem-cells: A phandle to the calibration cells provided by eFuse device. +- nvmem-cell-names: Should be "big_scale_calib", "small_scale_calib". Example: @@ -32,5 +34,7 @@ Example: interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; #io-channel-cells = <1>; hwlocks = <&hwlock 4>; + nvmem-cells = <&adc_big_scale>, <&adc_small_scale>; + nvmem-cell-names = "big_scale_calib", "small_scale_calib"; }; }; diff --git a/drivers/iio/adc/sc27xx_adc.c b/drivers/iio/adc/sc27xx_adc.c index 153c311..7940b23 100644 --- a/drivers/iio/adc/sc27xx_adc.c +++ b/drivers/iio/adc/sc27xx_adc.c @@ -5,10 +5,12 @@ #include #include #include +#include #include #include #include #include +#include /* PMIC global registers definition */ #define SC27XX_MODULE_EN 0xc08 @@ -87,16 +89,73 @@ struct sc27xx_adc_linear_graph { * should use the small-scale graph, and if more than 1.2v, we should use the * big-scale graph. */ -static const struct sc27xx_adc_linear_graph big_scale_graph = { +static struct sc27xx_adc_linear_graph big_scale_graph = { 4200, 3310, 3600, 2832, }; -static const struct sc27xx_adc_linear_graph small_scale_graph = { +static struct sc27xx_adc_linear_graph small_scale_graph = { 1000, 3413, 100, 341, }; +static const struct sc27xx_adc_linear_graph big_scale_graph_calib = { + 4200, 856, + 3600, 733, +}; + +static const struct sc27xx_adc_linear_graph small_scale_graph_calib = { + 1000, 833, + 100, 80, +}; + +static int sc27xx_adc_get_calib_data(u32 calib_data, int calib_adc) +{ + return ((calib_data & 0xff) + calib_adc - 128) * 4; +} + +static int sc27xx_adc_scale_calibration(struct sc27xx_adc_data *data, + bool big_scale) +{ + const struct sc27xx_adc_linear_graph *calib_graph; + struct sc27xx_adc_linear_graph *graph; + struct nvmem_cell *cell; + const char *cell_name; + u32 calib_data = 0; + void *buf; + size_t len; + + if (big_scale) { + calib_graph = &big_scale_graph_calib; + graph = &big_scale_graph; + cell_name = "big_scale_calib"; + } else { + calib_graph = &small_scale_graph_calib; + graph = &small_scale_graph; + cell_name = "small_scale_calib"; + } + + cell = nvmem_cell_get(data->dev, cell_name); + if (IS_ERR(cell)) + return PTR_ERR(cell); + + buf = nvmem_cell_read(cell, &len); + nvmem_cell_put(cell); + + if (IS_ERR(buf)) + return PTR_ERR(buf); + + memcpy(&calib_data, buf, min(len, sizeof(u32))); + + /* Only need to calibrate the adc values in the linear graph. */ + graph->adc0 = sc27xx_adc_get_calib_data(calib_data, calib_graph->adc0); + graph->adc1 = sc27xx_adc_get_calib_data(calib_data >> 8, + calib_graph->adc1); + + kfree(buf); + return 0; +} + static int sc27xx_adc_get_ratio(int channel, int scale) { switch (channel) { @@ -209,7 +268,7 @@ static void sc27xx_adc_volt_ratio(struct sc27xx_adc_data *data, *div_denominator = ratio & SC27XX_RATIO_DENOMINATOR_MASK; } -static int sc27xx_adc_to_volt(const struct sc27xx_adc_linear_graph *graph, +static int sc27xx_adc_to_volt(struct sc27xx_adc_linear_graph *graph, int raw_adc) { int tmp; @@ -390,6 +449,15 @@ static int sc27xx_adc_enable(struct sc27xx_adc_data *data) if (ret) goto disable_clk; + /* ADC channel scales' calibration from nvmem device */ + ret = sc27xx_adc_scale_calibration(data, true); + if (ret) + goto disable_clk; + + ret = sc27xx_adc_scale_calibration(data, false); + if (ret) + goto disable_clk; + return 0; disable_clk: