From patchwork Wed Jul 14 13:38:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Riedm=C3=BCller?= X-Patchwork-Id: 477115 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBCCAC11F67 for ; Wed, 14 Jul 2021 13:38:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B5740613D2 for ; Wed, 14 Jul 2021 13:38:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231819AbhGNNlo (ORCPT ); Wed, 14 Jul 2021 09:41:44 -0400 Received: from mickerik.phytec.de ([195.145.39.210]:56718 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231847AbhGNNln (ORCPT ); Wed, 14 Jul 2021 09:41:43 -0400 DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a4; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1626269930; x=1628861930; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=BkdkwmiGogTIJ3tL5zily69sBf7WMKTObrHPm+hw5mQ=; b=R2Gf5/K3uks2BR8+BP0f95/ZK5fP3yFG05o1EbKS0o8F//0ZQcqXJRBnTuIBEwCW 3gbTLjNoFO7NzV75pKZ3A4au4836s9lEMKsvNUJeb1pdfZhDQMdTyxYkk5bjAsUf iH1xpyd15El+3pBwIwKFppXa4ieCGaudum0ELaOEeDI=; X-AuditID: c39127d2-1d8f870000001daf-1c-60eee8e959f5 Received: from idefix.phytec.de (Unknown_Domain [172.16.0.10]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id 6A.57.07599.9E8EEE06; Wed, 14 Jul 2021 15:38:49 +0200 (CEST) Received: from augenblix2.phytec.de ([172.16.0.56]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2021071415384960-1154288 ; Wed, 14 Jul 2021 15:38:49 +0200 From: Stefan Riedmueller To: Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring Cc: Enrico Scholz , Stefan Riedmueller , Sakari Ailus , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 1/6] media: mt9p031: Read back the real clock rate Date: Wed, 14 Jul 2021 15:38:44 +0200 Message-Id: <20210714133849.1041619-2-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210714133849.1041619-1-s.riedmueller@phytec.de> References: <20210714133849.1041619-1-s.riedmueller@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 14.07.2021 15:38:49, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 14.07.2021 15:38:49 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrKLMWRmVeSWpSXmKPExsWyRoCBS/fli3cJBmem2VjMP3KO1WLvsQss Fp0Tl7BbXN41h82iZ8NWVotlm/4wWbTuPcJu8WnLNyYHDo/ZHTNZPTat6mTzmHcy0GPFyv9M Hp83yQWwRnHZpKTmZJalFunbJXBlTGr6zF5wiL/i58TrTA2MHbxdjJwcEgImEl03LjOB2EIC 2xglPl7h6mLkArIvMEpcbzzPCpJgEzCSWDCtkQkkISLQxiix40gzmMMs8JRR4sGth+wgVcIC rhKT7s8EG8UioCrx5M0KZhCbV8BOYsq2XywQ6+QlZl76DlbPKWAv0X30HwvEajuJO5fnM0LU C0qcnPmEBWSBhMAVRomFOzYwQjQLSZxefBZsKLOAtsSyha+ZJzAKzELSMwtJagEj0ypGodzM 5OzUosxsvYKMypLUZL2U1E2MwKA+PFH90g7GvjkehxiZOBgPMUpwMCuJ8C41epsgxJuSWFmV WpQfX1Sak1p8iFGag0VJnHcDb0mYkEB6YklqdmpqQWoRTJaJg1OqgVHlwPm25ZMm3v+q1P1X PeTKy/LfTv7C339l7HwZdKB1e4us4vc9/fc+iO4UzxINNrm0ZC5n68000wvTsxzCJbb+zNfy MHihNq99S6Hf6abZ9+b386XMSEi4MGnt/kUz/d86X35vluyw/9ev+MacJUln1G/6JrZbe+2O XcgqO2v+C3bbloMPxFmVWIozEg21mIuKEwEZlgjbWAIAAA== Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Enrico Scholz The real and requested clock can differ and because it is used to calculate PLL values, the real clock rate should be read. Signed-off-by: Enrico Scholz Signed-off-by: Stefan Riedmueller Reviewed-by: Laurent Pinchart --- drivers/media/i2c/mt9p031.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index 6eb88ef99783..9dea7c813852 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c @@ -229,6 +229,7 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); struct mt9p031_platform_data *pdata = mt9p031->pdata; + unsigned long ext_freq; int ret; mt9p031->clk = devm_clk_get(&client->dev, NULL); @@ -239,13 +240,15 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) if (ret < 0) return ret; + ext_freq = clk_get_rate(mt9p031->clk); + /* If the external clock frequency is out of bounds for the PLL use the * pixel clock divider only and disable the PLL. */ - if (pdata->ext_freq > limits.ext_clock_max) { + if (ext_freq > limits.ext_clock_max) { unsigned int div; - div = DIV_ROUND_UP(pdata->ext_freq, pdata->target_freq); + div = DIV_ROUND_UP(ext_freq, pdata->target_freq); div = roundup_pow_of_two(div) / 2; mt9p031->clk_div = min_t(unsigned int, div, 64); @@ -254,7 +257,7 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) return 0; } - mt9p031->pll.ext_clock = pdata->ext_freq; + mt9p031->pll.ext_clock = ext_freq; mt9p031->pll.pix_clock = pdata->target_freq; mt9p031->use_pll = true; From patchwork Wed Jul 14 13:38:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Riedm=C3=BCller?= X-Patchwork-Id: 477114 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 372B1C11F66 for ; Wed, 14 Jul 2021 13:38:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 205DE613C3 for ; Wed, 14 Jul 2021 13:38:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232684AbhGNNlr (ORCPT ); Wed, 14 Jul 2021 09:41:47 -0400 Received: from mickerik.phytec.de ([195.145.39.210]:56700 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232400AbhGNNlp (ORCPT ); Wed, 14 Jul 2021 09:41:45 -0400 DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a4; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1626269930; x=1628861930; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=qN6QTxTTKZhnbCx2gpq04CN4bCn0nWKxKQ/ztel5F0Q=; b=Hr8IDNoSA8mqF6jN4MkG8qhN5XEtwlzPUj8o9TtUgEG2VNwbqOAIICAMymKVB8B2 +wjtQrSNJ9IuLpwOuRWh1NBAtB1iFgVySZv4o2yAmMp88WMy7Qwd996vDoF2neFl OANntsCkU4IhrCZ2wR/OYrgtkNx/jfQZW66jqN6PHto=; X-AuditID: c39127d2-1e4f970000001daf-24-60eee8ead8d4 Received: from idefix.phytec.de (Unknown_Domain [172.16.0.10]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id 9C.57.07599.AE8EEE06; Wed, 14 Jul 2021 15:38:50 +0200 (CEST) Received: from augenblix2.phytec.de ([172.16.0.56]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2021071415385038-1154291 ; Wed, 14 Jul 2021 15:38:50 +0200 From: Stefan Riedmueller To: Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring Cc: Stefan Riedmueller , Sakari Ailus , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 4/6] media: mt9p031: Use BIT macro Date: Wed, 14 Jul 2021 15:38:47 +0200 Message-Id: <20210714133849.1041619-5-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210714133849.1041619-1-s.riedmueller@phytec.de> References: <20210714133849.1041619-1-s.riedmueller@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 14.07.2021 15:38:50, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 14.07.2021 15:38:50 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrNLMWRmVeSWpSXmKPExsWyRoCBS/fVi3cJBqs/G1jMP3KO1aJz4hJ2 i8u75rBZ9GzYymqxbNMfJovWvUfYLT5t+cbkwO4xu2Mmq8emVZ1sHvNOBnp83iQXwBLFZZOS mpNZllqkb5fAlXHk5Wq2gp2yFWsfHmFrYHwi0cXIySEhYCLx6/Qpli5GLg4hgW2MEv+W72WD cC4wSvxtvcMCUsUmYCSxYFojE0hCRKCNUWLHkWYwh1lgC6PE9MvL2UCqhAVMJTb9ncwKYrMI qEr83t0HVMTBwStgJ3F0YyLEOnmJmZe+s4PYnAL2Et1H/4EtEAIquXN5PiOIzSsgKHFy5hOw kyQErjBK3F33nBGiWUji9OKzzCA2s4C2xLKFr5knMArMQtIzC0lqASPTKkah3Mzk7NSizGy9 gozKktRkvZTUTYzAAD48Uf3SDsa+OR6HGJk4GA8xSnAwK4nwLjV6myDEm5JYWZValB9fVJqT WnyIUZqDRUmcdwNvSZiQQHpiSWp2ampBahFMlomDU6qBce1zqcAb+bY8KdGyL/rYJTWfX/6z pDd5mf/7sLS2uJl3MnoScpZOuT4jdYH+MwfNw54zMnrPHFbbd+OF9bZN1d9tGp/eWpayuEqE 7YnXmvbEicmnXR80phpbdR+J+p0WkyF65a5WEgPXjltix845Tt79w02zPvDfqocF4gmRC/9+ PzbPYvanm0osxRmJhlrMRcWJAL6XkuBOAgAA Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Make use of the BIT macro for setting individual bits. This improves readability and safety with respect to shifts. When on it also remove two zero value disable defines. Signed-off-by: Stefan Riedmueller --- drivers/media/i2c/mt9p031.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index ee2777059682..cbce8b88dbcf 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c @@ -76,40 +76,38 @@ #define MT9P031_PLL_CONFIG_1 0x11 #define MT9P031_PLL_CONFIG_2 0x12 #define MT9P031_PIXEL_CLOCK_CONTROL 0x0a -#define MT9P031_PIXEL_CLOCK_INVERT (1 << 15) +#define MT9P031_PIXEL_CLOCK_INVERT BIT(15) #define MT9P031_PIXEL_CLOCK_SHIFT(n) ((n) << 8) #define MT9P031_PIXEL_CLOCK_DIVIDE(n) ((n) << 0) #define MT9P031_RESTART 0x0b -#define MT9P031_FRAME_PAUSE_RESTART (1 << 1) -#define MT9P031_FRAME_RESTART (1 << 0) +#define MT9P031_FRAME_PAUSE_RESTART BIT(1) +#define MT9P031_FRAME_RESTART BIT(0) #define MT9P031_SHUTTER_DELAY 0x0c #define MT9P031_RST 0x0d -#define MT9P031_RST_ENABLE 1 -#define MT9P031_RST_DISABLE 0 +#define MT9P031_RST_ENABLE BIT(0) #define MT9P031_READ_MODE_1 0x1e #define MT9P031_READ_MODE_2 0x20 -#define MT9P031_READ_MODE_2_ROW_MIR (1 << 15) -#define MT9P031_READ_MODE_2_COL_MIR (1 << 14) -#define MT9P031_READ_MODE_2_ROW_BLC (1 << 6) +#define MT9P031_READ_MODE_2_ROW_MIR BIT(15) +#define MT9P031_READ_MODE_2_COL_MIR BIT(14) +#define MT9P031_READ_MODE_2_ROW_BLC BIT(6) #define MT9P031_ROW_ADDRESS_MODE 0x22 #define MT9P031_COLUMN_ADDRESS_MODE 0x23 #define MT9P031_GLOBAL_GAIN 0x35 #define MT9P031_GLOBAL_GAIN_MIN 8 #define MT9P031_GLOBAL_GAIN_MAX 1024 #define MT9P031_GLOBAL_GAIN_DEF 8 -#define MT9P031_GLOBAL_GAIN_MULT (1 << 6) +#define MT9P031_GLOBAL_GAIN_MULT BIT(6) #define MT9P031_ROW_BLACK_TARGET 0x49 #define MT9P031_ROW_BLACK_DEF_OFFSET 0x4b #define MT9P031_GREEN1_OFFSET 0x60 #define MT9P031_GREEN2_OFFSET 0x61 #define MT9P031_BLACK_LEVEL_CALIBRATION 0x62 -#define MT9P031_BLC_MANUAL_BLC (1 << 0) +#define MT9P031_BLC_MANUAL_BLC BIT(0) #define MT9P031_RED_OFFSET 0x63 #define MT9P031_BLUE_OFFSET 0x64 #define MT9P031_TEST_PATTERN 0xa0 #define MT9P031_TEST_PATTERN_SHIFT 3 -#define MT9P031_TEST_PATTERN_ENABLE (1 << 0) -#define MT9P031_TEST_PATTERN_DISABLE (0 << 0) +#define MT9P031_TEST_PATTERN_ENABLE BIT(0) #define MT9P031_TEST_PATTERN_GREEN 0xa1 #define MT9P031_TEST_PATTERN_RED 0xa2 #define MT9P031_TEST_PATTERN_BLUE 0xa3 @@ -199,7 +197,7 @@ static int mt9p031_reset(struct mt9p031 *mt9p031) ret = mt9p031_write(client, MT9P031_RST, MT9P031_RST_ENABLE); if (ret < 0) return ret; - ret = mt9p031_write(client, MT9P031_RST, MT9P031_RST_DISABLE); + ret = mt9p031_write(client, MT9P031_RST, 0); if (ret < 0) return ret; @@ -794,8 +792,7 @@ static int mt9p031_s_ctrl(struct v4l2_ctrl *ctrl) if (ret < 0) return ret; - return mt9p031_write(client, MT9P031_TEST_PATTERN, - MT9P031_TEST_PATTERN_DISABLE); + return mt9p031_write(client, MT9P031_TEST_PATTERN, 0); } ret = mt9p031_write(client, MT9P031_TEST_PATTERN_GREEN, 0x05a0); From patchwork Wed Jul 14 13:38:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Riedm=C3=BCller?= X-Patchwork-Id: 477113 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-21.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBAE0C11F68 for ; Wed, 14 Jul 2021 13:38:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C1476613CA for ; Wed, 14 Jul 2021 13:38:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232744AbhGNNls (ORCPT ); Wed, 14 Jul 2021 09:41:48 -0400 Received: from mickerik.phytec.de ([195.145.39.210]:56710 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232420AbhGNNlp (ORCPT ); Wed, 14 Jul 2021 09:41:45 -0400 DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a4; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1626269930; x=1628861930; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=XFkUzWvtOGkj5KMI8CZVs1m3WhPzoPy2JqrsYoCMdMQ=; b=kuUblTEqsQPJrOlxGlxMq07LNYCsqu6aEnQz4GDEsaD3tRpXIsAqDr0UYLekEKcr OIROxi7umWxWjeqGDfXKQgh+Kn0ADoo3gKyby1rU/QxqgTMLnHSQBH0h1zcLzIJy ixjA1LQG0IyBCch1Q3NU1O5SlHa1ytmdfOqXPWvdSMw=; X-AuditID: c39127d2-1d8f870000001daf-26-60eee8eaca32 Received: from idefix.phytec.de (Unknown_Domain [172.16.0.10]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id 2D.57.07599.AE8EEE06; Wed, 14 Jul 2021 15:38:50 +0200 (CEST) Received: from augenblix2.phytec.de ([172.16.0.56]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2021071415385065-1154292 ; Wed, 14 Jul 2021 15:38:50 +0200 From: Stefan Riedmueller To: Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring Cc: Stefan Riedmueller , Sakari Ailus , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 5/6] media: dt-bindings: mt9p031: Convert bindings to yaml Date: Wed, 14 Jul 2021 15:38:48 +0200 Message-Id: <20210714133849.1041619-6-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210714133849.1041619-1-s.riedmueller@phytec.de> References: <20210714133849.1041619-1-s.riedmueller@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 14.07.2021 15:38:50, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 14.07.2021 15:38:50 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrFLMWRmVeSWpSXmKPExsWyRoCBS/fVi3cJBoteGlvMP3KO1aJz4hJ2 i8u75rBZ9GzYymqxbNMfJovWvUfYLT5t+cbkwO4xu2Mmq8emVZ1sHvNOBnp83iQXwBLFZZOS mpNZllqkb5fAlXH9wnaWgs0aFfO7LjA1ML6Q62Lk5JAQMJH4+HECM4gtJLCNUeL9q7guRi4g +wKjxL/d01hAEmwCRhILpjUygSREBNoYJXYcaQZzmAW2MEpMv7ycDaRKWMBX4tKzHiYQm0VA VeL2psdA3RwcvAJ2Eh/elUFsk5eYeek7O4jNKWAv0X30HwvEZjuJO5fnM4LYvAKCEidnPmEB mS8hcIVR4u6654wQzUISpxefBTuVWUBbYtnC18wTGAVmIemZhSS1gJFpFaNQbmZydmpRZrZe QUZlSWqyXkrqJkZg+B6eqH5pB2PfHI9DjEwcjIcYJTiYlUR4lxq9TRDiTUmsrEotyo8vKs1J LT7EKM3BoiTOu4G3JExIID2xJDU7NbUgtQgmy8TBKdXAKHbSQlctsrF+U1DKO9PXYgGrplQ/ zV52pkv7ReFCPoX8G54XZIJ4pjnkm+RqOXKvUPqX+r118YQZTsF32zM6DjWem7nocerq0qef y1gFz/yplr/1wi+Yg2H/oaPhW8JP6V3vYpG2n5h2ztBx1XlXkYbFYXMe/ttmlXL+/o9ThjYX JqZ05awMU2Ipzkg01GIuKk4EAFs/itZNAgAA Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Convert mt9p031 sensor bindings to yaml schema. Also update the MAINTAINERS entry. Although input-clock-frequency and pixel-clock-frequency have not been definded as endpoint propierties in the textual bindings, the sensor does parse them from the endpoint. Thus move these properties to the endpoint in the new yaml bindings. Signed-off-by: Stefan Riedmueller --- .../bindings/media/i2c/aptina,mt9p031.yaml | 92 +++++++++++++++++++ .../devicetree/bindings/media/i2c/mt9p031.txt | 40 -------- MAINTAINERS | 1 + 3 files changed, 93 insertions(+), 40 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml delete mode 100644 Documentation/devicetree/bindings/media/i2c/mt9p031.txt diff --git a/Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml b/Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml new file mode 100644 index 000000000000..1531ecd1ed95 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/aptina,mt9p031.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aptina 1/2.5-Inch 5Mp CMOS Digital Image Sensor + +maintainers: + - Laurent Pinchart + +description: | + The Aptina MT9P031 is a 1/2.5-inch CMOS active pixel digital image sensor + with an active array size of 2592H x 1944V. It is programmable through a + simple two-wire serial interface. + +properties: + compatible: + enum: + - aptina,mt9p031 + - aptina,mt9p031m + + reg: + description: I2C device address + maxItems: 1 + + reset-gpios: + maxItems: 1 + description: Chip reset GPIO + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + input-clock-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 6000000 + maximum: 96000000 + description: Input clock frequency + + pixel-clock-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 96000000 + description: Target pixel clock frequency + + bus-type: + const: 5 + + bus-width: + const: 12 + + pclk-sample: + default: 0 + + required: + - input-clock-frequency + - pixel-clock-frequency + +required: + - compatible + - reg + - port + +additionalProperties: false + +examples: + - | + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + mt9p031@5d { + compatible = "aptina,mt9p031"; + reg = <0x5d>; + reset-gpios = <&gpio_sensor 0 0>; + + port { + mt9p031_1: endpoint { + input-clock-frequency = <6000000>; + pixel-clock-frequency = <96000000>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/media/i2c/mt9p031.txt b/Documentation/devicetree/bindings/media/i2c/mt9p031.txt deleted file mode 100644 index cb60443ff78f..000000000000 --- a/Documentation/devicetree/bindings/media/i2c/mt9p031.txt +++ /dev/null @@ -1,40 +0,0 @@ -* Aptina 1/2.5-Inch 5Mp CMOS Digital Image Sensor - -The Aptina MT9P031 is a 1/2.5-inch CMOS active pixel digital image sensor with -an active array size of 2592H x 1944V. It is programmable through a simple -two-wire serial interface. - -Required Properties: -- compatible: value should be either one among the following - (a) "aptina,mt9p031" for mt9p031 sensor - (b) "aptina,mt9p031m" for mt9p031m sensor - -- input-clock-frequency: Input clock frequency. - -- pixel-clock-frequency: Pixel clock frequency. - -Optional Properties: -- reset-gpios: Chip reset GPIO - -For further reading on port node refer to -Documentation/devicetree/bindings/media/video-interfaces.txt. - -Example: - - i2c0@1c22000 { - ... - ... - mt9p031@5d { - compatible = "aptina,mt9p031"; - reg = <0x5d>; - reset-gpios = <&gpio3 30 0>; - - port { - mt9p031_1: endpoint { - input-clock-frequency = <6000000>; - pixel-clock-frequency = <96000000>; - }; - }; - }; - ... - }; diff --git a/MAINTAINERS b/MAINTAINERS index a61f4f3b78a9..33dd81237a91 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12635,6 +12635,7 @@ M: Laurent Pinchart L: linux-media@vger.kernel.org S: Maintained T: git git://linuxtv.org/media_tree.git +F: Documentation/devicetree/bindings/media/i2c/aptina,mt9p031.yaml F: drivers/media/i2c/mt9p031.c F: include/media/i2c/mt9p031.h