From patchwork Wed Jul 14 18:06:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 476822 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp808016jao; Wed, 14 Jul 2021 11:07:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJweWz1BYAJjuIV12i1ipTdNef2pJroJOddcnVj3aTfxe1X10V/PtzWddUxyXD1NDmbsGVa+ X-Received: by 2002:ac2:59db:: with SMTP id x27mr5545974lfn.547.1626286045643; Wed, 14 Jul 2021 11:07:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626286045; cv=none; d=google.com; s=arc-20160816; b=yW6TEVDGmrL8rqHNUPmu2sQj0EFSYfGh/VWUd9EsmWqzi/kHiXge8+PMI7xvSJhzQi Y3e3Een50dgjXnXyQ2T7YV341vPOszej3KDInCL+hyUgpcYQKd0jLA6F98J4JvbuejUe lQzv/OkFyWP8QjK7rpLnR3nn/MnXgysQvs3KWDKbxALwme/xilDKlRJKEGszr+6fGBYW cXWk9R4Db1i3LwqI8STivtnPw3p23xNQ7hKmiTFaCpr5A69UBNNVgZLiajNrEQhLDi+I 2EpoCtfBGv8/3dCCIqbZqi1IyHZwSb5SRmaSEKUXcU+zTCEnnWp+RGjGD79YXVQNxe1w WlcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fx1IYlUB1apyvNip9CdKVB8bhhKr7Iu1pMhRVbOHLjQ=; b=a+SYJweTrZTP2d0oZ8JGImitLC4sv4WValxxtKrcFnuuWvy3u72QRA91IFqwTMTv/H Bygf0/RFIVaM60a+UBI7aHaRK9bLU/SrOe/O1+7Dj46Ucu+EWGrj1EouDQns3rO9uADr 1xeFUhUjbuUbAzkFqMMd8dfJJTp1yYvU1NE1bHQ3hqDHHbTIegoxTi/BTrkzpSk/l2Yo DzCsOC3UQDDpex1kjnn015jQtDCx/QfeWlS4nHk7z94jpXsTlwBJeTDzURSA55t8chHl a+t4L7Y7JGIrEM+Wruzwiw5umc/zprtKVGl5wVLC48tRqlGv09rexsOwcHsxzZvBNcR5 +8OA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vpXfsZxA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d13si4554257lfv.523.2021.07.14.11.07.25 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 14 Jul 2021 11:07:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vpXfsZxA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57112 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m3jI4-0002ur-Fr for patch@linaro.org; Wed, 14 Jul 2021 14:07:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33608) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m3jHM-0002uK-JE for qemu-devel@nongnu.org; Wed, 14 Jul 2021 14:06:40 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:42882) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m3jHL-0000qK-1y for qemu-devel@nongnu.org; Wed, 14 Jul 2021 14:06:40 -0400 Received: by mail-pf1-x432.google.com with SMTP id y4so2735659pfi.9 for ; Wed, 14 Jul 2021 11:06:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fx1IYlUB1apyvNip9CdKVB8bhhKr7Iu1pMhRVbOHLjQ=; b=vpXfsZxAj9HyJcTED1cx6W27B1XFidizESj0ocXKQ9v3bvkNbx6nFLchz2WMmaIUg1 DT3/kxCMQ4AG6f6Em02bjqwT3DiSal/dj2CcRHXIq9OUmyKYypnkbEaeRqAc3KNwUeVc 14elr+Da9hyI6QpePz71aJPZc+SdSALn5Wmlk1ui90CfSphu4WkE977OWKU644rKa23Q z4fDanpp95ra1YvCRGp4t1EHrpQDVSyoqKG/b9xD2yxxdtoxj+wniaKR5bg76KVvpCku bjgTR54uD0Do4zWg31yEurxOQRZfHyLJGo1aqYDXdUDAl/hKNo/YYWMywQpBlpRj1OW+ Km5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fx1IYlUB1apyvNip9CdKVB8bhhKr7Iu1pMhRVbOHLjQ=; b=T99eUGj1szBuXQQeBjrdOguyeVs1BWPqUZGPjr+CTv4bJ0YlElhodDkw9nyKc1UIA+ 12jhqQYeQIAk3HKLIV3ltEnF6i0xyF0g9njrOQ14dLKJSC0aQciVxiU850YyMh2ti4ts v6WVFw37XT9n52JKWE1MBrvDnFNB2ZzgVUuwIFhnIaRbQcYXeipPhGPN1PS5VZIFlbiE yU8gt/ouJp8Ih11OdNH7wPCqwXzikWqZ4LlfLV5jzcVF6FoWkCQgD8e6g56iWLdg6yND qb7BYosJmZAIXUUV183O/yRaxyn/ZemNyNZdDUX21sIIqKB4LT/LIVkYP8nJpH1d9FgX BRgw== X-Gm-Message-State: AOAM531oeg2vxd+UsPQg7Tq0jozqegZBmWmx3FHt3i9fgxmXSSc4k/ut DyDKBgsgbjhPHYKrxVH4Ing/YAi7djt+8A== X-Received: by 2002:a63:ff25:: with SMTP id k37mr10718246pgi.353.1626285997644; Wed, 14 Jul 2021 11:06:37 -0700 (PDT) Received: from localhost.localdomain ([75.147.178.105]) by smtp.gmail.com with ESMTPSA id d1sm2853521pju.16.2021.07.14.11.06.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jul 2021 11:06:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 1/2] target/arm: Export aarch64_sve_zcr_get_valid_len Date: Wed, 14 Jul 2021 11:06:34 -0700 Message-Id: <20210714180635.1648966-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210714180635.1648966-1-richard.henderson@linaro.org> References: <20210714180635.1648966-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rename from sve_zcr_get_valid_len and make accessible from outside of helper.c. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 ++ target/arm/helper.c | 8 +++++--- 2 files changed, 7 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index be9a4dceae..52e99344c5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1060,6 +1060,8 @@ int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, void *opaque); +uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len); + #ifdef TARGET_AARCH64 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/arm/helper.c b/target/arm/helper.c index 910ace4274..a49067c115 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6454,11 +6454,13 @@ int sve_exception_el(CPUARMState *env, int el) return 0; } -static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) +uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) { uint32_t end_len; - end_len = start_len &= 0xf; + start_len = MIN(start_len, ARM_MAX_VQ - 1); + end_len = start_len; + if (!test_bit(start_len, cpu->sve_vq_map)) { end_len = find_last_bit(cpu->sve_vq_map, start_len); assert(end_len < start_len); @@ -6484,7 +6486,7 @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); } - return sve_zcr_get_valid_len(cpu, zcr_len); + return aarch64_sve_zcr_get_valid_len(cpu, zcr_len); } static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, From patchwork Wed Jul 14 18:06:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 476821 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp807730jao; Wed, 14 Jul 2021 11:07:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz3d8Yu+ZFjM5i27gtu4bfYMiF/WoaIjj4PELPgPOHgmZnlXO7Y3DloeeUxDQwxKMayftVe X-Received: by 2002:a05:651c:1aa:: with SMTP id c10mr10527110ljn.56.1626286023851; Wed, 14 Jul 2021 11:07:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626286023; cv=none; d=google.com; s=arc-20160816; b=mKbPRbtU+g1MzzA5+fk+ZqZytwx59U6FPl/Z9+8wQ/hysyyPhLLkwoQzXpU09dUyIs anvJ/hHou4ibmLAuJwjDiC6LZzPp3JPg5IJIxQV4PaKGU80SaiPwY39bLWKwwIDjEx2A +RlMJlgnAjUDJq/j6u3UoAsWipcksoNjzN/0JGci9DXali07N0UGR+dU1Rr9j0zXqHaN VmQtGdnPCxX9REG+1SxFsE1dxYWTlhpwwDSkrst6rDKGkObZDeQr8LuuvE7bM2ntBA+3 ASgtoDs+jOwzPJdXfHQvZw4j9sl7F5NsWfJozgVVLPKLbRzQUmpvIOeDRxVXp39R+Cp0 +Kgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=EpDxd7UvP7T4oZGwdvqqavAoeBFhuX87JU5frFZXsCM=; b=xPgFdXI+ikJ9HKnBp7wz+y3C54KZ1XZQvF8fkAO6wQzUfKYmQ80k5AYn//ynRd3j87 UiOxwP4BLT5dbwrENP6gLHDatzauKtEoGLEkCdGtU9O19Zxigt1HqxSX+uJEY3iLV0a7 M0AAt3pTzfVvCjnPqFfj8Tuk6ied0xSYPndMr6z3n5DTfZP/6LsphjuRq8oWanFQuQEN 180oW/nzpvDLVn+1oLtFlVxDywIyX4E5sB3LWyzeCSjxVyW7XArO0GPDD3RALIk5WVcF EZki0Nxp5tFJ8yicn9cJ8cnDhhi823dVsEwzQLX3onPyUUyy595eVS4HvpxxV1gXx+UP 3/FQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VjjN0DBp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d28si5135549ljo.527.2021.07.14.11.07.03 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 14 Jul 2021 11:07:03 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VjjN0DBp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57160 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m3jHi-0002xg-KT for patch@linaro.org; Wed, 14 Jul 2021 14:07:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33622) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m3jHN-0002uy-Ly for qemu-devel@nongnu.org; Wed, 14 Jul 2021 14:06:41 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]:35526) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m3jHL-0000qU-KM for qemu-devel@nongnu.org; Wed, 14 Jul 2021 14:06:41 -0400 Received: by mail-pf1-x42a.google.com with SMTP id d12so2759300pfj.2 for ; Wed, 14 Jul 2021 11:06:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EpDxd7UvP7T4oZGwdvqqavAoeBFhuX87JU5frFZXsCM=; b=VjjN0DBpArHL/qDBnOYo9BSOtZiDDvYLGXBtpe7xLIOBE/3osT6Ds7dGfquHujyYqX ks+DN9CmWuGkDv4qiJ8booMbKo2bYL3Xqi3P3pXcTMKRcpKtsT+lRDlrqDMJNQ7505JB IUgyUdDQigUhrRzREGniNAxsXQlLcNACOzCb0+VdL5NVxlS288edWm3hW9uZ8gdBr/s0 HlT7iV3j3FOj+aK/iF8vt7IWEqF2CfqKjRT9gSvPvY5Tdi7u6USwWwr5iu76k0UPSKMw 6HmVfbU68RmDpAQ5V74V6T6PFD9k5vftFcDWHZEGh+uaZVEJ7trwX46i0n9/SdHnTjj5 QcqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EpDxd7UvP7T4oZGwdvqqavAoeBFhuX87JU5frFZXsCM=; b=iTZOIKUYVJ9g38TIWyXvnX0CVCUDOuiJ4muU0cdZ7viFmg5mte/xpRG9xYhAF94Brl qUFffRdmsVPV8eyT0Kny+ivH7izKH246RsDlIHiHt/cem/lQqOS410rAa+VZHF0PuitV QApeuH2tTDc/tCps21UBUhSE8Qst1sT2U31jtnhZaiBQWGIg0/Yi/0PBQzxzir9eY2JF S7qrIlWgtuDm6Rj8CdyZajAaC0axjHCvGCpkdXbN0V2SpxilWcPr1/RiZdFb5WJRFFkF IYFf9nd5vislt6XYu5/jS6zNksQojAVwHk3Ck0bNTEJgXVJYi/EedKTe4prUXyaLKlPC Dkaw== X-Gm-Message-State: AOAM531ZuTJGugbNq2KWLTSQ6h5SyxnqOae542y5i4Em1VPG9sUxETp/ 6soh4+fIx65DpjSNATDawkpWfOgGr9dA3w== X-Received: by 2002:a05:6a00:23cf:b029:2d5:302e:dc77 with SMTP id g15-20020a056a0023cfb02902d5302edc77mr11531588pfc.63.1626285998313; Wed, 14 Jul 2021 11:06:38 -0700 (PDT) Received: from localhost.localdomain ([75.147.178.105]) by smtp.gmail.com with ESMTPSA id d1sm2853521pju.16.2021.07.14.11.06.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jul 2021 11:06:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/2] target/arm: Add sve-default-vector-length cpu property Date: Wed, 14 Jul 2021 11:06:35 -0700 Message-Id: <20210714180635.1648966-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210714180635.1648966-1-richard.henderson@linaro.org> References: <20210714180635.1648966-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Mirror the behavour of /proc/sys/abi/sve_default_vector_length under the real linux kernel. We have no way of passing along a real default across exec like the kernel can, but this is a decent way of adjusting the startup vector length of a process. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/482 Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++++ target/arm/cpu.c | 14 ++++++++++-- target/arm/cpu64.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 70 insertions(+), 2 deletions(-) -- 2.25.1 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 52e99344c5..ffd82edaef 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1006,6 +1006,11 @@ struct ARMCPU { /* Used to set the maximum vector length the cpu will support. */ uint32_t sve_max_vq; +#ifdef CONFIG_USER_ONLY + /* Used to set the default vector length at process start. */ + uint32_t sve_default_vq; +#endif + /* * In sve_vq_map each set bit is a supported vector length of * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9cddfd6a44..b5a2c9eb45 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -201,7 +201,8 @@ static void arm_cpu_reset(DeviceState *dev) env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3); /* with reasonable vector length */ if (cpu_isar_feature(aa64_sve, cpu)) { - env->vfp.zcr_el[1] = MIN(cpu->sve_max_vq - 1, 3); + env->vfp.zcr_el[1] = + aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1); } /* * Enable TBI0 but not TBI1. @@ -1051,7 +1052,16 @@ static void arm_cpu_initfn(Object *obj) QLIST_INIT(&cpu->pre_el_change_hooks); QLIST_INIT(&cpu->el_change_hooks); -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY +# ifdef TARGET_AARCH64 + /* + * The linux kernel defaults to 512-bit vectors, when sve is supported. + * See documentation for /proc/sys/abi/sve_default_vector_length, and + * our corresponding sve-default-vector-length cpu property. + */ + cpu->sve_default_vq = 4; +# endif +#else /* Our inbound IRQ and FIQ lines */ if (kvm_enabled()) { /* VIRQ and VFIQ are unused with KVM but we add them to maintain diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c7a1626bec..0e44a4f154 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -559,6 +559,52 @@ static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) cpu->isar.id_aa64pfr0 = t; } +#ifdef CONFIG_USER_ONLY +/* Mirror linux /proc/sys/abi/sve_default_vector_length. */ +static void cpu_arm_set_sve_default_vec_len(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + uint32_t default_len, default_vq, remainder; + + if (!visit_type_uint32(v, name, &default_len, errp)) { + return; + } + + default_vq = default_len / 128; + remainder = default_len % 128; + + /* + * Note that the 512 max comes from include/uapi/asm/sve_context.h + * and is the maximum architectural width of ZCR_ELx.LEN. + */ + if (remainder || default_vq < 1 || default_vq > 512) { + error_setg(errp, "cannot set sve-default-vector-length"); + if (remainder) { + error_append_hint(errp, "Vector length not a multiple of 128\n"); + } else if (default_vq < 1) { + error_append_hint(errp, "Vector length smaller than 128\n"); + } else { + error_append_hint(errp, "Vector length larger than 65536\n"); + } + return; + } + + cpu->sve_default_vq = default_vq; +} + +static void cpu_arm_get_sve_default_vec_len(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + uint32_t value = cpu->sve_default_vq * 128; + + visit_type_uint32(v, name, &value, errp); +} +#endif + void aarch64_add_sve_properties(Object *obj) { uint32_t vq; @@ -571,6 +617,13 @@ void aarch64_add_sve_properties(Object *obj) object_property_add(obj, name, "bool", cpu_arm_get_sve_vq, cpu_arm_set_sve_vq, NULL, NULL); } + +#ifdef CONFIG_USER_ONLY + /* Mirror linux /proc/sys/abi/sve_default_vector_length. */ + object_property_add(obj, "sve-default-vector-length", "uint32", + cpu_arm_get_sve_default_vec_len, + cpu_arm_set_sve_default_vec_len, NULL, NULL); +#endif } void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)