From patchwork Tue Jul 13 13:05:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 475018 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 544AAC11F66 for ; Tue, 13 Jul 2021 13:06:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 36F47610CB for ; Tue, 13 Jul 2021 13:06:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236468AbhGMNJA (ORCPT ); Tue, 13 Jul 2021 09:09:00 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:43672 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236276AbhGMNI7 (ORCPT ); Tue, 13 Jul 2021 09:08:59 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 16DD5owV010324; Tue, 13 Jul 2021 08:05:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1626181550; bh=JcxS3BPguGIKB8ChrouzPygyBytSZSyQOD4ZRpL493I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ydMJdmdxIpEcMC1t2f4eKKJnktpW8HIXfTeWQ6LHPZlQuqbtjt1djkbeBSdI8l4Ap 8dQ7P2ulwRuaF18N2HyPyF2JuRGbaoh3qTt82TENYPi+9K9879qUANPmdp/Kj8/UMr wePtnFI7zrxy4w0FmFIuFMRBeWLPBHvZhfgc6DiA= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 16DD5oCi085738 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 13 Jul 2021 08:05:50 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 13 Jul 2021 08:05:49 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 13 Jul 2021 08:05:49 -0500 Received: from LT5CD112GSQZ.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 16DD5daB109825; Tue, 13 Jul 2021 08:05:45 -0500 From: Apurva Nandan To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Patrice Chotard , Boris Brezillon , , , CC: Apurva Nandan , Pratyush Yadav Subject: [PATCH 01/13] spi: spi-mem: Add DTR templates for cmd, address, dummy and data phase Date: Tue, 13 Jul 2021 13:05:26 +0000 Message-ID: <20210713130538.646-2-a-nandan@ti.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20210713130538.646-1-a-nandan@ti.com> References: <20210713130538.646-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Setting dtr field of spi_mem_op is useful when creating templates for DTR ops in spinand.h. Also, 2 bytes cmd phases are required when operating in Octal DTR SPI mode. Create new templates for dtr mode cmd, address, dummy and data phase in spi_mem_op, which set the dtr field to 1 and also allow passing the nbytes for the cmd phase. Signed-off-by: Apurva Nandan Acked-by: Mark Brown --- include/linux/spi/spi-mem.h | 87 ++++++++++++++++++++++++++----------- 1 file changed, 61 insertions(+), 26 deletions(-) diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index 85e2ff7b840d..73e52a3ecf66 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -13,46 +13,81 @@ #include -#define SPI_MEM_OP_CMD(__opcode, __buswidth) \ - { \ - .buswidth = __buswidth, \ - .opcode = __opcode, \ - .nbytes = 1, \ +#define SPI_MEM_OP_CMD_ALL_ARGS(__nbytes, __opcode, __buswidth, __dtr) \ + { \ + .buswidth = __buswidth, \ + .opcode = __opcode, \ + .nbytes = __nbytes, \ + .dtr = __dtr, \ } -#define SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth) \ - { \ - .nbytes = __nbytes, \ - .val = __val, \ - .buswidth = __buswidth, \ +#define SPI_MEM_OP_CMD(__opcode, __buswidth) \ + SPI_MEM_OP_CMD_ALL_ARGS(1, __opcode, __buswidth, 0) + +#define SPI_MEM_OP_CMD_DTR(__nbytes, __opcode, __buswidth) \ + SPI_MEM_OP_CMD_ALL_ARGS(__nbytes, __opcode, __buswidth, 1) + +#define SPI_MEM_OP_ADDR_ALL_ARGS(__nbytes, __val, __buswidth, __dtr) \ + { \ + .nbytes = __nbytes, \ + .val = __val, \ + .buswidth = __buswidth, \ + .dtr = __dtr, \ } +#define SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth) \ + SPI_MEM_OP_ADDR_ALL_ARGS(__nbytes, __val, __buswidth, 0) + +#define SPI_MEM_OP_ADDR_DTR(__nbytes, __val, __buswidth) \ + SPI_MEM_OP_ADDR_ALL_ARGS(__nbytes, __val, __buswidth, 1) + #define SPI_MEM_OP_NO_ADDR { } -#define SPI_MEM_OP_DUMMY(__nbytes, __buswidth) \ - { \ - .nbytes = __nbytes, \ - .buswidth = __buswidth, \ +#define SPI_MEM_OP_DUMMY_ALL_ARGS(__nbytes, __buswidth, __dtr) \ + { \ + .nbytes = __nbytes, \ + .buswidth = __buswidth, \ + .dtr = __dtr, \ } +#define SPI_MEM_OP_DUMMY(__nbytes, __buswidth) \ + SPI_MEM_OP_DUMMY_ALL_ARGS(__nbytes, __buswidth, 0) + +#define SPI_MEM_OP_DUMMY_DTR(__nbytes, __buswidth) \ + SPI_MEM_OP_DUMMY_ALL_ARGS(__nbytes, __buswidth, 1) + #define SPI_MEM_OP_NO_DUMMY { } -#define SPI_MEM_OP_DATA_IN(__nbytes, __buf, __buswidth) \ - { \ - .dir = SPI_MEM_DATA_IN, \ - .nbytes = __nbytes, \ - .buf.in = __buf, \ - .buswidth = __buswidth, \ +#define SPI_MEM_OP_DATA_IN_ALL_ARGS(__nbytes, __buf, __buswidth, __dtr) \ + { \ + .dir = SPI_MEM_DATA_IN, \ + .nbytes = __nbytes, \ + .buf.in = __buf, \ + .buswidth = __buswidth, \ + .dtr = __dtr, \ } -#define SPI_MEM_OP_DATA_OUT(__nbytes, __buf, __buswidth) \ - { \ - .dir = SPI_MEM_DATA_OUT, \ - .nbytes = __nbytes, \ - .buf.out = __buf, \ - .buswidth = __buswidth, \ +#define SPI_MEM_OP_DATA_IN(__nbytes, __buf, __buswidth) \ + SPI_MEM_OP_DATA_IN_ALL_ARGS(__nbytes, __buf, __buswidth, 0) + +#define SPI_MEM_OP_DATA_IN_DTR(__nbytes, __buf, __buswidth) \ + SPI_MEM_OP_DATA_IN_ALL_ARGS(__nbytes, __buf, __buswidth, 1) + +#define SPI_MEM_OP_DATA_OUT_ALL_ARGS(__nbytes, __buf, __buswidth, __dtr)\ + { \ + .dir = SPI_MEM_DATA_OUT, \ + .nbytes = __nbytes, \ + .buf.out = __buf, \ + .buswidth = __buswidth, \ + .dtr = __dtr, \ } +#define SPI_MEM_OP_DATA_OUT(__nbytes, __buf, __buswidth) \ + SPI_MEM_OP_DATA_OUT_ALL_ARGS(__nbytes, __buf, __buswidth, 0) + +#define SPI_MEM_OP_DATA_OUT_DTR(__nbytes, __buf, __buswidth) \ + SPI_MEM_OP_DATA_OUT_ALL_ARGS(__nbytes, __buf, __buswidth, 1) + #define SPI_MEM_OP_NO_DATA { } /** From patchwork Tue Jul 13 13:05:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 475017 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A915C11F67 for ; Tue, 13 Jul 2021 13:06:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2D2D1610CB for ; Tue, 13 Jul 2021 13:06:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236552AbhGMNJD (ORCPT ); Tue, 13 Jul 2021 09:09:03 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:43680 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236222AbhGMNJC (ORCPT ); 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Tue, 13 Jul 2021 08:05:54 -0500 Received: from LT5CD112GSQZ.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 16DD5daC109825; Tue, 13 Jul 2021 08:05:50 -0500 From: Apurva Nandan To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Patrice Chotard , Boris Brezillon , , , CC: Apurva Nandan , Pratyush Yadav Subject: [PATCH 02/13] mtd: spinand: Add enum spinand_proto to indicate current SPI IO mode Date: Tue, 13 Jul 2021 13:05:27 +0000 Message-ID: <20210713130538.646-3-a-nandan@ti.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20210713130538.646-1-a-nandan@ti.com> References: <20210713130538.646-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Unlike Dual and Quad SPI modes flashes, Octal DTR SPI NAND flashes require all instructions to be made in 8D-8D-8D protocol when the flash is in Octal DTR mode. Hence, storing the current SPI IO mode becomes necessary for correctly generating non-array access operations. Store the current SPI IO mode in the spinand struct using a reg_proto enum. This would act as a flag, denoting that the core should use the given SPI protocol for non-page access operations. Also provide basic macros for extracting buswidth and dtr mode information from the spinand_proto enum. Signed-off-by: Apurva Nandan --- drivers/mtd/nand/spi/core.c | 2 ++ include/linux/mtd/spinand.h | 30 ++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 446ba8d43fbc..a4f25649e293 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1153,6 +1153,7 @@ static void spinand_mtd_resume(struct mtd_info *mtd) struct spinand_device *spinand = mtd_to_spinand(mtd); int ret; + spinand->reg_proto = SPINAND_SINGLE_STR; ret = spinand_reset_op(spinand); if (ret) return; @@ -1179,6 +1180,7 @@ static int spinand_init(struct spinand_device *spinand) if (!spinand->scratchbuf) return -ENOMEM; + spinand->reg_proto = SPINAND_SINGLE_STR; ret = spinand_detect(spinand); if (ret) goto err_free_bufs; diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index 6988956b8492..f6093cd98d7b 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -140,6 +140,31 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_DATA_OUT(len, buf, 4)) +#define SPINAND_PROTO_BUSWIDTH_MASK GENMASK(6, 0) +#define SPINAND_PROTO_DTR_BIT BIT(7) + +#define SPINAND_PROTO_STR(__buswidth) \ + ((u8)(((__buswidth) - 1) & SPINAND_PROTO_BUSWIDTH_MASK)) +#define SPINAND_PROTO_DTR(__buswidth) \ + (SPINAND_PROTO_DTR_BIT | SPINAND_PROTO_STR(__buswidth)) + +#define SPINAND_PROTO_BUSWIDTH(__proto) \ + ((u8)(((__proto) & SPINAND_PROTO_BUSWIDTH_MASK) + 1)) +#define SPINAND_PROTO_IS_DTR(__proto) (!!((__proto) & SPINAND_PROTO_DTR_BIT)) + +/** + * enum spinand_proto - List allowable SPI protocol variants for read reg, + * write reg, blk erase, write enable/disable, page read + * and program exec operations. + */ +enum spinand_proto { + SPINAND_SINGLE_STR = SPINAND_PROTO_STR(1), + SPINAND_DUAL_STR = SPINAND_PROTO_STR(2), + SPINAND_QUAD_STR = SPINAND_PROTO_STR(4), + SPINAND_OCTAL_STR = SPINAND_PROTO_STR(8), + SPINAND_OCTAL_DTR = SPINAND_PROTO_DTR(8), +}; + /** * Standard SPI NAND flash commands */ @@ -407,6 +432,9 @@ struct spinand_dirmap { * this die. Only required if your chip exposes several dies * @cur_target: currently selected target/die * @eccinfo: on-die ECC information + * @reg_proto: select a variant of SPI IO protocol (single, quad, octal or + * octal DTR) for read_reg/write_reg/erase operations. Update on + * successful transition into a different SPI IO protocol. * @cfg_cache: config register cache. One entry per die * @databuf: bounce buffer for data * @oobbuf: bounce buffer for OOB data @@ -438,6 +466,8 @@ struct spinand_device { struct spinand_ecc_info eccinfo; + enum spinand_proto reg_proto; + u8 *cfg_cache; u8 *databuf; u8 *oobbuf; From patchwork Tue Jul 13 13:05:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 475012 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 873A8C07E95 for ; Tue, 13 Jul 2021 13:08:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 62E1461073 for ; Tue, 13 Jul 2021 13:08:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236603AbhGMNKt (ORCPT ); Tue, 13 Jul 2021 09:10:49 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:44012 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236636AbhGMNJK (ORCPT ); Tue, 13 Jul 2021 09:09:10 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 16DD692Y010440; Tue, 13 Jul 2021 08:06:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1626181569; bh=8RzEa7awEZEDwwWTSJhzA++iT0OALTq3Az0pHKaR+oQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=zFoa0+nq67e3TIX/C15TP3zL+MQ8BoFcTrsYQK+PRI3UGonWq6yJWgZHgnBOV+ceW +E639dxn8aqXzJ8c9N9dmrWOF1UZThaI1p4/ixNpGFaVM7imX7CCkexRXME7OXuiBv 93B505jPBijDmQC4khE6GLe2RVyO9G64DshBmk1E= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 16DD69SY004591 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 13 Jul 2021 08:06:09 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 13 Jul 2021 08:06:09 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 13 Jul 2021 08:06:09 -0500 Received: from LT5CD112GSQZ.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 16DD5daF109825; Tue, 13 Jul 2021 08:06:04 -0500 From: Apurva Nandan To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Patrice Chotard , Boris Brezillon , , , CC: Apurva Nandan , Pratyush Yadav Subject: [PATCH 05/13] mtd: spinand: Add adjust_op() in manufacturer_ops to modify the ops for manufacturer specific changes Date: Tue, 13 Jul 2021 13:05:30 +0000 Message-ID: <20210713130538.646-6-a-nandan@ti.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20210713130538.646-1-a-nandan@ti.com> References: <20210713130538.646-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Manufacturers might use a variation of standard SPI NAND flash instructions, e.g. Winbond W35N01JW changes the dummy cycle length for read register commands when in Octal DTR mode. Add new function in manufacturer_ops: adjust_op(), which can be called to correct the spi_mem op for any alteration in the instruction made by the manufacturers. And hence, this function can also be used for incorporating variations of SPI instructions in Octal DTR mode. Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf Signed-off-by: Apurva Nandan --- drivers/mtd/nand/spi/core.c | 3 +++ include/linux/mtd/spinand.h | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index a5334ad34f96..1e619b6d777f 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -63,6 +63,9 @@ static void spinand_setup_op(const struct spinand_device *spinand, op->data.buswidth = op_buswidth; op->data.dtr = op_is_dtr; } + + if (spinand->manufacturer->ops->adjust_op) + spinand->manufacturer->ops->adjust_op(op, spinand->reg_proto); } static void spinand_setup_reg_op(const struct spinand_device *spinand, diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index f6093cd98d7b..ebb19b2cec84 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -257,6 +257,8 @@ struct spinand_devid { /** * struct manufacurer_ops - SPI NAND manufacturer specific operations * @init: initialize a SPI NAND device + * @adjust_op: modify the ops for any variation in their cmd, address, dummy or + * data phase by the manufacturer * @cleanup: cleanup a SPI NAND device * * Each SPI NAND manufacturer driver should implement this interface so that @@ -264,6 +266,8 @@ struct spinand_devid { */ struct spinand_manufacturer_ops { int (*init)(struct spinand_device *spinand); + void (*adjust_op)(struct spi_mem_op *op, + const enum spinand_proto reg_proto); void (*cleanup)(struct spinand_device *spinand); }; From patchwork Tue Jul 13 13:05:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 475016 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1695C07E95 for ; Tue, 13 Jul 2021 13:06:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9A874610CB for ; Tue, 13 Jul 2021 13:06:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236558AbhGMNJO (ORCPT ); Tue, 13 Jul 2021 09:09:14 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:44028 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236222AbhGMNJO (ORCPT ); Tue, 13 Jul 2021 09:09:14 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 16DD6EvV010456; Tue, 13 Jul 2021 08:06:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1626181574; bh=uFIGS9or9g64JHvjFEOHyBuSmYIom1KO6yATBzd+i8k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=uXgdlz99rwGtyDbU1ZNcol1HBO9+0TQptkJXdmv1rnSQL1KjdLZIAEqMseSp8QYY1 X4kPmTfA2wbn3MNn2q0MV7DlaLyg1TMxGgGuRBF5s5srcKEY09PJuvMobWi6cw/P9I X7zJHw8PgILxwfP9yF/sRgu90zv5exmLGOSPLaIE= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 16DD6E0x004685 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 13 Jul 2021 08:06:14 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 13 Jul 2021 08:06:13 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 13 Jul 2021 08:06:13 -0500 Received: from LT5CD112GSQZ.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 16DD5daG109825; Tue, 13 Jul 2021 08:06:09 -0500 From: Apurva Nandan To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Patrice Chotard , Boris Brezillon , , , CC: Apurva Nandan , Pratyush Yadav Subject: [PATCH 06/13] mtd: spinand: Add macros for Octal DTR page read and write operations Date: Tue, 13 Jul 2021 13:05:31 +0000 Message-ID: <20210713130538.646-7-a-nandan@ti.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20210713130538.646-1-a-nandan@ti.com> References: <20210713130538.646-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Define new PAGE_READ_FROM_CACHE and PROG_LOAD op templates for Octal DTR SPI mode. These templates would used in op_variants and op_templates for defining Octal DTR read from cache and write to cache operations. Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf Signed-off-by: Apurva Nandan --- include/linux/mtd/spinand.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index ebb19b2cec84..35816b8cfe81 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -122,6 +122,12 @@ SPI_MEM_OP_DUMMY(ndummy, 4), \ SPI_MEM_OP_DATA_IN(len, buf, 4)) +#define SPINAND_PAGE_READ_FROM_CACHE_OCTALIO_DTR_OP(addr, ndummy, buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD_DTR(2, 0x9d9d, 8), \ + SPI_MEM_OP_ADDR_DTR(2, addr, 8), \ + SPI_MEM_OP_DUMMY_DTR(ndummy, 8), \ + SPI_MEM_OP_DATA_IN_DTR(len, buf, 8)) + #define SPINAND_PROG_EXEC_OP(addr) \ SPI_MEM_OP(SPI_MEM_OP_CMD(0x10, 1), \ SPI_MEM_OP_ADDR(3, addr, 1), \ @@ -140,6 +146,12 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_DATA_OUT(len, buf, 4)) +#define SPINAND_PROG_LOAD_OCTALIO_DTR(reset, addr, buf, len) \ + SPI_MEM_OP(SPI_MEM_OP_CMD_DTR(2, reset ? 0x0202 : 0x8484, 8), \ + SPI_MEM_OP_ADDR_DTR(2, addr, 8), \ + SPI_MEM_OP_NO_DUMMY, \ + SPI_MEM_OP_DATA_OUT_DTR(len, buf, 8)) + #define SPINAND_PROTO_BUSWIDTH_MASK GENMASK(6, 0) #define SPINAND_PROTO_DTR_BIT BIT(7) From patchwork Tue Jul 13 13:05:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 475015 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F3AEC07E96 for ; Tue, 13 Jul 2021 13:06:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 727906128C for ; Tue, 13 Jul 2021 13:06:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236222AbhGMNJX (ORCPT ); Tue, 13 Jul 2021 09:09:23 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:44090 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236616AbhGMNJX (ORCPT ); Tue, 13 Jul 2021 09:09:23 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 16DD6NBW010788; Tue, 13 Jul 2021 08:06:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1626181583; bh=Z+dB4EvIxzpNpYXg02AgomR/hSRcWS9Lo0ZQW7fNDtc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Oo0S+EXbHEbn2R/Gnz7WiTH5wedw8ONfFwwU9qXVakYoSvaMbphvjBJXxL6kR6/I1 QT1h1ANyBOncumQIn/knRs183Ir04iaoJoJh3yCyb1YIRyYbKAlw2nc2gvjOegZ8b4 at82K3v8yAuLpQrqpgU1pl9DrNZmBi9Rwdw8/EDQ= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 16DD6Nqe004963 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 13 Jul 2021 08:06:23 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 13 Jul 2021 08:06:23 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 13 Jul 2021 08:06:23 -0500 Received: from LT5CD112GSQZ.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 16DD5daI109825; Tue, 13 Jul 2021 08:06:19 -0500 From: Apurva Nandan To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Patrice Chotard , Boris Brezillon , , , CC: Apurva Nandan , Pratyush Yadav Subject: [PATCH 08/13] mtd: spinand: Reject 8D-8D-8D op_templates if octal_dtr_enale() is missing in manufacturer_op Date: Tue, 13 Jul 2021 13:05:33 +0000 Message-ID: <20210713130538.646-9-a-nandan@ti.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20210713130538.646-1-a-nandan@ti.com> References: <20210713130538.646-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The SPI NAND core doesn't know how to switch the flash to Octal DTR mode (i.e. which operations to perform). If the manufacturer hasn't implemented the octal_dtr_enable() manufacturer_op, the SPI NAND core wouldn't be able to switch to 8D-8D-8D mode and will also not be able to run in 1S-1S-1S mode due to already selected 8D-8D-8D read/write cache op_templates. So, avoid choosing a Octal DTR SPI op_template for read_cache, write_cache and update_cache operations, if the manufacturer_op octal_dtr_enable() is missing. Signed-off-by: Apurva Nandan --- drivers/mtd/nand/spi/core.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 19d8affac058..8711e887b795 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1028,6 +1028,8 @@ static int spinand_manufacturer_match(struct spinand_device *spinand, if (id[0] != manufacturer->id) continue; + spinand->manufacturer = manufacturer; + ret = spinand_match_and_init(spinand, manufacturer->chips, manufacturer->nchips, @@ -1035,7 +1037,6 @@ static int spinand_manufacturer_match(struct spinand_device *spinand, if (ret < 0) continue; - spinand->manufacturer = manufacturer; return 0; } return -ENOTSUPP; @@ -1097,6 +1098,10 @@ spinand_select_op_variant(struct spinand_device *spinand, unsigned int nbytes; int ret; + if (spinand_op_is_octal_dtr(&op) && + !spinand->manufacturer->ops->octal_dtr_enable) + continue; + nbytes = nanddev_per_page_oobsize(nand) + nanddev_page_size(nand); From patchwork Tue Jul 13 13:05:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 475014 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA12EC11F66 for ; Tue, 13 Jul 2021 13:06:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B51796127C for ; Tue, 13 Jul 2021 13:06:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236616AbhGMNJf (ORCPT ); Tue, 13 Jul 2021 09:09:35 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:52362 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236624AbhGMNJc (ORCPT ); Tue, 13 Jul 2021 09:09:32 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 16DD6Swa073741; Tue, 13 Jul 2021 08:06:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1626181588; bh=Lyim0eEMlMzpf2TTksokWoegGGpgV+YNxu+z186bpt8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mCRvDhbqLxeOPrP+wZVYT3eK9huUQCsarsAFUw5l9cTy6a4MXO9NaEYPemR109uD4 8FyyoHK4TUgxPOH4Ttc56M64DPTH0KhZG5pTAl2lT+HY6wRiQNzxkz0Px53omuk5A0 WNCQtXWGPWC4QaqUpr1x7tarpE7+mUnm088E9tNA= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 16DD6SLA101319 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 13 Jul 2021 08:06:28 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 13 Jul 2021 08:06:28 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 13 Jul 2021 08:06:27 -0500 Received: from LT5CD112GSQZ.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 16DD5daJ109825; Tue, 13 Jul 2021 08:06:23 -0500 From: Apurva Nandan To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Patrice Chotard , Boris Brezillon , , , CC: Apurva Nandan , Pratyush Yadav Subject: [PATCH 09/13] mtd: spinand: Add support for write volatile configuration register op Date: Tue, 13 Jul 2021 13:05:34 +0000 Message-ID: <20210713130538.646-10-a-nandan@ti.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20210713130538.646-1-a-nandan@ti.com> References: <20210713130538.646-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Volatile configuration register are a different set of configuration registers, i.e. they differ from the status registers. A different SPI instruction is required to write to these registers. Any changes to the Volatile Configuration Register get transferred directly to the Internal Configuration Register and instantly reflect on the device operation. In Winbond W35N01JW, these volatile configuration register must be configured in order to switch to Octal DTR SPI mode. Add support for writing to volatile configuration registers using a new WRITE_VCR_OP template. Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf Signed-off-by: Apurva Nandan --- drivers/mtd/nand/spi/core.c | 2 +- drivers/mtd/nand/spi/winbond.c | 28 ++++++++++++++++++++++++++++ include/linux/mtd/spinand.h | 1 + 3 files changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 8711e887b795..f577e72da2c4 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -442,7 +442,7 @@ static void spinand_ondie_ecc_save_status(struct nand_device *nand, u8 status) engine_conf->status = status; } -static int spinand_write_enable_op(struct spinand_device *spinand) +int spinand_write_enable_op(struct spinand_device *spinand) { struct spi_mem_op op = SPINAND_WR_EN_DIS_OP(true); diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c index 76684428354e..a7052a9ca171 100644 --- a/drivers/mtd/nand/spi/winbond.c +++ b/drivers/mtd/nand/spi/winbond.c @@ -7,6 +7,7 @@ * Boris Brezillon */ +#include #include #include #include @@ -114,6 +115,33 @@ static int winbond_spinand_init(struct spinand_device *spinand) return 0; } +static int winbond_write_vcr_op(struct spinand_device *spinand, u8 reg, u8 val) +{ + int ret; + struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x81, 1), + SPI_MEM_OP_ADDR(3, reg, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, spinand->scratchbuf, 1)); + + *spinand->scratchbuf = val; + + ret = spinand_write_enable_op(spinand); + if (ret) + return ret; + + ret = spi_mem_exec_op(spinand->spimem, &op); + if (ret) + return ret; + + /* + * Write VCR operation doesn't set the busy bit in SR, so can't perform + * a status poll. Minimum time of 50ns is needed to complete the write. + * So, give thrice the minimum required delay. + */ + ndelay(150); + return 0; +} + static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = { .init = winbond_spinand_init, }; diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index daa2ac5c3110..21a4e5adcd59 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -560,5 +560,6 @@ int spinand_match_and_init(struct spinand_device *spinand, int spinand_upd_cfg(struct spinand_device *spinand, u8 mask, u8 val); int spinand_select_target(struct spinand_device *spinand, unsigned int target); +int spinand_write_enable_op(struct spinand_device *spinand); #endif /* __LINUX_MTD_SPINAND_H */ From patchwork Tue Jul 13 13:05:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 475013 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9763C07E95 for ; Tue, 13 Jul 2021 13:06:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9778E61073 for ; Tue, 13 Jul 2021 13:06:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236655AbhGMNJq (ORCPT ); Tue, 13 Jul 2021 09:09:46 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:44276 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236468AbhGMNJp (ORCPT ); Tue, 13 Jul 2021 09:09:45 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 16DD6gxH010956; Tue, 13 Jul 2021 08:06:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1626181602; bh=7CJfXtOlHQEOrqAvEB+jfsLP21Q3p2+fLNoxk3QJ5NQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=a3DV0/qyGHl9zGntvwSliNx04HflCQEmiPBSbJuq+1bQ+yuYEFDjtvyQNUlfOQuju h/w6pYUvniPq7ozJdl4UlMsph+7jmWUOzHImNG+MWK03Jh8M/rBM4nguvrFBDBwJXx Rl7fY8KkMkVRAAEKh4NDG8Ld12fsl8ZuKYALMwf0= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 16DD6gjg101570 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 13 Jul 2021 08:06:42 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 13 Jul 2021 08:06:42 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 13 Jul 2021 08:06:42 -0500 Received: from LT5CD112GSQZ.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 16DD5daM109825; Tue, 13 Jul 2021 08:06:38 -0500 From: Apurva Nandan To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Patrice Chotard , Boris Brezillon , , , CC: Apurva Nandan , Pratyush Yadav Subject: [PATCH 12/13] mtd: spinand: Perform Power-on-Reset when runtime_pm suspend is issued Date: Tue, 13 Jul 2021 13:05:37 +0000 Message-ID: <20210713130538.646-13-a-nandan@ti.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20210713130538.646-1-a-nandan@ti.com> References: <20210713130538.646-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org A soft reset using FFh command doesn't erase the flash's configuration and doesn't reset the SPI IO mode also. This can result in the flash being in a different SPI IO mode, e.g. Octal DTR, when resuming from sleep. This would render the flash in an unusable state. Perform a Power-on-Reset (PoR), if available in the flash, when suspending the device by runtime_pm. This would set the flash to clean state for reinitialization during resume and would also ensure that it is in standard SPI IO mode (1S-1S-1S) before the resume begins. Signed-off-by: Apurva Nandan --- drivers/mtd/nand/spi/core.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c index 608f4eb85b0a..6fb3aa6af540 100644 --- a/drivers/mtd/nand/spi/core.c +++ b/drivers/mtd/nand/spi/core.c @@ -1329,6 +1329,21 @@ static void spinand_mtd_resume(struct mtd_info *mtd) spinand_ecc_enable(spinand, false); } +static int spinand_mtd_suspend(struct mtd_info *mtd) +{ + struct spinand_device *spinand = mtd_to_spinand(mtd); + int ret; + + if (!(spinand->flags & SPINAND_HAS_POR_CMD_BIT)) + return 0; + + ret = spinand_power_on_rst_op(spinand); + if (ret) + dev_err(&spinand->spimem->spi->dev, "suspend() failed\n"); + + return ret; +} + static int spinand_init(struct spinand_device *spinand) { struct device *dev = &spinand->spimem->spi->dev; @@ -1401,6 +1416,7 @@ static int spinand_init(struct spinand_device *spinand) mtd->_erase = spinand_mtd_erase; mtd->_max_bad_blocks = nanddev_mtd_max_bad_blocks; mtd->_resume = spinand_mtd_resume; + mtd->_suspend = spinand_mtd_suspend; if (nand->ecc.engine) { ret = mtd_ooblayout_count_freebytes(mtd);