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[209.51.188.17]) by mx.google.com with ESMTPS id d23si24066658wmd.215.2021.07.13.09.42.35 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Jul 2021 09:42:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hLxrnRie; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52246 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m3LUQ-0006rD-UH for patch@linaro.org; Tue, 13 Jul 2021 12:42:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41048) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m3LU9-0006oX-DX for qemu-devel@nongnu.org; Tue, 13 Jul 2021 12:42:17 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:38463) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m3LU7-0005c8-9J for qemu-devel@nongnu.org; Tue, 13 Jul 2021 12:42:17 -0400 Received: by mail-pl1-x633.google.com with SMTP id u3so6275313plf.5 for ; Tue, 13 Jul 2021 09:42:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CpJOU5mZm1ReiYCrMc7/11RGyN8K++oSudXAQV3mu7Q=; b=hLxrnRie01rUw0Ssrf52r0Z7c7gQHYYgLUuk6O9Z+ktdE7tbWegJHrZrGrR8OtKQCQ 8DbXiy7lkDI8Tm/drJLDQGuMxr0wTtK00ms+KrogSyvXFUTQzsrlqTTeuerZxGqWxxj9 ScYgC22MzCps09HggWbUFGTbOqHRAlGeU7fxOV9MVf79le+ZYset3k3/zEjDIQCa0llf d0T8VjAL1+kVp7hDJiGK8sKLUv8YQJFvHpe7RqLQitlpR1ZQdK1BpNitzeMSI7zK/r6W ClOoydvo2XlMFPsOD71RTeqnUTby2SOTJ9nGzCykQ3YvEdR1F11PVjAATgY7tpIZZLxg 0z7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CpJOU5mZm1ReiYCrMc7/11RGyN8K++oSudXAQV3mu7Q=; b=KThmnx8gvz0357cBs1QTcOAVefSUb1wDdJc/B7vMzQwe2/3MTKQOqFYGKIJo2Qh0Zi iLaxmIYB4Hsd/bRHVf5JivyLVcMNxv9pi49PCEIX+JUUlcFZ4iYX5C60ScUTI54rBuRz En8egvaexCs39pXeA+C5X0dwjNt4qhJqsX8XJfOvWYTSmQ466AVoshQotTEmtiGne37x pzqEdUIE+DcV3D+Avkw+TPfhs8Ci84IZLCTRfgwoVJhESftLAuk5QRNtYIxqOA+u4ECs tXGvyojsDuLeVpFoqHK9JU0sL7L5ZJVSAYI2sodWS23fmJlkq34E+57jRNi+ktQAEKwa SkjA== X-Gm-Message-State: AOAM53376Ygz5LGJerFWahQxJmpr92uJLJ60WIV78mDSu564U5+eJ7+L 3eo5W+MQfB0Kea9D3dpnu1//29pHUWbmuw== X-Received: by 2002:a17:90a:4404:: with SMTP id s4mr236811pjg.218.1626194532823; Tue, 13 Jul 2021 09:42:12 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id z13sm4947865pfn.94.2021.07.13.09.42.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jul 2021 09:42:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 01/14] target/i386: Tidy hw_breakpoint_remove Date: Tue, 13 Jul 2021 09:41:58 -0700 Message-Id: <20210713164211.1520109-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210713164211.1520109-1-richard.henderson@linaro.org> References: <20210713164211.1520109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dmitry Voronetskiy Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Dmitry Voronetskiy Since cpu_breakpoint and cpu_watchpoint are in a union, the code should access only one of them. Signed-off-by: Dmitry Voronetskiy Message-Id: <20210613180838.21349-1-davoronetskiy@gmail.com> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- target/i386/tcg/sysemu/bpt_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/sysemu/bpt_helper.c b/target/i386/tcg/sysemu/bpt_helper.c index 624f90b789..4d96a48a3c 100644 --- a/target/i386/tcg/sysemu/bpt_helper.c +++ b/target/i386/tcg/sysemu/bpt_helper.c @@ -109,9 +109,9 @@ static void hw_breakpoint_remove(CPUX86State *env, int index) case DR7_TYPE_DATA_WR: case DR7_TYPE_DATA_RW: - if (env->cpu_breakpoint[index]) { + if (env->cpu_watchpoint[index]) { cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[index]); - env->cpu_breakpoint[index] = NULL; + env->cpu_watchpoint[index] = NULL; } break; From patchwork Tue Jul 13 16:41:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 474691 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp4139298jao; Tue, 13 Jul 2021 09:43:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz23dudCVnSxvlIZUYXg44JvX3o45El/mvXc2me9BAS5w7G7FGFPd6T2VECXz62DFzVad/s X-Received: by 2002:adf:f74f:: with SMTP id z15mr7043903wrp.54.1626194608332; Tue, 13 Jul 2021 09:43:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626194608; cv=none; d=google.com; s=arc-20160816; b=KiGNz3D9rtAWZkNBPvWTjIlYlfI5W95+utb2jpn0ggbyzi/PxNPzDm4ZpTw1QFMcAe gK3kirqlzX/E4914EFUh2mDcWwv7ubFe72ZRvlB4QsMqFZZPICUhv94yeu/6a+kb8vas j0coES1Y+gwpv+RtFYYKBjaV25ZnB/ufLk59Oxr7/uYgNH8S4dW2n3hF5M7PI4lTd0Oe YDWTJ2/0JoIjDBs/ecCS8iK7kzsoupbmNPGjPz1L9dO1bJdhO4cVShhfmBAUbXxV6Hrt xR29Sa8htBBKGhlLtNZbtGcAj70OB+bdJeus99d3X5i6w1fsOB9sIcVLR9eLxUes0grt hwZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gdg2+FI6wU7Qn9o6Cy0BNLACOKnRn0YbZqg7tl+kffE=; b=wauGIKdszgtkl9FMm2RyOAbGgZr0v5RGBc5SVbhBaFa8nZtcdXsUW3xYiXHP0Ng2Br x5rIXGoCarh5NxZ4H/ILIHkEUWdlzu0pY5Lfwh4DntYeXQG7/GLTBGjXJpV654dyJgk/ p8prX3Miry3wq8JV2MxVOsSBlzqT9FGDDAq69/McPOD8dwtN+adSNqrG5qQaAF6n6ecj C0ULgJ3s0Csq/BzJybkCNMWW2BBLbVQoDORHMqyEBsa2kCI9qUmtEEiG56U7kjgDjTTU 9PHz7LFqUHThWVMQg4pmVpov4JILUNizr1rSVJePW1u4uM7o3Z0Q0fGh5wNyd9lZVWUx G5Yg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BgmnzWPM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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The code style is also fixed according to the transalte.c itself during the code motion. Signed-off-by: Ziqiao Kong Message-Id: <20210530150112.74411-1-ziqiaokong@gmail.com> Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 933 ++++++++++++++++++------------------ 1 file changed, 472 insertions(+), 461 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 3814ce2a3e..a43e577019 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -5919,503 +5919,514 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) /************************/ /* floats */ case 0xd8 ... 0xdf: - if (s->flags & (HF_EM_MASK | HF_TS_MASK)) { - /* if CR0.EM or CR0.TS are set, generate an FPU exception */ - /* XXX: what to do if illegal op ? */ - gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); - break; - } - modrm = x86_ldub_code(env, s); - mod = (modrm >> 6) & 3; - rm = modrm & 7; - op = ((b & 7) << 3) | ((modrm >> 3) & 7); - if (mod != 3) { - /* memory op */ - gen_lea_modrm(env, s, modrm); - switch(op) { - case 0x00 ... 0x07: /* fxxxs */ - case 0x10 ... 0x17: /* fixxxl */ - case 0x20 ... 0x27: /* fxxxl */ - case 0x30 ... 0x37: /* fixxx */ - { - int op1; - op1 = op & 7; - - switch(op >> 4) { - case 0: - tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LEUL); - gen_helper_flds_FT0(cpu_env, s->tmp2_i32); - break; - case 1: - tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LEUL); - gen_helper_fildl_FT0(cpu_env, s->tmp2_i32); - break; - case 2: - tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, - s->mem_index, MO_LEQ); - gen_helper_fldl_FT0(cpu_env, s->tmp1_i64); - break; - case 3: - default: - tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LESW); - gen_helper_fildl_FT0(cpu_env, s->tmp2_i32); - break; - } - - gen_helper_fp_arith_ST0_FT0(op1); - if (op1 == 3) { - /* fcomp needs pop */ - gen_helper_fpop(cpu_env); - } - } + { + if (s->flags & (HF_EM_MASK | HF_TS_MASK)) { + /* if CR0.EM or CR0.TS are set, generate an FPU exception */ + /* XXX: what to do if illegal op ? */ + gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); break; - case 0x08: /* flds */ - case 0x0a: /* fsts */ - case 0x0b: /* fstps */ - case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */ - case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */ - case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */ - switch(op & 7) { - case 0: - switch(op >> 4) { + } + modrm = x86_ldub_code(env, s); + mod = (modrm >> 6) & 3; + rm = modrm & 7; + op = ((b & 7) << 3) | ((modrm >> 3) & 7); + if (mod != 3) { + /* memory op */ + gen_lea_modrm(env, s, modrm); + switch (op) { + case 0x00 ... 0x07: /* fxxxs */ + case 0x10 ... 0x17: /* fixxxl */ + case 0x20 ... 0x27: /* fxxxl */ + case 0x30 ... 0x37: /* fixxx */ + { + int op1; + op1 = op & 7; + + switch (op >> 4) { + case 0: + tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LEUL); + gen_helper_flds_FT0(cpu_env, s->tmp2_i32); + break; + case 1: + tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LEUL); + gen_helper_fildl_FT0(cpu_env, s->tmp2_i32); + break; + case 2: + tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, + s->mem_index, MO_LEQ); + gen_helper_fldl_FT0(cpu_env, s->tmp1_i64); + break; + case 3: + default: + tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LESW); + gen_helper_fildl_FT0(cpu_env, s->tmp2_i32); + break; + } + + gen_helper_fp_arith_ST0_FT0(op1); + if (op1 == 3) { + /* fcomp needs pop */ + gen_helper_fpop(cpu_env); + } + } + break; + case 0x08: /* flds */ + case 0x0a: /* fsts */ + case 0x0b: /* fstps */ + case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */ + case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */ + case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */ + switch (op & 7) { case 0: - tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LEUL); - gen_helper_flds_ST0(cpu_env, s->tmp2_i32); + switch (op >> 4) { + case 0: + tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LEUL); + gen_helper_flds_ST0(cpu_env, s->tmp2_i32); + break; + case 1: + tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LEUL); + gen_helper_fildl_ST0(cpu_env, s->tmp2_i32); + break; + case 2: + tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, + s->mem_index, MO_LEQ); + gen_helper_fldl_ST0(cpu_env, s->tmp1_i64); + break; + case 3: + default: + tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LESW); + gen_helper_fildl_ST0(cpu_env, s->tmp2_i32); + break; + } break; case 1: - tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LEUL); - gen_helper_fildl_ST0(cpu_env, s->tmp2_i32); + /* XXX: the corresponding CPUID bit must be tested ! */ + switch (op >> 4) { + case 1: + gen_helper_fisttl_ST0(s->tmp2_i32, cpu_env); + tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LEUL); + break; + case 2: + gen_helper_fisttll_ST0(s->tmp1_i64, cpu_env); + tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, + s->mem_index, MO_LEQ); + break; + case 3: + default: + gen_helper_fistt_ST0(s->tmp2_i32, cpu_env); + tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LEUW); + break; + } + gen_helper_fpop(cpu_env); break; - case 2: - tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, - s->mem_index, MO_LEQ); - gen_helper_fldl_ST0(cpu_env, s->tmp1_i64); - break; - case 3: default: - tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LESW); - gen_helper_fildl_ST0(cpu_env, s->tmp2_i32); + switch (op >> 4) { + case 0: + gen_helper_fsts_ST0(s->tmp2_i32, cpu_env); + tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LEUL); + break; + case 1: + gen_helper_fistl_ST0(s->tmp2_i32, cpu_env); + tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LEUL); + break; + case 2: + gen_helper_fstl_ST0(s->tmp1_i64, cpu_env); + tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, + s->mem_index, MO_LEQ); + break; + case 3: + default: + gen_helper_fist_ST0(s->tmp2_i32, cpu_env); + tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LEUW); + break; + } + if ((op & 7) == 3) { + gen_helper_fpop(cpu_env); + } break; } break; - case 1: - /* XXX: the corresponding CPUID bit must be tested ! */ - switch(op >> 4) { - case 1: - gen_helper_fisttl_ST0(s->tmp2_i32, cpu_env); - tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LEUL); - break; - case 2: - gen_helper_fisttll_ST0(s->tmp1_i64, cpu_env); - tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, - s->mem_index, MO_LEQ); - break; - case 3: - default: - gen_helper_fistt_ST0(s->tmp2_i32, cpu_env); - tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LEUW); - break; - } + case 0x0c: /* fldenv mem */ + gen_helper_fldenv(cpu_env, s->A0, + tcg_const_i32(dflag - 1)); + break; + case 0x0d: /* fldcw mem */ + tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LEUW); + gen_helper_fldcw(cpu_env, s->tmp2_i32); + break; + case 0x0e: /* fnstenv mem */ + gen_helper_fstenv(cpu_env, s->A0, + tcg_const_i32(dflag - 1)); + break; + case 0x0f: /* fnstcw mem */ + gen_helper_fnstcw(s->tmp2_i32, cpu_env); + tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LEUW); + break; + case 0x1d: /* fldt mem */ + gen_helper_fldt_ST0(cpu_env, s->A0); + break; + case 0x1f: /* fstpt mem */ + gen_helper_fstt_ST0(cpu_env, s->A0); + gen_helper_fpop(cpu_env); + break; + case 0x2c: /* frstor mem */ + gen_helper_frstor(cpu_env, s->A0, + tcg_const_i32(dflag - 1)); + break; + case 0x2e: /* fnsave mem */ + gen_helper_fsave(cpu_env, s->A0, + tcg_const_i32(dflag - 1)); + break; + case 0x2f: /* fnstsw mem */ + gen_helper_fnstsw(s->tmp2_i32, cpu_env); + tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, + s->mem_index, MO_LEUW); + break; + case 0x3c: /* fbld */ + gen_helper_fbld_ST0(cpu_env, s->A0); + break; + case 0x3e: /* fbstp */ + gen_helper_fbst_ST0(cpu_env, s->A0); + gen_helper_fpop(cpu_env); + break; + case 0x3d: /* fildll */ + tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, + s->mem_index, MO_LEQ); + gen_helper_fildll_ST0(cpu_env, s->tmp1_i64); + break; + case 0x3f: /* fistpll */ + gen_helper_fistll_ST0(s->tmp1_i64, cpu_env); + tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, + s->mem_index, MO_LEQ); gen_helper_fpop(cpu_env); break; default: - switch(op >> 4) { - case 0: - gen_helper_fsts_ST0(s->tmp2_i32, cpu_env); - tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LEUL); - break; - case 1: - gen_helper_fistl_ST0(s->tmp2_i32, cpu_env); - tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LEUL); - break; - case 2: - gen_helper_fstl_ST0(s->tmp1_i64, cpu_env); - tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, - s->mem_index, MO_LEQ); - break; - case 3: - default: - gen_helper_fist_ST0(s->tmp2_i32, cpu_env); - tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LEUW); - break; - } - if ((op & 7) == 3) - gen_helper_fpop(cpu_env); - break; + goto unknown_op; } - break; - case 0x0c: /* fldenv mem */ - gen_helper_fldenv(cpu_env, s->A0, tcg_const_i32(dflag - 1)); - break; - case 0x0d: /* fldcw mem */ - tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LEUW); - gen_helper_fldcw(cpu_env, s->tmp2_i32); - break; - case 0x0e: /* fnstenv mem */ - gen_helper_fstenv(cpu_env, s->A0, tcg_const_i32(dflag - 1)); - break; - case 0x0f: /* fnstcw mem */ - gen_helper_fnstcw(s->tmp2_i32, cpu_env); - tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LEUW); - break; - case 0x1d: /* fldt mem */ - gen_helper_fldt_ST0(cpu_env, s->A0); - break; - case 0x1f: /* fstpt mem */ - gen_helper_fstt_ST0(cpu_env, s->A0); - gen_helper_fpop(cpu_env); - break; - case 0x2c: /* frstor mem */ - gen_helper_frstor(cpu_env, s->A0, tcg_const_i32(dflag - 1)); - break; - case 0x2e: /* fnsave mem */ - gen_helper_fsave(cpu_env, s->A0, tcg_const_i32(dflag - 1)); - break; - case 0x2f: /* fnstsw mem */ - gen_helper_fnstsw(s->tmp2_i32, cpu_env); - tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, - s->mem_index, MO_LEUW); - break; - case 0x3c: /* fbld */ - gen_helper_fbld_ST0(cpu_env, s->A0); - break; - case 0x3e: /* fbstp */ - gen_helper_fbst_ST0(cpu_env, s->A0); - gen_helper_fpop(cpu_env); - break; - case 0x3d: /* fildll */ - tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEQ); - gen_helper_fildll_ST0(cpu_env, s->tmp1_i64); - break; - case 0x3f: /* fistpll */ - gen_helper_fistll_ST0(s->tmp1_i64, cpu_env); - tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEQ); - gen_helper_fpop(cpu_env); - break; - default: - goto unknown_op; - } - } else { - /* register float ops */ - opreg = rm; + } else { + /* register float ops */ + opreg = rm; - switch(op) { - case 0x08: /* fld sti */ - gen_helper_fpush(cpu_env); - gen_helper_fmov_ST0_STN(cpu_env, - tcg_const_i32((opreg + 1) & 7)); - break; - case 0x09: /* fxchg sti */ - case 0x29: /* fxchg4 sti, undocumented op */ - case 0x39: /* fxchg7 sti, undocumented op */ - gen_helper_fxchg_ST0_STN(cpu_env, tcg_const_i32(opreg)); - break; - case 0x0a: /* grp d9/2 */ - switch(rm) { - case 0: /* fnop */ - /* check exceptions (FreeBSD FPU probe) */ - gen_helper_fwait(cpu_env); + switch (op) { + case 0x08: /* fld sti */ + gen_helper_fpush(cpu_env); + gen_helper_fmov_ST0_STN(cpu_env, + tcg_const_i32((opreg + 1) & 7)); break; - default: - goto unknown_op; - } - break; - case 0x0c: /* grp d9/4 */ - switch(rm) { - case 0: /* fchs */ - gen_helper_fchs_ST0(cpu_env); + case 0x09: /* fxchg sti */ + case 0x29: /* fxchg4 sti, undocumented op */ + case 0x39: /* fxchg7 sti, undocumented op */ + gen_helper_fxchg_ST0_STN(cpu_env, tcg_const_i32(opreg)); break; - case 1: /* fabs */ - gen_helper_fabs_ST0(cpu_env); - break; - case 4: /* ftst */ - gen_helper_fldz_FT0(cpu_env); - gen_helper_fcom_ST0_FT0(cpu_env); - break; - case 5: /* fxam */ - gen_helper_fxam_ST0(cpu_env); - break; - default: - goto unknown_op; - } - break; - case 0x0d: /* grp d9/5 */ - { - switch(rm) { - case 0: - gen_helper_fpush(cpu_env); - gen_helper_fld1_ST0(cpu_env); - break; - case 1: - gen_helper_fpush(cpu_env); - gen_helper_fldl2t_ST0(cpu_env); - break; - case 2: - gen_helper_fpush(cpu_env); - gen_helper_fldl2e_ST0(cpu_env); - break; - case 3: - gen_helper_fpush(cpu_env); - gen_helper_fldpi_ST0(cpu_env); - break; - case 4: - gen_helper_fpush(cpu_env); - gen_helper_fldlg2_ST0(cpu_env); - break; - case 5: - gen_helper_fpush(cpu_env); - gen_helper_fldln2_ST0(cpu_env); - break; - case 6: - gen_helper_fpush(cpu_env); - gen_helper_fldz_ST0(cpu_env); + case 0x0a: /* grp d9/2 */ + switch (rm) { + case 0: /* fnop */ + /* check exceptions (FreeBSD FPU probe) */ + gen_helper_fwait(cpu_env); break; default: goto unknown_op; } - } - break; - case 0x0e: /* grp d9/6 */ - switch(rm) { - case 0: /* f2xm1 */ - gen_helper_f2xm1(cpu_env); break; - case 1: /* fyl2x */ - gen_helper_fyl2x(cpu_env); - break; - case 2: /* fptan */ - gen_helper_fptan(cpu_env); - break; - case 3: /* fpatan */ - gen_helper_fpatan(cpu_env); - break; - case 4: /* fxtract */ - gen_helper_fxtract(cpu_env); - break; - case 5: /* fprem1 */ - gen_helper_fprem1(cpu_env); - break; - case 6: /* fdecstp */ - gen_helper_fdecstp(cpu_env); - break; - default: - case 7: /* fincstp */ - gen_helper_fincstp(cpu_env); - break; - } - break; - case 0x0f: /* grp d9/7 */ - switch(rm) { - case 0: /* fprem */ - gen_helper_fprem(cpu_env); - break; - case 1: /* fyl2xp1 */ - gen_helper_fyl2xp1(cpu_env); - break; - case 2: /* fsqrt */ - gen_helper_fsqrt(cpu_env); - break; - case 3: /* fsincos */ - gen_helper_fsincos(cpu_env); - break; - case 5: /* fscale */ - gen_helper_fscale(cpu_env); - break; - case 4: /* frndint */ - gen_helper_frndint(cpu_env); - break; - case 6: /* fsin */ - gen_helper_fsin(cpu_env); - break; - default: - case 7: /* fcos */ - gen_helper_fcos(cpu_env); - break; - } - break; - case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */ - case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */ - case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */ - { - int op1; - - op1 = op & 7; - if (op >= 0x20) { - gen_helper_fp_arith_STN_ST0(op1, opreg); - if (op >= 0x30) - gen_helper_fpop(cpu_env); - } else { - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); - gen_helper_fp_arith_ST0_FT0(op1); + case 0x0c: /* grp d9/4 */ + switch (rm) { + case 0: /* fchs */ + gen_helper_fchs_ST0(cpu_env); + break; + case 1: /* fabs */ + gen_helper_fabs_ST0(cpu_env); + break; + case 4: /* ftst */ + gen_helper_fldz_FT0(cpu_env); + gen_helper_fcom_ST0_FT0(cpu_env); + break; + case 5: /* fxam */ + gen_helper_fxam_ST0(cpu_env); + break; + default: + goto unknown_op; } - } - break; - case 0x02: /* fcom */ - case 0x22: /* fcom2, undocumented op */ - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); - gen_helper_fcom_ST0_FT0(cpu_env); - break; - case 0x03: /* fcomp */ - case 0x23: /* fcomp3, undocumented op */ - case 0x32: /* fcomp5, undocumented op */ - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); - gen_helper_fcom_ST0_FT0(cpu_env); - gen_helper_fpop(cpu_env); - break; - case 0x15: /* da/5 */ - switch(rm) { - case 1: /* fucompp */ - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); - gen_helper_fucom_ST0_FT0(cpu_env); - gen_helper_fpop(cpu_env); - gen_helper_fpop(cpu_env); break; - default: - goto unknown_op; - } - break; - case 0x1c: - switch(rm) { - case 0: /* feni (287 only, just do nop here) */ + case 0x0d: /* grp d9/5 */ + { + switch (rm) { + case 0: + gen_helper_fpush(cpu_env); + gen_helper_fld1_ST0(cpu_env); + break; + case 1: + gen_helper_fpush(cpu_env); + gen_helper_fldl2t_ST0(cpu_env); + break; + case 2: + gen_helper_fpush(cpu_env); + gen_helper_fldl2e_ST0(cpu_env); + break; + case 3: + gen_helper_fpush(cpu_env); + gen_helper_fldpi_ST0(cpu_env); + break; + case 4: + gen_helper_fpush(cpu_env); + gen_helper_fldlg2_ST0(cpu_env); + break; + case 5: + gen_helper_fpush(cpu_env); + gen_helper_fldln2_ST0(cpu_env); + break; + case 6: + gen_helper_fpush(cpu_env); + gen_helper_fldz_ST0(cpu_env); + break; + default: + goto unknown_op; + } + } break; - case 1: /* fdisi (287 only, just do nop here) */ + case 0x0e: /* grp d9/6 */ + switch (rm) { + case 0: /* f2xm1 */ + gen_helper_f2xm1(cpu_env); + break; + case 1: /* fyl2x */ + gen_helper_fyl2x(cpu_env); + break; + case 2: /* fptan */ + gen_helper_fptan(cpu_env); + break; + case 3: /* fpatan */ + gen_helper_fpatan(cpu_env); + break; + case 4: /* fxtract */ + gen_helper_fxtract(cpu_env); + break; + case 5: /* fprem1 */ + gen_helper_fprem1(cpu_env); + break; + case 6: /* fdecstp */ + gen_helper_fdecstp(cpu_env); + break; + default: + case 7: /* fincstp */ + gen_helper_fincstp(cpu_env); + break; + } break; - case 2: /* fclex */ - gen_helper_fclex(cpu_env); + case 0x0f: /* grp d9/7 */ + switch (rm) { + case 0: /* fprem */ + gen_helper_fprem(cpu_env); + break; + case 1: /* fyl2xp1 */ + gen_helper_fyl2xp1(cpu_env); + break; + case 2: /* fsqrt */ + gen_helper_fsqrt(cpu_env); + break; + case 3: /* fsincos */ + gen_helper_fsincos(cpu_env); + break; + case 5: /* fscale */ + gen_helper_fscale(cpu_env); + break; + case 4: /* frndint */ + gen_helper_frndint(cpu_env); + break; + case 6: /* fsin */ + gen_helper_fsin(cpu_env); + break; + default: + case 7: /* fcos */ + gen_helper_fcos(cpu_env); + break; + } break; - case 3: /* fninit */ - gen_helper_fninit(cpu_env); + case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */ + case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */ + case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */ + { + int op1; + + op1 = op & 7; + if (op >= 0x20) { + gen_helper_fp_arith_STN_ST0(op1, opreg); + if (op >= 0x30) { + gen_helper_fpop(cpu_env); + } + } else { + gen_helper_fmov_FT0_STN(cpu_env, + tcg_const_i32(opreg)); + gen_helper_fp_arith_ST0_FT0(op1); + } + } break; - case 4: /* fsetpm (287 only, just do nop here) */ + case 0x02: /* fcom */ + case 0x22: /* fcom2, undocumented op */ + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fcom_ST0_FT0(cpu_env); break; - default: - goto unknown_op; - } - break; - case 0x1d: /* fucomi */ - if (!(s->cpuid_features & CPUID_CMOV)) { - goto illegal_op; - } - gen_update_cc_op(s); - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); - gen_helper_fucomi_ST0_FT0(cpu_env); - set_cc_op(s, CC_OP_EFLAGS); - break; - case 0x1e: /* fcomi */ - if (!(s->cpuid_features & CPUID_CMOV)) { - goto illegal_op; - } - gen_update_cc_op(s); - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); - gen_helper_fcomi_ST0_FT0(cpu_env); - set_cc_op(s, CC_OP_EFLAGS); - break; - case 0x28: /* ffree sti */ - gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); - break; - case 0x2a: /* fst sti */ - gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); - break; - case 0x2b: /* fstp sti */ - case 0x0b: /* fstp1 sti, undocumented op */ - case 0x3a: /* fstp8 sti, undocumented op */ - case 0x3b: /* fstp9 sti, undocumented op */ - gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); - gen_helper_fpop(cpu_env); - break; - case 0x2c: /* fucom st(i) */ - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); - gen_helper_fucom_ST0_FT0(cpu_env); - break; - case 0x2d: /* fucomp st(i) */ - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); - gen_helper_fucom_ST0_FT0(cpu_env); - gen_helper_fpop(cpu_env); - break; - case 0x33: /* de/3 */ - switch(rm) { - case 1: /* fcompp */ - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); + case 0x03: /* fcomp */ + case 0x23: /* fcomp3, undocumented op */ + case 0x32: /* fcomp5, undocumented op */ + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); gen_helper_fcom_ST0_FT0(cpu_env); gen_helper_fpop(cpu_env); - gen_helper_fpop(cpu_env); break; - default: - goto unknown_op; - } - break; - case 0x38: /* ffreep sti, undocumented op */ - gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); - gen_helper_fpop(cpu_env); - break; - case 0x3c: /* df/4 */ - switch(rm) { - case 0: - gen_helper_fnstsw(s->tmp2_i32, cpu_env); - tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32); - gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0); + case 0x15: /* da/5 */ + switch (rm) { + case 1: /* fucompp */ + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); + gen_helper_fucom_ST0_FT0(cpu_env); + gen_helper_fpop(cpu_env); + gen_helper_fpop(cpu_env); + break; + default: + goto unknown_op; + } break; - default: - goto unknown_op; - } - break; - case 0x3d: /* fucomip */ - if (!(s->cpuid_features & CPUID_CMOV)) { - goto illegal_op; - } - gen_update_cc_op(s); - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); - gen_helper_fucomi_ST0_FT0(cpu_env); - gen_helper_fpop(cpu_env); - set_cc_op(s, CC_OP_EFLAGS); - break; - case 0x3e: /* fcomip */ - if (!(s->cpuid_features & CPUID_CMOV)) { - goto illegal_op; - } - gen_update_cc_op(s); - gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); - gen_helper_fcomi_ST0_FT0(cpu_env); - gen_helper_fpop(cpu_env); - set_cc_op(s, CC_OP_EFLAGS); - break; - case 0x10 ... 0x13: /* fcmovxx */ - case 0x18 ... 0x1b: - { - int op1; - TCGLabel *l1; - static const uint8_t fcmov_cc[8] = { - (JCC_B << 1), - (JCC_Z << 1), - (JCC_BE << 1), - (JCC_P << 1), - }; - + case 0x1c: + switch (rm) { + case 0: /* feni (287 only, just do nop here) */ + break; + case 1: /* fdisi (287 only, just do nop here) */ + break; + case 2: /* fclex */ + gen_helper_fclex(cpu_env); + break; + case 3: /* fninit */ + gen_helper_fninit(cpu_env); + break; + case 4: /* fsetpm (287 only, just do nop here) */ + break; + default: + goto unknown_op; + } + break; + case 0x1d: /* fucomi */ if (!(s->cpuid_features & CPUID_CMOV)) { goto illegal_op; } - op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1); - l1 = gen_new_label(); - gen_jcc1_noeob(s, op1, l1); - gen_helper_fmov_ST0_STN(cpu_env, tcg_const_i32(opreg)); - gen_set_label(l1); + gen_update_cc_op(s); + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fucomi_ST0_FT0(cpu_env); + set_cc_op(s, CC_OP_EFLAGS); + break; + case 0x1e: /* fcomi */ + if (!(s->cpuid_features & CPUID_CMOV)) { + goto illegal_op; + } + gen_update_cc_op(s); + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fcomi_ST0_FT0(cpu_env); + set_cc_op(s, CC_OP_EFLAGS); + break; + case 0x28: /* ffree sti */ + gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); + break; + case 0x2a: /* fst sti */ + gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); + break; + case 0x2b: /* fstp sti */ + case 0x0b: /* fstp1 sti, undocumented op */ + case 0x3a: /* fstp8 sti, undocumented op */ + case 0x3b: /* fstp9 sti, undocumented op */ + gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); + gen_helper_fpop(cpu_env); + break; + case 0x2c: /* fucom st(i) */ + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fucom_ST0_FT0(cpu_env); + break; + case 0x2d: /* fucomp st(i) */ + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fucom_ST0_FT0(cpu_env); + gen_helper_fpop(cpu_env); + break; + case 0x33: /* de/3 */ + switch (rm) { + case 1: /* fcompp */ + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); + gen_helper_fcom_ST0_FT0(cpu_env); + gen_helper_fpop(cpu_env); + gen_helper_fpop(cpu_env); + break; + default: + goto unknown_op; + } + break; + case 0x38: /* ffreep sti, undocumented op */ + gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fpop(cpu_env); + break; + case 0x3c: /* df/4 */ + switch (rm) { + case 0: + gen_helper_fnstsw(s->tmp2_i32, cpu_env); + tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32); + gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0); + break; + default: + goto unknown_op; + } + break; + case 0x3d: /* fucomip */ + if (!(s->cpuid_features & CPUID_CMOV)) { + goto illegal_op; + } + gen_update_cc_op(s); + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fucomi_ST0_FT0(cpu_env); + gen_helper_fpop(cpu_env); + set_cc_op(s, CC_OP_EFLAGS); + break; + case 0x3e: /* fcomip */ + if (!(s->cpuid_features & CPUID_CMOV)) { + goto illegal_op; + } + gen_update_cc_op(s); + gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); + gen_helper_fcomi_ST0_FT0(cpu_env); + gen_helper_fpop(cpu_env); + set_cc_op(s, CC_OP_EFLAGS); + break; + case 0x10 ... 0x13: /* fcmovxx */ + case 0x18 ... 0x1b: + { + int op1; + TCGLabel *l1; + static const uint8_t fcmov_cc[8] = { + (JCC_B << 1), + (JCC_Z << 1), + (JCC_BE << 1), + (JCC_P << 1), + }; + + if (!(s->cpuid_features & CPUID_CMOV)) { + goto illegal_op; + } + op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1); + l1 = gen_new_label(); + gen_jcc1_noeob(s, op1, l1); + gen_helper_fmov_ST0_STN(cpu_env, tcg_const_i32(opreg)); + gen_set_label(l1); + } + break; + default: + goto unknown_op; } - break; - default: - goto unknown_op; } } break; From patchwork Tue Jul 13 16:42:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 474696 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp4142382jao; Tue, 13 Jul 2021 09:47:02 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy59+rPLkjY+cEfo/756iZaerRZqfaRqqAsc/9dLVoxtXk3+RJ06Dzk2juPyb3Jm/GwM9TX X-Received: by 2002:a5d:6b91:: with SMTP id n17mr6946028wrx.385.1626194822366; Tue, 13 Jul 2021 09:47:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626194822; cv=none; d=google.com; s=arc-20160816; b=xO+ScVfGo64D713Hlzdqw4PGhS3FpKCKsDQ0f0Cof5gFQfbtsfya8Y+E/wXnbPEg0s RRt5y6NQco6VOZx4UIM+gianGvj0up5McTZtSaNbR5BfSmqaBZrDJNEov41G8G3LdQkW 5VJsC9mSwNEEAt08mJuM7jqK0kQ1q8XMrly3wg/DJ46TCjsP7y95IxTxtkm5aCyjjh4U mbuCccoSF+LNrItFGbIn9YghUottvonBLTESm9EGK3ArdaZZvyFw5lZFq2iXYNzLckhD dyk8cd6xpO97fOJ7LA233NWHFwGDoAgtmaiAubWlVjxOK0JJEGDH1iWcUL3p7wJVVBgW rJUw== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id l20si4608986wmg.3.2021.07.13.09.47.02 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Jul 2021 09:47:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZBiGSyRc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39988 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m3LYi-0000fY-B1 for patch@linaro.org; Tue, 13 Jul 2021 12:47:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41112) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m3LUB-0006qy-HE for qemu-devel@nongnu.org; Tue, 13 Jul 2021 12:42:19 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:35756) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m3LU7-0005da-Nc for qemu-devel@nongnu.org; Tue, 13 Jul 2021 12:42:19 -0400 Received: by mail-pj1-x102c.google.com with SMTP id h1-20020a17090a3d01b0290172d33bb8bcso1827483pjc.0 for ; Tue, 13 Jul 2021 09:42:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cYyCuRRmAK2Rie5jBdr3R+LAqWVke2VP4TG50eB3qqU=; b=ZBiGSyRcGFJCvpFrQwW2Xizu7CILQqueQQylkF+YeKs4PT0ZPSbsRQYNKWmZjdgNwL NlhI0pE555NlsQ/dV/eKeTQfHz6g4Vay+Tf1qz92r1t4VN1mltKi+SygKuiHIp21rNNv prY1DwEYBC8JkK6Na/3T9fVR6HoQ0geP9uUHAcHdG9B0HommMkDkU6+g46Gh/Sd2QW3y Wy3YzScJACqS4jq/KYZ2oOLllcqozYGaE45sHVQGxy3qfklZg0Jr5ssIB9kM0O8Opv0m pEZ6p/k0VnLCR+pzADq6uM/K8DBqHbmjhrYKjcDwKDJwwll9kLLjns/Rn5UdN52hnBrd Vhyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cYyCuRRmAK2Rie5jBdr3R+LAqWVke2VP4TG50eB3qqU=; b=B+5FXDUv4dv2CBqByroZhGG6lnQW3cmBEF5U+FgMr1tlQF8Gd5B6erO7/GjPhTRscG R2oSZeQB0y7qOCPHQqr4zs0wGEVM8o3FwnyqFJjW84/dBghCSNWeE/WuQs+3yCAcVkKZ zTZ+eir1R5t9fRi4Rg/ZhKFxMDU/3Mu8JhiPR4BU5/nD/ai2CDPlhLHx2ZWAndqxEnbz pu3JXDSNQBbxLv+u2mpkdXxEqhA45BsaEyoVTY7UMQ83qPvHQ4GAL+i4Vz4awx2pcn/5 KmV/3toqbOfGvJhrGRlEUaoSdnM9YhHuXS8xbgoKDzMAD0B5YJ2xD9dqvRnpIcWriU0C yGEA== X-Gm-Message-State: AOAM531bQGKt1K+nimLZxuUrkTtaTH0PIafJ6tqsCTS6D0WNwDzHPKWL aumqQ1mu/z7KaVnljAvbBloLVPS7wYh/0g== X-Received: by 2002:a17:90b:3a89:: with SMTP id om9mr2828110pjb.91.1626194534269; Tue, 13 Jul 2021 09:42:14 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id z13sm4947865pfn.94.2021.07.13.09.42.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jul 2021 09:42:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 03/14] target/i386: Split out do_fninit Date: Tue, 13 Jul 2021 09:42:00 -0700 Message-Id: <20210713164211.1520109-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210713164211.1520109-1-richard.henderson@linaro.org> References: <20210713164211.1520109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do not call helper_fninit directly from helper_xrstor. Do call the new helper from do_fsave. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/i386/tcg/fpu_helper.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 74bbe94b80..beb63be432 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -727,7 +727,7 @@ void helper_fwait(CPUX86State *env) } } -void helper_fninit(CPUX86State *env) +static void do_fninit(CPUX86State *env) { env->fpus = 0; env->fpstt = 0; @@ -742,6 +742,11 @@ void helper_fninit(CPUX86State *env) env->fptags[7] = 1; } +void helper_fninit(CPUX86State *env) +{ + do_fninit(env); +} + /* BCD ops */ void helper_fbld_ST0(CPUX86State *env, target_ulong ptr) @@ -2451,18 +2456,7 @@ static void do_fsave(CPUX86State *env, target_ulong ptr, int data32, ptr += 10; } - /* fninit */ - env->fpus = 0; - env->fpstt = 0; - cpu_set_fpuc(env, 0x37f); - env->fptags[0] = 1; - env->fptags[1] = 1; - env->fptags[2] = 1; - env->fptags[3] = 1; - env->fptags[4] = 1; - env->fptags[5] = 1; - env->fptags[6] = 1; - env->fptags[7] = 1; + do_fninit(env); } void helper_fsave(CPUX86State *env, target_ulong ptr, int data32) @@ -2834,7 +2828,7 @@ void helper_xrstor(CPUX86State *env, target_ulong ptr, uint64_t rfbm) if (xstate_bv & XSTATE_FP_MASK) { do_xrstor_fpu(env, ptr, ra); } else { - helper_fninit(env); + do_fninit(env); memset(env->fpregs, 0, sizeof(env->fpregs)); } } From patchwork Tue Jul 13 16:42:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 474695 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp4141307jao; Tue, 13 Jul 2021 09:45:46 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx6EzONn76OyVdpsy3ji2trmrGdhZXVHFH4Ekn/upF65NTpn4zT76Li+67aOomEw+5opnNd X-Received: by 2002:a05:600c:2105:: with SMTP id u5mr1928821wml.18.1626194746480; Tue, 13 Jul 2021 09:45:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626194746; cv=none; d=google.com; s=arc-20160816; b=q1cbN+Rlqr0IZRj0PEwBmffU3oWVJ2F4WyBUnA6kmmQuNhoa4cvm2nxjmoyD1cWn+U TC6MC7vqQnCT4zghHOiao68yjwByxkX9Gm/wgYxFXoOJQWAlMQbO54EnbbsFDdWJR3I4 PJnSjQZv+eIGivZ8rptyAR7aJAaCtb+BQ8hu3vvkEsdmL+vxPBsRPR7dvkIl7E8HXouN 1rQ2ATY4cPSY9IajSSAdHA5hosKK80UcbkoJYYxnZIEwy3uMRRsN7/n6SYt4iG+cjCOR jLqnxymZDRJmocQvoI2VseT/WHkY/mT/qcVfaL8kvV3ntBxAGM82WcxqaOEzbFC4E+dI 3rIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9Vn3OZCvKq6jSOiidVy5UivM/a7wIKe+2cpNk3bOhtM=; b=JE7JbATkTx2woKTroCezQZANJfiHJ8umEdkygqIMGWO23uD93N0f+fFzyq4Khb7+U4 eSzgjFCrj5Grvgw6NGQyTZ798yTGyk6HIXQb5UvHJDr8HdmmeUAuTkRZf4cLmgA4LkHQ DCMuHpbFuOfWV8uO2ZzGA7DPUwI2iMhs3f1BCE0ogObylPmX2AtoRgmeM9Qcy1MxLBq6 /10M3/c5DrwSc5NzBy3igeC/hlVeL5VBumnipMLBt/Eu41PSaN/Hm1dJyogZURi7qwSe a0hsI6NayB9odp8t0Ff1JcT2AFl+9MfsmlA4WEtIfSG2djmtctq66uyECG98Dqzu6iMp 531g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kK9Un3gc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k3si23489419wrv.399.2021.07.13.09.45.46 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Jul 2021 09:45:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kK9Un3gc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33164 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m3LXV-0004Sq-B5 for patch@linaro.org; Tue, 13 Jul 2021 12:45:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41136) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m3LUC-0006sj-GF for qemu-devel@nongnu.org; Tue, 13 Jul 2021 12:42:21 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:39799) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m3LU8-0005dy-6Q for qemu-devel@nongnu.org; Tue, 13 Jul 2021 12:42:20 -0400 Received: by mail-pf1-x436.google.com with SMTP id b12so20158184pfv.6 for ; Tue, 13 Jul 2021 09:42:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9Vn3OZCvKq6jSOiidVy5UivM/a7wIKe+2cpNk3bOhtM=; b=kK9Un3gciO8zsk1qIulRH828nLWrtn7Tzye9QMDw85jBTR6LPibvcaCzeP6q0mVtDc aFjkr3yAUW+TmwcieqNoNjHyhHD4ozaAsrvc9m/Pwo6X+JI5VP9uWHOhcP1YQW6Ur7Bz QxLIPJ4JUVvNZNW0hmjiZmzxLm5iNP3ObJSO4PTjAUcG/sPIqqlWsd8qNyatuPvfWK0o K/dfViFouyFngXjJ16rSE7T08JYN7upEMtLizDwfc2oXJRJT/6H33yLeg/7X3GkRNEvt HA/o1+hUcwpMXJBaIzXKjmLhnDd2eNBPoZaOALK8FxCQOr3ZXIOuVOJ5rhqXglWvTc7t hyXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9Vn3OZCvKq6jSOiidVy5UivM/a7wIKe+2cpNk3bOhtM=; b=KB7nTJwUEGYrzohgxGi8YIFQarq7BuLo7rf0D/RgCIFiai6qfzIAuHsYyTa/HgqtJ9 x4bIpMuZwZ4BsxBl/zNR013rojIqK4eaad3ihmJUAze50hNfIeT2FobChmvC/B4zNMwX MDbh6Pv95pXLsrIre4A0knU6paNRgb8QgNYGWy4z1ja3xpbRSuGhVAsWZv2LSxl5iTvj gg+GVmf38e2rgp1SChzR/NCgW+sFubvEzmzCh0eFFfWiuJ66Gh4rGfFSYcemeebkwpiv 2GWIUPA5ok5UTcXqRYSwYt1cjBZv7NPDqEwY25mV7TG2vQzEHGsJbkEziqar1HZkMBsI MBfA== X-Gm-Message-State: AOAM531tAOnQupl4qUYStGAMU1Xlve38++E5fV9Ppm6PIXrvpzf0LZyV /WjzuXQKlntXrF3wNnYD/K4qN1HmxMU9yg== X-Received: by 2002:a62:8209:0:b029:32e:54d4:7e27 with SMTP id w9-20020a6282090000b029032e54d47e27mr2507125pfd.10.1626194534880; Tue, 13 Jul 2021 09:42:14 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id z13sm4947865pfn.94.2021.07.13.09.42.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jul 2021 09:42:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 04/14] target/i386: Correct implementation for FCS, FIP, FDS and FDP Date: Tue, 13 Jul 2021 09:42:01 -0700 Message-Id: <20210713164211.1520109-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210713164211.1520109-1-richard.henderson@linaro.org> References: <20210713164211.1520109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ziqiao Kong Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Ziqiao Kong Update FCS:FIP and FDS:FDP according to the Intel Manual Vol.1 8.1.8. Note that CPUID.(EAX=07H,ECX=0H):EBX[bit 13] is not implemented by design in this patch and will be added along with TCG features flag in a separate patch later. Signed-off-by: Ziqiao Kong Message-Id: <20210530150112.74411-2-ziqiaokong@gmail.com> [rth: Push FDS/FDP handling down into mod != 3 case; free last_addr.] Signed-off-by: Richard Henderson --- target/i386/cpu.h | 2 ++ target/i386/tcg/fpu_helper.c | 20 ++++++++++------- target/i386/tcg/translate.c | 43 +++++++++++++++++++++++++++++++++++- 3 files changed, 56 insertions(+), 9 deletions(-) -- 2.25.1 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8f3747dd28..3dc52deaef 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1437,6 +1437,8 @@ typedef struct CPUX86State { FPReg fpregs[8]; /* KVM-only so far */ uint16_t fpop; + uint16_t fpcs; + uint16_t fpds; uint64_t fpip; uint64_t fpdp; diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index beb63be432..cdd8e9f947 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -731,6 +731,10 @@ static void do_fninit(CPUX86State *env) { env->fpus = 0; env->fpstt = 0; + env->fpcs = 0; + env->fpds = 0; + env->fpip = 0; + env->fpdp = 0; cpu_set_fpuc(env, 0x37f); env->fptags[0] = 1; env->fptags[1] = 1; @@ -2378,19 +2382,19 @@ static void do_fstenv(CPUX86State *env, target_ulong ptr, int data32, cpu_stl_data_ra(env, ptr, env->fpuc, retaddr); cpu_stl_data_ra(env, ptr + 4, fpus, retaddr); cpu_stl_data_ra(env, ptr + 8, fptag, retaddr); - cpu_stl_data_ra(env, ptr + 12, 0, retaddr); /* fpip */ - cpu_stl_data_ra(env, ptr + 16, 0, retaddr); /* fpcs */ - cpu_stl_data_ra(env, ptr + 20, 0, retaddr); /* fpoo */ - cpu_stl_data_ra(env, ptr + 24, 0, retaddr); /* fpos */ + cpu_stl_data_ra(env, ptr + 12, env->fpip, retaddr); /* fpip */ + cpu_stl_data_ra(env, ptr + 16, env->fpcs, retaddr); /* fpcs */ + cpu_stl_data_ra(env, ptr + 20, env->fpdp, retaddr); /* fpoo */ + cpu_stl_data_ra(env, ptr + 24, env->fpds, retaddr); /* fpos */ } else { /* 16 bit */ cpu_stw_data_ra(env, ptr, env->fpuc, retaddr); cpu_stw_data_ra(env, ptr + 2, fpus, retaddr); cpu_stw_data_ra(env, ptr + 4, fptag, retaddr); - cpu_stw_data_ra(env, ptr + 6, 0, retaddr); - cpu_stw_data_ra(env, ptr + 8, 0, retaddr); - cpu_stw_data_ra(env, ptr + 10, 0, retaddr); - cpu_stw_data_ra(env, ptr + 12, 0, retaddr); + cpu_stw_data_ra(env, ptr + 6, env->fpip, retaddr); + cpu_stw_data_ra(env, ptr + 8, env->fpcs, retaddr); + cpu_stw_data_ra(env, ptr + 10, env->fpdp, retaddr); + cpu_stw_data_ra(env, ptr + 12, env->fpds, retaddr); } } diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index a43e577019..8520d5a1e2 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -5920,6 +5920,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) /* floats */ case 0xd8 ... 0xdf: { + bool update_fip = true; + if (s->flags & (HF_EM_MASK | HF_TS_MASK)) { /* if CR0.EM or CR0.TS are set, generate an FPU exception */ /* XXX: what to do if illegal op ? */ @@ -5932,7 +5934,14 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) op = ((b & 7) << 3) | ((modrm >> 3) & 7); if (mod != 3) { /* memory op */ - gen_lea_modrm(env, s, modrm); + AddressParts a = gen_lea_modrm_0(env, s, modrm); + TCGv ea = gen_lea_modrm_1(s, a); + TCGv last_addr = tcg_temp_new(); + bool update_fdp = true; + + tcg_gen_mov_tl(last_addr, ea); + gen_lea_v_seg(s, s->aflag, ea, a.def_seg, s->override); + switch (op) { case 0x00 ... 0x07: /* fxxxs */ case 0x10 ... 0x17: /* fixxxl */ @@ -6060,20 +6069,24 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x0c: /* fldenv mem */ gen_helper_fldenv(cpu_env, s->A0, tcg_const_i32(dflag - 1)); + update_fip = update_fdp = false; break; case 0x0d: /* fldcw mem */ tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUW); gen_helper_fldcw(cpu_env, s->tmp2_i32); + update_fip = update_fdp = false; break; case 0x0e: /* fnstenv mem */ gen_helper_fstenv(cpu_env, s->A0, tcg_const_i32(dflag - 1)); + update_fip = update_fdp = false; break; case 0x0f: /* fnstcw mem */ gen_helper_fnstcw(s->tmp2_i32, cpu_env); tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUW); + update_fip = update_fdp = false; break; case 0x1d: /* fldt mem */ gen_helper_fldt_ST0(cpu_env, s->A0); @@ -6085,15 +6098,18 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x2c: /* frstor mem */ gen_helper_frstor(cpu_env, s->A0, tcg_const_i32(dflag - 1)); + update_fip = update_fdp = false; break; case 0x2e: /* fnsave mem */ gen_helper_fsave(cpu_env, s->A0, tcg_const_i32(dflag - 1)); + update_fip = update_fdp = false; break; case 0x2f: /* fnstsw mem */ gen_helper_fnstsw(s->tmp2_i32, cpu_env); tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0, s->mem_index, MO_LEUW); + update_fip = update_fdp = false; break; case 0x3c: /* fbld */ gen_helper_fbld_ST0(cpu_env, s->A0); @@ -6116,6 +6132,19 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) default: goto unknown_op; } + + if (update_fdp) { + int last_seg = s->override >= 0 ? s->override : a.def_seg; + + tcg_gen_ld_i32(s->tmp2_i32, cpu_env, + offsetof(CPUX86State, + segs[last_seg].selector)); + tcg_gen_st16_i32(s->tmp2_i32, cpu_env, + offsetof(CPUX86State, fpds)); + tcg_gen_st_tl(last_addr, cpu_env, + offsetof(CPUX86State, fpdp)); + } + tcg_temp_free(last_addr); } else { /* register float ops */ opreg = rm; @@ -6136,6 +6165,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0: /* fnop */ /* check exceptions (FreeBSD FPU probe) */ gen_helper_fwait(cpu_env); + update_fip = false; break; default: goto unknown_op; @@ -6305,9 +6335,11 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 2: /* fclex */ gen_helper_fclex(cpu_env); + update_fip = false; break; case 3: /* fninit */ gen_helper_fninit(cpu_env); + update_fip = false; break; case 4: /* fsetpm (287 only, just do nop here) */ break; @@ -6428,6 +6460,15 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto unknown_op; } } + + if (update_fip) { + tcg_gen_ld_i32(s->tmp2_i32, cpu_env, + offsetof(CPUX86State, segs[R_CS].selector)); + tcg_gen_st16_i32(s->tmp2_i32, cpu_env, + offsetof(CPUX86State, fpcs)); + tcg_gen_st_tl(tcg_constant_tl(pc_start - s->cs_base), + cpu_env, offsetof(CPUX86State, fpip)); + } } break; /************************/ From patchwork Tue Jul 13 16:42:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 474690 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp4138680jao; Tue, 13 Jul 2021 09:42:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwYWTiMLeVg+sinTykyra9rxL+MYqd6m2Wfi1PPna1Idez8Hx7MNIjg8DGyfXi2ZL1gSF9S X-Received: by 2002:a1c:48a:: with SMTP id 132mr263984wme.157.1626194559216; Tue, 13 Jul 2021 09:42:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626194559; cv=none; d=google.com; s=arc-20160816; b=A5+iJ79itSFnMPHCEYNVhePjFrewLgkJjdZaVhMB8T7XUTSXNsyXF4unrBv1gMaaBu rVdEnXwfZ2B1oOg9oghOpokVlwUjFpWxUBbP6mGrEj6XbCX6ZEHtCzSxg54MHZ2SmVgS PWUGTV+W8teQPgeHKWxkISjNXtDDA3J5/t5jj4YQKH4ETrNLDnWyCECcSFbFkTHglmfT 8/5YEdH8SQzhUAVR99TKhcvRQeholSfXMvfY1156hoE96kiclVnoNFHty2zF+hpfT78x DEma6ee54JjADgoIneKSRrEx7bjp0mvamrdEvL7CXnwQToONzlTmYQxfDd+JZ9+Vibzw Et0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fkcNcRIjqT1hq788GGq0h2qjDz4eiWFcxGo3OTTzr8A=; b=kYQN68Zo/oGnZllujm2GnfOpmiTs6Xu6D0D9suEDAmPyDcyk1gE095godJ4BEnUMGt 5AybbOHrSydrBGsH/0QHwDy8Ac7EqZxKS5w4q6Gp6AVtq8BaqS/ONddZqAO3sc0UveS6 it8dIevxAdqoRHCXYe2727MSw5JAAlUKk2krOQT1oDceFbjg+fPrg/0WU/Uuo5IKukor zjTwADWmFKXOPxWGv1ZNBCM+3t4tzUR1t8wRVdY9lGAXfx2E0rxib2XgNh6AyxtswRxu CnqjqLSYaLpUGdX4N4AIP/K4RP4M8TYldh388LWJSfRsGMoaAjm8PIk5a0PRmA9t/DM1 D7ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vJiFP139; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Use tcg_constant_i64 while we're at it. Signed-off-by: Richard Henderson --- target/alpha/translate.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) -- 2.25.1 diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 833d3baa7b..b439b57a66 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -1084,15 +1084,11 @@ static void gen_msk_l(DisasContext *ctx, TCGv vc, TCGv va, int rb, bool islit, static void gen_rx(DisasContext *ctx, int ra, int set) { - TCGv tmp; - if (ra != 31) { ld_flag_byte(ctx->ir[ra], ENV_FLAG_RX_SHIFT); } - tmp = tcg_const_i64(set); - st_flag_byte(ctx->ir[ra], ENV_FLAG_RX_SHIFT); - tcg_temp_free(tmp); + st_flag_byte(tcg_constant_i64(set), ENV_FLAG_RX_SHIFT); } static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode) From patchwork Tue Jul 13 16:42:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 474699 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp4144587jao; Tue, 13 Jul 2021 09:49:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz0cU0KrMQlm0EBSK9JyNV1w5ETkcJyf3cleLC+NsQl26ZZRDC+UkAAANkGfAoY69k/LTso X-Received: by 2002:adf:eec5:: with SMTP id a5mr6805775wrp.317.1626194981115; Tue, 13 Jul 2021 09:49:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626194981; cv=none; d=google.com; s=arc-20160816; b=RkfN86OXop+LH7hfu5FW1Cb7nSCy3dp54bohcigxIefMO71ENXq0CZlpmU5Dxyv4Gc goPU24NBk8Dp9HeIFxFcNqXxCVugF49RNLRlNC8gcdd/+Qho2ad8AaPcjOXnWYrWyPaO 0NjZUIbAm3p/6LYmghQEvdYDSWRrNtp/DzxkCBZHkAqhZZlHv4ga4+Aw+z0OVCikAgat U1b5uHrHbED1pBIVBlRI85nbcSeAeYlOe2KnUg2ziTvMSwaGDI5e5D1JxfPlJooX3och LSu0XwDlUDBdHqsmzxR3kx56rj/O29W0qB1XE8kLu9hZt9AE0sJbWEG1zi8OtHSXzWFu e82Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=TQm8Lq1Aaz3TmiNuToYyV4nWNe9sSLlo6H/vCDNuu6I=; b=Si6P0zqhFaNSfAMdBmS/7d8q2MN9t1mzYCB4QEXteXJnwO5tjskU4DyCqd6IMI3ewC Dn/Qk/05OQba52hgVi5qBOzdI8ZyQloGxmxdnonwK/Z351lUtzcZK1U8Ejjhp5yrVWaH TVK/aVYcIw6rJ3QPRVwwR7D0nHLGzsu8LCewP5LxOkO2UQ0iuw3YAuqp65t2MiYCMfc/ MOqYR1I8DKimwRpUh3U9QKta6FsFQC9dKbzm2gZIG5RFCIWRkb29xPjcorsemK1HnNCM EmMknNztJM5dlFEoX90p9y+7J3PpGlMFvY73FR8SVs56RbmdkJwxSaPOuSwlIP4YrctW ryow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rP73IFhb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n1si23411369wmn.194.2021.07.13.09.49.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Jul 2021 09:49:41 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rP73IFhb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47036 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m3LbI-0005QJ-47 for patch@linaro.org; Tue, 13 Jul 2021 12:49:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41114) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m3LUB-0006rJ-NL for qemu-devel@nongnu.org; Tue, 13 Jul 2021 12:42:19 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:43830) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m3LU9-0005ew-5H for qemu-devel@nongnu.org; Tue, 13 Jul 2021 12:42:19 -0400 Received: by mail-pj1-x102e.google.com with SMTP id x21-20020a17090aa395b029016e25313bfcso2497066pjp.2 for ; Tue, 13 Jul 2021 09:42:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=TQm8Lq1Aaz3TmiNuToYyV4nWNe9sSLlo6H/vCDNuu6I=; b=rP73IFhbEnPMGZLtDwUK6Ki5zio/OaNH669Z03EzVn19iN2pjLGZjYyZw5O02EXDCa N65DfgB6b5Lmn6mXVr1XZDCJ/D39VouKFzr9jMvKf3u2fB/dYr2QOXFCV5/rNXpFfIey hbJerPezhBxApgI6NIkYOxbbFdtW40uSNZZFmTXnH7PSu8Yy9kRF83Ef5/ANH2gVV6h6 6B0jaImfd8ReWLOVzXXB43nxBjUgn4gMR9oklt+nnbOV+y2K3kr+SjuczafE4dMxhsCt kF6Yx6dGwUYztiKBiGXTi4njbQtwT03iL7//KvgtOSOnVLigvzYhRxQp6v78WoU5B8FN 7wHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TQm8Lq1Aaz3TmiNuToYyV4nWNe9sSLlo6H/vCDNuu6I=; b=JwYAHf1rWrNwmYusNn+698eOgEnaEF1l+ZKku0EpurOg7MkGlatwdel0f+TvPhpHtd qLxT3XPEeYCCP9BWuMOevKTqeX21O0z14bZ6R5qWRJ5gQnFph+zBn2jp1mdzZxbxGu2S wp0f+uRSecVy+88TtuMbDbU979Iffo9oH9heX8t/YjcQhiDDypaE1BtTfJcTEZgNQOBm +/XSdjfaEI9mkpSOp8tQv1gTYmGX8qdnaEUgBiwwqBBgFRmFlg11Ux7zRBmZWnfoUQ4O Lpcytv2YJsNCgw2TrOUGN7mhodoaghTKowCcojQ6HUY0YsLIABzIBj8EMgPCfYRISY2Z XKnw== X-Gm-Message-State: AOAM533tthJ3J0W4OMs5kX7cXkEOeWVrJGxNcnlJox9DzO7oh7pAt8Dv S8Csj5O3S+LyivIW6Dzkc5n27dCiUClEYQ== X-Received: by 2002:a17:90a:4884:: with SMTP id b4mr206230pjh.173.1626194535958; Tue, 13 Jul 2021 09:42:15 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id z13sm4947865pfn.94.2021.07.13.09.42.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jul 2021 09:42:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 06/14] target/alpha: Use dest_sink for HW_RET temporary Date: Tue, 13 Jul 2021 09:42:03 -0700 Message-Id: <20210713164211.1520109-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210713164211.1520109-1-richard.henderson@linaro.org> References: <20210713164211.1520109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This temp is automatically freed, just like ctx->lit. But we're about to remove ctx->lit, so use sink instead. Signed-off-by: Richard Henderson --- target/alpha/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 diff --git a/target/alpha/translate.c b/target/alpha/translate.c index b439b57a66..64c4865dda 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2717,7 +2717,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn) /* Pre-EV6 CPUs interpreted this as HW_REI, loading the return address from EXC_ADDR. This turns out to be useful for our emulation PALcode, so continue to accept it. */ - ctx->lit = vb = tcg_temp_new(); + vb = dest_sink(ctx); tcg_gen_ld_i64(vb, cpu_env, offsetof(CPUAlphaState, exc_addr)); } else { vb = load_gpr(ctx, rb); From patchwork Tue Jul 13 16:42:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 474697 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp4142629jao; Tue, 13 Jul 2021 09:47:19 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxoETzXLXFFHn3hL7K0ryBpcT4j/2aAadzZKuhAzedSB8iVvnYY+OECv/C6fMeuUbPX8gCi X-Received: by 2002:a7b:cd9a:: with SMTP id y26mr337086wmj.76.1626194839774; Tue, 13 Jul 2021 09:47:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626194839; cv=none; d=google.com; s=arc-20160816; b=RobQeTQ6i2beQkPvYstOSGOSnVswItDDcg7rnw5dLB5NdUt6L0EiL6nycsq+HtW81z 80ZX9yL63BVjT0uOLicKCYKupsVzcGuJhACgD3ubXul7SxZW2YWuMiP/Fr8mQyAdbeC6 USPNt0oyLj992Jg/YG5OZFqA41rFZxb+B35ZbC81GSLwXsQ5dDKhdb3lODBfDsr9A7rd KrdmIapExmTRohX49Wrnz/69JYWD+5mEEzRYPHVU5GI+4GciDYKZx/ktkeKCPAXdtRk9 /sLuLKB7Qu4yVxDwBcaRicprY7ORFDojTHhvi9io7/mva5iPKR8SkHmdinBisTZqCNgF k77g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=UXF13QTS5AJHAq5VT/9hnMvu0uSbL+4zu4FScleCGMI=; b=gr9LKDqLuhMP4E0oIJ3EHgLylGicE7QfDV6yLknDRZpMZSh0jtE7FT+h/yNmwDmx1w KMK49SIx4Y1LRbJvTCCYEQUtvh9zg0Hx9rZfOCKtB4GF8BpRWj7Ma1BsQi7HpxTRMGFU BTMLvXOCcmxwsJnwCQEAEssKVu88HQiqDoTm6vNpSsZzD0OqGKlLCOCffdkzHma40uT8 VkJ6miWd+Wxkrumd0yB0eKFHfAfQ9C7Co0j0h2lDOvvBULPzgm4smjMN6NC5QjxIM5fe U1C0Feq+F/y84KFEOeFfro0757G2iZD/+bhOPTgy5tx2WJ52PKyvZOkY6q4bY1hYRT/E BYdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=auIbAaMZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u17si24629090wmq.148.2021.07.13.09.47.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Jul 2021 09:47:19 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=auIbAaMZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40846 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m3LZ0-0001DO-RQ for patch@linaro.org; Tue, 13 Jul 2021 12:47:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41160) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m3LUD-0006tR-7R for qemu-devel@nongnu.org; Tue, 13 Jul 2021 12:42:21 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:46920) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m3LU9-0005fH-MX for qemu-devel@nongnu.org; Tue, 13 Jul 2021 12:42:20 -0400 Received: by mail-pj1-x102d.google.com with SMTP id b5-20020a17090a9905b029016fc06f6c5bso2490232pjp.5 for ; Tue, 13 Jul 2021 09:42:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UXF13QTS5AJHAq5VT/9hnMvu0uSbL+4zu4FScleCGMI=; b=auIbAaMZJ8l3mhaJmIb7KsrJTMttOAlcM/4UPIF2HR4ynwPWgZdc+IsL2Nbs8aDdia g2ARGztMRVTyPPJa/EHOcaovZafy7yNnJIWGo+xwlLDYKGidzjVu4UjzX7KQ/SFSVBqN HGqLv9w83E+yUyuIUuTkzoKVbga/0cFV4ORL2VIHKWPNUuKbI/ouVIO6XCDKteINdf1G 1HBhmZwh6fg2Hmti2zRSODbtc8iOFk391v9UlPkulsXZ1DltlTDOOE/KPSZZxRwKQrT8 ugN9TGBlfR2B7vRf5fhMyZ0JrLVa/V8reS9sRQMnwr9sTuxfcVp+hiDaEnsmVxxvpukz c1zA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UXF13QTS5AJHAq5VT/9hnMvu0uSbL+4zu4FScleCGMI=; b=hzsKOCQr5S49zGXUNXTzb86u7f7187xZQfV+3+R2uCbB4PNI/Ik2EZ/SDWvnMcRIOh JCIJGaWI3hOXQenj2Ua11XuYc9oMhb+HwGsZtA1QvWZb0HoyN4zkccGkt7iL/xyrO6Mq g3qvfnXIns9jr/CAOGxrB1aTc612O8X4Y7HtCrQKce2pjLZSdToBfyFvhuZQ22/+dk2H edvie6xRDFPEXrNozEujYj1YaYLb4xSMtAsBkXAnqM6VQN5Vf0ZmnN58w92WhWDctDrr UpQwg64u9UF6g6Ji8Hwywe0w8rYpCDEqAuVEH4xNpn6skSdD2XVWEial5Fj62O23yDa7 +2Xg== X-Gm-Message-State: AOAM532FQiL02Q61nfbwOBt2ORIM49uuoxgRgG0YnnRMVhenJWRL8NJy e1qrgfAnBgyo6Ry2puK0+wdlkczhs+x6eg== X-Received: by 2002:a17:90a:1704:: with SMTP id z4mr207727pjd.213.1626194536418; Tue, 13 Jul 2021 09:42:16 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id z13sm4947865pfn.94.2021.07.13.09.42.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jul 2021 09:42:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 07/14] target/alpha: Use tcg_constant_i64 for zero and lit Date: Tue, 13 Jul 2021 09:42:04 -0700 Message-Id: <20210713164211.1520109-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210713164211.1520109-1-richard.henderson@linaro.org> References: <20210713164211.1520109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These constant temps do not need to be freed, and therefore need less bookkeeping from tcg producers. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/alpha/translate.c | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) -- 2.25.1 diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 64c4865dda..58c0e08c0c 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -66,8 +66,6 @@ struct DisasContext { /* Temporaries for $31 and $f31 as source and destination. */ TCGv zero; TCGv sink; - /* Temporary for immediate constants. */ - TCGv lit; }; /* Target-specific return values from translate_one, indicating the @@ -157,7 +155,7 @@ void alpha_translate_init(void) static TCGv load_zero(DisasContext *ctx) { if (!ctx->zero) { - ctx->zero = tcg_const_i64(0); + ctx->zero = tcg_constant_i64(0); } return ctx->zero; } @@ -177,14 +175,6 @@ static void free_context_temps(DisasContext *ctx) tcg_temp_free(ctx->sink); ctx->sink = NULL; } - if (ctx->zero) { - tcg_temp_free(ctx->zero); - ctx->zero = NULL; - } - if (ctx->lit) { - tcg_temp_free(ctx->lit); - ctx->lit = NULL; - } } static TCGv load_gpr(DisasContext *ctx, unsigned reg) @@ -200,8 +190,7 @@ static TCGv load_gpr_lit(DisasContext *ctx, unsigned reg, uint8_t lit, bool islit) { if (islit) { - ctx->lit = tcg_const_i64(lit); - return ctx->lit; + return tcg_constant_i64(lit); } else if (likely(reg < 31)) { return ctx->ir[reg]; } else { @@ -2992,7 +2981,6 @@ static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) ctx->zero = NULL; ctx->sink = NULL; - ctx->lit = NULL; /* Bound the number of insns to execute to those left on the page. */ bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; From patchwork Tue Jul 13 16:42:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 474703 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp4146670jao; Tue, 13 Jul 2021 09:52:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx1LMPohdxLuuk9jBzCgS6PEnmWdbf98VxnfLcsMEy1wVQ1Lb2El6tubY9nvorGjfpT4lK9 X-Received: by 2002:a67:f359:: with SMTP id p25mr7573960vsm.37.1626195127514; Tue, 13 Jul 2021 09:52:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626195127; cv=none; d=google.com; s=arc-20160816; b=JNyEkHu9vAtH2ELRgoEFbxaqiVrB8QlkrUl+HPsb/AvZ6++6A6tbSMp8vxiBanQHaR 7StVZAaxr6UiSSv1oTxTfymk81/1G/wo9ihIENJogc/Jl+NbPVISSLsmgyUCjaO6FL4p fY7mQCYUrkHbMEuwG5iCaiR57F97w6E9Kfq66C/OfJ0EydnOIKBUiLCnd2zC9V9OiTWa 2dM9NoSbOlDDV2eCJ/cIIcrS64I1AR3XweamoqctaDLSJfwEoRI3OqhO5AsHKo6I6vQX q+YsrjbIXNcX3jFZbv4UUzYx4I+N8s2WGgMvgWcULs7bgSV5LDMF3YrIU8iWffnNIjWp P1oA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=KuDDoLNIk68fDtCCr2zu8W55ZPfrf4mbWdcj3lhD6LA=; b=nVQRaq6xAjL0YTDcrHCkTW+v0eQNI1lYmuaU5lLOf/UAjmeEmU/DNa+bC9pfZ4+kxx ZDMHTY4kOmIVif1NIDETJOTDeVsFPCHgMEahF6FNPRUu/PkYk1X/1wTtyTjuR32eiBP0 3dVi24t33hKvrblWznjPAnaAgjgJi4SN8scBNu2E94YNvC2nJvRGk115nxQT0oJPuQ+8 sqds9gXijvPC2icezrUVznyHaxx6zuX+uDKdfIuOD66EAVKRLCSu/Qa1YKXLOLOpLEFV r8hVlnyO1KPrkK+o52oSjIXb2lOs0m4WVhrJ7g9isYSgwnoOp1/R7VFUmpeGZ+NrWi3z YQjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=stMahCLE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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These uses are all local, with the allocate and free close together. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/alpha/translate.c | 46 ++++++++++++---------------------------- 1 file changed, 14 insertions(+), 32 deletions(-) -- 2.25.1 diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 58c0e08c0c..103c6326a2 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -250,11 +250,9 @@ static void gen_excp_1(int exception, int error_code) { TCGv_i32 tmp1, tmp2; - tmp1 = tcg_const_i32(exception); - tmp2 = tcg_const_i32(error_code); + tmp1 = tcg_constant_i32(exception); + tmp2 = tcg_constant_i32(error_code); gen_helper_excp(cpu_env, tmp1, tmp2); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp1); } static DisasJumpType gen_excp(DisasContext *ctx, int exception, int error_code) @@ -474,15 +472,11 @@ static DisasJumpType gen_bcond_internal(DisasContext *ctx, TCGCond cond, return DISAS_NORETURN; } else { - TCGv_i64 z = tcg_const_i64(0); - TCGv_i64 d = tcg_const_i64(dest); - TCGv_i64 p = tcg_const_i64(ctx->base.pc_next); + TCGv_i64 z = load_zero(ctx); + TCGv_i64 d = tcg_constant_i64(dest); + TCGv_i64 p = tcg_constant_i64(ctx->base.pc_next); tcg_gen_movcond_i64(cond, cpu_pc, cmp, z, d, p); - - tcg_temp_free_i64(z); - tcg_temp_free_i64(d); - tcg_temp_free_i64(p); return DISAS_PC_UPDATED; } } @@ -684,22 +678,19 @@ static void gen_fp_exc_raise(int rc, int fn11) if (!(fn11 & QUAL_I)) { ignore |= FPCR_INE; } - ign = tcg_const_i32(ignore); + ign = tcg_constant_i32(ignore); /* ??? Pass in the regno of the destination so that the helper can set EXC_MASK, which contains a bitmask of destination registers that have caused arithmetic traps. A simple userspace emulation does not require this. We do need it for a guest kernel's entArith, or if we were to do something clever with imprecise exceptions. */ - reg = tcg_const_i32(rc + 32); + reg = tcg_constant_i32(rc + 32); if (fn11 & QUAL_S) { gen_helper_fp_exc_raise_s(cpu_env, ign, reg); } else { gen_helper_fp_exc_raise(cpu_env, ign, reg); } - - tcg_temp_free_i32(reg); - tcg_temp_free_i32(ign); } static void gen_cvtlq(TCGv vc, TCGv vb) @@ -792,7 +783,7 @@ IEEE_INTCVT(cvtqt) static void gen_cpy_mask(TCGv vc, TCGv va, TCGv vb, bool inv_a, uint64_t mask) { - TCGv vmask = tcg_const_i64(mask); + TCGv vmask = tcg_constant_i64(mask); TCGv tmp = tcg_temp_new_i64(); if (inv_a) { @@ -804,7 +795,6 @@ static void gen_cpy_mask(TCGv vc, TCGv va, TCGv vb, bool inv_a, uint64_t mask) tcg_gen_andc_i64(vc, vb, vmask); tcg_gen_or_i64(vc, vc, tmp); - tcg_temp_free(vmask); tcg_temp_free(tmp); } @@ -1178,12 +1168,9 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode) case 0x3E: /* WTINT */ - { - TCGv_i32 tmp = tcg_const_i32(1); - tcg_gen_st_i32(tmp, cpu_env, -offsetof(AlphaCPU, env) + - offsetof(CPUState, halted)); - tcg_temp_free_i32(tmp); - } + tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, + -offsetof(AlphaCPU, env) + + offsetof(CPUState, halted)); tcg_gen_movi_i64(ctx->ir[IR_V0], 0); return gen_excp(ctx, EXCP_HALTED, 0); @@ -1334,12 +1321,8 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv vb, int regno) case 253: /* WAIT */ - { - TCGv_i32 tmp = tcg_const_i32(1); - tcg_gen_st_i32(tmp, cpu_env, -offsetof(AlphaCPU, env) + - offsetof(CPUState, halted)); - tcg_temp_free_i32(tmp); - } + tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, + -offsetof(AlphaCPU, env) + offsetof(CPUState, halted)); return gen_excp(ctx, EXCP_HALTED, 0); case 252: @@ -2712,9 +2695,8 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn) vb = load_gpr(ctx, rb); } tcg_gen_movi_i64(cpu_lock_addr, -1); + st_flag_byte(load_zero(ctx), ENV_FLAG_RX_SHIFT); tmp = tcg_temp_new(); - tcg_gen_movi_i64(tmp, 0); - st_flag_byte(tmp, ENV_FLAG_RX_SHIFT); tcg_gen_andi_i64(tmp, vb, 1); st_flag_byte(tmp, ENV_FLAG_PAL_SHIFT); tcg_temp_free(tmp); From patchwork Tue Jul 13 16:42:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 474698 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp4142972jao; Tue, 13 Jul 2021 09:47:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz2GYxXaN4vO0k16KCaXPnqbwy/k37sYcIxspVd25GhC1vwrE7O6FqueGrkXhme5DUtcymy X-Received: by 2002:a05:600c:a45:: with SMTP id c5mr298863wmq.153.1626194861096; Tue, 13 Jul 2021 09:47:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626194861; cv=none; d=google.com; s=arc-20160816; b=s2ekESFLCeDnhx0GGuj+LNW3egG9EcCx0l1xcxTWovXvqXasof8X35czJgxwcXgo9A 3FPIyVpec/BLqubU+FWJdEq/I7P91RSutkIA6+S7HocJ6Abw5GpFzRNCTvMM9vgGeE4T qJ5FsdLdjpEjNOn0BXmW54alylo344q6Dq2a2JczmhPqhwKJOxeO+x+qrKkKKCYGKPqh fPM1LlGa0J9slKZOVx0NPSmTOxtATqgJyQDGdZxsgAMTAlhgGTOyH5FC7AzuomG4YDau 8p/EixftIBXsbg0HWWLd+XZbbsf7FB+cx0uL9mpA9+Iy7JvBwYQZOP3CMTtzmsewc0LT MFCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9YUKtvJ3DiCKvRhTAIKBYXvq8J1GX8aw6iywB1LJsnI=; b=vfPPYMkC5guIIiTK4x0gTx7c7kQTw9BNzKICY3T6Ecj70Fqsctww7YfJ6V8lUm91+U 5wcVFyvclb0mxzYsD4JrCw0n1FH7zMpI81nohBQuhzWGWV1nZgUpktQtiVXVneJxyPqV UsnFubhTwMj6+Xhu21+tGQ0pIaYlB9nqhoEfaDY681oicYUDPVQO3OnlFJv6bNItHsJH /hZWQCg8/dQayqrAgqkazGZSIxnIvweJQIqGtccFYqcJ7hg/+8xJZuLUm9woteIv/lh0 63DRjyenMeOdLzzs8Af57Fazzy6AY0Hpuza8wy7ZcVnvmpUyNGyMcWBWLLn1j3vpz2GY bXng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=l0rIJ6aR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Stafford Horne Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 42 ++++++++----------------------------- 1 file changed, 9 insertions(+), 33 deletions(-) -- 2.25.1 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 37c3e3e0a3..1e3b019c59 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -129,9 +129,7 @@ void openrisc_translate_init(void) static void gen_exception(DisasContext *dc, unsigned int excp) { - TCGv_i32 tmp = tcg_const_i32(excp); - gen_helper_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); + gen_helper_exception(cpu_env, tcg_constant_i32(excp)); } static void gen_illegal_exception(DisasContext *dc) @@ -538,13 +536,11 @@ static bool trans_l_extbz(DisasContext *dc, arg_da *a) static bool trans_l_cmov(DisasContext *dc, arg_dab *a) { - TCGv zero; + TCGv zero = tcg_constant_tl(0); check_r0_write(dc, a->d); - zero = tcg_const_tl(0); tcg_gen_movcond_tl(TCG_COND_NE, cpu_R(dc, a->d), cpu_sr_f, zero, cpu_R(dc, a->a), cpu_R(dc, a->b)); - tcg_temp_free(zero); return true; } @@ -632,15 +628,11 @@ static bool trans_l_jal(DisasContext *dc, arg_l_jal *a) static void do_bf(DisasContext *dc, arg_l_bf *a, TCGCond cond) { target_ulong tmp_pc = dc->base.pc_next + a->n * 4; - TCGv t_next = tcg_const_tl(dc->base.pc_next + 8); - TCGv t_true = tcg_const_tl(tmp_pc); - TCGv t_zero = tcg_const_tl(0); + TCGv t_next = tcg_constant_tl(dc->base.pc_next + 8); + TCGv t_true = tcg_constant_tl(tmp_pc); + TCGv t_zero = tcg_constant_tl(0); tcg_gen_movcond_tl(cond, jmp_pc, cpu_sr_f, t_zero, t_true, t_next); - - tcg_temp_free(t_next); - tcg_temp_free(t_true); - tcg_temp_free(t_zero); dc->delayed_branch = 2; } @@ -813,44 +805,28 @@ static bool trans_l_adrp(DisasContext *dc, arg_l_adrp *a) static bool trans_l_addi(DisasContext *dc, arg_rri *a) { - TCGv t0; - check_r0_write(dc, a->d); - t0 = tcg_const_tl(a->i); - gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), t0); - tcg_temp_free(t0); + gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), tcg_constant_tl(a->i)); return true; } static bool trans_l_addic(DisasContext *dc, arg_rri *a) { - TCGv t0; - check_r0_write(dc, a->d); - t0 = tcg_const_tl(a->i); - gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), t0); - tcg_temp_free(t0); + gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), tcg_constant_tl(a->i)); return true; } static bool trans_l_muli(DisasContext *dc, arg_rri *a) { - TCGv t0; - check_r0_write(dc, a->d); - t0 = tcg_const_tl(a->i); - gen_mul(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), t0); - tcg_temp_free(t0); + gen_mul(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), tcg_constant_tl(a->i)); return true; } static bool trans_l_maci(DisasContext *dc, arg_l_maci *a) { - TCGv t0; - - t0 = tcg_const_tl(a->i); - gen_mac(dc, cpu_R(dc, a->a), t0); - tcg_temp_free(t0); + gen_mac(dc, cpu_R(dc, a->a), tcg_constant_tl(a->i)); return true; } From patchwork Tue Jul 13 16:42:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 474693 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp4140224jao; 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[209.51.188.17]) by mx.google.com with ESMTPS id n5si7723555wmi.121.2021.07.13.09.44.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Jul 2021 09:44:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=q9WkDpCE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60850 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m3LWP-00046u-P8 for patch@linaro.org; Tue, 13 Jul 2021 12:44:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41190) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m3LUE-0006u5-E0 for qemu-devel@nongnu.org; Tue, 13 Jul 2021 12:42:22 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:37825) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m3LUB-0005gO-Ce for qemu-devel@nongnu.org; Tue, 13 Jul 2021 12:42:22 -0400 Received: by mail-pj1-x1030.google.com with SMTP id o3-20020a17090a6783b0290173ce472b8aso1803342pjj.2 for ; Tue, 13 Jul 2021 09:42:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9Ox+DD1VyGDD2SWlngk4YcouD6dR00XZiALJU9OxjL4=; b=q9WkDpCEdlMjMvspJD322CtxcGko6rp1HFq6WoZv0+ZaFhh6CD3wzql3YcyMykPwpI S2k6pD6E9AGmQCHj4BTYq36mL/zIP+EtsiBxtIe5p76MQ5KuF0o+1u8souy8GSapwDCe PlWah6aQNH/4i4RP1eRS/vkVA4DDWvy675risDCpn/xwtNOgJXV5pn/+NJtDiQhJsuXG 5oBihygk9SFdb/FwIorcqWPLCjZ2RLeu3EODCq0fCltDH/wBPXxlTiqhV0qLp+j/pZO+ t/kPqyfAEl0jK7r7jLdh5AfIVlojlfQDXNT1Xzaq4kIxFNGcygZDUPb4wwdy/U0Ij5oY rSYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9Ox+DD1VyGDD2SWlngk4YcouD6dR00XZiALJU9OxjL4=; b=i27l/AQZRWSYe55XLxRgosYMf0uxkI4jX4jKCLBp4qgWFmKiB6Zh3YzVKT51vlKNaZ IuYhFKEAoUgeN4wx7Uwb83/fa432I9KQoxcTX188AaB1JuG9xqM/A/GErhZc6fcSPLhB upr24z0m4Xq2CNKS7wM1rVoqmLWi4SIzQaw9fcmvd0CGflB98vBOh2M4IoFORTVDgVrH dHYsTyAVZnIeeyRcnMGFqNWh56HVyURTaWsyNFaHQSpzFamaFiYuwy5KfRvW+mvvL/oD bQ4paSh9l0VvOzbkSvcK//tGANs8bNZ3MjRf58ZYMOAfPUdXlgfnxtrkc2MEvW5wFCy3 Ae0Q== X-Gm-Message-State: AOAM532CgHPnF4LuIddS0Ix5ygFBHIpEIaOMjby9CfnHJeUFMF0nAl93 c5tou0y/m/MF6CTXAQyeZ224QYd7Z/CIgA== X-Received: by 2002:a17:90a:7bc3:: with SMTP id d3mr214428pjl.145.1626194538162; Tue, 13 Jul 2021 09:42:18 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id z13sm4947865pfn.94.2021.07.13.09.42.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jul 2021 09:42:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 10/14] target/openrisc: Use tcg_constant_tl for dc->R0 Date: Tue, 13 Jul 2021 09:42:07 -0700 Message-Id: <20210713164211.1520109-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210713164211.1520109-1-richard.henderson@linaro.org> References: <20210713164211.1520109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The temp allocated for tcg_const_tl is auto-freed at branches, but pure constants are not. So we can remove the extra hoop jumping in trans_l_swa. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) -- 2.25.1 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 1e3b019c59..2db529b7de 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -732,12 +732,6 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a) ea = tcg_temp_new(); tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i); - /* For TB_FLAGS_R0_0, the branch below invalidates the temporary assigned - to cpu_regs[0]. Since l.swa is quite often immediately followed by a - branch, don't bother reallocating; finish the TB using the "real" R0. - This also takes care of RB input across the branch. */ - dc->R0 = cpu_regs[0]; - lab_fail = gen_new_label(); lab_done = gen_new_label(); tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_lock_addr, lab_fail); @@ -745,7 +739,7 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a) val = tcg_temp_new(); tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value, - cpu_regs[a->b], dc->mem_idx, MO_TEUL); + cpu_R(dc, a->b), dc->mem_idx, MO_TEUL); tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value); tcg_temp_free(val); @@ -1601,7 +1595,7 @@ static void openrisc_tr_tb_start(DisasContextBase *db, CPUState *cs) /* Allow the TCG optimizer to see that R0 == 0, when it's true, which is the common case. */ if (dc->tb_flags & TB_FLAGS_R0_0) { - dc->R0 = tcg_const_tl(0); + dc->R0 = tcg_constant_tl(0); } else { dc->R0 = cpu_regs[0]; } From patchwork Tue Jul 13 16:42:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 474701 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp4145670jao; Tue, 13 Jul 2021 09:50:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwAhlMRs6TzO0PPLpzTrUZApK1MmLFT3UByr9maNceSSJYZdc7cF/n2pug8UWQFK5WUivGq X-Received: by 2002:adf:f085:: with SMTP id n5mr7112053wro.148.1626195050550; Tue, 13 Jul 2021 09:50:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626195050; cv=none; d=google.com; s=arc-20160816; b=a4S9V9Pq4ziNv6FnHG32bmWjH2+Jk3hbhvFqU286PN2NOfpULP6eojWq170jy6Xzum Uc30V77ThRZyc/r215i8a3i+oUm3qkqwKkqa7OAMJwmEqRY+MK7qx/ocEZKe+55asr9S RA7cbvabqcsP58djIMWQAjvrm5UngcfXQmKEYAGun8ZlNR4PplyC09TStgzvTs9JBIhf kxCrlve6lEmrowLFsjT1vzON6OhMoUVy5N5UAX5zMzFS9a3VnACp2hfQmcLpmK9LHUnm 6/1OKExRDBzVYKmziaNfdORxjRChmx/e4K2DUdbkSdsKtqTwjfHwXYdTXCufGMOLNrFG aFBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=l5PqM6iGSweKZSS09TGPy9jM/MAv4I7LtiO9ZGckioo=; b=sArf/udw5rOXHtK+mjNS7qjqUR17cWE06NonD44H3eUzgJUVSE2uqdYERZKxsSQn76 UJpxrdr/gUREUlCsI7zy9p3xUF1oHW5mWg+hY5BrP1Ux3FiDxPtJBhLekudBoxmxVm08 pg4ADCw1/WyHomRfxA1p3A3UKwige/LZYDqVTFjZVLLYryyQu6bBOpxjg2+K+QDAtnG7 5lD8+nRRs4vOE5fsHnBAB+S9soSOHNELqK/+GJzWdxLbMUkNL55nRSJOASe2lPMHhreQ qMbrp6VMtNXRhhxNmdfNXIR8/vYxnVRWEzAsFBgn76w/DEJhzU6nouxdD/1249Fhn9eR sW4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Qp1pi/xi"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n7si16507470wrm.176.2021.07.13.09.50.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Jul 2021 09:50:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Qp1pi/xi"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47942 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m3LcP-000632-JX for patch@linaro.org; Tue, 13 Jul 2021 12:50:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41196) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m3LUE-0006u8-JR for qemu-devel@nongnu.org; Tue, 13 Jul 2021 12:42:22 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:33373) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m3LUC-0005gn-7X for qemu-devel@nongnu.org; Tue, 13 Jul 2021 12:42:22 -0400 Received: by mail-pl1-x629.google.com with SMTP id d1so6185095plg.0 for ; Tue, 13 Jul 2021 09:42:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=l5PqM6iGSweKZSS09TGPy9jM/MAv4I7LtiO9ZGckioo=; b=Qp1pi/xijJ3l5zDukur8AAb6SI1qrJBbW7UckSBVDBlFdjZJ48z7ty7P2gijabMufK lbyXKyYR07XKWWlvWOiLW71yfzv7Gv3OcUWtoRIObzxn+ggaxUrf+i8SVNXj86CbqdXg j7Y9JV9SacZpCxtlDbILTayDgTcmgg9NLmEJsH4cIPlqacB21DHoQJzC0S6jpaOjtseC qveKbvHZT+2de3w7/HMHzIyF5B0UKvRUi3UaXejTRVQBT8Ufbs6g+B1kGtqxEKEXVXaY 9eUCD79JR3XKg6WOWbSPvt/vlzWGpGOp5SGEK1GCqUw9oH8AcXXVpthYZs2zaSt6tvHg umGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=l5PqM6iGSweKZSS09TGPy9jM/MAv4I7LtiO9ZGckioo=; b=VF6SVArPiR6kHkp7WMREJ7+bM5JbdZxIutGUre9BEKm/QJQPoSITursw88NO58p8Nx A6CnJg/FZHddI/IZJujHK0IMfCFnhi45qTb7moxq0S709PDRDf4mOfSkf1Mud0nCqbLS Varu/LEl94LDa4W0xnzVPSvV1vitrcjSs6dd8uxj2pd0uCHApe2v/EqHN1hJN1DLsu4m rOwFTF9yQ64l+HIl5bF2Oe94GTgvvJ/nwl6eCt7/LCwPFXB35786KL0dv40gNO6bfrn+ 2/U5RRNDtNNOORKqJHEO7t+bBcjdE99lChVgVyR2Z5g4Q8XtemnqbiewWc8Nj2DGxLaQ Z0OA== X-Gm-Message-State: AOAM533KmLGUKFwkl4sahM6PSWj0UYSyeo8dsbwUYF0mDy1svokSHffW bh6Tm3zTMabpNM4fYYXHXWRszq7Q5eBCPA== X-Received: by 2002:a17:90a:a60f:: with SMTP id c15mr5029285pjq.187.1626194538823; Tue, 13 Jul 2021 09:42:18 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id z13sm4947865pfn.94.2021.07.13.09.42.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jul 2021 09:42:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 11/14] target/openrisc: Cache constant 0 in DisasContext Date: Tue, 13 Jul 2021 09:42:08 -0700 Message-Id: <20210713164211.1520109-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210713164211.1520109-1-richard.henderson@linaro.org> References: <20210713164211.1520109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?b?w6k=?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We are virtually certain to have fetched constant 0 once, at the beginning of the TB, so we might as well use it elsewhere. Reviewed-by: Stafford Horne Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 2db529b7de..6aba4c2ffc 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -52,6 +52,8 @@ typedef struct DisasContext { /* The temporary corresponding to register 0 for this compilation. */ TCGv R0; + /* The constant zero. */ + TCGv zero; } DisasContext; static inline bool is_user(DisasContext *dc) @@ -536,10 +538,8 @@ static bool trans_l_extbz(DisasContext *dc, arg_da *a) static bool trans_l_cmov(DisasContext *dc, arg_dab *a) { - TCGv zero = tcg_constant_tl(0); - check_r0_write(dc, a->d); - tcg_gen_movcond_tl(TCG_COND_NE, cpu_R(dc, a->d), cpu_sr_f, zero, + tcg_gen_movcond_tl(TCG_COND_NE, cpu_R(dc, a->d), cpu_sr_f, dc->zero, cpu_R(dc, a->a), cpu_R(dc, a->b)); return true; } @@ -630,9 +630,8 @@ static void do_bf(DisasContext *dc, arg_l_bf *a, TCGCond cond) target_ulong tmp_pc = dc->base.pc_next + a->n * 4; TCGv t_next = tcg_constant_tl(dc->base.pc_next + 8); TCGv t_true = tcg_constant_tl(tmp_pc); - TCGv t_zero = tcg_constant_tl(0); - tcg_gen_movcond_tl(cond, jmp_pc, cpu_sr_f, t_zero, t_true, t_next); + tcg_gen_movcond_tl(cond, jmp_pc, cpu_sr_f, dc->zero, t_true, t_next); dc->delayed_branch = 2; } @@ -1594,8 +1593,9 @@ static void openrisc_tr_tb_start(DisasContextBase *db, CPUState *cs) /* Allow the TCG optimizer to see that R0 == 0, when it's true, which is the common case. */ + dc->zero = tcg_constant_tl(0); if (dc->tb_flags & TB_FLAGS_R0_0) { - dc->R0 = tcg_constant_tl(0); + dc->R0 = dc->zero; } else { dc->R0 = cpu_regs[0]; } From patchwork Tue Jul 13 16:42:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 474700 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp4144632jao; Tue, 13 Jul 2021 09:49:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyRG9f0+EOa2baqwxL6Cv+b54NftXL76K7Go4k7jd3Al9QxjpXdoxM9n9j8idW8rqCzZn6i X-Received: by 2002:a05:6000:180b:: with SMTP id m11mr7020443wrh.6.1626194984707; Tue, 13 Jul 2021 09:49:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626194984; cv=none; d=google.com; s=arc-20160816; b=dnZfWJA8fWqSX4RY/vssUQsHXmLm1KOAuOXEZIsQdrHhBl64bEBiw90+4ZRhfZ65Tx NZgQqjZO1bEGP6gxfFDi07T0yCk08JkQMMSj69bhQEAmC5OnkGNhbLtOX8zsKRPLN4ha xBzC0326St0UvIEhGYSZqsJaQ6lOGp5gGC0K8on9Mg3LwIeGpfI0K4AxN0WHrJMWpcGq KsvlN84irKm1TrMXSFWQ4rFBToRJuKcmyOuCsQxynUA/o9GNsOk2WKuUsDW+PdOlcmYu 6AuvyFLVGUoqWSUv7YWKQe/F+66CruDZIHUCHfaxK1FMQwvxAnaCmfJRFUJwZcoBcsTS 5QPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NgDcFwijqvI5Ustjzi412a6qyjRC0UcEnEWmUALegEQ=; b=tPiezHiuf58IJ3gdyHaofQQMwNS3R86EDZmuWE5SM36gooIl9O1c6jrkhic5EEhNt3 5cAmAnajOjw5AhaOuftF80Jw/wG4XxlG19lNKybJkNxVzCB56NWZktqTUzbpyS2mtAIr 4PncPYks70FP69XLK3ySEKdOw8SYLeJ5ROr9Id497S0gjZwwvBtkxuHTMuMY06uy3ByT kUa8Bwl3/dTHV18kCTcrIDFrTzUUStfCifhP7FRNfzdbP/YoYDrhC7kjhwB2DLOrMHqw hpdorttsm4F5Xx4l9NOgxHii9RSjp1OW/so9kHa1eZhAAAnB1ypC56iShhpKsr22Hhd6 XYHQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UtAP+N0V; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p12si24410876wrf.178.2021.07.13.09.49.44 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Jul 2021 09:49:44 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UtAP+N0V; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47402 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m3LbL-0005gI-O6 for patch@linaro.org; Tue, 13 Jul 2021 12:49:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41236) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m3LUG-0006wg-2p for qemu-devel@nongnu.org; Tue, 13 Jul 2021 12:42:24 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:44688) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m3LUC-0005hS-Tc for qemu-devel@nongnu.org; Tue, 13 Jul 2021 12:42:23 -0400 Received: by mail-pf1-x434.google.com with SMTP id p36so10460874pfw.11 for ; Tue, 13 Jul 2021 09:42:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NgDcFwijqvI5Ustjzi412a6qyjRC0UcEnEWmUALegEQ=; b=UtAP+N0VLB7vjoOe328EuJCbOheLmI6MpvCMqEP+gcKTOvx73b5IfF4QEu3wHUigyS ZIaKo6yS9Fog5D8lYDorS24LyTAPY2/ZaHMrrPTijOkNQsHNs6wnMpE6dVOc4otgBV2z sqfYuweMLaN0tUBfMPoTTrDzNGlpUg97P2Fb8T3GYdTNMlrYiehIoO3KLtjCdbZUhRaz 34BKvYjkf/Iod4nA5xdq0TpmzGIMSjJiI2eUAm82j51TNVhRSG0OHrIHuHRahXSvvZSH kt6WYieVUjSbAgdCRY+D6+vf9eGzONbM1gMUopFEPxu88tDbJs7iJpUYU0t8vC6hh2UX jqmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NgDcFwijqvI5Ustjzi412a6qyjRC0UcEnEWmUALegEQ=; b=mFZwNxfCBErgWuOUJfQSXkE5oXvpmrYPHKYNPKM3YPB03ZfedLoxCXzzqji3W1yDAz DttxOv99bXzA9bGQkwmvUi4XukWlEGI0XqB+EJtx/HUJpjmyD8CgmtYXjLNYNMBpJdpU My7orBc3/cwb+ShNh1OAe2RVIXnouLxkk2fV1EjCp2f/TJurAEwJ6xYHN/9TfUxxstzc WqQfquno93e6UKop2nRofD+IWAdHACMJ6twpHojajmI/tuDmluL4jSnNDcEsrtqfpiCr YtJiCa8GFbA6urxCJXLF1r08+Xk7L2Pfg2t3k3mjOpqZFK0sqGrBBwdszHHwblQYIOGg Opmw== X-Gm-Message-State: AOAM5307u8T3Kw6FGflCE5PzqLvdw/alvOPQquScUGxjRtNGiG8n3Tc2 Tzqp7WphD2w35pUgRz+yAtd/Bx/lc4hijQ== X-Received: by 2002:aa7:8683:0:b029:32e:2a35:941e with SMTP id d3-20020aa786830000b029032e2a35941emr3072513pfo.44.1626194539415; Tue, 13 Jul 2021 09:42:19 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id z13sm4947865pfn.94.2021.07.13.09.42.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jul 2021 09:42:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 12/14] target/openrisc: Use dc->zero in gen_add, gen_addc Date: Tue, 13 Jul 2021 09:42:09 -0700 Message-Id: <20210713164211.1520109-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210713164211.1520109-1-richard.henderson@linaro.org> References: <20210713164211.1520109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We still need the t0 temporary for computing overflow, but we do not need to initialize it to zero first. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/translate.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) -- 2.25.1 diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 6aba4c2ffc..059da48475 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -199,10 +199,10 @@ static void gen_ove_cyov(DisasContext *dc) static void gen_add(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) { - TCGv t0 = tcg_const_tl(0); + TCGv t0 = tcg_temp_new(); TCGv res = tcg_temp_new(); - tcg_gen_add2_tl(res, cpu_sr_cy, srca, t0, srcb, t0); + tcg_gen_add2_tl(res, cpu_sr_cy, srca, dc->zero, srcb, dc->zero); tcg_gen_xor_tl(cpu_sr_ov, srca, srcb); tcg_gen_xor_tl(t0, res, srcb); tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov); @@ -216,11 +216,11 @@ static void gen_add(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) static void gen_addc(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) { - TCGv t0 = tcg_const_tl(0); + TCGv t0 = tcg_temp_new(); TCGv res = tcg_temp_new(); - tcg_gen_add2_tl(res, cpu_sr_cy, srca, t0, cpu_sr_cy, t0); - tcg_gen_add2_tl(res, cpu_sr_cy, res, cpu_sr_cy, srcb, t0); + tcg_gen_add2_tl(res, cpu_sr_cy, srca, dc->zero, cpu_sr_cy, dc->zero); + tcg_gen_add2_tl(res, cpu_sr_cy, res, cpu_sr_cy, srcb, dc->zero); tcg_gen_xor_tl(cpu_sr_ov, srca, srcb); tcg_gen_xor_tl(t0, res, srcb); tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov); From patchwork Tue Jul 13 16:42:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 474702 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp4146376jao; Tue, 13 Jul 2021 09:51:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzieFOCdoE+KiR86INhgrkyLIor4eErqUvF92H10OvtsokkhKUfkWsjCk9gCHpkNbWAtvbH X-Received: by 2002:adf:f907:: with SMTP id b7mr6969241wrr.357.1626195107308; Tue, 13 Jul 2021 09:51:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626195107; cv=none; d=google.com; s=arc-20160816; b=DcbrrKDQvtm6hLcJ4vpt1l73aXkTPqMlgVYoOFnlR/61BM4Hp2RdewNQ10oV3g+HLB PN14Ex7epS+k4UCYmRRho2wLcB8aKWYrCP9KV3PjHqhOFqSuFO0rRIw8fizuONVbZVaw 3+Ejsuk4TFfBO96yIi0nna2lAz1VPgV/BYMe7xuh3nwZpATh5zZJFnYEEVYM3h2f8MH2 WeCOR50Q5M+guaTGAnXk2Xq1aCTrnnWVUnuctmk4ELZ0k39VewryJEiLCpuGLTaHQUgy DSoM2p92A28ZwMOPCmXqJboOIv6Yxn64e16fovs7bqk7J46QB48XvxCyxiXE/HgWdMs8 PcHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=9g0TMe4PewTmlA7yR++xZQeLCjd2V186Zm/OTs48w30=; b=zNjxEFWWSW+HQOr0vYcvyMmFoYiCHnltntyg4rKY0v18arekFyQS4iJynv+nVhVK3S TvVNaF/0exA/0ccZeM7ataTX9qQmSe3cmxWKuW11GAhbLQXSDC92ZMhQKjql3hzzqqm1 Z0JpNvC52nG6uZvBTaPDxP8uBRq2oSZ13NqqzjwPIVZ/ys341+YVgINZhVYqb6zOe2AZ B7ps4xZzKSbPyBh57cvnbtjFpM6Jr+7ipgmqyigckC8mv+r3P6gDS8h4j5qI+kDLCyXl VF54kae5S/FqERNjS+CAm+UtOOjBo1G9hWFBiiNuLPC/Ar/GqO34UR+iSwwtZdE3qoh+ DVLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oliKWXqE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/translate.c | 56 +++++++++++++---------------------------- 1 file changed, 18 insertions(+), 38 deletions(-) -- 2.25.1 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 835120c038..fa668072d0 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -144,6 +144,7 @@ #define tcg_gen_sextract_reg tcg_gen_sextract_i64 #define tcg_const_reg tcg_const_i64 #define tcg_const_local_reg tcg_const_local_i64 +#define tcg_constant_reg tcg_constant_i64 #define tcg_gen_movcond_reg tcg_gen_movcond_i64 #define tcg_gen_add2_reg tcg_gen_add2_i64 #define tcg_gen_sub2_reg tcg_gen_sub2_i64 @@ -238,6 +239,7 @@ #define tcg_gen_sextract_reg tcg_gen_sextract_i32 #define tcg_const_reg tcg_const_i32 #define tcg_const_local_reg tcg_const_local_i32 +#define tcg_constant_reg tcg_constant_i32 #define tcg_gen_movcond_reg tcg_gen_movcond_i32 #define tcg_gen_add2_reg tcg_gen_add2_i32 #define tcg_gen_sub2_reg tcg_gen_sub2_i32 @@ -771,9 +773,7 @@ static inline target_ureg iaoq_dest(DisasContext *ctx, target_sreg disp) static void gen_excp_1(int exception) { - TCGv_i32 t = tcg_const_i32(exception); - gen_helper_excp(cpu_env, t); - tcg_temp_free_i32(t); + gen_helper_excp(cpu_env, tcg_constant_i32(exception)); } static void gen_excp(DisasContext *ctx, int exception) @@ -787,12 +787,9 @@ static void gen_excp(DisasContext *ctx, int exception) static bool gen_excp_iir(DisasContext *ctx, int exc) { - TCGv_reg tmp; - nullify_over(ctx); - tmp = tcg_const_reg(ctx->insn); - tcg_gen_st_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[CR_IIR])); - tcg_temp_free(tmp); + tcg_gen_st_reg(tcg_constant_reg(ctx->insn), + cpu_env, offsetof(CPUHPPAState, cr[CR_IIR])); gen_excp(ctx, exc); return nullify_end(ctx); } @@ -1150,13 +1147,12 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1, } if (!is_l || cond_need_cb(c)) { - TCGv_reg zero = tcg_const_reg(0); + TCGv_reg zero = tcg_constant_reg(0); cb_msb = get_temp(ctx); tcg_gen_add2_reg(dest, cb_msb, in1, zero, in2, zero); if (is_c) { tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cpu_psw_cb_msb, zero); } - tcg_temp_free(zero); if (!is_l) { cb = get_temp(ctx); tcg_gen_xor_reg(cb, in1, in2); @@ -1242,7 +1238,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1, cb = tcg_temp_new(); cb_msb = tcg_temp_new(); - zero = tcg_const_reg(0); + zero = tcg_constant_reg(0); if (is_b) { /* DEST,C = IN1 + ~IN2 + C. */ tcg_gen_not_reg(cb, in2); @@ -1258,7 +1254,6 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1, tcg_gen_eqv_reg(cb, in1, in2); tcg_gen_xor_reg(cb, cb, dest); } - tcg_temp_free(zero); /* Compute signed overflow if required. */ sv = NULL; @@ -2449,17 +2444,16 @@ static bool trans_probe(DisasContext *ctx, arg_probe *a) form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false); if (a->imm) { - level = tcg_const_i32(a->ri); + level = tcg_constant_i32(a->ri); } else { level = tcg_temp_new_i32(); tcg_gen_trunc_reg_i32(level, load_gpr(ctx, a->ri)); tcg_gen_andi_i32(level, level, 3); } - want = tcg_const_i32(a->write ? PAGE_WRITE : PAGE_READ); + want = tcg_constant_i32(a->write ? PAGE_WRITE : PAGE_READ); gen_helper_probe(dest, cpu_env, addr, level, want); - tcg_temp_free_i32(want); tcg_temp_free_i32(level); save_gpr(ctx, a->t, dest); @@ -2599,17 +2593,13 @@ static bool trans_lpa(DisasContext *ctx, arg_ldst *a) static bool trans_lci(DisasContext *ctx, arg_lci *a) { - TCGv_reg ci; - CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); /* The Coherence Index is an implementation-defined function of the physical address. Two addresses with the same CI have a coherent view of the cache. Our implementation is to return 0 for all, since the entire address space is coherent. */ - ci = tcg_const_reg(0); - save_gpr(ctx, a->t, ci); - tcg_temp_free(ci); + save_gpr(ctx, a->t, tcg_constant_reg(0)); cond_free(&ctx->null_cond); return true; @@ -2710,8 +2700,6 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf *a) * currently implemented as idle. */ if ((rt == 10 || rt == 31) && r1 == rt && r2 == rt) { /* PAUSE */ - TCGv_i32 tmp; - /* No need to check for supervisor, as userland can only pause until the next timer interrupt. */ nullify_over(ctx); @@ -2722,10 +2710,8 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf *a) nullify_set(ctx, 0); /* Tell the qemu main loop to halt until this cpu has work. */ - tmp = tcg_const_i32(1); - tcg_gen_st_i32(tmp, cpu_env, -offsetof(HPPACPU, env) + - offsetof(CPUState, halted)); - tcg_temp_free_i32(tmp); + tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, + offsetof(CPUState, halted) - offsetof(HPPACPU, env)); gen_excp_1(EXCP_HALTED); ctx->base.is_jmp = DISAS_NORETURN; @@ -2833,7 +2819,7 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) add2 = tcg_temp_new(); addc = tcg_temp_new(); dest = tcg_temp_new(); - zero = tcg_const_reg(0); + zero = tcg_constant_reg(0); /* Form R1 << 1 | PSW[CB]{8}. */ tcg_gen_add_reg(add1, in1, in1); @@ -2851,7 +2837,6 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) tcg_gen_add2_i32(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zero); tcg_temp_free(addc); - tcg_temp_free(zero); /* Write back the result register. */ save_gpr(ctx, a->t, dest); @@ -2967,9 +2952,8 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a) */ gen_helper_ldc_check(addr); - zero = tcg_const_reg(0); + zero = tcg_constant_reg(0); tcg_gen_atomic_xchg_reg(dest, addr, zero, ctx->mmu_idx, mop); - tcg_temp_free(zero); if (a->m) { save_gpr(ctx, a->b, ofs); @@ -3882,15 +3866,13 @@ static bool trans_fcmp_f(DisasContext *ctx, arg_fclass2 *a) ta = load_frw0_i32(a->r1); tb = load_frw0_i32(a->r2); - ty = tcg_const_i32(a->y); - tc = tcg_const_i32(a->c); + ty = tcg_constant_i32(a->y); + tc = tcg_constant_i32(a->c); gen_helper_fcmp_s(cpu_env, ta, tb, ty, tc); tcg_temp_free_i32(ta); tcg_temp_free_i32(tb); - tcg_temp_free_i32(ty); - tcg_temp_free_i32(tc); return nullify_end(ctx); } @@ -3904,15 +3886,13 @@ static bool trans_fcmp_d(DisasContext *ctx, arg_fclass2 *a) ta = load_frd0(a->r1); tb = load_frd0(a->r2); - ty = tcg_const_i32(a->y); - tc = tcg_const_i32(a->c); + ty = tcg_constant_i32(a->y); + tc = tcg_constant_i32(a->c); gen_helper_fcmp_d(cpu_env, ta, tb, ty, tc); tcg_temp_free_i64(ta); tcg_temp_free_i64(tb); - tcg_temp_free_i32(ty); - tcg_temp_free_i32(tc); return nullify_end(ctx); } From patchwork Tue Jul 13 16:42:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 474692 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp4139777jao; Tue, 13 Jul 2021 09:44:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx9GusU05BdSAZ07f9hnLY9V0h2FrtaQ4djgN1YsVNeAfsunO4BevF//dN9bXbbwvq6MkYm X-Received: by 2002:a05:600c:3507:: with SMTP id h7mr178368wmq.9.1626194647342; Tue, 13 Jul 2021 09:44:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626194647; cv=none; d=google.com; s=arc-20160816; b=afbkj9feawI1sApyXHzNY1m17Tf6E1BjLeq/ODnwW/tcwgAYfGCkhKZfaEImgj0K3M e/d3aQ5V0IOHLLfR/cYtGgbe05hV23ZZ3RTboRlDYpDzLQy9ueasj88J4KGEjlBfPQ7e +weweH0wMIas/GhsqNQYzJbxZGBgYyxGegIccRkr4IitDjcQR16PqNbaRJSTv/Nq9YQO QUpwVrBzxMvIqFfIQPHU91L5mgFQFkz6sua5/urb+qvg2bvY1kaNshghMg7GuGJwmdNE 2Oi2aAP/lpM7CAzkA853Sy8VJPxlGTeTiAghiUUbZ3qGOLqEvx7bvqLs4jyr195l6rwk 7pvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=XIRufaelCqcDThyPCfIwauMBr0gxGhP21bSIuzV5jtE=; b=hnjQwcRPP1tcgywbIWYXJk2tLzQ/FED+dk7uuWtRjIA1fMd9/BUZfB0Q7QadlyvzH6 MNFUKs6IKMHz5tOvzwPxHGRezwFZfxK9SIUU6W00SZXa6vL/TZUbThWMjfiFmVBopj5m 2p6nuAt9lHG0q1F64Wsize2FAthxVq59fzYFK2fIMTBrpYdii64wQ67q+0wqeNl4dvny Hu3mZq0OVFiV6Bg+qOtsCaxEJ9dZmAAzXOMAQjn86m79Eh8C7fd1GqMcy3ZYhGt52j9v sxAo1qXknMD5tnYE5xx7aF4NGJOY70yDCnKxkNCBtKjxBj/ZRRWQK4QqyhRHyBkxNH7m 7dag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qPtOMHs5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h22si4100716wmb.201.2021.07.13.09.44.07 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Jul 2021 09:44:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qPtOMHs5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55676 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m3LVu-0000iJ-9H for patch@linaro.org; Tue, 13 Jul 2021 12:44:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41234) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m3LUF-0006wT-VK for qemu-devel@nongnu.org; Tue, 13 Jul 2021 12:42:23 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]:37839) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m3LUE-0005hx-02 for qemu-devel@nongnu.org; Tue, 13 Jul 2021 12:42:23 -0400 Received: by mail-pg1-x52f.google.com with SMTP id t9so22131865pgn.4 for ; Tue, 13 Jul 2021 09:42:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XIRufaelCqcDThyPCfIwauMBr0gxGhP21bSIuzV5jtE=; b=qPtOMHs5JOoPf3+tW//LAfW5OSqNKknZLPrg8HFK6OMaMzyWqocB/9pwUARnrN5hK5 5wbPGOFpY1+LPUH3w6FtQVhKw7Pvk1d7tsupb6vVM1fzkF4TUaFfQyxG9rnuyUPjlFlj yjib1o1cyEgbVrQxwFNOWNnjfz1H3r0UXiPrsDBPHaeGdCzILiAy8Iij94jfAYkho3w1 /+w4PRcGDBVoWWLy94GhDgfd9ln6Gmnoh60zHAxfQMPoikL4r8nIBwq6chvuCEXd47cC kQjP9FrXq5bwbogyTUu4BY2UrjjSTM+K35vtGaTS0XCQc9UBq3qbz2Hr3POBFR3CL8VC +v6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XIRufaelCqcDThyPCfIwauMBr0gxGhP21bSIuzV5jtE=; b=MRZksn7OgF2/82zeHPMVDeY5AonAZRrovAtfXAKIrijfreDb6sRx96+s36MD9cqOtg N2sSJJ7vULo2cl/f7b353p40XMiLzBtmoDe1BENTN6wpL2KgrBt0G6FSVosXg1DVP8fn bUpKQTOfqUTaY6Km0ReXVdtfvMdgyHlK7Yyq2fvZvQ3217361tq4KKKNVjNmJ1oDIO/k gXVUO7aXCV86kx6FzOlNZTPkabZH5OhNqndBVeqPO9YRlc9WoSvq2ARNDNyhkhk+LTY9 lpE8Uiv6I6L1p3g+hoL4Cz+w8EZvePlSZrD4s/S1ngWzEJ6ijI1MTERxV7sLNzUWVz8z Oz3w== X-Gm-Message-State: AOAM5323XSo1MsCgzeae0puBWEvkwiTY2mKnd1+W9H4lnLp8ltjDEMzF mD+0Kog9w/r0x4NpwAodNJqVvZFL2u0hMg== X-Received: by 2002:aa7:8602:0:b029:32d:3e9b:27de with SMTP id p2-20020aa786020000b029032d3e9b27demr5382822pfn.39.1626194540614; Tue, 13 Jul 2021 09:42:20 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id z13sm4947865pfn.94.2021.07.13.09.42.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Jul 2021 09:42:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 14/14] target/hppa: Clean up DisasCond Date: Tue, 13 Jul 2021 09:42:11 -0700 Message-Id: <20210713164211.1520109-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210713164211.1520109-1-richard.henderson@linaro.org> References: <20210713164211.1520109-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The a0_is_n flag is redundant with comparing a0 to cpu_psw_n. The a1_is_0 flag can be removed by initializing a1 to $0, which also means that cond_prep can be removed entirely. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 43 +++++++++-------------------------------- 1 file changed, 9 insertions(+), 34 deletions(-) -- 2.25.1 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index fa668072d0..2552747138 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -252,8 +252,6 @@ typedef struct DisasCond { TCGCond c; TCGv_reg a0, a1; - bool a0_is_n; - bool a1_is_0; } DisasCond; typedef struct DisasContext { @@ -448,9 +446,7 @@ static DisasCond cond_make_n(void) return (DisasCond){ .c = TCG_COND_NE, .a0 = cpu_psw_n, - .a0_is_n = true, - .a1 = NULL, - .a1_is_0 = true + .a1 = tcg_constant_reg(0) }; } @@ -458,7 +454,7 @@ static DisasCond cond_make_0_tmp(TCGCond c, TCGv_reg a0) { assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS); return (DisasCond){ - .c = c, .a0 = a0, .a1_is_0 = true + .c = c, .a0 = a0, .a1 = tcg_constant_reg(0) }; } @@ -482,26 +478,14 @@ static DisasCond cond_make(TCGCond c, TCGv_reg a0, TCGv_reg a1) return r; } -static void cond_prep(DisasCond *cond) -{ - if (cond->a1_is_0) { - cond->a1_is_0 = false; - cond->a1 = tcg_const_reg(0); - } -} - static void cond_free(DisasCond *cond) { switch (cond->c) { default: - if (!cond->a0_is_n) { + if (cond->a0 != cpu_psw_n) { tcg_temp_free(cond->a0); } - if (!cond->a1_is_0) { - tcg_temp_free(cond->a1); - } - cond->a0_is_n = false; - cond->a1_is_0 = false; + tcg_temp_free(cond->a1); cond->a0 = NULL; cond->a1 = NULL; /* fallthru */ @@ -559,9 +543,8 @@ static TCGv_reg dest_gpr(DisasContext *ctx, unsigned reg) static void save_or_nullify(DisasContext *ctx, TCGv_reg dest, TCGv_reg t) { if (ctx->null_cond.c != TCG_COND_NEVER) { - cond_prep(&ctx->null_cond); tcg_gen_movcond_reg(ctx->null_cond.c, dest, ctx->null_cond.a0, - ctx->null_cond.a1, dest, t); + ctx->null_cond.a1, dest, t); } else { tcg_gen_mov_reg(dest, t); } @@ -668,11 +651,9 @@ static void nullify_over(DisasContext *ctx) assert(ctx->null_cond.c != TCG_COND_ALWAYS); ctx->null_lab = gen_new_label(); - cond_prep(&ctx->null_cond); /* If we're using PSW[N], copy it to a temp because... */ - if (ctx->null_cond.a0_is_n) { - ctx->null_cond.a0_is_n = false; + if (ctx->null_cond.a0 == cpu_psw_n) { ctx->null_cond.a0 = tcg_temp_new(); tcg_gen_mov_reg(ctx->null_cond.a0, cpu_psw_n); } @@ -685,7 +666,7 @@ static void nullify_over(DisasContext *ctx) } tcg_gen_brcond_reg(ctx->null_cond.c, ctx->null_cond.a0, - ctx->null_cond.a1, ctx->null_lab); + ctx->null_cond.a1, ctx->null_lab); cond_free(&ctx->null_cond); } } @@ -699,10 +680,9 @@ static void nullify_save(DisasContext *ctx) } return; } - if (!ctx->null_cond.a0_is_n) { - cond_prep(&ctx->null_cond); + if (ctx->null_cond.a0 != cpu_psw_n) { tcg_gen_setcond_reg(ctx->null_cond.c, cpu_psw_n, - ctx->null_cond.a0, ctx->null_cond.a1); + ctx->null_cond.a0, ctx->null_cond.a1); ctx->psw_n_nonzero = true; } cond_free(&ctx->null_cond); @@ -1178,7 +1158,6 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1, /* Emit any conditional trap before any writeback. */ cond = do_cond(cf, dest, cb_msb, sv); if (is_tc) { - cond_prep(&cond); tmp = tcg_temp_new(); tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(cpu_env, tmp); @@ -1273,7 +1252,6 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1, /* Emit any conditional trap before any writeback. */ if (is_tc) { - cond_prep(&cond); tmp = tcg_temp_new(); tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(cpu_env, tmp); @@ -1399,7 +1377,6 @@ static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1, if (is_tc) { TCGv_reg tmp = tcg_temp_new(); - cond_prep(&cond); tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(cpu_env, tmp); tcg_temp_free(tmp); @@ -1855,7 +1832,6 @@ static bool do_cbranch(DisasContext *ctx, target_sreg disp, bool is_n, } taken = gen_new_label(); - cond_prep(cond); tcg_gen_brcond_reg(c, cond->a0, cond->a1, taken); cond_free(cond); @@ -1952,7 +1928,6 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg dest, tcg_gen_lookup_and_goto_ptr(); return nullify_end(ctx); } else { - cond_prep(&ctx->null_cond); c = ctx->null_cond.c; a0 = ctx->null_cond.a0; a1 = ctx->null_cond.a1;