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Mon, 12 Jul 2021 08:59:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 1/3] qemu/atomic: Remove pre-C11 atomic fallbacks Date: Mon, 12 Jul 2021 08:59:16 -0700 Message-Id: <20210712155918.1422519-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210712155918.1422519-1-richard.henderson@linaro.org> References: <20210712155918.1422519-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, pbonzini@redhat.com, crobinso@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We now require c11, so the fallbacks are now dead code Signed-off-by: Richard Henderson --- configure | 7 -- include/qemu/atomic.h | 204 +++--------------------------------------- 2 files changed, 10 insertions(+), 201 deletions(-) -- 2.25.1 diff --git a/configure b/configure index 85db248ac1..95e0a08938 100755 --- a/configure +++ b/configure @@ -3915,18 +3915,11 @@ cat > $TMPC << EOF int main(void) { uint64_t x = 0, y = 0; -#ifdef __ATOMIC_RELAXED y = __atomic_load_n(&x, __ATOMIC_RELAXED); __atomic_store_n(&x, y, __ATOMIC_RELAXED); __atomic_compare_exchange_n(&x, &y, x, 0, __ATOMIC_RELAXED, __ATOMIC_RELAXED); __atomic_exchange_n(&x, y, __ATOMIC_RELAXED); __atomic_fetch_add(&x, y, __ATOMIC_RELAXED); -#else - typedef char is_host64[sizeof(void *) >= sizeof(uint64_t) ? 1 : -1]; - __sync_lock_test_and_set(&x, y); - __sync_val_compare_and_swap(&x, y, 0); - __sync_fetch_and_add(&x, y); -#endif return 0; } EOF diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h index 3ccf84fd46..c5d6df6bf8 100644 --- a/include/qemu/atomic.h +++ b/include/qemu/atomic.h @@ -60,8 +60,9 @@ (unsigned short)1, \ (expr)+0)))))) -#ifdef __ATOMIC_RELAXED -/* For C11 atomic ops */ +#ifndef __ATOMIC_RELAXED +#error "Expecting C11 atomic ops" +#endif /* Manual memory barriers * @@ -239,193 +240,8 @@ #define qatomic_xor(ptr, n) \ ((void) __atomic_fetch_xor(ptr, n, __ATOMIC_SEQ_CST)) -#else /* __ATOMIC_RELAXED */ - -#ifdef __alpha__ -#define smp_read_barrier_depends() asm volatile("mb":::"memory") -#endif - -#if defined(__i386__) || defined(__x86_64__) || defined(__s390x__) - -/* - * Because of the strongly ordered storage model, wmb() and rmb() are nops - * here (a compiler barrier only). QEMU doesn't do accesses to write-combining - * qemu memory or non-temporal load/stores from C code. - */ -#define smp_mb_release() barrier() -#define smp_mb_acquire() barrier() - -/* - * __sync_lock_test_and_set() is documented to be an acquire barrier only, - * but it is a full barrier at the hardware level. Add a compiler barrier - * to make it a full barrier also at the compiler level. - */ -#define qatomic_xchg(ptr, i) (barrier(), __sync_lock_test_and_set(ptr, i)) - -#elif defined(_ARCH_PPC) - -/* - * We use an eieio() for wmb() on powerpc. This assumes we don't - * need to order cacheable and non-cacheable stores with respect to - * each other. - * - * smp_mb has the same problem as on x86 for not-very-new GCC - * (http://patchwork.ozlabs.org/patch/126184/, Nov 2011). - */ -#define smp_wmb() ({ asm volatile("eieio" ::: "memory"); (void)0; }) -#if defined(__powerpc64__) -#define smp_mb_release() ({ asm volatile("lwsync" ::: "memory"); (void)0; }) -#define smp_mb_acquire() ({ asm volatile("lwsync" ::: "memory"); (void)0; }) -#else -#define smp_mb_release() ({ asm volatile("sync" ::: "memory"); (void)0; }) -#define smp_mb_acquire() ({ asm volatile("sync" ::: "memory"); (void)0; }) -#endif -#define smp_mb() ({ asm volatile("sync" ::: "memory"); (void)0; }) - -#endif /* _ARCH_PPC */ - -/* - * For (host) platforms we don't have explicit barrier definitions - * for, we use the gcc __sync_synchronize() primitive to generate a - * full barrier. This should be safe on all platforms, though it may - * be overkill for smp_mb_acquire() and smp_mb_release(). - */ -#ifndef smp_mb -#define smp_mb() __sync_synchronize() -#endif - -#ifndef smp_mb_acquire -#define smp_mb_acquire() __sync_synchronize() -#endif - -#ifndef smp_mb_release -#define smp_mb_release() __sync_synchronize() -#endif - -#ifndef smp_read_barrier_depends -#define smp_read_barrier_depends() barrier() -#endif - -#ifndef signal_barrier -#define signal_barrier() barrier() -#endif - -/* These will only be atomic if the processor does the fetch or store - * in a single issue memory operation - */ -#define qatomic_read__nocheck(p) (*(__typeof__(*(p)) volatile*) (p)) -#define qatomic_set__nocheck(p, i) ((*(__typeof__(*(p)) volatile*) (p)) = (i)) - -#define qatomic_read(ptr) qatomic_read__nocheck(ptr) -#define qatomic_set(ptr, i) qatomic_set__nocheck(ptr,i) - -/** - * qatomic_rcu_read - reads a RCU-protected pointer to a local variable - * into a RCU read-side critical section. The pointer can later be safely - * dereferenced within the critical section. - * - * This ensures that the pointer copy is invariant thorough the whole critical - * section. - * - * Inserts memory barriers on architectures that require them (currently only - * Alpha) and documents which pointers are protected by RCU. - * - * qatomic_rcu_read also includes a compiler barrier to ensure that - * value-speculative optimizations (e.g. VSS: Value Speculation - * Scheduling) does not perform the data read before the pointer read - * by speculating the value of the pointer. - * - * Should match qatomic_rcu_set(), qatomic_xchg(), qatomic_cmpxchg(). - */ -#define qatomic_rcu_read(ptr) ({ \ - typeof(*ptr) _val = qatomic_read(ptr); \ - smp_read_barrier_depends(); \ - _val; \ -}) - -/** - * qatomic_rcu_set - assigns (publicizes) a pointer to a new data structure - * meant to be read by RCU read-side critical sections. - * - * Documents which pointers will be dereferenced by RCU read-side critical - * sections and adds the required memory barriers on architectures requiring - * them. It also makes sure the compiler does not reorder code initializing the - * data structure before its publication. - * - * Should match qatomic_rcu_read(). - */ -#define qatomic_rcu_set(ptr, i) do { \ - smp_wmb(); \ - qatomic_set(ptr, i); \ -} while (0) - -#define qatomic_load_acquire(ptr) ({ \ - typeof(*ptr) _val = qatomic_read(ptr); \ - smp_mb_acquire(); \ - _val; \ -}) - -#define qatomic_store_release(ptr, i) do { \ - smp_mb_release(); \ - qatomic_set(ptr, i); \ -} while (0) - -#ifndef qatomic_xchg -#if defined(__clang__) -#define qatomic_xchg(ptr, i) __sync_swap(ptr, i) -#else -/* __sync_lock_test_and_set() is documented to be an acquire barrier only. */ -#define qatomic_xchg(ptr, i) (smp_mb(), __sync_lock_test_and_set(ptr, i)) -#endif -#endif -#define qatomic_xchg__nocheck qatomic_xchg - -/* Provide shorter names for GCC atomic builtins. */ -#define qatomic_fetch_inc(ptr) __sync_fetch_and_add(ptr, 1) -#define qatomic_fetch_dec(ptr) __sync_fetch_and_add(ptr, -1) - -#define qatomic_fetch_add(ptr, n) __sync_fetch_and_add(ptr, n) -#define qatomic_fetch_sub(ptr, n) __sync_fetch_and_sub(ptr, n) -#define qatomic_fetch_and(ptr, n) __sync_fetch_and_and(ptr, n) -#define qatomic_fetch_or(ptr, n) __sync_fetch_and_or(ptr, n) -#define qatomic_fetch_xor(ptr, n) __sync_fetch_and_xor(ptr, n) - -#define qatomic_inc_fetch(ptr) __sync_add_and_fetch(ptr, 1) -#define qatomic_dec_fetch(ptr) __sync_add_and_fetch(ptr, -1) -#define qatomic_add_fetch(ptr, n) __sync_add_and_fetch(ptr, n) -#define qatomic_sub_fetch(ptr, n) __sync_sub_and_fetch(ptr, n) -#define qatomic_and_fetch(ptr, n) __sync_and_and_fetch(ptr, n) -#define qatomic_or_fetch(ptr, n) __sync_or_and_fetch(ptr, n) -#define qatomic_xor_fetch(ptr, n) __sync_xor_and_fetch(ptr, n) - -#define qatomic_cmpxchg(ptr, old, new) \ - __sync_val_compare_and_swap(ptr, old, new) -#define qatomic_cmpxchg__nocheck(ptr, old, new) qatomic_cmpxchg(ptr, old, new) - -/* And even shorter names that return void. */ -#define qatomic_inc(ptr) ((void) __sync_fetch_and_add(ptr, 1)) -#define qatomic_dec(ptr) ((void) __sync_fetch_and_add(ptr, -1)) -#define qatomic_add(ptr, n) ((void) __sync_fetch_and_add(ptr, n)) -#define qatomic_sub(ptr, n) ((void) __sync_fetch_and_sub(ptr, n)) -#define qatomic_and(ptr, n) ((void) __sync_fetch_and_and(ptr, n)) -#define qatomic_or(ptr, n) ((void) __sync_fetch_and_or(ptr, n)) -#define qatomic_xor(ptr, n) ((void) __sync_fetch_and_xor(ptr, n)) - -#endif /* __ATOMIC_RELAXED */ - -#ifndef smp_wmb #define smp_wmb() smp_mb_release() -#endif -#ifndef smp_rmb #define smp_rmb() smp_mb_acquire() -#endif - -/* This is more efficient than a store plus a fence. */ -#if !defined(__SANITIZE_THREAD__) -#if defined(__i386__) || defined(__x86_64__) || defined(__s390x__) -#define qatomic_mb_set(ptr, i) ((void)qatomic_xchg(ptr, i)) -#endif -#endif /* qatomic_mb_read/set semantics map Java volatile variables. They are * less expensive on some platforms (notably POWER) than fully @@ -435,16 +251,16 @@ * use. See docs/devel/atomics.rst for more discussion. */ -#ifndef qatomic_mb_read #define qatomic_mb_read(ptr) \ qatomic_load_acquire(ptr) -#endif -#ifndef qatomic_mb_set -#define qatomic_mb_set(ptr, i) do { \ - qatomic_store_release(ptr, i); \ - smp_mb(); \ -} while(0) +#if !defined(__SANITIZE_THREAD__) && \ + (defined(__i386__) || defined(__x86_64__) || defined(__s390x__)) +/* This is more efficient than a store plus a fence. */ +# define qatomic_mb_set(ptr, i) ((void)qatomic_xchg(ptr, i)) +#else +# define qatomic_mb_set(ptr, i) \ + ({ qatomic_store_release(ptr, i); smp_mb(); }) #endif #define qatomic_fetch_inc_nonzero(ptr) ({ \ From patchwork Mon Jul 12 15:59:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 473134 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp3071496jao; Mon, 12 Jul 2021 08:59:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzzDnZ54yQonyN32JNA+BBb5Bx6wDEOfl6BJb/MLOO3jYtDGCzG5r9+jZ3BCjReggi4M5Ek X-Received: by 2002:a67:e8cf:: with SMTP id y15mr6388180vsn.47.1626105585560; Mon, 12 Jul 2021 08:59:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626105585; cv=none; d=google.com; s=arc-20160816; b=l+Z8Am/biYQDX7bsiC+F4S+bBX15QAWkMNApTAN5mwqU3UnbIq2RzAM8+UwiCgPwTt Vcnr7cFjBP0Nb8/qvOgUh0rE3+kn4aMrY5Mx9nh+IbVQDglGGBNTrhdyllL95wd1EjlP XuZXXPuX+KTOjrleBR/BQ5D08rK6aSxTMr8CmOIFg7Nza6etJBgWx5dtc3uGYuE62UP7 BW/vkvpwFqDHPIU2td3cLcf0+6PBDIIpBXKBhe/G0rdZEjLAZBwdTrSOdwBuHWKBR0tl lj/tf7mQgaztQf7kyYOMw8G3L3cgeNUveFcy/Jy1OEci71V5wBrOUdmHSvUianODQ/pG DHGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=L/58asou9sVz0CWQlJ3eJYnasOlqmgcxUQzFR2mZ0sk=; b=vMCHBTMfh1y/57T5+mhoZUMTt4mmnK9eIhqpkYQY2GycMUvYM+bebYX0pPhnGyqSqi 1QQeWFro4j9PhPyHR/ix9SpCbRA5d/jhapw2vX0eFy1d4u0yYAqflM8IjeihJnnystBR sOV7Ltsyr6rdTNozNd1X4jUhggrMdVakTKVpaWI/kBqh/tC/RAqMqxYHjSsRFiKgReaw E8FYjCEbD7hjKJxg6OVr1JmgZKtQ/ZvMp1pvc8hz8ROmGsUxBFqHDx28ZgvXf2XLOL9x Ih3Z093pUD2tyuPE3kusGEeDWN5tM/aHvCqYbFthdw3PKpDc4QvAWxH28CaxyLyyfvdg +Rhw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Rr4l8Pq0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d125si12692093vkf.26.2021.07.12.08.59.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 12 Jul 2021 08:59:45 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Rr4l8Pq0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47360 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m2yLQ-0000Ro-U9 for patch@linaro.org; Mon, 12 Jul 2021 11:59:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35416) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m2yL5-0000MS-Ms for qemu-devel@nongnu.org; Mon, 12 Jul 2021 11:59:27 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:39605) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m2yL4-00074i-4F for qemu-devel@nongnu.org; Mon, 12 Jul 2021 11:59:23 -0400 Received: by mail-pg1-x52d.google.com with SMTP id a2so18711313pgi.6 for ; Mon, 12 Jul 2021 08:59:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L/58asou9sVz0CWQlJ3eJYnasOlqmgcxUQzFR2mZ0sk=; b=Rr4l8Pq0Fru7J1aM6DENrUZ3knxuIUnxPuYfR+bOhE9P5T44c+aIwtoNyGvqJE+K4c ZDXFGVrHPHJf34K9PqfxXNv7U9+KQjJEtqVyTl1IFYOglKuhH6YKKLM8sii4YOrphBL/ 4nG4ne69zYgkwRKErlSmkWw04nQYoq5U+19I5R6TDH62+QjdbwBN6C5cMcQR7TPQgNlf TUC0oOta5NMOtm72W/TXcl1zeoRGey8HPuUcBnuPbK/dZlwHGoyUAfC0gWA3RPAG2Qd2 5Qt8+MmAbkKZ0+/W3+diOw7S92G7Q59uLu7IhMFPra30XY3TjnVYYHP//qLKKNuqy/aw gqEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L/58asou9sVz0CWQlJ3eJYnasOlqmgcxUQzFR2mZ0sk=; b=VGJDp/yT1DNfypaCufVWRCwnd6LdLx6GWAzbtlSzUb/iLxW6DdE6aI1M1Ij6NFlLYU qOPCkVn48PuccycLqIhgjtpU3m2XBySnHW8ihU173LfPUCXNvN39ewF4nt9QjxFNxHam Wi9V+Gv4fJXVbp3gIxWfuVMhPuxEIKsiHrcpD8SueqL7/oCO7foKMqxlK7oTJXLHQycO JgKSAn/NgBT9kSyPsAW4tAom4pJ5v+iJH1YYd3c0/kFjfg3R7/oc5/MfQMFLe0LX9fan uJ31LIJwAwd8I/CaMDlh6c7u2mFQ1YSw5jIOfjxz0qJiZ+g6uA3BmFT5VZVbWK9VMXUu zn+w== X-Gm-Message-State: AOAM532NfYUMp8G8Pzr8pl2NoFFjTR3kfTSqVk54RXF6A7dihiigskk+ pbKgL0+tAkMoYFb2fDSy5Gs8XDomCkWP7w== X-Received: by 2002:a05:6a00:2403:b029:309:8a37:2d51 with SMTP id z3-20020a056a002403b02903098a372d51mr54062484pfh.79.1626105560566; Mon, 12 Jul 2021 08:59:20 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id j16sm16745021pfi.165.2021.07.12.08.59.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jul 2021 08:59:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/3] qemu/atomic: Use macros for CONFIG_ATOMIC64 Date: Mon, 12 Jul 2021 08:59:17 -0700 Message-Id: <20210712155918.1422519-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210712155918.1422519-1-richard.henderson@linaro.org> References: <20210712155918.1422519-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, pbonzini@redhat.com, crobinso@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Clang warnings about questionable atomic usage get localized to the inline function in atomic.h. By using a macro, we get the full traceback to the original use that caused the warning. Signed-off-by: Richard Henderson --- include/qemu/atomic.h | 25 +++++-------------------- 1 file changed, 5 insertions(+), 20 deletions(-) -- 2.25.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h index c5d6df6bf8..bf89855209 100644 --- a/include/qemu/atomic.h +++ b/include/qemu/atomic.h @@ -273,26 +273,11 @@ /* Abstractions to access atomically (i.e. "once") i64/u64 variables */ #ifdef CONFIG_ATOMIC64 -static inline int64_t qatomic_read_i64(const int64_t *ptr) -{ - /* use __nocheck because sizeof(void *) might be < sizeof(u64) */ - return qatomic_read__nocheck(ptr); -} - -static inline uint64_t qatomic_read_u64(const uint64_t *ptr) -{ - return qatomic_read__nocheck(ptr); -} - -static inline void qatomic_set_i64(int64_t *ptr, int64_t val) -{ - qatomic_set__nocheck(ptr, val); -} - -static inline void qatomic_set_u64(uint64_t *ptr, uint64_t val) -{ - qatomic_set__nocheck(ptr, val); -} +/* Use __nocheck because sizeof(void *) might be < sizeof(u64) */ +#define qatomic_read_i64 qatomic_read__nocheck +#define qatomic_read_u64 qatomic_read__nocheck +#define qatomic_set_i64 qatomic_set__nocheck +#define qatomic_set_u64 qatomic_set__nocheck static inline void qatomic64_init(void) { From patchwork Mon Jul 12 15:59:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 473136 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp3074140jao; Mon, 12 Jul 2021 09:02:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxFdiMJZrwPWiM4biNb89ieF1joG4XIcFwjyXqiBOack3xND0UTcmxfPRKUKQiTy/AooSZi X-Received: by 2002:a7b:c316:: with SMTP id k22mr15083899wmj.56.1626105737430; Mon, 12 Jul 2021 09:02:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1626105737; cv=none; d=google.com; s=arc-20160816; b=UGRYVIEUtvl0+pD6q40Uveg22nGvpOtlFXnfFUM4M7Y7iD167QE1NQrInu4Bw7uOTm AcsHyBOJippcE5yU4Fs9s4sAuc+lEAQTlLa87Ke3Vst1JyUC4kXDQOfJbOuHEpg+9Ood a4GPZ4oGINRgL1g0EWceLh7hTQPGPB8bd0uUr+m396y1cHVEF/va4uhEwSjkSnvS5r0S /p8FoqsIkkhxaeAG3/3K8+EFvfnTg67KsoQoZUll3//7kmeZ0x8I6WsWASKUTbHKS0Xw 61klyEmaLSvvADa9YOS5AO6Y0+LM/q3jvFAPaAhN1nD0KhKclMaR5Zr6ZrAbI9MKxMRx vlGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=T+H4xJOdclX41RzHCXkYk0QTpQSN2UXGitrvAjova9Y=; b=W2Nsyvd2pA3YV7SQXyFzPoI81R8bTWOXCcfrH2tUBcLBUloqdBXUMuZgxXfW49vgDy U4SBtjsAtMtGFUBKV2V3mLZmFCUZE7JyLPdMuNirVd7YZACOIx2UX1i82qSDsvWQPwl0 Xq5BBhnkD3QBAT5UzhGZ1bY2uS04Xt4aZYYwwiQA02AfRyLVBvIX41hjulLXk329Rl8t U3/c+P12HOcggFXgLZ3M+9v7hUAeJzD0nc5ysqfw0mjSEK8npFgWINTb+NExME8Evhq4 gMB+ftcLHCCSbW9ISdg8PzC3DNue6So2s3c1VXXQw5XKftlneWT8tHJ9d07fWM8+eZyH gO7Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="hv/W9EfL"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m17si24768663wmg.88.2021.07.12.09.02.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 12 Jul 2021 09:02:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="hv/W9EfL"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47432 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m2yNs-0000UI-9x for patch@linaro.org; Mon, 12 Jul 2021 12:02:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35418) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m2yL9-0000Nm-Cv for qemu-devel@nongnu.org; Mon, 12 Jul 2021 11:59:27 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:35340) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m2yL4-000759-DD for qemu-devel@nongnu.org; Mon, 12 Jul 2021 11:59:27 -0400 Received: by mail-pg1-x52a.google.com with SMTP id v7so18725339pgl.2 for ; Mon, 12 Jul 2021 08:59:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=T+H4xJOdclX41RzHCXkYk0QTpQSN2UXGitrvAjova9Y=; b=hv/W9EfLFSGRnP0eeXoPohDuSVF+lu4KQfqa26tKk3D++6X/Agq0XYWZpOQR9z8K2h 7MNuwGmSg+j32u9twFPUx9Gef3NWq7xcTghvqdi+8M6S2OlB32Z7Jhc9DbOwzFc5EJfg oZ9fJJr+wObRQbA38iUqjxvflb63dMzklJZU4ISNdnDyqqw2Lt6h9APux8+Y1VUBKtZ6 fnC1O2ciMMu+PClEz4DQiLmewDgfbSnhWf4gcTwNMzUaDxsFaGvDC65/NaPt6ANIjIkK xoYpHZiKtDIL3BJPqBBYDnhnK72N8iLv0GziUGaY9jC151zKZgaLudEcIe6xHQ6FKQ7O exbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=T+H4xJOdclX41RzHCXkYk0QTpQSN2UXGitrvAjova9Y=; b=taIVtmMathcFfJWQ7zkownBK0ztKq2IdvqD/xOp3PluusxB9Dky2kkeKkbayhv3iko GXwpnuNG7VKoCkrcXdWeahkcibXxceTOZK7xKzWWD7Fv5lKVJa0SqFm6xoC9OtRPxucT 4lYXZFCvqrToiD2vYCElbjXPecB1r9FnYgLbd0KfXtc3AEWwFv9OnQ9s7UpLXYz1HPRi DcqBfDCoDmX/V7MwjOvWxztokcJRgw+6oheeBSHlN+Dap/zmw1uwAODPhdehdIZjFmiK pqVajkdRi3UhtKDdNTkPOpWBHX/B/aXjRsxC/Rbujd3R0S2rh29URp0lnoM/wYcb+sg4 92UA== X-Gm-Message-State: AOAM532piTX9l509FL0ZQwVUDFyPMdajBj5zn2/ITHDcRiMbsDHoKNxK KqV9K/5p6QXFU8BDXEoYWVlMpWswTZGfxg== X-Received: by 2002:a62:c501:0:b029:32a:dfe9:8648 with SMTP id j1-20020a62c5010000b029032adfe98648mr10123860pfg.28.1626105561184; Mon, 12 Jul 2021 08:59:21 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id j16sm16745021pfi.165.2021.07.12.08.59.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jul 2021 08:59:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 3/3] configure: Conditionally disable clang-12 -Watomic-alignment Date: Mon, 12 Jul 2021 08:59:18 -0700 Message-Id: <20210712155918.1422519-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210712155918.1422519-1-richard.henderson@linaro.org> References: <20210712155918.1422519-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, pbonzini@redhat.com, crobinso@redhat.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The i386 abi does not align uint64_t (or double) in structures to 8 bytes, only to 4 bytes. Furthermore, the hardware does not require 8 byte alignent for cmpxchg8b, so the warning is confusing and useless. Retain the warning for hosts (notably x86_64) where the ABI is sane, and one has to do something extraordinary to remove alignment. Signed-off-by: Richard Henderson --- configure | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.25.1 diff --git a/configure b/configure index 95e0a08938..163b4edee2 100755 --- a/configure +++ b/configure @@ -3927,6 +3927,22 @@ if compile_prog "" "" ; then atomic64=yes fi +# Test for clang atomic misalignment warning vs ABI structure misalignment. +# E.g. i386 only aligns structures to 4 bytes by default. +if test "$atomic64" = "yes" ; then +cat > $TMPC << EOF +#include +struct X { uint64_t x; }; +uint64_t foo(struct X *p) { return __atomic_exchange_n(&p->x, 0, 0); } +EOF + if ! compile_prog "-Werror" "" ; then + if cc_has_warning_flag "-Wno-atomic-alignment" ; then + glib_cflags="-Wno-atomic-alignment $glib_cflags" + CONFIGURE_CFLAGS="$CONFIGURE_CFLAGS -Wno-atomic-alignment" + fi + fi +fi + ######################################### # See if --dynamic-list is supported by the linker ld_dynamic_list="no"