From patchwork Fri Jul 9 17:31:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 471943 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92725C07E9B for ; Fri, 9 Jul 2021 17:32:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 78F0C613F2 for ; Fri, 9 Jul 2021 17:32:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229979AbhGIRew (ORCPT ); Fri, 9 Jul 2021 13:34:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229949AbhGIRev (ORCPT ); Fri, 9 Jul 2021 13:34:51 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C6EF5C0613E9 for ; Fri, 9 Jul 2021 10:32:06 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id p1so24648597lfr.12 for ; Fri, 09 Jul 2021 10:32:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KLWZj85HgqkOqv1HxmNCRrODidaWLC0A2DygbxwWKbA=; b=o6PnS0GeNa0e7e9IYLaOaw2dOPONtiUFh8iGm+grX09+xf9s+u3UnRFEcT+jYTQHnV WEpXItGnvRJbeiYiS7aCO9/dI09CI3C0+NkCoBvacPZeDMej5vIphi+4vrIbjDQW3xJF vDiwYl6+v2PmzA5r8Ll8sY6saB67KiDDc0VH+75xLCL6hhhU6CgckOqXCn8tPnJxQsNH o9cXFxRV83CmhIB7HXDzl9fWBd9kCfQ0DUiEJycPQ1N0sgeHMATjzVxE2p+Lb+rP+xfh 3Or7cmus14QExq/lBPH874ms5L6m2fdjG335qnw51bkqMafMN3GpK4N4OEGt8kko8aZi LJrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KLWZj85HgqkOqv1HxmNCRrODidaWLC0A2DygbxwWKbA=; b=gk46acOTffN8Cabrs7rcDrkRx82At3fW6KtLQTuf90Neq8oxDVHOExakqKvuwstFci DKYAgKfK3jdlGpS929RkfPuoMjKl6h0OiQMf4NA2/pSd25SEiqnnUIfn0qc/i5VHaIJe 4T+4Ekek920zaD829HBOVZ8LolackQM0T77yZajFhnyirA5FodABdauRmhDMZEnpJ0SJ sZqbjy5bpFWEkWnP/jpENlrZUEmkgHp4Z856aJH171DNACyqIqOxc6X29zfpRHhgXHsb wcNX0hQwaJq7k/8HtofzE1tndPhu6FSBHwAAi3HbxuWMXbViGaZftQk9Q9x7v0axaPKp qpkw== X-Gm-Message-State: AOAM532W9l/fx+4OdZkO39EJzv9Itn0jq9wz+GK6QuUwAMsge26p90QF 3mKo9YUEEIJ8P5MqDbDZBjgNKw== X-Google-Smtp-Source: ABdhPJwEQLoRd1w6PfNkPyS9S5rZ2TWa8UqsLDK3TnyBxmXnZv1cIcW+tsqWV/9Ow4rAE/e4Pem26Q== X-Received: by 2002:a19:8c0f:: with SMTP id o15mr29897641lfd.509.1625851924989; Fri, 09 Jul 2021 10:32:04 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id b14sm511129lfb.132.2021.07.09.10.32.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 10:32:04 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [PATCH v3 1/7] dt-bindings: clock: qcom, dispcc-sm8x50: add mmcx power domain Date: Fri, 9 Jul 2021 20:31:56 +0300 Message-Id: <20210709173202.667820-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210709173202.667820-1-dmitry.baryshkov@linaro.org> References: <20210709173202.667820-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On sm8250 dispcc requires MMCX power domain to be powered up before clock controller's registers become available. For now sm8250 was using external regulator driven by the power domain to describe this relationship. Switch into specifying power-domain and required opp-state directly. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- .../devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 0cdf53f41f84..d5c4fed56b6e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -55,6 +55,11 @@ properties: reg: maxItems: 1 + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + required: - compatible - reg @@ -69,6 +74,7 @@ additionalProperties: false examples: - | #include + #include clock-controller@af00000 { compatible = "qcom,sm8250-dispcc"; reg = <0x0af00000 0x10000>; @@ -89,5 +95,6 @@ examples: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd SM8250_MMCX>; }; ... From patchwork Fri Jul 9 17:31:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 472414 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E964BC07E9C for ; Fri, 9 Jul 2021 17:32:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D821C613F4 for ; Fri, 9 Jul 2021 17:32:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230091AbhGIRex (ORCPT ); Fri, 9 Jul 2021 13:34:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229815AbhGIRev (ORCPT ); Fri, 9 Jul 2021 13:34:51 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8042DC0613E5 for ; Fri, 9 Jul 2021 10:32:07 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id c28so24195415lfp.11 for ; Fri, 09 Jul 2021 10:32:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+l6RNZfO6t53h33tKaqwIC7dbp1+6FXvY3b6ZyHCbIM=; b=kQuxiBVKZRCQhRmh45OAszosxWefqx6abf0JSPJUbxbD9VD1vshSdblR4to5B1zeIM gd8P/SUQNBTpNjdAGm/Vt/WxQYMdp1eyfknRL6zQz2yYIj8SjED/S67WvXdGuFsHcucV yP7AV5XY9AkTDI7TM3U+dXuVLX1325XamDBt0rTAkgGP2JDMyPzB8GXg6cYbjBGMEMBA cfWkwwa5VIvDB/nR3p/Mnpr4zWOd+f7R9OEUH0nlcdlJJit2FFVL11Wi+mdCgOesS+JZ 1Em+7pkqqScZifBTk7Jm6onIvpzJUbHEAe9vNdZgnPmHzI+OrF/rfvb/1XwAtWGOm+YA nW/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+l6RNZfO6t53h33tKaqwIC7dbp1+6FXvY3b6ZyHCbIM=; b=iGd2S5cVr/NejSgrrb2GowOjgAEhCoHArYqe4xZZgHHq2nJR7e8zkODwlpGCavLhFT jDQR7IsgaWaGVLmZmk86/LgIbICpxmhZZmmNoiMuQNVI/H45vCJUguhgNTiuFcX4LJxj Z8j7n+dqo1wPvK74BZvhl+ruIMnq/qEbEt76bvQSp9CVUGT6/5ME2DikWcSLe7OduO8c nz8+JGM8X/1TP/ITJQ5DRstlLp1yjba2B52u1RMTbjpuB//DcCwEK70AV3+ZrowF5nhm tuHVOGWleQwU2UBqHp4uV2DATMPYFu+6A4dccBtwqfMtpGE6FaCFYVZggbNA+C+esX+L 55Ug== X-Gm-Message-State: AOAM530CqQ7mnzQUzsMCP8BSCSrpwnIR1bmmanckCOH+3PkZLrayp5HR wluwk8J5lLWkWaUe2iM2jCwuTw== X-Google-Smtp-Source: ABdhPJyYC2SMo3GbiZe2sCoQeOOag4DBODidkGofQbLQmNSpc0jDQUBnJbh9tjna+TVj5nncPrh8Xw== X-Received: by 2002:a19:6d01:: with SMTP id i1mr30576206lfc.422.1625851925764; Fri, 09 Jul 2021 10:32:05 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id b14sm511129lfb.132.2021.07.09.10.32.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 10:32:05 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [PATCH v3 2/7] dt-bindings: clock: qcom, videocc: add mmcx power domain Date: Fri, 9 Jul 2021 20:31:57 +0300 Message-Id: <20210709173202.667820-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210709173202.667820-1-dmitry.baryshkov@linaro.org> References: <20210709173202.667820-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On sm8250 videocc requires MMCX power domain to be powered up before clock controller's registers become available. For now sm8250 was using external regulator driven by the power domain to describe this relationship. Switch into specifying power-domain and required opp-state directly. Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/clock/qcom,videocc.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml index 567202942b88..db4ada6acf27 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml @@ -47,6 +47,11 @@ properties: reg: maxItems: 1 + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + required: - compatible - reg @@ -61,6 +66,7 @@ additionalProperties: false examples: - | #include + #include clock-controller@ab00000 { compatible = "qcom,sdm845-videocc"; reg = <0x0ab00000 0x10000>; @@ -69,5 +75,6 @@ examples: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd SM8250_MMCX>; }; ... From patchwork Fri Jul 9 17:31:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 472413 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61535C11F6B for ; Fri, 9 Jul 2021 17:32:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4E32C613DF for ; Fri, 9 Jul 2021 17:32:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230075AbhGIRez (ORCPT ); Fri, 9 Jul 2021 13:34:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230106AbhGIRex (ORCPT ); Fri, 9 Jul 2021 13:34:53 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3EFF8C0613EE for ; Fri, 9 Jul 2021 10:32:08 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id z9so9190870ljm.2 for ; Fri, 09 Jul 2021 10:32:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nxb0rTITqHJRawqSXL04SAf8WBgwW80hUq+O1u57DwA=; b=d5QZUBy6PgE977UqHLcQ5LPYx0MYxAJIp4VNIZ+CLvguQ5qz6KAlf+rcQ9NmgYEb6e iKkEgBTulrlIDQiaP3XlbVfUHYrvxMc8LwRa2u+XX6mY+gPzvIC5DkmnfhyDb53djR+N 02RU24UU+csi+UeTI94IwFq0N6ds3LWTHgkzkWVCs7v6lSBW+oV3g4RLBtwDoN55knO7 2fE7URYaEm5L9CniSPIkNiak/1eQGE3N77AvXfIMlZKydOlioSALlYbH3vbEtloxcRus HAHNUGVo8uf5dLmJjXnGjr6+I4b0F2nJAR/voL5uR7pkAVh+RbUmCoVZHoEfkyRKE7p1 qayw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nxb0rTITqHJRawqSXL04SAf8WBgwW80hUq+O1u57DwA=; b=tN8+asociXmMupe/oR63NZb6p3yTm2AB5aavTmtINDOHMKRb/pcsaU81WcVxXvGS2D 4DzlUlc3hJGz66+W5g6ztNglCuLbcrljkFgCGPv+CDmNYt3RhtoIqEbUmrZKnffE3kKV 1VAINGMLb9UgAbUstCQDMsRCFKa6Ek3M15nLn927PCPYcGCNW2QoRsKX4AuGaNPQbPju mtYipWc4Od2NV8Y0esrFojy4BhgXasL3W+ilVjUJoYn7E/Sgc4byYWjbrwu8LIpJAyDJ cF93jX8q4rhkweiUfg34iBsutjwLyHs24rJEoKcLwQyf7UXZ9C41tyDPO200f4o+1Xxz 7DPA== X-Gm-Message-State: AOAM5319QxdqIwUYHT6A/onU0J5QNcC8LoeWCTUGINCdUHNO052t1ma+ qgVyGIv13SaO+dJkQ4fTWH+9qw== X-Google-Smtp-Source: ABdhPJwdaUwCS3dvf1IcAmVy2j7ammaRPmfbi/eXqpqhFPVtY+j2eJVccaHqfasX6ea+y04xjJc3AA== X-Received: by 2002:a2e:97d1:: with SMTP id m17mr17280087ljj.168.1625851926598; Fri, 09 Jul 2021 10:32:06 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id b14sm511129lfb.132.2021.07.09.10.32.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 10:32:06 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [PATCH v3 3/7] clk: qcom: gdsc: enable optional power domain support Date: Fri, 9 Jul 2021 20:31:58 +0300 Message-Id: <20210709173202.667820-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210709173202.667820-1-dmitry.baryshkov@linaro.org> References: <20210709173202.667820-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On sm8250 dispcc and videocc registers are powered up by the MMCX power domain. Currently we use a regulator to enable this domain on demand, however this has some consequences, as genpd code is not reentrant. Teach Qualcomm clock controller code about setting up runtime PM and using specified for gdsc powerup. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/common.c | 37 +++++++++++++++++++++++++++++++------ drivers/clk/qcom/gdsc.c | 4 ++++ 2 files changed, 35 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index 60d2a78d1395..43d8f8feeb3c 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -10,6 +10,7 @@ #include #include #include +#include #include "common.h" #include "clk-rcg.h" @@ -224,6 +225,11 @@ static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec, return cc->rclks[idx] ? &cc->rclks[idx]->hw : NULL; } +static void qcom_cc_pm_runtime_disable(void *data) +{ + pm_runtime_disable(data); +} + int qcom_cc_really_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc, struct regmap *regmap) { @@ -241,6 +247,18 @@ int qcom_cc_really_probe(struct platform_device *pdev, if (!cc) return -ENOMEM; + pm_runtime_enable(dev); + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + pm_runtime_put(dev); + pm_runtime_disable(dev); + return ret; + } + + ret = devm_add_action_or_reset(dev, qcom_cc_pm_runtime_disable, dev); + if (ret) + goto err; + reset = &cc->reset; reset->rcdev.of_node = dev->of_node; reset->rcdev.ops = &qcom_reset_ops; @@ -251,7 +269,7 @@ int qcom_cc_really_probe(struct platform_device *pdev, ret = devm_reset_controller_register(dev, &reset->rcdev); if (ret) - return ret; + goto err; if (desc->gdscs && desc->num_gdscs) { scd = devm_kzalloc(dev, sizeof(*scd), GFP_KERNEL); @@ -262,11 +280,11 @@ int qcom_cc_really_probe(struct platform_device *pdev, scd->num = desc->num_gdscs; ret = gdsc_register(scd, &reset->rcdev, regmap); if (ret) - return ret; + goto err; ret = devm_add_action_or_reset(dev, qcom_cc_gdsc_unregister, scd); if (ret) - return ret; + goto err; } cc->rclks = rclks; @@ -277,7 +295,7 @@ int qcom_cc_really_probe(struct platform_device *pdev, for (i = 0; i < num_clk_hws; i++) { ret = devm_clk_hw_register(dev, clk_hws[i]); if (ret) - return ret; + goto err; } for (i = 0; i < num_clks; i++) { @@ -286,14 +304,21 @@ int qcom_cc_really_probe(struct platform_device *pdev, ret = devm_clk_register_regmap(dev, rclks[i]); if (ret) - return ret; + goto err; } ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc); if (ret) - return ret; + goto err; + + pm_runtime_put(dev); return 0; + +err: + pm_runtime_put(dev); + + return ret; } EXPORT_SYMBOL_GPL(qcom_cc_really_probe); diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index 51ed640e527b..ccd36617d067 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -439,6 +439,8 @@ int gdsc_register(struct gdsc_desc *desc, continue; if (scs[i]->parent) pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd); + else if (!IS_ERR_OR_NULL(dev->pm_domain)) + pm_genpd_add_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd); } return of_genpd_add_provider_onecell(dev->of_node, data); @@ -457,6 +459,8 @@ void gdsc_unregister(struct gdsc_desc *desc) continue; if (scs[i]->parent) pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd); + else if (!IS_ERR_OR_NULL(dev->pm_domain)) + pm_genpd_remove_subdomain(pd_to_genpd(dev->pm_domain), &scs[i]->pd); } of_genpd_del_provider(dev->of_node); } From patchwork Fri Jul 9 17:31:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 471885 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp517369jao; Fri, 9 Jul 2021 10:32:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyACoCPiXq2yt8UHvOdcVK+9Nod5xH2mKlztWdaQsjErr1FfDGucvjBib81tb3U1mF2t3gk X-Received: by 2002:a92:6e07:: with SMTP id j7mr12812860ilc.71.1625851938606; Fri, 09 Jul 2021 10:32:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625851938; cv=none; d=google.com; s=arc-20160816; b=fBDbjvn5gXWSwL/DOIgfYRS0ZiejNKLrnTilPqAI62Unv8CgD6uZAvYir4/feOMFBO 1FgmLol0UDp4C2nnNYzVhcKng6HKzaTdgH4XlBjUKpqyUvhtvkqLwNEpFMKbghM+FkF3 FQ2sITbQifGuvURMbrR/CPYoIjjKVGCtPzKEk1q8EoAZoGjccHghkPtYsEQ37mAkRkiD e0CTkOjXdnOetzf9odbae+Pr8/V38iu+9lFFoQAKr1h6RxZ932Gyd8HH+ihpLbGlWE7p anMVMP2eXZxSjgnEogafyyvwZfo025xVNubDFL0LIwVLwTCdnMmz8GET2nn/dXmau5nJ AEjw== ARC-Message-Signature: i=1; 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Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gdsc.c | 66 ++++++++++++++++++++++++++++++++++++++--- drivers/clk/qcom/gdsc.h | 2 ++ 2 files changed, 64 insertions(+), 4 deletions(-) -- 2.30.2 diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index ccd36617d067..6bec31fccb09 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -50,6 +51,30 @@ enum gdsc_status { GDSC_ON }; +static int gdsc_pm_runtime_get(struct gdsc *sc) +{ + int ret; + + if (!sc->rpm_dev) + return 0; + + ret = pm_runtime_get_sync(sc->rpm_dev); + if (ret < 0) { + pm_runtime_put_noidle(sc->rpm_dev); + return ret; + } + + return 0; +} + +static int gdsc_pm_runtime_put(struct gdsc *sc) +{ + if (!sc->rpm_dev) + return 0; + + return pm_runtime_put_sync(sc->rpm_dev); +} + /* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */ static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status) { @@ -232,9 +257,8 @@ static void gdsc_retain_ff_on(struct gdsc *sc) regmap_update_bits(sc->regmap, sc->gdscr, mask, mask); } -static int gdsc_enable(struct generic_pm_domain *domain) +static int _gdsc_enable(struct gdsc *sc) { - struct gdsc *sc = domain_to_gdsc(domain); int ret; if (sc->pwrsts == PWRSTS_ON) @@ -290,11 +314,28 @@ static int gdsc_enable(struct generic_pm_domain *domain) return 0; } -static int gdsc_disable(struct generic_pm_domain *domain) +static int gdsc_enable(struct generic_pm_domain *domain) { struct gdsc *sc = domain_to_gdsc(domain); int ret; + ret = gdsc_pm_runtime_get(sc); + if (ret) + return ret; + + ret = _gdsc_enable(sc); + if (ret) { + gdsc_pm_runtime_put(sc); + return ret; + } + + return 0; +} + +static int _gdsc_disable(struct gdsc *sc) +{ + int ret; + if (sc->pwrsts == PWRSTS_ON) return gdsc_assert_reset(sc); @@ -329,6 +370,18 @@ static int gdsc_disable(struct generic_pm_domain *domain) return 0; } +static int gdsc_disable(struct generic_pm_domain *domain) +{ + struct gdsc *sc = domain_to_gdsc(domain); + int ret; + + ret = _gdsc_disable(sc); + if (ret) + return ret; + + return gdsc_pm_runtime_put(sc); +} + static int gdsc_init(struct gdsc *sc) { u32 mask, val; @@ -425,6 +478,8 @@ int gdsc_register(struct gdsc_desc *desc, for (i = 0; i < num; i++) { if (!scs[i]) continue; + if (pm_runtime_enabled(dev)) + scs[i]->rpm_dev = dev; scs[i]->regmap = regmap; scs[i]->rcdev = rcdev; ret = gdsc_init(scs[i]); @@ -486,7 +541,10 @@ void gdsc_unregister(struct gdsc_desc *desc) */ int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain) { + struct gdsc *sc = domain_to_gdsc(domain); + /* Do nothing but give genpd the impression that we were successful */ - return 0; + /* Get the runtime PM device only */ + return gdsc_pm_runtime_get(sc); } EXPORT_SYMBOL_GPL(gdsc_gx_do_nothing_enable); diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index 5bb396b344d1..a82982df0a55 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -25,6 +25,7 @@ struct reset_controller_dev; * @resets: ids of resets associated with this gdsc * @reset_count: number of @resets * @rcdev: reset controller + * @rpm_dev: runtime PM device */ struct gdsc { struct generic_pm_domain pd; @@ -58,6 +59,7 @@ struct gdsc { const char *supply; struct regulator *rsupply; + struct device *rpm_dev; }; struct gdsc_desc { From patchwork Fri Jul 9 17:32:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 471883 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp517327jao; Fri, 9 Jul 2021 10:32:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwo8m9Ujp1nN//hGOZ4/cKQnADeMjNvG+O+GvsKGNAchEREGsWAA6GXU2Hedb3onju8Xtil X-Received: by 2002:a92:d246:: with SMTP id v6mr26018748ilg.191.1625851935968; Fri, 09 Jul 2021 10:32:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625851935; cv=none; d=google.com; s=arc-20160816; b=iEGLxHrlAIhtqgMCgfhVXsqx274ZezD+9eQ6FDl3Qaq4hxzPvmAaDlj+flH8WpoSjb DhEwMuqYYVQWiI5KzPcaQOhnCiP2+3W0AGsT+XI1D1mYKB3gYb9puFzclhcMCJgaxUWA w3cbQUJ1MAtAS8ZLxfrCROHG7FlI8sNIQtwbqbY6e7hehK/BEXT5ESpdRe95rnRZvPTl sM/qydRMk40iHhQSblNrNXzMDxy/wW7kG95hnZJ0licWepqBalQh16ww6nm2/pbeIV55 0L6X9dJJ9d96pmUSmfje0redbt4KDZo6OtPsLBk+tjeq3pfep2tmPwB2ZFPGZfkUGNsJ jCEg== ARC-Message-Signature: i=1; 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Drop the now unused mmcx regulator. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) -- 2.30.2 Reviewed-by: Bjorn Andersson diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 4c0de12aaba6..2a468b85dc09 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -271,13 +271,6 @@ memory@80000000 { reg = <0x0 0x80000000 0x0 0x0>; }; - mmcx_reg: mmcx-reg { - compatible = "regulator-fixed-domain"; - power-domains = <&rpmhpd SM8250_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; - regulator-name = "MMCX"; - }; - pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; @@ -2362,7 +2355,7 @@ videocc: clock-controller@abf0000 { clocks = <&gcc GCC_VIDEO_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>; - mmcx-supply = <&mmcx_reg>; + power-domains = <&rpmhpd SM8250_MMCX>; clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; #clock-cells = <1>; #reset-cells = <1>; @@ -2627,7 +2620,7 @@ opp-358000000 { dispcc: clock-controller@af00000 { compatible = "qcom,sm8250-dispcc"; reg = <0 0x0af00000 0 0x10000>; - mmcx-supply = <&mmcx_reg>; + power-domains = <&rpmhpd SM8250_MMCX>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&dsi0_phy 0>, <&dsi0_phy 1>, From patchwork Fri Jul 9 17:32:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 471884 Delivered-To: patch@linaro.org Received: by 2002:a02:c94a:0:0:0:0:0 with SMTP id u10csp517358jao; Fri, 9 Jul 2021 10:32:18 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyrf1BzeuIX5yrdKLaxPEjKkdYrCoGvIcttsr/Pytzkz6fa1DBd1nsRZMbY/8GwJITEJaBN X-Received: by 2002:a92:d246:: with SMTP id v6mr26018859ilg.191.1625851937965; Fri, 09 Jul 2021 10:32:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1625851937; cv=none; d=google.com; s=arc-20160816; b=Xb52sWVp2ZHwyai8Qx/VOB+aMCccOSABOR3XVmJLysJONm7B4uvAqSQKMOpz7iPPNx pcIwXKTp2UADeDYljXtjnKO9wFLxJCNPLFVtBvEdpxK4NpwHlK3YntZUGST9O8aG77pR txua6Izr+NawmcpS7R61wITd0Oqpk8ra3DhLcDDW6Prlu1e9Qx0mtG+X3V1ZV23/Yuq1 zcRzBZWzv4i0PO3usVc1IF4HK8K9GWZJq5CJ3+sPdO8PiA8pehB4YD88ICAs6ZldX0jp SirXdZ2/6ZrY6Aw1f77iyyxXAfG3YdcPxO+xqyrFsZaDd2zSd7weJQz62KFsjsBd6sL8 AWsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=f0ldkE5j34OXHAqh3I/xyyl0k1n40wAos/+0qzuAEic=; b=Z8JqTSzwM88HeJYqA7XJ7pkKiCnvN/FsotnJ1xJRzBPcxld2R5S8+Z6GfBJEQmWvgL 3djz4oJNyM8YGO9ocaylr0lCBth4VGyMnc0Q1Wm+XylAfvHzTXLZfRugXJrc7t/WLQ6r aOpT6cxCHsoxJtsP+ov9CafwKJ2Qremxv8ObctO+M1dhU4vLRF8+rUI49P2ma5qCbKBb h3KW/L5pv5wErnsP9BQ2a/7QOZbf/H5Y5JDPfwsNFEych6VhkY7YOz6NUHYrCP+trpDN vZpLR0vSO3L4RhsWLBdCef7cJfMQr+b4auMB6nEXgGH8RkHtT+RMG3idRRGN8aeLkkce kaFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=p4MDQnpF; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/dispcc-sm8250.c | 1 - 1 file changed, 1 deletion(-) -- 2.30.2 Reviewed-by: Bjorn Andersson diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index de09cd5c209f..dfbfe64b12f6 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -955,7 +955,6 @@ static struct gdsc mdss_gdsc = { }, .pwrsts = PWRSTS_OFF_ON, .flags = HW_CTRL, - .supply = "mmcx", }; static struct clk_regmap *disp_cc_sm8250_clocks[] = { From patchwork Fri Jul 9 17:32:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 471940 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8DDEEC11F70 for ; Fri, 9 Jul 2021 17:32:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 74914613DF for ; Fri, 9 Jul 2021 17:32:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230180AbhGIRe7 (ORCPT ); Fri, 9 Jul 2021 13:34:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230211AbhGIRe4 (ORCPT ); Fri, 9 Jul 2021 13:34:56 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64A90C0613E5 for ; Fri, 9 Jul 2021 10:32:11 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id a18so24659487lfs.10 for ; Fri, 09 Jul 2021 10:32:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OW6r9Ztak14Z94NLN85hpavnPWferFff+9qy6SUKk4g=; b=FrxLNPysWTbK6msNrS77oo1V4NLdNkri1hMORbbVvbWnWUfTditLVD1NZEyi+EIkhe Ytl9GL9s7p+GxeHZSa0K1KVSHbHt7Db+9PZoaOBAiMDhKNzGPF7vIz4gxe0bV3Ijw0fu KO1XVn5897fkEBOsj2zwZJvWih3RQDHTsVQgcr9nkNrpxaiWUBPlLL/DvWhDF9Lj/zad p1+qpPBsUSq6yG1B9o1K7uNG+flJ7Bl5oK8vUla4zQnjwj/A3nKVXsVHFuy6X8xNFf2C PKQldZcDzARyowiHBxpuxrTx2Vsr3ZnfqA/S3Wlh2aEHPN/3VRBjC+KyVGaNIBfaJJDm iodA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OW6r9Ztak14Z94NLN85hpavnPWferFff+9qy6SUKk4g=; b=tXoLcB/tqffoR+ZJ55FoWvGKzU4+LmH7fSIPvqTAW4EtWMtpmuY9IRdomen3kNSkGx b20s7K06aBSsp5sRJYQusO+KsLtIwb135SBH+F7xG0bydD5hktjDRPoW/YYtfFiSrn/f pc+PlL+ouGvuzdmPn59lcqsMwKWASMKB5XUxBnes82+gFVYoaHDog1nBoV5Qt0fzEvRL m2Cpy0KJ0DZjNtWWf7o2pgSqAhHIWv10r0r9HqglDVEwRtwxFr/72fipiXoI/imD7jm/ GVOoIJ8CotkG6zriFyt2PO0RMyc0AFa2ykAmTlhnHl23TF8g+G1OGVURUpKXbg+vFmDw PTJg== X-Gm-Message-State: AOAM533KMTZAcgDKuBP3GdFc+G+L1HbnNuBh9jqsLTa1n04S1nKFTgQQ KwFYHWH/zNM+ikzJdRn4idMHaQ== X-Google-Smtp-Source: ABdhPJxUjTJVOzCEta2wUHL7FVm04+6VVBlwN0yiMRnKs+nVtnq3uEoz/4a6MO5w5EjHJcZlqo9D2g== X-Received: by 2002:ac2:48a9:: with SMTP id u9mr9304635lfg.277.1625851929692; Fri, 09 Jul 2021 10:32:09 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id b14sm511129lfb.132.2021.07.09.10.32.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 10:32:09 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Stephen Boyd , Taniya Das , Jonathan Marek , Michael Turquette Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Bryan O'Donoghue , Mark Brown , Ulf Hansson , linux-kernel@vger.kernel.org Subject: [PATCH v3 7/7] clk: qcom: videocc-sm8250: stop using mmcx regulator Date: Fri, 9 Jul 2021 20:32:02 +0300 Message-Id: <20210709173202.667820-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210709173202.667820-1-dmitry.baryshkov@linaro.org> References: <20210709173202.667820-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Now as the common qcom clock controller code has been taught about power domains, stop mentioning mmcx supply as a way to power up the clock controller's gdscs. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson --- drivers/clk/qcom/videocc-sm8250.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/clk/qcom/videocc-sm8250.c b/drivers/clk/qcom/videocc-sm8250.c index 7b435a1c2c4b..eedef85d90e5 100644 --- a/drivers/clk/qcom/videocc-sm8250.c +++ b/drivers/clk/qcom/videocc-sm8250.c @@ -276,7 +276,6 @@ static struct gdsc mvs0c_gdsc = { }, .flags = 0, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct gdsc mvs1c_gdsc = { @@ -286,7 +285,6 @@ static struct gdsc mvs1c_gdsc = { }, .flags = 0, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct gdsc mvs0_gdsc = { @@ -296,7 +294,6 @@ static struct gdsc mvs0_gdsc = { }, .flags = HW_CTRL, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct gdsc mvs1_gdsc = { @@ -306,7 +303,6 @@ static struct gdsc mvs1_gdsc = { }, .flags = HW_CTRL, .pwrsts = PWRSTS_OFF_ON, - .supply = "mmcx", }; static struct clk_regmap *video_cc_sm8250_clocks[] = {